AN-1025 [FAIRCHILD]
Maximum Power Enhancement Techniques for SuperSOTTM-3 Power MOSFETs; 对于SuperSOTTM - 3功率MOSFET最大功率增强技术
| 型号： | AN-1025 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Maximum Power Enhancement Techniques for SuperSOTTM-3 Power MOSFETs |
| 文件： | 总11页 (文件大小：256K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AN1025
April, 1996
Maximum Power Enhancement Techniques for SuperSOTTM-3 Power
MOSFETs
Alan Li, Brij Mohan, Steve Sapp, Izak Bencuya, Linh Hong
1. Introduction
As packages become smaller, achieving efficient thermal performance for power applications
requires that the designers employ new methods of meliorating the heat flow out of devices.
Thus the purpose of this paper is to aid the user in maximizing the power handling capability of
the SuperSOTTM-3 (SOT-23) Power MOSFET offered by Fairchild Semiconductor. This effort
allows the user to take full advantage of the exceptional performance features of Fairchild’s
state-of-the-art Power MOSFET which offers very low on-resistance and improved junction-to-
case (RθJC) thermal resistance. Ultimately the user may achieve improved component perfor-
mance and higher circuit board packing density by using the thermal solution suggested below.
In natural cooling, the method of improving power performance should be focused on the opti-
mum design of copper mounting pads. The design should take into consideration the size of the
copper and its placement on either or both of the board surfaces. A copper mounting pad is
important because the drain lead of the Power MOSFET is mounted directly onto the pad. The
pad acts as a heatsink to reduce thermal resistance and leads to improved power performance.
D
S
G
Figure 1. SuperSOTTM-3 Power MOSFET has the same package dimensions as the SOT-23 but the
maximized copper lead frame reduces the junction-to-case thermal resistance RθJC to 75oC/W.
2. Theory
When a device operates in a system under the steady-state condition, the maximum power
dissipation is determined by the maximum junction temperature rating, the ambient tempera-
ture, and the junction-to-ambient thermal resistance.
PDmax = (TJmax - TA)/ RθJC (2.1)
The term junction refers to the point of thermal reference of the semiconductor. Equation 2.1
can also be applied to the transient-state:
PDmax (t) = [ TJmax - TA] / RθJC (t) (2.2)
Rev B, August 1998
1
where PDmax(t) and RθJC(t) are time dependent. By using the transient thermal resistance curves
shown in the data sheet, a transient temperature change can be calculated. The transient thermal
behavior is a complicated subject because RθJA(t) increases non-linearly with time and the condi-
tions of the power pulse. A more thorough treatment of transient power analysis is beyond the
scope of this document and the reader can refer to [13] for details. Nevertheless, Fairchild provides
a Discrete SPICE Thermal Model (LIT#570240-002) for general thermal evaluation. The user may
find these models helpful in determining the dynamic power and temperature limits in the applica-
tion.
RθJA has two distinct elements, RθJC junction-to-case and RθCA case-to-ambient thermal resistance.
RθJA = RθJC + RθCA (2.3)
The case thermal reference of the SuperSOTTM-3 Power MOSFET is defined as the point of con-
tact between the drain lead of the package and the mounting surface.
RθCA is influenced by many variables such as ambient temperature, board layout, and cooling
method. Due to the lack of an industry standard, the value of RθCA is not easily defined and can
affect RθJA significantly. In addition, the case reference may be defined differently by various manu-
facturers. Under such conditions, it becomes difficult to define RθCA from the component manufac-
turer standpoint. On the other hand, RθJC is independent of users’ conditions and can be accu-
rately measured by the component manufacturer.
Therefore, in this paper an effort has been made to define a procedure which can be used to
quantify the junction-to-ambient thermal resistance RθJA which is more useful to the circuit board
designer.
3. Result
The scope of the investigation has been limited to the size of copper mounting pad and its relative
surface placement on the board. In still air with no heatsink, the application of these heat dissipa-
tion methods is the most cost effective thermal solution. A total of sixteen different combinations
of 2 Oz copper pad sizes and their placement were designed to study their influence on RθJA
thermal resistance. The configurations of the board layout are shown in figure 2 and table 1.
Layouts 1 to 6 have the copper pad sizes from 0.001 to 0.4 square inches on the top side of the
board (top side is defined as the component side of the board). Layouts 7 to 11 have copper pad
sizes from 0.02 to 0.4 square inches on the bottom side of the board. Layouts 12 to 16 have
copper pad sizes from 0.02 to 0.4 square inches divided equally on both sides of the board.
2
1
2
12
7
13
14
8
9
3
4
15
10
5
16
11
6
i
c
o
n
l
Se m
d
u c t o r
Figure 2. Top Side of the 4.5”x5” SuperSOTTM-3 Thermal Board. Complete scale drawings are shown in
section 5.
2 Oz Copper Mounting Pad
Area (in2)
Relative Placement on
Board
Layout
1-6
0.001, 0.02, 0.05, 0.1, 0.25, 0.4 Top
7-11
0.02, 0.05, 0.1, 0.25, 0.4
0.02, 0.05, 0.1, 0.25, 0.4
Bottom
1/2 Top and 1/2 Bottom
12-16
Table 1: Thermal Board Configurations
RθJA was calculated from the relationship between power and the change of junction temperature.
If readers are interested in the test conditions and method, they are encouraged to refer to appen-
dix B for details.
300
4.5"x5" FR-4 Board
TA = 25o
Still Air
C
250
200
150
100
50
1/2Top+1/2Bottom Cu
Bottom Cu
Top Cu
0
0.1
0.2
0.3
2
0.4
2oz COPPER MOUNT ING PAD AREA (in
)
Figure 3. SuperSOTTM-3 Junction-to-Ambient thermal resistance versus copper mounting pad area
and its surface placement.
3
Plots in figure 3 show the relationship of RθJA versus the copper mounting pad area and its surface
placement on the board. It is apparent that increasing copper mounting pad area considerably
lowers RθJA from approximately 270 to 160oC/W in the range from 0.001 to 0.4 square inches. In
addition, placing all the copper on the top side of the board further reduces RθJA by 2 to 15oC/W
when compared with the other two placements.
By substituting the thermal resistance, ambient temperature, and the maximum junction tempera-
ture rating into equation 2.1, the steady-state maximum power dissipation curves can be obtained
and are shown in figure 4.
A 30% increase in the power handling can be achieved by increasing the copper pad area on top
of the board from 0.001 to 0.02 in2, layout 2. This thermal pad fits directly under the package, so
that no additional board space is required. For maximum performance, it is recommended to put
extra copper on the bottom of the board connected to the top pad by through-hole thermal vias.
0.8
Top Cu
1/2Top+1/2Bottom Cu
0.7
Bottom Cu
0.6
Recom mended 0.02 in^2 package sized Cu to achieve 0.6W
0.5
4.5"x5" FR-4 Board
TA = 25o
Still Air
C
0.4
0
0.1
0.2
0.3
2
0.4
2oz COPPER MOUNT ING PAD AREA (in
)
Figure 4. Maximum Power Dissipation Curves for SuperSOTTM-3. 0.02 in² 2 Oz copper mounting pad
area, layout 2, is recommended to achieve approximately 0.6W.
4. Conclusion
Fairchild Semiconductor has attempted to define the thermal performance of the SuperSOTTM-3
Power MOSFET, from a systems point of view. It has been demonstrated that significant thermal
improvement can be achieved in the maximum power dissipation through the proper design of
copper mounting pads on the circuit board. The results can be summarized as follows:
•
•
•
Enlarged copper mounting pads, on either one or both sides of the board, are effective in
reducing the case-to-ambient thermal resistance RθCA
Placement of the copper pads on the top side of the board gives the best thermal perfor-
.
mance.
The most cost effective approach of designing layout 2 0.02 square inches copper pad directly
under the package, without occupying additional board space, can increase the maximum
power from approximately 0.46 to 0.6W.
4
5. SuperSOTTM-3 (SOT-23) Thermal Board Top and Bottom View
5
Appendix A
Heat Flow Theory Applied to Power MOSFETs
When a Power MOSFET operates with an appreciable current, its junction temperature is el-
evated. It is important to quantify its thermal limits in order to achieve acceptable performance and
reliability. This limit is determined by summing the individual parts consisting of a series of
temperature rises from the semiconductor junction to the operating environment. A one dimen-
sional steady-state model of conduction heat transfer is demonstrated in figure 5. The heat gener-
ated at the device junction flows through the die to the die attach pad, through the lead frame to the
surrounding case material, to the printed circuit board, and eventually to the ambient environment.
There are also secondary heat paths. One is from the package to the ambient air. The other is
from the drain lead frame to the detached source and gate leads then to the printed circuit board.
These secondary heat paths are assumed to be negligible contributors to the heat flow in this
analysis.
θ
θ θ
JA= R JC+ R C A
R
θ
TJ-TA = PD * R JA
Lead Frame
Di e
Case Reference for
thermal coupel in
θ
R
JC measurement
Junction Reference
θ
R
C A
S our ce, Gate Mounting Pad
(Poor Thermal Path)
θ
R
JC
= 25 oC
MoldedP ackage
T
A
Boa rd
Drain Mounting Pad
RθC A(Applications Variables )
Vi a
Extended Copper Pal ne
RθJ C (Component Variables)
Mounting Pad Size, Mater ial, Shape &L ocation
P lacement of M ounting Pad
PCB Size& Material
Amount of thermal Via
Tra c es Le ngth & Width
L eadframe Siz e & Mate ria l
No. of Conduct ion Pins
DieSi ze
Die Attach Material
Molding Compound Size& Material
Adjacent Heat Sources
Air Flow Rate and Volume of Air
Ambient Temperature
.....e. tc
Figure 5: Cross-sectional view of a Power MOSFET mounted on a printed circuit board. Note that the
case temperature is measured at the point where the drain lead(s) contact with the mounting pad
surface.
The increase of junction temperature above the surrounding environment is directly proportional to
dissipated power and the thermal resistance.
The steady-state junction-to-ambient thermal resistance, RθJA, is defined as
RθJA = ( TJ - TA ) / P
where TJ is the average temperature of the device junction. The term junction refers to the point of
thermal reference of the semiconductor device. TA is the average temperature of the ambient
environment. P is the power applied to the device which changes the junction temperature.
RθJA is a function of the junction-to-case RθJC and case-to-ambient RθCA thermal resistance
RθJA = RθJC + RθCA
Rev B, August 1998
6
where the case of a Power MOSFET is defined at the point of contact between the drain lead(s)
and the mounting pad surface. RθJC can be controlled and measured by the component manufac-
turer independent of the application and mounting method and is therefore the best means of
comparing various suppliers component specifications for thermal performance. On the other hand,
it is difficult to quantify RθCA due to heavy dependence on the application. Before using the data
sheet thermal data, the user should always be aware of the test conditions and justify the compat-
ibility in the application.
Appendix B
Thermal Measurement
Prior to any thermal measurement, a K factor must be determined. It is a linear factor related to
the change of intrinsic diode voltage with respect to the change of junction temperature. From the
slope of the curve shown in figure 6, K factor can be determined. It is approximately 2.2mV/oC for
most Power MOSFET devices.
NDS9956 VSD vs Temperature
0.7
VGS = 0V
0.6
0.5
ISD = 20mA
10mA
0.4
5mA
1mA = 2.39 mV/°C
2mA
2mA = 2.33
1mA
0.3
5mA = 2.25
10mA = 2.19
20mA = 2.13
0.2
25
50
75 100
Temperature (°C)
125
150
Figure 6. K factors, slopes of a VSD vs temperature curves, of a typical Power MOSFET
After the K factor calibration, the drain-source diode voltage of the device is measured prior to any
heating. A pulse is then applied to the device and the drain-source diode voltage is measured
30us following the end of the power pulse. From the change of the drain-source diode voltage, the
K factor, input power, and the reference temperature, the time dependent single pulsed junction-to-
reference thermal resistance can be calculated. From the single pulse curve on figure 7, duty
cycle curves can be determined. Note: a curve set in which RθJA is specified indicates that the part
was characterized using the ambient as the thermal reference. The board layout specified in the
data sheet notes will help determine the applicability of the curve set.
7
1
D= 0.5
0.5
0.2
0.1
0.2
0.1
R
(t)= r(t) * R
θJA
= See Note 1a, b,
c
θJA
R
JA
θ
0.05
0.02
0.01
0.05
0.02
0.01
P(pk)
t
1
Single Pulse
t
2
0.005
T - T = P * R
(t)
JA
θ
J
A
0.002
0.001
Duty Cycle, D= t /t
1
2
0.0001
0.001
0.01
0.1
1
10
100
300
t , TIME(sec)
1
Figure 7. Normalized Transient Thermal Resistance Curves
B.1 Junction-to-Ambient Thermal Resistance Measurement
Equipment and Setup:
•
•
•
Tesec DV240 Thermal Tester
1 cubic foot still air environment
Thermal Test Board with 16 layouts defined by the size of the copper mounting pad and their
relative surface placement. For layouts with copper on the top and bottom planes, there are
0.02 inch copper plated vias (heat pipes) connecting the two planes. See figure 2 and table 1
on the thermal application note for board layout and description. The conductivity of the FR-4
PCB used is 0.29 W/m-C. The length is 5.00 inches ± 0.005; width 4.50 inches ± 0.005; and
thickness 0.062 inches ± 0.005. 2Oz copper clad PCB.
The junction-to-ambient thermal measurement was conducted in accordance with the require-
ments of MIL-STD-883 and MIL-STD-750 with the exception of using 2 Oz copper and measuring
diode current at 10mA.
A test device is soldered on the thermal test board with minimum soldering. The copper mounting
pad reaches the remote connection points through fine traces. Jumpers are used to bridge to the
edge card connector. The fine traces and jumpers do not contribute significant thermal dissipation
but serve the purpose of electrical connections. Using the intrinsic diode voltage measurement
described above, the junction-to-ambient thermal resistance can be calculated.
B.2 Junction-to-Case Thermal Resistance Measurement
Equipment and Setup:
•
•
•
Tesec DV240 Thermal Tester
large aluminum heat sink
type-K thermocouple with FLUKE 52 K/J Thermometer
The drain lead(s) is soldered on a 0.5 x 1.5 x 0.05 copper plate. The plate is mechanically clamped
to a heat sink which is large enough to be considered ideal. Thermal grease is applied in-between
the two planes to provide good thermal contact. Theoretically the case temperature should be held
constant regardless of the conditions. Thus a thermocouple is used and fixed at the point of
contact between the drain lead(s) and the copper plate surface, to account for any heatsink
temperature change. Using the intrinsic diode voltage measurement described earlier, the junc-
tion-to-case thermal resistance can be obtained. A plot of junction-to-case thermal resistance for
8
various packages is shown in figure 8. Note RθJC can vary with die size and the effect is more
prominent as RθJC decreases.
Junction-to-Case Thermal Resistance
80
*
Dual Leadframes
** Triple Leadframes
rjcall.pre 10/4/95
68
*
60
40
20
0
53.3
*
38.9
30
23.8
**
20.8
17.6
15
13.3
7.4
5
1
Figure 8. Junction-to-case thermal resistance RθJC of various surface mount Power MOSFET
packages.
9
References
[1] K. Azar, S.S. Pan, J. Parry, H. Rosten, “Effect of Circuit Board Parameters on Thermal Performance of Electronic
Components in Natural Convection Cooling,” IEEE 10th annual Semi-Therm Conference, Feb. 1994.
[2] A. Bar-Cohen, & A.D. Krauss, “Advances in Thermal Modeling of Electronic Components & Systems,” Vol 1,
Hemisphere Publishing, Washington, D.C., 1988.
[3] R.T. Bilson, M.R. Hepher, J.P. McCarthy, “The Impact of Surface Mounted Chip Carrier Packaging on Thermal
Management in Hybrid Microcircuit,” Thermal Management Concepts in Microelectronics Packaging, InterFairchild
Society for Hybrid Microelectronics, 1984.
[4] R.A. Brewster, R.A. Sherif, “Thermal Analysis of A Substrate with Power Dissipation in the Vias,” IEEE 8th Annual
Semi-Therm Conf., Austin, Tx , Feb. 1992.
[5] D. Edwards, “Thermal Enhancement of IC Packages, “ IEEE 10th Annual Semi-Therm Conf., San Jose, Ca, Feb.
1994.
[6] S.S. Furkay, “Convective Heat Transfer in Electronic Equipment: An Overview,” Thermal Management Concepts,
1984.
[7] C. Harper, Electronic Packaging & Interconnection Handbook, McGraw-Hill, NY, 1991, Ch. 2.
[8] Y.M. Kasem, R.K. Williams, “Thermal Design Principles and Characterization of Miniaturized Surface-Mount Pack-
ages for Power Electronics,” IEEE 10th annual Semi-Therm Conf., San Jose, Ca, Feb. 1994.
[9] V. Manno, N.R. Kurita, K. Azar, “Experimental Characterization of Board Conduction Effect,” IEEE 9th Annual Semi-
Therm Conf., 1993.
[10] J.W. Sofia, “Analysis of Thermal Transient Data with Synthesized Dynamic Models for Semiconductor Devices,”
IEEE 10th Annual Semi-Therm Conf., San Jose, Ca, Feb. 1994.
[11]G.R. Wagner, “Circuit Board Material/Construction and its Effect on Thermal Management,” Thermal Management
Concepts, 1984.
[12] M. Wills, “Thermal Analysis of Air-Cooled Cbs,” Electron Prod., pp. 11-18, May 1983.
[13] Motorola Application Note AN-569.
10
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The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
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POP™
PowerTrench™
QS™
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Quiet Series™
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SuperSOT™-6
SuperSOT™-8
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GTO™
HiSeC™
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