74ACT1284MTCX [ETC]
4-Bit Bus Transceiver ; 4位总线收发器\n
| 型号： | 74ACT1284MTCX |
| 厂家： | 
ETC |
| 描述： | 4-Bit Bus Transceiver
|
| 文件： | 总7页 (文件大小：266K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1996
Revised November 2000
74ACT1284
IEEE 1284 Transceiver
General Description
Features
The 74ACT1284 contains four non-inverting bidirectional
buffers and three non-inverting buffers with open Drain out-
puts and high drive capability on the B Ports. It is intended
to provide a standard signaling method for a bi-direction
parallel peripheral in an Extended Capabilities Port mode
(ECP).
■ TTL-compatible inputs
■ A Ports have standard 4 mA totem pole outputs
■ Typical input hysteresis of 0.5V
■ B Port high drive source/sink capability of 14 mA
■ Bidirectional non-inverting buffers
■ Supports IEEE P1284 Level 1 and Level 2 signaling
standards for bidirectional parallel communications
between personal computers and printing peripherals
The HD (active HIGH) input pin enables the B Ports to
switch from open Drain to a high drive totem pole output,
capable of sourcing 14 mA on all seven buffers. The DIR
input determines the direction of data flow on the bidirec-
tional buffers. DIR (active HIGH) enables data flow from
A Ports to B Ports. DIR (active LOW) enables data flow
from B Ports to A Ports.
■ B Port outputs in High Impedance mode during power
down
■ Guaranteed 4000V minimum ESD protection
Ordering Code:
Order Number Package Number
Package Description
74ACT1284SC
74ACT1284MSA
74ACT1284MTC
M20B
MSA20
MTC20
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
Description
HD
High Drive Enable input (Active HIGH)
Direction Control Input
Side A Inputs or Outputs
Side B Inputs or Outputs
Side A Inputs
DIR
A
B
1 - A4
1 - B4
A5 - A7
5 - B7
B
Side B Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation
DS011683
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Truth Table
Inputs
Outputs
DIR
HD
L
L
B1- B4 Data to A1 - A4, and
A
5 - A7 Data to B5 - B7 (Note 1)
B1- B4 Data to A1 - A4, and
5 - A7 Data to B5 - B7
L
H
A
H
H
L
A1 - A7 Data to B1 - B7 (Note 2)
A1 - A7 Data to B1 - B7
H
Note 1: B5 - B7 Open Drain Outputs
Note 2: B1 - B7 Open Drain Outputs
Logic Diagram
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2
Absolute Maximum Ratings(Note 3)
(Note 4)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
Supply Voltage (VCC
)
4.7V to 5.5V
0V to VCC
DC Input Diode Current (IIK
VI = −0.5V
)
Input Voltage (VI)
−20 mA
+20 mA
Output Voltage (VO)
0V to VCC
VI = VCC + 0.5V
Operating Temperature (TA)
−40°C to +85°C
DC Input Voltage (VI) A Side
DC Input Voltage (VI) B Side
DC Output Diode Current (IOK
−0.5V to VCC + 0.5V
−2V to +7V
)
V
V
O = −0.5V
−20 mA
+20 mA
O = VCC + 0.5V
DC Output Voltage (VO) A Side
DC Output Voltage (VO) B Side
DC Output Source
−0.5V to VCC + 0.5V
−2V to +7V
Note 3: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
or Sink Current (IO)
± 50 mA
DC VCC or Ground Current
Note 4: Either voltage limit or current limit is sufficient to protect inputs.
per Output Pin (ICC or IGND
)
± 50 mA
Storage Temperature (TSTG
)
−65°C to +150°C
DC Electrical Characteristics
VCC
Guaranteed Limits
Symbol
VIH
Parameter
Units
Conditions
Recognized
T
A = +25°C
T
A = 0°C to +70°C
T
A = −40°C to +85°C
(V)
4.7
5.5
4.7
5.5
Minimum HIGH Level
Input Voltage
2.0
2.0
0.8
0.8
4.5
2.0
2.0
0.8
0.8
4.5
2.0
2.0
0.8
0.8
4.5
V
V
High Signal
Recognized
Low Signal
VIL
Maximum LOW Level
Input Voltage
VOH
Minimum HIGH Level
Output Voltage
I
OUT = −50 µA (An)
IN = VIL or VIH (Note 5)
V
4.7
4.7
V
3.7
2.4
0.2
3.7
2.4
0.2
3.7
2.4
0.2
I
I
I
OH = −4 mA (An)
OH = −14 mA (Bn)
OUT = 50 µA (An)
VOL
Maximum LOW Level
Output Voltage
VIN = VIL or VIH (Note 5)
V
0.4
0.4
0.4
I
I
OH = 4 mA (An)
OH = 14 mA (Bn)
IIN
Maximum Input
VI = VCC, GND
5.5
5.5
5.5
±0.1
1.5
±1.0
1.5
µA
Leakage Current
(DIR, A5, A6, A7, HD)
ICCT
ICC
Maximum ICC/Input
Maximum Quiescent
Supply Current
mA VI = VCC − 2.1V
400
±20
100
400
500
µA
µA
µA
V
IN = VCC or GND
O = VCC, GND
IOZ
Maximum Output
5.5
0.0
±20
±20
V
Leakage Current
IOFF
Maximum B-Side Power Down
Leakage Current
100
100
V
OUT = 5.25V
T + − VT−
∆
Input Hysteresis
5.0
5.0
5.0
0.4
22
8
0.4
22
8
0.35
24
6
V
Ω
Ω
V
VT
RD
Maximum Output Impedance
Minimum Output Impedance
Bn (Note 6)
Bn (Note 6)
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: This parameter is guaranteed but not tested, characterized only: RD is the measure of the B-Side output impedance with the output in the HIGH
state.
3
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AC Electrical Characteristics
T
A = +25°C
T
A = 0°C to +70°C
CC = 4.7V − 5.5V
T
A = −40°C to +85°C
Figure
Number
Symbol
Parameter
V
CC = 4.7V − 5.5V
V
V
CC = 4.7V − 5.5V
Units
Min
Max
20.0
20.0
20.0
20.0
Min
Max
20.0
20.0
20.0
20.0
Min
Max
24.0
24.0
24.0
24.0
tPHL
A1- A7 to B1 - B7
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
ns
ns
ns
ns
Figure 1
Figure 2
Figure 3
Figure 3
tPLH
A1- A7 to B1 - B7
B1 - B4 to A1 - A4
B1 - B4 to A1 - A4
Output Enable Time
HD to B1 - B7
tPHL
tPLH
tpEnable
2.0
2.0
20.0
20.0
2.0
2.0
20.0
20.0
2.0
2.0
24.0
24.0
ns
ns
Figure 2
Figure 2
tpDisable
Output Disable Time
HD to B1 - B7
tSKEW
tPLH
tPHL
tr, tf
Output Slew Rate
B1 - B7
Figures
1, 2
0.05
0.40
120
0.05
0.40
120
0.05
0.40
120
V/ns
ns
tRISE and tFALL
Figure 4
(Note 8)
B
1 - B7 (Note 7)
Note 7: Open Drain
Note 8: This parameter is guaranteed but not tested, characterized only.
Note: Pulse Generator for all pulses; Rate ≤ 1.0 MHz; AO ≤ 50Ω; tf ≤ 2.5 ns, tr ≤ 2.5 ns.
Capacitance
Symbol
CIN
CI/O
Parameter
Input Capacitance
I/O Pin Capacitance
Typ
4.0
Units
Conditions
pF
pF
V
CC = OPEN (HD, DIR A5 - A7)
CC = 5.0V
12.0
V
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4
AC Loading and Waveforms
tSLEW measures between 10% to 90% on the tPHL Transition
tSLEW measures between 10% to 90% on the tPLH Transition
FIGURE 1. Port A to B Propagation Delay Waveforms
FIGURE 2. B Output Test Load and Waveforms
FIGURE 3. B to A Direction Test Load and Waveforms for Outputs A1 - A4
FIGURE 4. A to B Direction Test Load and Waveforms for Open Drain B1 - B7
5
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA20
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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相关型号：
74ACT1284SCX_NL
Line Transceiver, 7 Func, 7 Driver, 7 Rcvr, CMOS, PDSO20, 0.300 INCH, MS-013, SOIC-20
FAIRCHILD
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