74ACT138 [STMICROELECTRONICS]
3 TO 8 LINE DECODER (INVERTING); 3至8线译码器（反相）
| 型号： | 74ACT138 |
| 厂家： | 
ST |
| 描述： | 3 TO 8 LINE DECODER (INVERTING) |
| 文件： | 总10页 (文件大小：280K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74ACT138
3 TO 8 LINE DECODER (INVERTING)
■
■
HIGH SPEED: t = 5ns (TYP.) at V = 5V
PD CC
LOW POWER DISSIPATION:
I
= 4µA(MAX.) at T =25°C
CC
A
■
■
■
■
■
■
■
COMPATIBLE WITH TTL OUTPUTS
= 2V (MIN.), V = 0.8V (MAX.)
50Ω TRANSMISSION LINE DRIVING
CAPABILITY
V
IH
IL
DIP
SOP
TSSOP
T & R
SYMMETRICAL OUTPUT IMPEDANCE:
|I | = I = 24mA (MIN)
OH
OL
BALANCED PROPAGATION DELAYS:
ORDER CODES
PACKAGE
t
t
PLH
PHL
TUBE
OPERATING VOLTAGE RANGE:
(OPR) = 4.5V to 5.5V
DIP
SOP
74ACT138B
74ACT138M
V
CC
74ACT138MTR
74ACT138TTR
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138
IMPROVED LATCH-UP IMMUNITY
TSSOP
Three enable inputs are provided to ease cascade
connection and application of address decoders
for memory systems.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
DESCRIPTION
The 74ACT138 is an advanced high-speed CMOS
3 TO 8 LINE DECODER (INVERTING) fabricated
with sub-micron silicon gate and double-layer
2
metal wiring C MOS tecnology.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
If the device is enabled, 3 binary select inputs (A,
B, and C) determine which one of the outputs will
go low. If enable input G1 is held low or either G2A
or G2B is held high, the decoding function is
inhibited and all the 8 outputs go to high.
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 2001
1/10
74ACT138
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL
A, B, C
NAME AND FUNCTION
1, 2, 3
4, 5
6
Address Inputs
G2A, G2B Enable Inputs
G1
Enable Input
Outputs
15, 14, 13,
12, 11, 10, 9,
7
Y0 to Y7
8
GND
Ground (0V)
16
V
Positive Supply Voltage
CC
TRUTH TABLE
INPUTS
OUTPUTS
ENABLE
G2A
SELECT
B
G2B
G1
C
A
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
X
X
H
L
L
L
L
L
L
L
L
X
H
X
L
L
L
L
L
L
L
L
L
X
X
X
L
X
X
X
L
X
X
X
L
H
H
H
L
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
X
X
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
H
H
L
H
H
L
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
H
X : Don’t Care
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
2/10
74ACT138
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
Supply Voltage
-0.5 to +7
V
V
CC
V
DC Input Voltage
-0.5 to V + 0.5
I
CC
V
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
-0.5 to V + 0.5
V
O
CC
I
± 20
± 20
mA
mA
mA
mA
°C
°C
IK
I
OK
I
± 50
O
I
or I
T
DC V
or Ground Current
CC
± 400
CC
GND
Storage Temperature
-65 to +150
300
stg
T
Lead Temperature (10 sec)
L
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
Supply Voltage
4.5 to 5.5
V
V
CC
V
Input Voltage
0 to V
I
CC
V
Output Voltage
0 to V
V
O
CC
T
Operating Temperature
-55 to 125
8
°C
ns/V
op
Input Rise and Fall Time V = 4.5 to 5.5V (note 1)
dt/dv
CC
1) V from 0.8V to 2.0V
IN
3/10
74ACT138
DC SPECIFICATIONS
Test Condition
Value
T
= 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
CC
(V)
Min. Typ. Max. Min. Max. Min. Max.
V
High Level Input
Voltage
4.5
5.5
4.5
5.5
4.5
V
= 0.1 V or
O
2.0
2.0
1.5
1.5
2.0
2.0
2.0
2.0
IH
V
-0.1V
V
V
CC
V
Low Level Input
Voltage
V = 0.1 V or
O
1.5
0.8
0.8
0.8
0.8
0.8
0.8
IL
V
-0.1V
1.5
CC
V
High Level Output
Voltage
I =-50 µA
4.4
5.4
4.49
4.4
5.4
4.4
5.4
3.7
4.7
OH
O
I =-50 µA
5.5
4.5
5.5
4.5
5.5
4.5
5.5
5.49
O
I =-24 mA
3.86
4.86
3.76
4.76
O
I =-24 mA
O
V
Low Level Output
Voltage
I =50 µA
0.001 0.1
0.001 0.1
0.36
0.1
0.1
0.1
0.1
0.5
0.5
OL
O
V
I =50 µA
O
I =24 mA
0.44
0.44
O
I =24 mA
0.36
O
I
Input Leakage Cur-
rent
I
V = V
or GND
CC
5.5
5.5
5.5
± 0.1
± 1
1.5
40
± 1
1.6
80
µA
mA
µA
I
I
Max I /Input
V = V - 2.1V
0.6
CCT
CC
I
CC
I
Quiescent Supply
Current
CC
V = V
or GND
CC
4
I
I
V
= 1.65 V max
= 3.85 V min
75
50
mA
mA
OLD
OLD
Dynamic Output
Current (note 1, 2)
5.5
I
V
OHD
-75
-50
OHD
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, R = 500 Ω, Input t = t = 3ns)
L
L
r
f
Test Condition
Value
-40 to 85°C -55 to 125°C Unit
Min. Typ. Max. Min. Max. Min. Max.
T
= 25°C
Symbol
Parameter
A
V
CC
(V)
t
t
t
t
Propagation Delay
Time A, B, C to Y
PLH PHL
(*)
5.0
5.0
9.0
8.0
10.0
9.0
10.5
9.5
ns
ns
5.0
5.0
t
Propagation Delay
Time G1 to Y
PLH PHL
(*)
(*)
t
Propagation Delay
Time G2A or G2B
to Y
PLH PHL
5.5
8.5
10.0
10.5
ns
5.0
(*) Voltage range is 5.0V ± 0.5V
4/10
74ACT138
CAPACITIVE CHARACTERISTICS
Test Condition
Value
-40 to 85°C -55 to 125°C Unit
T
= 25°C
Symbol
Parameter
A
V
CC
(V)
Min. Typ. Max. Min. Max. Min. Max.
C
Input Capacitance
5.0
4
pF
pF
IN
C
Power Dissipation
Capacitance (note
1)
PD
f
= 10MHz
5.0
60
IN
1) C is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
PD
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
= C x V x f + I /n (per circuit)
PD CC IN CC
CC(opr)
TEST CIRCUIT
C
R
R
= 50pF or equivalent (includes jig and probe capacitance)
L
L
T
= R = 500Ω or equivalent
1
= Z
of pulse generator (typically 50Ω)
OUT
WAVEFORM 1: PROPAGATION DELAYS FOR INVERTING OUTPUTS (f=1MHz; 50% duty cycle)
5/10
74ACT138
WAVEFORM2:PROPAGATIONDELAYSFORNON-INVERTINGOUTPUTS(f=1MHz;50%dutycycle)
6/10
74ACT138
Plastic DIP-16 (0.25) MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
0.51
0.77
TYP.
MAX.
MIN.
0.020
0.030
MAX.
a1
B
b
1.65
0.065
0.5
0.020
0.010
b1
D
E
e
0.25
20
0.787
8.5
2.54
0.335
0.100
0.700
e3
F
17.78
7.1
5.1
0.280
0.201
I
L
3.3
0.130
Z
1.27
0.050
P001C
7/10
74ACT138
SO-16 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
1.75
0.2
MIN.
MAX.
0.068
0.007
0.064
0.018
0.010
A
a1
a2
b
0.1
0.004
1.65
0.46
0.25
0.35
0.19
0.013
0.007
b1
C
0.5
0.019
c1
D
45 (typ.)
9.8
5.8
10
0.385
0.228
0.393
0.244
E
6.2
e
1.27
8.89
0.050
0.350
e3
F
3.8
4.6
0.5
4.0
5.3
0.149
0.181
0.019
0.157
0.208
0.050
0.024
G
L
1.27
0.62
M
S
8 (max.)
P013H
8/10
74ACT138
TSSOP16 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
1.1
MIN.
MAX.
0.433
0.006
0.374
0.0118
0.0079
0.201
0.256
0.176
A
A1
A2
b
0.05
0.85
0.19
0.09
4.9
0.10
0.9
0.15
0.95
0.30
0.20
5.1
0.002
0.335
0.0075
0.0035
0.193
0.246
0.169
0.004
0.354
c
D
5
6.4
0.197
0.252
E
6.25
4.3
6.5
E1
e
4.4
4.48
0.173
0.65 BSC
4o
0.0256 BSC
4o
K
0o
8o
0o
8o
L
0.50
0.60
0.70
0.020
0.024
0.028
A2
A
K
L
b
e
A1
c
E
D
E1
PIN 1 IDENTIFICATION
1
9/10
74ACT138
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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10/10
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