AP22850SH8-7_技术文档

AP22850

10V SINGLE CHANNEL PROGRAMMABLE LOAD SWITCH

Description

Pin Assignments

AP22850 is an integrated P-Channel load switch, which features an

adjustable ramp-up and discharge rate that can be set via an external

capacitor and a resistor, respectively. In addition, it incorporates a

“power good” output to flag when the switch is fully enhanced. The P-

Channel switch has a typical R_DS(ON)of 21mΩ, enabling a current

handling capability of up to 8A.

Top View

Bottom View

SS

1

2

3

4

8

7

6

5

8

7

6

5

1

2

3

4

SS

EN

DIS

PG

EN

VIN

VOUT

VIN

VBIAS

GND

AP22850 is designed to operate from 4.5V to 11V. The near-zero

quiescent supply current makes it ideal for use in battery powered

distribution systems where power consumption is a concern.

W-DFN2020-8

Even as a P-Channel load switch, AP22850 does not require an

external gate pull-up resistor, and consequently, stays true to its

headlining feature of near-zero quiescent current specification. It also

features circuitry to suppress fast input transients (with EN low) from

coupling to VOUT.

Applications

Feature



Integrated Load Switches in Ultrabook PCs

Power Up/Down Sequencing in Ultrabook PCs

Tablets



Near-Zero Quiescent Current

No External Gate Pull-Up Resistor Required

Suppresses Fast Transients on VIN

Notebooks / Netbooks

E-Readers

4.5V to 11V Input Voltage Range

Low Typical R_DS(ON)of 21mΩ

Consumer Electronics

Set-Top Boxes

Adjustable Start-Up and Discharge Rate

Small Form Factor Package W-DFN2020-8

– Footprint of just 4mm²

Industrial Systems

Telecom Systems



Thermally Efficient Package with an Exposed Pad

Case Material: Molded Plastic, “Green” Molding Compound.

UL Flammability Classification Rating 94V-0

Moisture Sensitivity: Level 1 per J-STD-020

Lead-Free Plating (NiPdAu Finish over Copper Leadframe).



e4

Terminals: Solderable per MIL-STD-202, Method 208



Weight: TBD grams (Approximate)

Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)

Halogen and Antimony Free. “Green” Device (Note 3)

Notes:

1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.

2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green"

and Lead-free.

3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and

<1000ppm antimony compounds.

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March 2015

AP22850

Document number: DS36540 Rev. 2 - 2

AP22850

Typical Applications Circuit

VIN

VOUT

R_DIS

C_SS

C_L

R_L

VBIAS

EN

DIS

SS

AP22850

ON

R_PULL-UP

OFF

PG

GND

Pin Descriptions

Pin Name

SS

Pin Number

Function

Soft-Start Adjust

1

2

An external capacitor connected between this pin and VOUT sets the ramp-up time of VOUT

Enable Input

Active high

EN

Input Voltage

Connects to the Source of the P-channel MOSFET

VIN

3, 4

5

GND

VBIAS

PG

Ground

Supply Voltage

Recommended range: 2.5V ≤ VBIAS ≤ 5.5V

6

Power Good

7

Open-drain output to indicate when the P-channel pass switch is fully enhanced

Output Discharge

DIS

8

An external resistor between DIS and VOUT sets the discharge rate of VOUT

Output Voltage

PAD connects to the Drain of the P-channel MOSFET

VOUT

PAD

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AP22850

Document number: DS36540 Rev. 2 - 2

AP22850

Functional Block Diagram

VIN

VOUT

SS

PG

VBIAS

Gate Drive

Power

Good

DIS

EN

GND

Absolute Maximum Ratings (@T_A= +25°C, unless otherwise specified.) (Note 4)

Symbol

V_IN

Parameter

Ratings

Units

V

Input Voltage

Output Voltage

Enable Voltage

12.0

6.0

V

V_OUT

V_EN

V

Bias Voltage

Load Current

6.0

V

V_BIAS

I_L

8.0

A

Maximum Junction Temperature

Storage Temperature

125

°C

W

T_J(max)

T_ST

−55 to +150

0.35

1.8

(Note 5)

(Note 6)

(Note 5)

(Note 6)

Power Dissipation

P_D

300

Thermal Resistance, Junction to Ambient

Thermal Resistance, Junction to Case

°C/W

R_θJA

60

-

5

R_θJC

Notes:

4. Stresses greater than the 'Absolute Maximum Ratings' specified above may cause permanent damage to the device. These are stress ratings only;

functional operation of the device at these or any other conditions exceeding those indicated in this specification is not implied. Device reliability may be

affected by exposure to absolute maximum rating conditions for extended periods of time.

5. For a device surface mounted on minimum recommended pad layout, in still air conditions; the device is measured when operating in a steady state

condition.

6. For a device surface mounted on 25mm by 25mm by 1.6mm FR4 PCB with high coverage of single sided 2oz copper, in still air conditions; the device is

measured when operating in a steady state condition.

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March 2015

AP22850

Document number: DS36540 Rev. 2 - 2

AP22850

Recommended Operating Conditions (@T_A= +25°C, unless otherwise specified.)

Symbol

V_IN

Parameter

Min

4.5

2.5

0

Max

11.0

5.5

Units

V

Input Voltage

V_BIAS

V_EN

Bias Voltage

V

Enable Voltage

5.5

V

Power Good Voltage Range

0

11.0

+85

V

V_PG

Operating Ambient Temperature

−40

°C

T_A

Electrical Characteristics (@T_A= +25°C, V_BIAS= 2.5V – 5.5V, C_IN= 1µF, C_L= 100nF, unless otherwise specified.)

Symbol

Parameters

Conditions

Min

Typ

Max

Unit

-

5.0

3.0

1.0

200

V_IN= 10.0V

V_IN= 8.4V

V_IN= 5.0V

V_INQuiescent Current

nA

I_VIN

_

I_OUT= 0A

Q

V_BIASQuiescent Current

V_INShutdown Current

V_BIASShutdown Current

-

1.0

2.0

200

nA

I_VBIAS

_

V_IN= 12.0V, I_OUT= 0A

V_IN= 12.0V, V_EN= 0V

Q

I_{VIN_SD}

I_{VBIAS_SD}

-

21

23

31

33

V_IN= 10.0V

V_IN= 8.4V

V_IN= 5.0V

Load Switch On-Resistance

mΩ

R_DS(ON)

I_OUT= −1A

EN Input Logic High Voltage

EN Input Logic Low Voltage

EN Input Leakage

-

1.0

-

V

V_{IH_EN}

V_{IL_EN}

-

0.5

100

nA

I_{LEAK_EN}

V_EN= V_BIAS

-

8

11

16

Ω

V_BIAS= 5.0V

V_BIAS= 2.5V

Discharge FET On-Resistance

R_{DS_DIS}

V_EN= 0V, I_DIS= 10mA

11

Power Good Output Low Level

-

0.2

V

V_{OL_PG}

I_{OZ_PG}

I_{OL_PG}= 100µA, V_EN= 0V

V_PG= V_BIAS, V_EN= V_BIAS

Power Good High-Impedance Current

0.05

µA

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March 2015

AP22850

Document number: DS36540 Rev. 2 - 2

AP22850

Switching Characteristics (@T_A= +25°C, V_BIAS= 2.5V – 5.5V, C_IN= 1µF, C_L= 100nF, unless otherwise specified)

Symbol

Parameters

Conditions

Min

Typ

Max

Unit

100

102

104

70

V_IN= 10.0V

V_IN= 8.4V

V_IN= 5.0V

V_IN= 10.0V

V_IN= 8.4V

V_IN= 5.0V

V_IN= 10.0V

V_IN= 8.4V

V_IN= 5.0V

V_IN= 10.0V

V_IN= 8.4V

V_IN= 5.0V

V_IN= 10.0V

V_IN= 8.4V

V_IN= 5.0V

V_IN= 10.0V

V_IN= 8.4V

V_IN= 5.0V

Output Rise Time

-

µs

t_RISE

R_L= 10Ω, C_SS= 10nF

Output Turn-ON Delay Time

Output Fall Time

-

75

µs

t_ON

t_FALL

t_OFF

t_D

R_L= 10Ω, C_SS= 10nF

82

70

R_L= Open, R_DIS= 240Ω,

C_SS= 10nF

71

75

41

R_L= Open, R_DIS= 240Ω,

C_SS= 10nF

Output Turn-OFF Delay Time

Output Start Delay Time

Power Good Delay Time

45

60

12

16

R_L= 10Ω, C_SS= 10nF

22

250

230

205

t_PG

t_ON/t_OFFWaveforms

50%

V_EN

V_OUT

V_PG

t_ON

t_OFF

90%

50%

V_OUT

10%

t_D

t_RISE

t_FALL

50%

t_PG

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March 2015

AP22850

Document number: DS36540 Rev. 2 - 2

AP22850

Typical Performance Characteristics (@T_A= +25°C, VBIAS = 5V, unless otherwise specified.)

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AP22850

Document number: DS36540 Rev. 2 - 2

AP22850

Typical Performance Characteristics (cont.) (@T_A= +25°C, VBIAS = 5V, unless otherwise specified.)

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AP22850

Document number: DS36540 Rev. 2 - 2

AP22850

Typical Performance Characteristics (cont.) (@T_A= +25°C, VBIAS = 5V, unless otherwise specified.)

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March 2015

AP22850

Document number: DS36540 Rev. 2 - 2

AP22850

Application Information

Theory of Operation

The AP22850 is a load switch that can be used to isolate or power-down part of a system in order to reduce power consumption, particularly in

battery-powered devices. The PMOS pass element in AP22850 is turned on when the EN pin is pulled high. This provides a controlled current

source to decrease the voltage on the SS pin to GND, effectively turning on the PMOS pass switch and connecting VOUT to VIN.

During the turn-on phase, once the SS voltage reaches close to GND, the PMOS pass switch is fully enhanced with maximum available

overdrive. Power is deemed to be good and the Power Good (PG) output is pulled high via an external pull-up resistor. The rise-time on VOUT is

controlled by the value of the external capacitor between the SS and VOUT pin.

When EN is pulled low, the switch turns off and isolates VOUT from VIN. In addition, PG is pulled to indicate that the power is no longer good.

The discharge pin keeps VOUT grounded while EN is low. The fall time on VOUT is largely controlled by the value of the discharge resistor and

the capacitance on the output.

Input and Output Voltage

The Input Voltage (VIN) should be between 4.5V and 11V. With the switch is activated, the Output Voltage (VOUT) will be the input voltage

minus the voltage drop across the device.

Enable

The GPIO compatible EN input allows the output current to be switched on and off. A high signal (switch on) should be at least 1V, and the low

signal (switch off) no higher than 0.5V.

This pin should not be left floating. It is advisable to hold EN low when applying or removing power.

VBIAS

The VBIAS input provides a positive power supply to the controller circuitry. It should be set in the range of 2.5V to 5.5V. VBIAS signal is

essential for the device to power up and should be set before the switch is enabled.

Power Good

Power Good is an open-drain output that indicates when the pass switch is enhanced enough to deliver current to the load. PG is high (open-

drain high impedance) when power is deemed good, and low when the power is deemed to not be good.

PG can be pulled up to any voltage to a maximum of 11V, although it is recommended to pull it up to VOUT with a resistor greater than 20kΩ.

The advantage of pulling up PG to VOUT is that when EN is low, VOUT is also grounded. Thus, no power is wasted in the pull-up resistor.

If this feature is not required, then PG pin can be left floating

Input and Output Capacitors

AP22850 does not require any capacitor on VIN for successful operation. In addition, this device has no input-to-output capacitor ratio stipulation

to account for current through the body diode. However, to minimize voltage dip on VIN due to inrush current at start-up, a capacitor can be

place on VIN.

For heavier loads, it is recommended that the VIN and VOUT trace lengths be kept to a minimum. In addition, a bulk capacitor (≥ 10μF) may also

be placed close to the VOUT pin. If using a bulk capacitor on VOUT, it is important to control the inrush current by choosing an appropriate soft-

start time in order to minimize the droop on the input supply.

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March 2015

AP22850

Document number: DS36540 Rev. 2 - 2

AP22850

Application Information (cont.)

Adjustable Slew Rate/Soft-Start

SS pin allows the output ramp time of the switch to be controlled using an external capacitor (C_SS). This timing capacitor is connected between the

SS and VOUT pin. Rise times (in µs) for different values of C_SSand V_INare shown in the table below with V_BIAS= 5.5V.

Rise Time (in μs)

Measured at +25°C using 0805 X7R 10% 50V capacitors, C_L= 100nF, R_DIS= 1K, R_L= 10Ω

V_IN

4.5V

7.0V

9.0V

11.0V

C_SS

1nF

13.6

97.2

955

12.4

99.2

12.0

98.8

11.4

97.9

1253

10nF

100nF

1,075

1,154

Table 1 Timing Capacitors and Rise Times

Adjustable Discharge

When EN goes low, VOUT is discharged to ground through the discharge resistor (R_DIS) on the DIS pin. A value greater than 240Ω is

recommended for R_DIS

.

While the discharge/fall-time on VOUT can be controlled using R_DIS, capacitors on VOUT and SS also contribute to the timing. Higher discharge

resistance increases the RC time constant and hence, the discharge time. Fall times (in µs) for different values of R_DISand V_INare shown in the

table below with V_BIAS= 5.5V.

Fall Time (in µs)

1,206 250mW 1%

Discharge resistor (Ω)

Measured at +25°C, C_L= 100nF, C_SS= 1nF, R_L= open

5V

11V

240

71.8

264.2

1,029

69.5

276.7

1,078

1,000

3,900

Table 2 Discharge Resistors and Output Voltage Fall Time

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March 2015

AP22850

Document number: DS36540 Rev. 2 - 2

AP22850

Board Layout and Thermal Considerations

Due to the high current capacity of the load switch, PCB layout needs to ensure good thermal distribution during operation. The top and bottom of

AP22850EV1, (the evaluation board for AP22850), can be seen below.

Figure 3 PCB Copper Layout & Silk Screen – Top

Figure 4 PCB Copper Layout & Silk Screen – Bottom

Thermal vias are used directly underneath the chip to help distribute the heat from the device. The ground plane on the underside of the board

effectively acts as a large heatsink. The widths of the tracks carrying VIN and VOUT are kept wide. Vias are also distributed around the board to

aid thermal conduction and to ensure a consistent potential, particularly around the ground connections of the capacitors. All capacitors used are

located as close as possible to the AP22850 to minimize any parasitic effects.

The maximum junction temperature of the AP22850 is +125°C. To ensure that this is not exceeded, the following equation can be used to give an

approximation of junction temperature. Temperature readings taken with a thermal camera can also give a good approximation of power

dissipation with the use of this equation. The board layout has a major influence on the parameter _ꢀꢁ.

ꢂ ꢃꢄꢂ ꢅ ꢆ _ꢀꢁꢄꢇꢄꢈ_ꢉꢊ

ꢀ

ꢁ

Where,

ꢂ

ꢁ

= Junction Temperature (°C)

= Ambient Temperature (°C)

ꢀ

_ꢀꢁ= Junction to Ambient Thermal Impedance (°C/W)

ꢈ_ꢉ= Power Dissipation (voltage drop across device ꢇ output current) (W)

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March 2015

AP22850

Document number: DS36540 Rev. 2 - 2

AP22850

Ordering Information

AP22850 XYZ-7

Package

Packing

SH8 : W-DFN2020-8

-7 : Tape and Reel

7” Tape and Reel

Part Number Suffix

-7

Packaging

(Note 7)

Package

Code

Part Number

Quantity

AP22850SH8-7

SH8

W-DFN2020-8

3,000/Tape & Reel

Note:

7. Pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which can be found on our website at

http://www.diodes.com/datasheets/ap02001.pdf.

Marking Information

W-DFN2020-8

( Top View )

XX : Identification code

Y : Year 0~9

W : Week : A~Z : 1~26 week;

a~z : 27~52 week; z represents

52 and 53 week

XX

Y W X

X : A~Z : Internal Code

Device

Package

Identification Code

AP22850SH8-7

W-DFN2020-8

WC

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March 2015

AP22850

Document number: DS36540 Rev. 2 - 2

AP22850

Package Outline Dimensions (All dimensions in mm)

Please see AP02002 at http://www.diodes.com/datasheets/ap02002.pdf for the latest version.

A1

A

W-DFN2020-8

Type C

A3

Seating Plane

Dim Min

Max Typ

A

A1

A3

b

D

D2

E

E2

e

K

0.770 0.830 0.800

D

D2

0

-

0.05 0.02

0.152

-

D2/2

0.20 0.30 0.25

1.950 2.075 2.000

1.50 1.70 1.60

1.950 2.075 2.000

0.80 1.00 0.90

K

Pin #1 ID

R

E2/2

0

.

2

E

0

E2

0

-

0.50

0.125

L

0.240 0.340 0.290

All Dimensions in mm

L

e

b

Suggested Pad Layout

Please see AP02001 at http://www.diodes.com/datasheets/ap02001.pdf for the latest version.

X2

G

Y

Dimensions Value (in mm)

C

G

G1

X

X1

X2

Y

Y1

Y2

0.500

0.200

0.210

0.300

1.600

1.750

0.490

0.900

2.300

G1

Y2

Y1

X1

X

C

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AP22850

Document number: DS36540 Rev. 2 - 2

AP22850

IMPORTANT NOTICE

DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT,

INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

(AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION).

Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes

without further notice to this document and any product described herein. Diodes Incorporated does not assume any liability arising out of the

application or use of this document or any product described herein; neither does Diodes Incorporated convey any license under its patent or

trademark rights, nor the rights of others. Any Customer or user of this document or products described herein in such applications shall assume

all risks of such use and will agree to hold Diodes Incorporated and all the companies whose products are represented on Diodes Incorporated

website, harmless against all damages.

Diodes Incorporated does not warrant or accept any liability whatsoever in respect of any products purchased through unauthorized sales channel.

Should Customers purchase or use Diodes Incorporated products for any unintended or unauthorized application, Customers shall indemnify and

hold Diodes Incorporated and its representatives harmless against all claims, damages, expenses, and attorney fees arising out of, directly or

indirectly, any claim of personal injury or death associated with such unintended or unauthorized application.

Products described herein may be covered by one or more United States, international or foreign patents pending. Product names and markings

noted herein may also be covered by one or more United States, international or foreign trademarks.

This document is written in English but may be translated into multiple languages for reference. Only the English version of this document is the

final and determinative format released by Diodes Incorporated.

LIFE SUPPORT

Diodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems without the express

written approval of the Chief Executive Officer of Diodes Incorporated. As used herein:

A. Life support devices or systems are devices or systems which:

1. are intended to implant into the body, or

2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the

labeling can be reasonably expected to result in significant injury to the user.

B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the

failure of the life support device or to affect its safety or effectiveness.

Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or systems, and

acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any

use of Diodes Incorporated products in such safety-critical, life support devices or systems, notwithstanding any devices- or systems-related

information or support that may be provided by Diodes Incorporated. Further, Customers must fully indemnify Diodes Incorporated and its

representatives against any damages arising out of the use of Diodes Incorporated products in such safety-critical, life support devices or systems.

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March 2015

AP22850

Document number: DS36540 Rev. 2 - 2


型号：	AP22850SH8-7
厂家：	DIODES INCORPORATED
描述：	Buffer/Inverter Based Peripheral Driver, 驱动光电二极管接口集成电路
文件：	总14页 (文件大小：1029K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AP22850SH8-7 [DIODES]

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