IMISM530ATB [CYPRESS]
Processor Specific Clock Generator, 120MHz, CMOS, PDSO20, TSSOP-20;
| 型号： | IMISM530ATB |
| 厂家： | 
CYPRESS |
| 描述： | Processor Specific Clock Generator, 120MHz, CMOS, PDSO20, TSSOP-20 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总16页 (文件大小：162K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
+/+
SM530
Approved Product
Low EMI Spectrum Spread Clock
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
Reduces Systemic EMI.
•
•
•
•
•
•
•
•
Desktop/Laptop Computer
Modems
Modulates external source clock.
3 - 5 Volt power supply.
Scanners, Printers, Copiers, Fax Machines, MFP’s
Disk and CD-ROM Drives
Automotive and EmbeddedSystems
Networking, LAN/WAN
14 to 120 MHz.operating frequency range
Output is multiplied or divided by 1, 2 or 4.
Digitally controlled modulation.
TTL/CMOS compatible outputs.
Center and Down Spread modulation.
Compliant with all major CISC, RISC and
DSP processors.
Digital Cameras, Games
LCD displays
BENEFITS
•
•
•
•
Low short term jitter.
•
•
•
•
•
Time to Market
Synchronous output enable.
Lower cost of compliance
Power down mode for low current operation
Available in 20 pin SSOP and TSSOP
packages.
Programmable EMI reduction
No degradation in Rise/Fall times
Lower component and PCB layer count
GENERAL DESCRIPTION
The IMI SM530 is a Spectrum Spread Clock Modulator designed for the purpose of reducing the Electro- Magnetic
Interference (EMI) found in today’s high speed digital systems. The SM530 is well suited for a wide range of digital
system applications that require a reduction of radiated energy. This unwanted radiated energy is usually found in
the odd harmonics of digital system clocks. By increasing the bandwidth of the digital clock, measured EMI at the
fundamental and harmonic frequencies is greatly reduced. This reduction in radiated energy can significantly
reduce the cost of complying with regulatory requirements and time to market, without degrading clock and timing
signals.
The IMI SM530 is extremely versatile and flexible in that program control is available for each of the operating
modes. Program control is provided for Input Frequency, Output Frequency Multiplication, Output Bandwidth,
Center/Down Spread of Fout, Modulation ON/OFF and Fout state during Power Down Mode
Depending on the range of operation, the output clock, Fout, can be a multiple (1, 2, 4) or a fraction (1, 1/2, 1/4) of
the input frequency. The SM530 can synchronously stop the modulated output at the low logic level. The power-
down mode adds the flexibility of operating in a completely static mode for reduced standby current and simplified
system board testing.
There are many benefits to using the SM530 Low EMI Clock Modulator. The most important benefit is reducing
the amount of clock related EMI by as much as 12 - 18 dB., depending on the application. Refer to SM532
datasheet for the 16 pin SOIC version, which only supports Center-Spread operation.
International Microcircuits,Inc.
525 Los Coches St., Milpitas, 95035 408-263-6300, FAX 408-263-6571
http:/www.imicorp.com
1/5/99
Rev. 1.6
Page 1 of 16
+/+
SM530
Approved Product
Low EMI Spectrum Spread Clock
D_C STOP SSON
10
4
5
LF
7
S2
14
S3
11
R0
17
R1
16
SSCG and
Power
Down
Control
Phase
Detector
VCO
OSCin
Divide
by R
1
OSCout
REFout
Fout
20
15
2
Divide
by N
Divide by 1, 2, 4
6
9
S0 S1
Figure 1. Block Diagram
ORDERING INFORMATION
Operating
Temperature Range
Part No.
Package
IMISM530AYB
IMISM530ATB
20 pin SSOP
00C to 700C
00C to 700C
20 pin TSSOP
Marking Example:
IMI
SM530AYB
Date Code, Lot#
IMISM530AYB
Flow
B = Commercial
Package
Y = SSOP
T = TSSOP
Revisions
IMI Device Number
International Microcircuits,Inc.
1/5/99
525 Los Coches St., Milpitas, 95035 408-263-6300, FAX 408-263-6571
http:/www.imicorp.com
Rev. 1.6
Page 2 of 16
+/+
SM530
Approved Product
Low EMI Spectrum Spread Clock
1
2
20
19
18
17
16
15
14
13
12
11
OSCin
OSCout
AVDD
D_C
REFout.
OVDD
OVSS
R0
3
4
5
R1
STOP
6
Fout
S2
S0
LF
7
AVSS
8
DVSS
DVDD
S3
9
S1
SSON
10
Figure 2. SM530, SSOP/TSSOP Package Pin Assignment
Pin Descriptions
Pin No. Pin Name
I/O
TYPE
Description
1,2
OSCin,
OSCout
I/O
CMOS
Pins form an on-chip reference oscillator when connected to terminals of
an external parallel resonant crystal. OSCin may be connected to a
TTL/CMOS external clock source. AC coupling may be required. If
OSCin is connected to an external clock other than crystal, leave
OSCout (pin 2) unconnected. The input frequency range is 14 to 120
Mhz @ 5.0 VDC
3
4
AVDD
D_C
Power
I
Power
TTL
Analog circuit positive power supply.
Input selection pin used to determine the center frequency position of
modulated Fout (pin 15). Pin 4 has internal pull-down resistor.
D_C = 0: Down Spread.
D_C = 1: Center Spread.
5
STOP
I
I
TTL
TTL
When = 1, synchronously stops Fout clock at a logic low state.
Pin 5 has internal pull-down resistor.
Input control used to select the frequency multiplication at Fout, relative
to the reference clock. See table on page 5.
6,9
S0, S1
S0 has internal pull-down, S1 has internal pull-up.
Single ended tri-state output of the phase detector. A two pole passive
loop filter is connected to LF. See table on page 7 for proper values.
Analog circuit ground.
Input control pin used to enable modulation at the Fout pin.
SSON = 0 = Modulation ON, SSON = 1 = Modulation OFF.
Has internal pull-down.
7
LF
O
Analog
8
10
AVSS
SSON
Ground
I
Ground
TTL
11, 14
12
S3, S2
DVDD
I
TTL
Input control pins, set the amount of modulation at Fout. See table on
page 6 for settings. S2 has internal pull-up, S3 has internal pull-down.
Digital positive power supply. Should be kept separate from analog
power for best performance.
Power
Power
13
15
16, 17
DVSS
Fout
R1, R0
Ground
Ground
TTL
TTL
Digital circuit ground.
Modulated clock output.
Input pins control the input frequency range as described in table on
page 5. R0 and R1 have internal pull-up.
O
I
18
19
20
OVSS
OVDD
REFout
Ground
Power
O
Ground
Power
TTL
Oscillator circuit ground. Can be common to DVSS.
Oscillator circuit positive power supply. Can be common to DVDD.
Buffered output of the crystal or external clock input. (Unmodulated)
Table 1.
International Microcircuits,Inc.
1/5/99
525 Los Coches St., Milpitas, 95035 408-263-6300, FAX 408-263-6571
http:/www.imicorp.com
Rev. 1.6
Page 3 of 16
+/+
SM530
Approved Product
Low EMI Spectrum Spread Clock
ABSOLUTE MAXIMUM RATINGS
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields;
however, precautions should be taken to avoid application of any voltage higher than the absolute maximum rated
voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range, VSS < ( Vin or
Vout) < VDD. All digital inputs are tied high or low internally. Refers to electrical specifications for operating
supply range.
Item
Supply Voltage
Symbol
VDD
VIRvss
VORvss
∆Vpp
Min.
0
-0.3
Max.
6.0
VDD +0.3
VDD +0.3
+100
+100
+ 70
+ 150
Units
VDC
VDC
VDC
mv
Input, relative to VSS
Output, relative to VSS
AVDD relative to DVDD
AVSS relative to DVSS
Temperature, Operating
Temperature, Storage
-0.3
-100
-100
0
mv
∆Vss
TOP
TST
0 C
- 65
0 C
Table 2.
Electrical Characteristics
Characteristic
Symbol
Min.
Typ.
-
-
-
-
-
-
-
-
Max.
0.8
-
100
100
0.4
-
0.4
-
-
Units
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
VIL
-
Vdc
Vdc
µA
VIH
2.0
IIL
-
IIH
-
µA
Output Low Voltage IOL= 8mA, VDD = 5V
Output High Voltage IOH = 8mA, VDD = 5V
Output Low Voltage IOL= 5mA, VDD = 3.3V
Output High Voltage IOH = 3mA,VDD = 3.3V
Input Capacitance (Pin-1)
VOL
VOH
VOL
VOH
Cin1
-
Vdc
Vdc
Vdc
Vdc
pf
VDD-1.0
-
2.4
-
3
Output Capacitance (Pin-2)
Cin2
-
5
-
pf
Pull-Up Resistor values (pins 9, 14, 16 and 17)
Pull-Down resistor values (pins 4, 5, 6, 10, 11)
Tri-State Leakage Current (pins 7, 15 and 20)
Static Supply Current (Power Down mode)
5 Volt Dynamic Supply Current
Rpu
Rpd
IOZ
IDD
ICC
100K
150K
-
-
-
167K
250K
5.0
-
300K
350K
-
250
30
Ohms
Ohms
µA
µA
ma
25
(Operating mode)
3 Volt Dynamic Supply Current
ICC
-
18
20
ma
(Operating mode)
Short Circuit Current (Fout)
ISC
-
-
30
ma
Test measurements performed at VDD = 3.3V +/-5% and 5V +/-10%, TA = 0°C to 70°C
Table 3.
International Microcircuits,Inc.
1/5/99
525 Los Coches St., Milpitas, 95035 408-263-6300, FAX 408-263-6571
http:/www.imicorp.com
Rev. 1.6
Page 4 of 16
+/+
SM530
Approved Product
Low EMI Spectrum Spread Clock
Timing Characteristics
Characteristic
Symbol
tTLH
tTHL
tTLH
tTHL
tTLH
tTHL
tTLH
tTHL
TsymF1
tj1s
Min
3.3
2.1
0.7
0.6
4.8
2.9
1.6
1.1
45
Typ
3.5
Max
3.8
2.5
0.8
0.8
5.4
3.4
1.9
1.5
55
Units
ns
Output Rise Time Measured at 10% - 90% @ 5 VDC
Output Fall Time Measured at 10% - 90% @ 5 VDC
Output Rise Time Measured at 0.8V - 2.0V @ 5 VDC
Output Fall Time Measured at 0.8V - 2.0 V @ 5 VDC
Output Rise Time Measured at 10% - 90% @ 3.3 VDC
Output Fall Time Measured at 10% - 90% @ 3.3 VDC
Output Rise Time Measured at 0.8V - 2.0V @ 3.3 VDC
Output Fall Time Measured at 0.8V - 2.0 V @ 3.3 VDC
Output Duty Cycle
2.3
ns
0.75
0.7
ns
ns
5.0
ns
3.2
ns
1.75
1.3
ns
ns
50
%
Peak-to Peak Jitter One Sigma (SSON = 1)
-
250
500
ps
Measurements performed at VDD = 3.3V +/-5% and 5V +/-10%, TA = 0°C to 70°C, CL = 15pF, Fout = 50.0 MHz.
Table 4.
FREQUENCY SELECTION TABLE
The following table provides the necessary information for setting the control lines for proper operation of the
SM530 and for any frequency within its operating range. Note that the table includes operating frequencies at 3.3
and 5.0 VDC. The 3.3 VDC columns are lower in frequency than the 5.0 VDC operation due to the characteristics
of the VCO.
VDD = 5 Volts +/- 10%
VDD = 3.3 Volts +/- 5%
Fin (Range)
(MHz)
Fout/ Fout (Range) Multiplier Input Range Fin (Range) Fout/ Fout (Range)
Fin
X
Note
(MHz)
MIN
Settings
Settings
(MHz)
MIN MAX
See
14
14
14
Fin
X
Note
1
2
4
(MHz)
MIN
MIN
MAX
MAX
S1
0
S0
R1
X
0
R0
X
1
MAX
See
30
30
0
1
0
1
14
14
14
1
2
4
14
28
56
30
60
120
0
22.5
22.5
22.5
14
28
56
22.5
45
90
1
0
0
1
1
30
1
30
30
30
60
60
60
0.5
1
2
15
30
60
30
60
120
0
1
1
1
0
1
1
1
1
0
0
0
25
25
25
45
45
45
0.5
1
2
12.5
25
50
22.5
45
90
60
60
60
120
120
120
0.25
0.5
1
15
30
60
30
60
120
0
1
1
1
0
1
1
1
1
1
1
1
50
50
50
90
90
90
0.25
0.5
1
12.5
25
50
22.5
45
90
Note: Selects Power Down state, see table 7 below. X = don’t care condition.
Table 5. Frequency Selection Table
International Microcircuits,Inc.
1/5/99
525 Los Coches St., Milpitas, 95035 408-263-6300, FAX 408-263-6571
http:/www.imicorp.com
Rev. 1.6
Page 5 of 16
+/+
SM530
Approved Product
Low EMI Spectrum Spread Clock
MODULATION AND POWER DOWN SELECTIONS
The bandwidth of the modulation applied to Fout is controlled by two input control lines, S2 and S3. Also, S2 and
S3 control the state the SM530 will go to when the Power Down mode is selected. The Power Down mode is
selected when both S0 and S1 are set to a logic state 0. Refer to the tables below for the proper selection of
Modulation Bandwidth and Power Down state.
Modulation Selection Table
Modulation
Settings\
D_C = 0
Down Spread
D_C = 1
Center Spread
Total Bandwidth
1.25 %
S3
S2
Low
High
Low
High
0
0
1
1
0
1
0
1
98.75 %
97.50 %
95.00 %
90.00 %
100 %
100 %
100 %
100 %
99.375 %
98.75 %
97.50 %
95.00 %
100.625 %
101.25 %
102.50 %
105.00 %
2.50 %
5.00 %
10.0 %
Table 6. Modulation Selection Table
Power Down Selection Table
Fout State
Factory Test
S0
0
S1
0
S2
0
S3
1
Hi-Z
0
0
0
0
0
1
0
1
0
1
0
0
1
0
Table 7. Power Down Selection Table
Note:
The STOP and POWER DOWN functions are two separate operations. Selecting STOP does not place the
SM530 in the power down mode. POWER DOWN is selected by setting S0 = 0 and S1 = 0.
International Microcircuits,Inc.
525 Los Coches St., Milpitas, 95035 408-263-6300, FAX 408-263-6571
http:/www.imicorp.com
1/5/99
Rev. 1.6
Page 6 of 16
+/+
SM530
Approved Product
Low EMI Spectrum Spread Clock
Loop Filters
The SM530 requires an external loop filter to provide the proper operation and modulation profile for a given input
frequency. The loop filter is connected to pin 7 (LF) of the SM530 and is a typical 2 pole low pass filter. Since the
SM530 operates over such a wide range of frequencies, the loop filter will change depending on the frequency of
operation. The following loop filter values are recommended for best performance and modulation profile at 3.0
volts and 5.0 volts VDD. Operating voltage is measured at the VDD pin of the SM530.
Notice that the selection of Loop Filter values only depends on the input frequency and VDD voltage, and
does not depend on the R and S settings.
LF #1
LF #2
LF #3
LF
LF
LF
R1
R1
R1
1 K ohm
1.5 K ohm
2 K ohm
C7
C7
C7
1,000 pF
680 pF
390 pF
C6
C6
C6
10,000 pF
6,800 pF
3,900 pF
Figure 3. Recommended Loop Filter
Recommended Loop Filter Values
Input Frequency
Input
Range
Low
Middle
High
VDD +/-5%
Loop
Filter #
Range (MHz)
14.0 to 22.5
25.0 to 45.0
50.0 to 90.0
C6 (pF)
10,000
10,000
10,000
C7 (pF)
R1 (KΩ)
1.0
3.3
3.3
3.3
1,000
1,000
1,000
1
1
1
1.0
1.0
Input
Range
Low
Low
VDD +/-10%
Input Frequency
Range (MHz)
Loop
Filter #
C6 (pF)
10,000
6,800
C7 (pF)
1,000
680
R1 (KΩ)
1.0
5.0
5.0
14.0 to 19.9
20.0 to 24.9
1
2
1.5
5.0
25.0 to 29.9
2.0
3,900
390
3
Low
5.0
5.0
5.0
30.0 to 39.9
40.0 to 49.9
50.0 to 59.9
1.0
1.5
2.0
10,000
6,800
3,900
1,000
680
390
1
2
3
Middle
Middle
Middle
5.0
5.0
5.0
60.0 to 79.9
80.0 to 99.9
100.0 to 120.0
1.0
1.5
2.0
10,000
6,800
3,900
1,000
680
390
1
2
3
High
High
High
Table 8.
The component values listed in Table 8 are recommended values using commonly manufactured components.
Note that there are actually 3 different sets of loop filter values. Due to the VCO characteristics, the table is
divided in to 3 volt operation and 5 volt operation. Referring to the table above, it is apparent that one set of loop
filter values is all that is needed in the 3 volt operation. In the 5 volt operation, each input operating range is
divided into 3 sections which require a different loop filter for optimal performance. The best loop filter for any
application is the one that, provides the required EMI reduction, maintains system integrity, has a modulation
profile shown on page 8 and uses commonly available components.
International Microcircuits,Inc.
525 Los Coches St., Milpitas, 95035 408-263-6300, FAX 408-263-6571
http:/www.imicorp.com
1/5/99
Rev. 1.6
Page 7 of 16
+/+
SM530
Approved Product
Low EMI Spectrum Spread Clock
SSCG Modulation Profile
The modulation rate of the SM530 within any range is typically 20 - 40 kHz. With the correct loop filter connected
to pin 7, the following profile will provide the best EMI reduction. This profile can be seen on a Time Domain
Fmax
50.625
50.468
+1.25%
50.312
50.156
Fcenter
2.5%
50.000
49.844
49.687
49.531
49.375
-1.25%
Fmin
15
0
5
10
20
25
30
35
Time (microseconds)
Analyzer.
Figure 4. Modulation Profile
THEORY OF OPERATION
The SM530 is a Phase Lock Loop (PLL) type clock generator using Direct Digital Synthesis (DDS). By precisely
controlling the bandwidth of the output clock, the SM530 becomes a Low EMI clock generator. The theory and
detailed operation of the SM530 will be discussed in the following sections.
EMI
All digital clocks generate unwanted energy in their harmonics. Conventional digital clocks are square waves with
a duty cycle that is very close to 50 %. Because of the 50/50 duty cycle, digital clocks generate most of their
harmonic energy in the odd harmonics, i.e.; 3rd, 5th, 7th etc. It is possible to reduce the amount of energy contained
in the fundamental and harmonics by increasing the bandwidth of the fundamental clock frequency. Conventional
digital clocks have a very high Q factor, which means that all of the energy at that frequency is concentrated in a
very narrow bandwidth, consequently, higher energy peaks. Regulatory agencies test electronic equipment by the
amount of peak energy radiated from the equipment. By reducing the peak energy at the fundamental and
harmonic frequencies, the equipment under test is able to satisfy agency requirements for Electro-Magnetic
Interference (EMI). Conventional methods of reducing EMI have been to use shielding, filtering, multi-layer PCB’s
etc. The SM530 uses the approach of reducing the peak energy in the clock by increasing the clock bandwidth,
and lowering the Q.
International Microcircuits,Inc.
525 Los Coches St., Milpitas, 95035 408-263-6300, FAX 408-263-6571
http:/www.imicorp.com
1/5/99
Rev. 1.6
Page 8 of 16
+/+
SM530
Approved Product
Low EMI Spectrum Spread Clock
SSCG
SSCG uses a patented technology of modulating the clock over a very narrow bandwidth and controlled rate of
change, both peak and cycle to cycle. The SM530 takes a narrow band digital reference clock in the range of 14 -
120 MHz and produces a clock that sweeps between a controlled start and stop frequency and precise rate of
change. The bandwidth of the output clock is programmable. Using two control lines on the SM530, the
bandwidth of the modulated clock can be controlled over four descrete settings, 1.25, 2.50, 5.0 and 10%. To
understand what happens to an SSCG clock, consider that we have a 50 MHz clock with a 50 % duty cycle. From
a 50 MHz clock we know the following;
Clock Frequency = Fc = 50 MHz.
Clock Period = Tc = 1/50 MHz = 20 ns.
50 %
50 %
Tc = 20 ns.
Figure 5. Unmodulated Clock
Consider that this 50 MHz clock is applied to the OSCin input of the SM530, either as an externally driven clock or
as the result of a parallel resonant crystal connected to pins 1 and 2 of the SM530. Also consider that the SM530
is programmed for the following operation;
Range (R0, R1) =
Multiplier (S0, S1) =
D_C =
SSON =
% Modulation (S2, S3) =
0, 1
0, 1
1
1
1, 0
Mid Range
X1
Center Spread
Modulation is OFF
2.50 % Spread
International Microcircuits,Inc.
525 Los Coches St., Milpitas, 95035 408-263-6300, FAX 408-263-6571
http:/www.imicorp.com
1/5/99
Rev. 1.6
Page 9 of 16
+/+
SM530
Low EMI Spectrum Spread Clock
50.00MHz
Approved Product
Center
49.375 MHz
min.
50.625 MH
max.
From the above parameters, the output clock at Fout will be 50.625 MHz.
With modulation turned off, the frequency of Fout will always rest at the high
end of the programmed spectrum. In this case, +1.25 % of 50 MHz is .625
MHz, equals 50.625 MHz.
Modulation
Off.
When modulation is turned ON, the clock at Fout begins sweeping downward
to the minimum extreme of -1.25 % of 50 MHz which is 50 MHz - .625 MHz =
49.375 MHz. When the clock reaches 49.375, the SM530 begins sweeping
back up to the maximum extreme of 50.625 MHz. If we were to look at this
clock on a spectrum analyzer we would see the following picture. Keep in
mind that this is a drawing of a perfect clock with no noise.
We see that the original 50 MHz reference clock is at the center Frequency,
Cf, and the minimum and maximum extremes are positioned symmetrically
about the center frequency. This type of modulation is called Center-
Spread. Diagram 6 illustrates this as it is seen on a spectrum analyzer.
Note that when modulation is turned off, the Fout clock is at the maximum
extreme of the bandwidth.
Figure 6.
Diagram 7 below shows our 50 MHz clock as it would be seen on an oscilloscope. The top trace is the non-
modulated reference clock, or the REFout clock at pin 20. The bottom trace is the modulated clock at pin 15.
From this comparison chart you can see that the frequency is decreasing and the period of each successive clock
is increasing. The Tc measurements on the left and right of the bottom trace indicate the period of the clock as it
moves from the center frequency at 50 Mhz and the minimum frequency at 49.375 MHz. extremes of the clock.
Intermediate clock changes are small and accumulate to achieve the total period deviation. The reverse of this
diagram would show the clock period gettting smaller as the frequency increases.
Tc = 20.00 ns.
Tc = 20.253 ns.
Figure 7. Period Comparison Chart
There are certain cases where center spread modulation is not applicable. If the maximum design frequency of
the intended application is 50 MHz and becomes unstable above 50 MHz, then increasing the clock to 50.625 MHz
might cause unwanted system problems.
To accommodate this situation, the SM530 has an operating mode where the maximum Fout frequency never
exceeds the reference frequency, not including any multiplier that might be applied. This type of modulation is
called Down Spread. The effective center frequency of the Fout clock is shifted down by one-half the amount of
the applied modulation.
International Microcircuits,Inc.
525 Los Coches St., Milpitas, 95035 408-263-6300, FAX 408-263-6571
http:/www.imicorp.com
1/5/99
Rev. 1.6
Page 10 of 16
+/+
SM530
Approved Product
Low EMI Spectrum Spread Clock
If the amount of clock spread is set for 2.50%, the effective center frequency of Fout is now 1.25 % less than 50
MHz or 49.375 MHz, when modulation is turned on. When modulation is turned off, the Fout frequency will go to
50.0 MHz, since this is the maximum extreme of the applied modulation settings. The one drawback to down
spread modulation is that the effective center frequency of the clock is, in this case, 1.25 % slower, which means
that the performance of the system may be 1.25 % slower.
Using the above operating parameters for the SM530 and selecting Down Spread, the operating bandwidth will be
as follows;
Range (R0, R1) =
Multiplier (S0, S1) =
D_C =
SSON =
% Modulation (S2, S3) = 1, 0
0, 1
0, 1
0
Mid Range
X1
Down Spread
Modulation is ON
2.50 % Spread
0
To calculate the frequency extremes for these conditions in Down Spread mode, first determine the effective
center frequency, Cf. In this case Cf is;
Cf = OSCin - (OSCin X % Spread)
Cf = 50 MHz - (50 MHz X .0125)
Cf = 50 MHz - 0.625 MHz
Cf = 49.375 MHz
With the effective center frequency at 49.375 MHz, we can now determine the minimum and maximum extremes.
Fmax = Cf + (Cf X % Spread)
Fmax = 49.375 + (49.375 X .0125)
Fmax = 49.375 + .617
Fmin = Cf - (Cf X % Spread)
Fmin = 49.375 - (49.375 X .0125)
Fmin = 49.375 - .617
Fmax = 49.99 MHz
Fmin = 48.758 MHz
Another way of calculating the bandwidth in the Down Spread mode is to use the OSCin frequency as the starting
point and multiplying the % Spread by 2. This assumes that the multiplier is 1. If the multiplier is 2, then you
would use 2 times the OSCin in the formula.
Fmax = OSCin
Fmin = OSCin - (OSCin X (2 X % Spread))
Fmin = 50 MHz - (50 X (2 X .0125))
Fmin = 50 - 1.25
Fmin = 48.75 MHz
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49.375 MHz
center
This is illustrated in the diagram to the right. You can see that the effective
center frequency is 49.375 MHz and the min and max extremes are 1.25
% on either side of the center. Or using the second approach, the OSCin
frequency is the max frequency and the min frequency is 2.5 % down from
the reference.
48.75 MHz
min
50.00 MHz
max
Looking at diagram 8, you will note that the peak amplitude of the 50 MHz
non-modulated clock is higher than the wideband modulated clock. This
difference in peak amplitudes between modulated and unmodulated
clocks is the reason why SSCG clocks are so effective in digital systems.
This and the previous illustrations refer to the fundamental frequency of a
clock. A very important characteristic of the SSCG clock is that the
bandwidth of the harmonics is multiplied by the harmonic number. In other
words, if the bandwidth of a 50 MHz clock is 1.35 MHz, the bandwidth of
the 3rd harmonic will be 3 times 1.35, or 4.05 MHz. The amount of
bandwidth is relative to the amount of peak energy in the clock.
Consequently, the wider the bandwidth, the greater the energy reduction of
the clock.
Figure 8.
Most applications will not have a problem meeting agency specifications at the fundamental frequency. It is the
higher harmonics that usually cause the most problems. With an SSCG clock, the bandwidth and peak energy
reduction increases with the harmonic number. Consider that the 11th harmonic of our 50 MHz clock is 550 MHz.
With a total spread of 1.35 MHz at 50 MHz, the spread at the 11th harmonic would be 14.85 MHz which greatly
reduces the peak energy content. It is typical to see as much as 12 to 18 dB. of reduction at the higher
harmonics, due to a modulated clock.
Referring to diagram 6 on page 10 and diagram 8 above, you can see that the peak amplitude of the non-
modulated clock is much higher than the peak amplitude of the modulated clock. This is the reason the SM530 is
used for EMI reduction. The amount of EMI reduction is dependent on the application. The difference in the peak
energy of the modulated clock and the non-modulated clock in typical applications will see a 2 - 3 db. reduction at
the fundamental and as much as 8 - 10 db. reduction at the intermediate harmonics, 3rd, 5th, 7th etc. At the higher
harmonics, it is quite possible to reduce the peak harmonic energy, compared to the unmodulated clock, by as
much as 12 to 18 db.
The dB reduction for a give frequency and spread can be calculated using a simple formula. This formula is only
helpful in determining a relative dB reduction for a given application. This formula assumes an ideal clock with
50% duty cycle and therfore only predicts the EMI reduction of even harmonics. Other circumstances such as
non-ideal clock and noise will affect the actual dB reduction. The formula is as follows;
dB = 6.5 + 9(Log10(F)) + 9(Log10(P))
Where; F = Frequency in Mhz, P = total % spread (2.5% = .025)
Using a 50 Mhz clock with a 2.5% spread, the theoretical dB reduction would be;
db @ 50 Mhz (Fund) = 6.5 + 15.29 - 14.42 = 7.37
dB @ 150 Mhz (3rd) = 6.5 + 19.58 - 14.42 = 11.66
dB @ 550 Mhz (11th) = 6.5 + 24.66 - 14.42 = 16.74
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Modulation Profile
The SM530 moves from max. to min. frequencies of its bandwidth at a pre-determined rate and profile. The
modulation frequency is determined by the input frequency and an internal divider. All 3 operating ranges
modulate the Fout clock at from 20 to 40 kHz. The three operating ranges are 14 - 30 MHz, 30 - 60 MHz and 60
to 120 MHz. If OSCin = 15 MHz, the modulation rate is 20 kHz. If OSCin is 60 MHz, in mid-range, the modulation
rate would be 40 kHz. To provide the proper modulation rate the input reference frequency is divided by a fixed
number in each range. The input reference frequency is divided by 750 in Low Range, 1500 in Mid Range and
3000 in the High Range. From these numbers, the modulation rate can be determined for any input frequency.
Example:
OSCin = 45.378 MHz, Input Range = Mid, Input divisor = 1500
Fmod = OSCin /1500
Fmod = 30.252 kHz
If you have a clock frequency that was on the boundary of the Mid-range and the High range of operation, the
choice of selecting which range to use would be determined by which modulation rate is desired. If you choose
the Mid-range, the modulation rate would be 40 kHz, while choosing the High range would yield a 20 kHz
modulation rate. There is some operational overlap between ranges, such that 58 MHz in the Mid-Range would
give the same results as 58 MHz in the High-Range, except for the modulation rate. This type of operation is not
recommended unless it is thoroughly tested.
The modulation profile of the SM530 is not a linear sweep from max to min and back. The OSCin reference clock
determines the modulation frequency but the internal SSCG control logic determines the actual modulation profile.
The modulation profile can best be described by comparing the instantaneous frequency at Fout with time. The
illustration in diagram 9 below is a representation of the modulation profile of the SM530 as displayed on a Time
Domain Analyzer.
Fmax
50.625
50.468
+1.25%
50.312
50.156
Fcenter
2.5%
50.000
49.844
49.687
49.531
49.375
-1.25%
Fmin
15
0
5
10
20
25
30
35
Time (microseconds)
Figure 9. Frequency Profile in Time Domain
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As can be seen from the diagram above, the Fout/Time profile progresses through frequencies depending on
where it is in the sweep. If the frequency is in the middle of the sweep, the rate of change is slower compared to
the rate at the extremes of the band. When the frequency is nearing the end of the band, it is moving through
these frequencies faster, since it has to sweep through these same frequencies again after reversing direction.
This modulation profile is one of the key elements to the SM530. Using a linear sweep through all frequencies
would not give as good of results in EMI reduction.
APPLICATION NOTES AND SCHEMATICS
The schematic diagram shown below is a simple minimum component application example of an SM530 design.
In the case shown below, the control lines are configured for the following parameters;
Input Frequency: Mid-Range
Multiplier: X1 Modulation: 2.50 %
SSON: On
Refer to loop filter values on Table 8, page 7, for operation at 3.3 Volts DC.
* L1 and C9 are required when Y1 is a 3rd. overtone crystal.
R2
VCC = 3.3 VDC
VDD
10 ohm.
50 MHz
C2
C3
C1
22 uf. 0.1 uf.
0.1 uf.
12
3
Y1
C9
DVDD
AVDD
1
19
18
*
OSCin
OVDD
OVSS
L1
C4
2
.033 uf.
OSCout
330 nh.
0.1 uf.
*
C5
C8
27 pf.
4
27 pf.
D_C
20
Reference Clock
REFout
(Not Modulated)
17
R0
SM530
16
VDD
R1
6
S0
9
15
5
Modulated Clock
Output
S1
Fout
14
S2
11
S3
STOP
10
LF
SSON
DVSS AVSS
7
13
8
R1
1 K
C6
10,000 pf.
C7
1000 pf.
Figure 10. Application Schematic
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Rev. 1.6
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SM530
Approved Product
Low EMI Spectrum Spread Clock
The SM530 has an internal Analog Power and Ground and a Digital Power and Ground. In the example above,
the digital and analog circuits are connected together. If noise is a concern, it is recommended that the Analog
and Digital Power and Grounds be separated. The loop filter shown above is recommended for operation at 3.14 -
3.47 VDC. This filter can also be used in 5.0 VDC operations when operating in the low frequency end of each of
the three input frequency ranges. Refer to table 8 on page 7 for loop filter information. Also note, the crystal, Y1,
is a third overtone 50 Mhz crystal, which requires an inductor and decoupling capacitor to OSCout.
Diagram 11 below shows the equivalent internal oscillator circuit for the SM530.
Equivalent Oscillator Circuit
250 K
.
1
1
2
Xin
3 pF
2
.
Xout
5 pF
Figure 11. Equivalent Oscillator Circuit.
PCB Layout Example
The SM530 Spectrum Spread Clock is a PLL type hybrid circuit. This means that is contains both digital and
analog circuits on the same die. The Phase Detector, Loop Filter and VCO are analog circuits that must operate
in a very low noise environment for best performance. There are several ways to keep this noise to a minimum,
such as bypass capacitors on all power pins and separating the analog and digital power and ground planes. The
diagram below uses the first approach of placing bypass capacitors as close to every power pin as possible. In
addition, all ground pins should be connected directly to the ground plane with little or no trace length. Note also
that only the power and ground circuits of the SM530 have been shown. Other circuits such as the Loop Filter
components must be located as close to the Loop Filter pin as possible, for best performance.
22 uf.
10 ohm
VSS
VCC
Pin 1
0.1 uf.
VSS
VSS
0.1 uf.
VSS
VSS
VSS
0.1 uf.
Figure 12. SM530 Single Power Plane PCB Layout
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PACKAGE DIMENSIONS AND DRAWINGS
C
20 PIN SSOP OUTLINE DIMENSIONS
L
INCHES
NOM
MILLIMETERS
MIN NOM MAX
SYMBOL
MIN
MAX
H
E
A
A1
A2
B
0.068
0.002
0.066
0.010
0.005
0.278
0.205
0.073
0.078 1.73
0.008 0.05
0.070 1.68
0.015 0.25
0.009 0.13
0.289 7.07
0.212 5.20
1.86
0.13
1.73
0.30
0.15
7.20
5.30
1.99
0.21
1.78
0.38
0.22
7.33
5.38
0.005
0.068
0.012
D
a
C
D
E
0.006
A2
0.284
A
0.209
A1
e
0.0256 BSC
0.307
0.65 BSC
e
H
a
0.301
0°
0.311 7.65
7.80
4°
7.90
8°
0.95
B
4°
8°
0°
L
0.022
0.030
0.037 0.55
0.75
C
20 PIN TSSOP OUTLINE DIMENSIONS
L
INCHES
NOM
-
MILLIMETERS
NOM MAX
SYMBOL
MIN
-
MAX
.047
.006
.035
.012
-
MIN
-
H
E
A
A1
A2
B
-
0.10
-
1.20
.002
.004
-
0.05
-
0.15
0.90
0.30
-
-
.007
-
0.95
-
0.19
-
.245
-
D
a
C
D
E
A2
.252
.169
.256
.173
.026 BSC
.252
40
.260
.177
6.40
4.30
6.50
4.40
0.65 BSC
6.60
4.50
A
A1
e
e
H
a
.246
00
.258
80
6.25
00
6.40
40
6.55
B
80
L
.020
.025
.030
0.50
0.62
5
0.75
Disclaimer
International Microcircuits, Inc, reserves the right to change or modify the information contained in this data sheet, without notice.
International Microcircuits, Inc., does not assume any liability arising out of the application or use of any product or circuit described herein.
International Microcircuits, Inc., does not convey any license under its patent rights nor the rights of others. International Microcircuits, Inc.
does not authorize its products for use as critical components in life-support systems or critical medical instruments, where a malfunction or
failure may reasonably be expected to result in significant injury to the user.
International Microcircuits,Inc.
525 Los Coches St., Milpitas, 95035 408-263-6300, FAX 408-263-6571
http:/www.imicorp.com
1/5/99
Rev. 1.6
Page 16 of 16
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