IMIC9812DYB_技术文档

C9812

Low EMI Clock Generator for Intel 810E Chipset Systems

Approved Product

Product Features

Frequency Table (MHz)

•

Intel’s 810E clock solution

SEL2

SEL1 SEL0

CPU

SDRAM

PCI

3 copies of CPU Clock (CPU[0:1] and CPU_ITP)

9 copies of SDRAM Clock (SDRAM[0:7] and DCLK)

8 copies of PCI Clock

2 copies of 3V66 Clock

2 copies of APIC Clock, synchronous to PCI Clock

1 REF Clock

1 USB Clock (Non SSC)

1 DOT Clock (Non SSC)

Power Down Feature

X

0

1

0

1

0

1

0

1

X

Tristate

Test mode (see table2)

66.6

100

33.3

100

33.3

133.3

Table 1

Note: The following clocks remain fixed frequencies

except in Test Mode.

3V66=66.6MHz, USB/DOT=48MHz, REF=14.318MHz

and IOAPIC=33.3MHz.

Spread Spectrum Support

I²C Support for turning off unused clocks

Block Diagram

Pin Configuration

XIN

36pF

56

SEL2/REF

VDD

1

2

3

4

VSS

300K

IOAPIC0

IOAPIC1

VDDI

55

54

53

52

XIN

XOUT

VSS

XOUT

VDD

5

CPU0

REF / SEL2

1

6

7

8

9

VSS

VDDC

CPU1

CPU2_ITP

VSS

SDRAM0

SDRAM1

VDDS

SDRAM2

SDRAM3

VSS

SDRAM4

SDRAM5

VDDS

SDRAM6

SDRAM7

VSS

51

50

49

3V660

3V661

VDDI

VDD

PCI0_ICH

PCI1

48

47

46

45

44

43

42

41

IOAPIC(0:1)

CPU(0:2)

s2

ioapic

cpu

2

3

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Rin

C

9

8

1

2

VDDC

PCI2

VSS

PCI3

PCI4

VSS

PCI5

PCI6

PCI7

VDD

VDDA

VSSA

VSS

USB

DOT

VDD

SEL0

i2c-clk

i2c-data

SCLK

SDATA

VDDS

VDD

40

39

38

37

36

VDD

SDRAM(0:7), DCLK

3V66(0:1)

sdram

66m

pci

9

2

s1

SEL1

SEL0

PD#

s0

35

34

33

pwr_dwn#

DCLK

VDD

PD#

SCLK

SDATA

VDD

24

25

26

27

32

31

30

PCI(0:7)

DOT

8

1

PLL1

Rin

28

SEL1

29

48

PD#

USB

i2c-clk

i2c-data

PLL2

Fig.1

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,

MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571

http://www.imicorp.com

Rev 1.1

11/12/1999

Page 1 of 16

C9812

Low EMI Clock Generator for Intel 810E Chipset Systems

Approved Product

Pin Description

PIN No.

Pin Name

PWR

VDD

I/O TYPE

I/O

Description

3.3V 14.318 MHz clock output.

1

SEL2/REF

This pin also serves as the select strap (associates with SEL0 &

1, see app. note page 5) for clock frequencies during power up.

Refer to Table 1 for detail. This pin has an internal pull-down

(Typ. 70KΩ).

3

4

VDD

I

O

OSC1 14.318MHz Crystal input

XIN

XOUT

PCI0/ICH

PCI(1..7)

14.318MHz Crystal output

3.3V PCI clock outputs

11, 12, 13,

15, 16, 18,

19, 20

7, 8

25

26

VDD

O

I

3.3V Fixed 66.6 MHz clock outputs

3.3V Fixed 48 MHz clock outputs

3.3V LVTTL compatible inputs for logic selection. Has an

internal pull-up (Typ. 250KΩ)

3V66(0,1)

USB

DOT

28, 29

SEL(0,1)

30

31

32

VDD

I

SDATA

SCLK

PD#

I²C compatible SDATA input. Has an internal pull-up (>100KΩ)

I²C compatible SCLK input. Has an internal pull-up (>100KΩ)

3.3V LVTTL compatible input. Device enters powerdown mode

When held LOW. Has an internal pull-up (>100KΩ)

3.3V output running 100MHz

34

VDD

VDDS

O

DCLK

SDRAM(7..0)

36, 37, 39,

40, 42, 43,

45, 46

3.3V output running 100MHz. All SDRAM outputs can be turned

off through I²C.

49, 50, 52

VDDC

VDDI

-

O

2.5V Host bus clock outputs. 66, 100 or 133MHz depending on

state of SEL(2..0)

2.5V clock outputs running rising edge synchronous with the

PCI clock.

3.3V Power Supply

CPU(2)_ITP,

CPU(1,0)

IOAPIC(1,0)

54, 55

2, 9, 10, 21,

27, 33

VDD

22

23

51, 53

5, 6,14, 17,

24, 35, 41,

47, 48, 56

38, 44

-

Analog circuitry 3.3V Power Supply

Analog circuitry power supply Ground pins.

2.5V Power Supply’s

VDDA

VSSA

VDDC, VDDI

VSS

-

Common Ground pins.

-

3.3V power support for SDRAM clock output drivers.

VDDS

A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin. If these bypass capacitors

are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces.

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,

MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571

http://www.imicorp.com

Rev 1.1

11/12/1999

Page 2 of 16

C9812

Low EMI Clock Generator for Intel 810E Chipset Systems

Approved Product

Test Mode Function

Test Mode Functionality

SEL2 SEL1

SEL0

CPU

SDRAM

3V66

PCI

48 MHz

REF

IOAPIC

x

0

1

TCLK/2

TCLK/3

Table 2

TCLK/6

TCLK/2

TCLK

TCLK/6

Note: TCLK is a test clock over driven on the XIN input during test mode.

Power Management Functions

Power Management on this device is controlled by a single pin, PD# (pin32). When PD# is high (default) the device is in

running and all signals are active.

When PD# is asserted (forced) low, the device is in shutdown (or in power down) mode and all power supplies (3.3V and

2.5V except for VDDA/pin 27) may be removed. When in power down, all outputs are synchronously stopped in a low

state (see Fig.2 below), all PLL’s are shut off, and the crystal oscillator is disabled. When the device is shutdown the I²C

function is also disabled.

Power Management Timing

0nS

100MHz

10nS

20nS

30nS

40nS

50nS

CPU

3V66

66MHz

33MHz

PCI

IOAPIC

PWRDN#

Undefined

SDRAM 100MHz

14.3MHz

48MHz

REF

USB

Fig.2

Power Management Current

Maximum 2.5 Volt Current

Consumption (VDD2.5 =2.625)

Maximum 3.3 Volt Current Consumption

(VDD3.3 = 3.465 V)

PD#, SEL[2..0]

(CPU Clock)

0XXX (Power down)

1010 (66MHz)

100 µA

70 mA

100 mA

200 µA

280 mA

1011 (100MHz)

111X (133MHz)

133 mA

Table 3

When exiting the power down mode, the designer must supply power to the VDD pins first, a minimum of 200mS before

releasing the PD# pin high.

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,

MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571

http://www.imicorp.com

Rev 1.1

11/12/1999

Page 3 of 16

C9812

Low EMI Clock Generator for Intel 810E Chipset Systems

Approved Product

Clock Synchronization and Phase Alignment

This device incorporates IOAPIC clock synchronization. With this feature, the IOAPIC clocks are derived from the CPU

clock. The IOAPIC clock lags the CPU clock by the specified 1.5 to 3.5 nSec. Figure 3 shows the relationship between

the CPU and IOAPIC clocks.

Device Clock Phase Relationships

0nS

10nS

20nS

30nS

40nS

CPU CLOCK

66MHz

2.5nS

100MHz

133MHz

5nS

Sync

7.5nS

5nS

SDRAM CLOCK

100MHz

3V66 CLOCK

PCI CLOCK

66MHz

33MHz

1.5~3.5nS

IOAPIC CLOCK

33MHz

Fig.3

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,

MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571

http://www.imicorp.com

Rev 1.1

11/12/1999

Page 4 of 16

C9812

Low EMI Clock Generator for Intel 810E Chipset Systems

Approved Product

Power on Bi-Directional Pins

Power Up Condition:

Pin1 is a Power up bi-directional pin and is used for selecting the host frequency in page 1, table 1. During power-up of

the device, this pin is in input mode (see Fig 4, below), therefore; it is considered an input select pins internal to the IC.

After a settling time, the selection data is latch into the internal control register and this pin becomes a clock output.

VDD RAIL

POWER SUPPLY

RAMP

REF / SEL2

(Pin 1)

-

Hi-Z INPUTS

TOGGLE OUTPUTS

SELECT DATA IS LATCHED INTO REGISTER THEN PIN BECOMES A REF CLOCK OUTPUT SIGNAL

Fig.4

Strapping Resistor Options:

The power up bi-directional pins have a large value pull-down each (70KΩ), therefore, a selection “0” is the default. If the

system uses a slow power supply (over 5mS settling time), then it is recommended to use an external Pull-down in

order to insure a low selection.

Fig. 5 If a selection “0” is desired, then a jumper is placed on JP1 to a 10KΩ resistor as implemented as shown in Fig.5.

Please note the selection resistor (Rdn) is placed before the Damping resistor (Rd) close to the pin.

JP1

Vdd

Jumper

3

2

1

Rsel

10K

IMI C9812

Rd

Load

Bidirectional

Fig. 5

70K

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,

MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571

http://www.imicorp.com

Rev 1.1

11/12/1999

Page 5 of 16

C9812

Low EMI Clock Generator for Intel 810E Chipset Systems

Approved Product

2-Wire I²C Control Interface

The 2-wire control interface implements a write slave only interface according to Philips I²C specification. (See Fig. 7 / P.

8). The device can be read back by using standard I²C command bytes. Sub addressing is not supported, thus all

preceding bytes must be sent in order to change one of the control bytes. The 2-wire control interface allows each clock

output to be individually enabled or disabled. 100 Kbits/second (standard mode) data transfer is supported.

During normal data transfer, the SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK

is high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is high is used to indicate the

start of a data transfer cycle. A low to high transition on SDATA while SDCLK is high indicates the end of a data transfer

cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer

cycle is an 8-bit address. W#=0 in write mode.

The device will respond to writes to 10 bytes (max) of data to address D2 by generating the acknowledge (low) signal on

the SDATA wire following reception of each byte. Data is transferred MSB first at a max rate of 100kbits/S. The device

will not respond to any other control interface conditions, and previously set control registers are retained.

I²C Test Circuitry

+ 5V

2.2 K

Device under Test

DATAIN

SDATA

SCLK

+ 5V

2.2 K

+ 5V

DATAOUT

2.2 K

CLOCK

Fig.6

Note: Buffer is 7407 with VCC @ 5.0 V

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,

Rev 1.1

11/12/1999

MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571

http://www.imicorp.com

Page 6 of 16

C9812

Low EMI Clock Generator for Intel 810E Chipset Systems

Approved Product

Serial Control Registers

NOTE: The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true

power up. Bytes are set to the values shown only on true power up.

Following the acknowledge of the Address Byte, two additional bytes must be sent:

1) “Command Code “ byte, and

2) “Byte Count” byte.

Although the data (bits) in these two bytes are considered “don’t care”; they must be sent and will be acknowledged.

After the Command Code and the Count bytes have been acknowledged, the below described sequence (Byte 0, Byte 1,

and Byte2) will be valid and acknowledged.

Byte 0: CPU Clock Register (1=Enable, 0=Disable, Default=07)

Byte 1: SDRAM Clock Register (1=Enable, 0=Disable, Default=FF)

Bit

7

6

5

4

3

2

1

0

@Pup

Pin#

-

Description

Reserved

Spread spectrum mode

DOT

Bit

7

6

5

4

3

2

1

0

@Pup

Pin#

36

37

39

40

42

43

45

46

Description

SDRAM7

SDRAM6

SDRAM5

SDRAM4

SDRAM3

SDRAM2

SDRAM1

SDRAM0

0

1

-

26

25

49

USB

CPU2_ITP

Byte 2: PCI Clock Register (1=Enable, 0=Disable, Default=FE)

Byte 3: Reserved Register (Default=00)

Byte 4: Reserved Register (Default=00)

Byte 5: SSCG Control Register (Default=00)

Bit

7

@Pup

Pin#

20

19

18

16

15

13

12

-

Description

PCI7

1

0

6

PCI6

5

PCI5

4

PCI4

Bit

7

@Pup

Pin#

Description

Spread Mode (0=down, 1=center)

Ref. Table 4

Reserved

3

PCI3

0

-

2

PCI2

6

5

4

1

PCI1

0

Reserved

3

Reserved

2

Reserved

1

Reserved

0

Reserved

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,

MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571

http://www.imicorp.com

Rev 1.1

11/12/1999

Page 7 of 16

C9812

Low EMI Clock Generator for Intel 810E Chipset Systems

Approved Product

ACK

SDATA IS OUTPUT PIN

COMMAND BYTE

(DON'TCARE)

1

0

1

0

1

0

SDATA IS INPUT PIN

SDATA

MSB

LSB

SCLK

8

START CONDITION

CONTINUED

ACK

COUNT BYTE

(DON'TCARE)

BYTE 0

(VALID DATA)

BYTE N (LAST

VALID DATA)

CONTINUED

8

STOP CONDITION

Figure 7

I²C Communications Waveforms

Test and Measurement Condition

Output under Test

Probe

Load Cap

3.3V signals

2.5V signals

tDC

-

3.3V

2.5V

2.4V

1.5V

2.0V

1.25V

0.4V

0V

Tr

Tf

Tr

Tf

Fig.8

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,

MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571

http://www.imicorp.com

Rev 1.1

11/12/1999

Page 8 of 16

C9812

Low EMI Clock Generator for Intel 810E Chipset Systems

Approved Product

Spread Spectrum Clock Generation (SSCG)

Spread Spectrum is a modulation technique applied here for maximum efficiency in minimizing Electro-Magnetic

Interference radiation generated from repetitive digital signals mainly clocks. A clock accumulates EM energy at the

center frequency it is generating. Spread Spectrum distributes this energy over a small frequency bandwidth therefore

spreading the same amount of energy over a spectrum. This technique is achieved by modulating the clock down from

(Fig.9A) or around the center (Fig.9B) of its resting frequency by a certain percentage (which also determines the

energy distribution bandwidth). In this device, Spread Spectrum is enabled by setting I2C byte0, bit3 = 1. The default of

the device at power up keeps the Spread Spectrum disabled, it is therefore, important to have I2C accessibility to turn-

on the Spread Spectrum function. Once the Spread Spectrum is enabled, the spread bandwidth option is selected by

SST(0:2) in I2C byte 5, bits 5, 6 & 7 following tables 4A, and 4B below.

In Down Spread mode the center frequency is shifted down from its rested (non-spread) value by ½ of the total spread

%. (eg.: assuming the center frequency is 100MHz in non-spread mode; when down spread of –0.5% is enabled, the

center frequency shifts to 99.75MHz.).

In Center Spread mode, the Center frequency remains the same as in the non-spread mode.

Down Spread

Center Spread

Fig.9A

Fig.9B

Spread Spectrum Selection Tables

Center Frequency

Spread

%

Down Frequency

(MHz)

Spread

%

I²C BYTE5

Bit[7:5]

I²C BYTE5

Bit[7:5]

(MHz)

100

101

110

111

66/100/133.3

000

001

010

011

66/100/133.3

- 0.5

- 0.7

- 1.0

- 1.5

± 0.25

± 0.35

± 0.5

± 0.7

Table 4B

Table 4A

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,

MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571

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Rev 1.1

11/12/1999

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C9812

Low EMI Clock Generator for Intel 810E Chipset Systems

Approved Product

Maximum Ratings

This device contains circuitry to protect the inputs

against damage due to high static voltages or electric

field; however, precautions should be taken to avoid

application of any voltage higher than the maximum

rated voltages to this circuit. For proper operation, Vin

Maximum Input Voltage Relative to VSS: VSS - 0.3V

Maximum Input Voltage Relative to VDD: VDD + 0.3V

Storage Temperature:

Operating Temperature:

Maximum ESD protection

Maximum Power Supply:

-65ºC to + 150ºC

0ºC to +70ºC

2KV

and Vout should be constrained to the range:

VSS<(Vin or Vout)<VDD

Unused inputs must always be tied to an appropriate

logic voltage level (either VSS or VDD).

5.5V

DC Parameters

Characteristic

Symbol Min

Typ

Max

1.0

Units

Vdc

µA

Conditions

Input Low Voltage

VIL1

VIH1

VIL2

VIH2

IIL

-

Note 1

Input High Voltage

2.0

-

1.0

-

Input Low Voltage

Note 2

Input High Voltage

2.2

-66

Input Low Current (@VIL = VSS)

Input High Current (@VIL =VDD)

Tri-State leakage Current

Dynamic Supply Current

Static Supply Current

Input pin capacitance

Output pin capacitance

Pin capacitance

-5

For internal Pull up resistors,

Notes 1,3

IIH

5

µA

Ioz

-

10

280

100

300

5

µA

Idd3.3V

Idd2.5V

Isdd

-

mA

µA

Sel2 = Sel1 = Sel0 = 1, Note 4

Sel2 = Sel1 = Sel0 = x, Note 4

-

Cin

-

pF

Cout

Lpin

-

6

pF

-

7

nH

Clock Stablization Time

Crystal pin capacitance

Crystal DC Bias Voltage

Crystal Startup time

tstab

Cxtal

V_BIAS

Txs

3

32

-

34

-

mSec

pF

Measured from VDD – 3.15 volts

38

0.7Vdd

40

Measured from Pin to Ground. Note 5

0.3Vdd

-

Vdd/2

-

V

From Stable 3.3V power supply.

µS

VDD=VDDS = 3.3V ±5%, VDDC = VDDI = 2.5 ± 5%, TA = 0º to +70ºC

Applicable to input signals: Sel(0:1), PD#

Applicable to Sdata, and Sclk.

Note1:

Note2:

Note3:

Although internal pull-up resistors have a typical value of 250K, this value may vary between 200K and 500K. Internal Pull-down resisters

are typically 70K in value.

Note4:

Note5:

All outputs loaded as per table below.

Although the device will reliably interface with crystals of a 17pF – 20pF C_Lrange, it is optimized to interface with a typical C_L= 18pF

crystal specifications.

Clock Name

Max Load (in pF)

CPU, IOAPIC, REF, USB

PCI, SDRAM, 3V66(0,1)

DOT

20

30

15

Table 5.

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,

MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571

http://www.imicorp.com

Rev 1.1

11/12/1999

Page 10 of 16

C9812

Low EMI Clock Generator for Intel 810E Chipset Systems

Approved Product

AC Parameters

133 MHz Host

100 MHz Host

Symbol

Parameter

Units

Notes

Min

7.5

1.87

1.67

0.4

-

Max

8.0

-

Min

10.0

3.0

2.8

0.4

-

Max

10.5

-

TPeriod

THIGH

TLOW

CPU(0:1) period

CPU(0:1) high time

CPU(0:1) low time

nS

pS

nS

pS

nS

pS

nS

pS

5, 6, 8

6,10

-

6, 11

6, 7

Tr / Tf

TSKEW

TCCJ

CPU(0:1) rise and fall times

CPU0 to CPU1 Skew time

CPU(0:1) Cycle to Cycle Jitter

APIC(0:1) period

1.6

175

250

-

1.6

175

250

-

6, 8, 9

5, 6, 8

6,10

-

TPeriod

THIGH

TLOW

Tr / Tf

60.0

25.5

25.3

0.4

-

60.0

25.5

25.3

0.4

-

APIC(0:1) high time

-

APIC(0:1) low time

-

N/S

1.6

500

16.0

-

6, 11

6, 7

APIC(0:1) rise and fall times

APIC(0:1) Cycle to Cycle Jitter

3V66-(0:1) period

1.6

500

16.0

-

TCCJ

6, 8, 9

5, 6, 8

6,10

TPeriod

THIGH

TLOW

Tr / Tf

15.0

5.25

5.05

0.4

-

15.0

5.25

5.05

0.4

-

3V66-(0:1) high time

3V66-(0:1) low time

-

6, 11

6, 7

3V66-(0:1) rise and fall times

3V66-0 to 3V66-1 Skew time

3V66-(0:1) Cycle to Cycle Jitter

PCI(0:7) period

1.6

250

500

-

1.6

250

500

-

TSKEW

TCCJ

6, 8, 9

5, 6, 8

6,10

-

TPeriod

THIGH

TLOW

Tr / Tf

30.0

12.0

0.5

-

30.0

12.0

0.5

-

PCI(0:7) period

-

PCI(0:7) low time

-

6, 11

6, 7

PCI(0:7) rise and fall times

2.0

500

2.0

500

TSKEW

(Any PCI clock) to (Any PCI clock)

Skew time

6, 8, 9

TCCJ

PCI(0:7) Cycle to Cycle Jitter

-

500

-

500

pS

nS

6, 8, 9

5, 6, 8

TPeriod

48MHz period ( conforms to

+167ppm max)

20.8299 20.8333 20.8299 20.8333

Tr / Tf

TCCJ

48MHz rise and fall times

48MHz Cycle to Cycle Jitter

REF period

1.0

4.0

500

71.0

4.0

1.0

4.0

500

71.0

4.0

nS

pS

nS

pS

nS

mS

6, 7

6, 8, 9

5, 6, 8

6, 7

6, 8

13

-

69.8413

1.0

-

69.8413

1.0

TPeriod

Tr / Tf

REF rise and fall times

TCCJ

REF Cycle to Cycle Jitter

-

1000

10.0

3

-

1000

10.0

3

tpZL, tpZH

tpLZ, tpZH

tstable

Output enable delay (all outputs)

Output disable delay (all outputs)

All clock Stabilization from power-up

1.0

13

12

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,

MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571

http://www.imicorp.com

Rev 1.1

11/12/1999

Page 11 of 16

C9812

Low EMI Clock Generator for Intel 810E Chipset Systems

Approved Product

Switching Characteristics

Characteristic

Symbol

Min

Typ

Max

55

Units

%

Conditions

Output Duty Cycle

CPU to SDRAM

CPU to 3V66

-

45

50

-

Note 6

TPD1

TPD2

TPD3

tPD

-

500

-

pS

nS

pS

CPU = 133.3MHz, Notes 6, 7

CPU = 66.6/100/133.3MHz Notes 6, 7

see Notes 6, 7

-

SDRAM to 3V66

3V66 to PCI

-

1.5

-

PCI to IOAPIC

tPD

-

0

-

1

Skew (CPU0-CPU1)

Skew (SDRAM-SDRAM)

Skew (APIC-APIC)

Skew (3V66-3V66)

Skew (PCI – PCI)

Cycle to Cycle Jitter

tSKEW1

tSKEW2

tSKEW3

tSKEW4

TSKEW5

∆P1

175

250

175

500

250

500

-

see Notes 6, 7

-

CPU, and SDRAM, Notes 6 & 7

-

IOAPIC, USB, DOT, 3V66, PCI,

Notes 6, 7

∆P2

Cycle to Cycle Jitter

-

1,000

pS

REF, Notes 6& 7

∆P3

VDD=VDDS=3.3V ±5%, VDDC=VDDI=2.5±5%, TA=0 to 70ºC

Note 6: All outputs loaded as per table 5 below. Probes are placed on the pins and taken at 1.5V levels for 3.3V signals and at 1.25V for 2.5V

signals.

Note 7: This measurement is applicable with Spread Spectrum ON or OFF.

Output Buffer Characteristics

Buffer Characteristics for CPU

Characteristic

Symbol

IOH₁

IOH₂

IOL₁

Z0

Min

-28

-26

12

Typ

-61

-58

24

Max

-107

Units

mA

Conditions

Vout =VDDC - 0.4V

Pull-Up Current

-101

40

mA

Vout = 1.2 V

Vout = 0.4 V

Vout = 1.2 V

Pull-Down Current

Dynamic Output Impedance

mA

27

56

93

mA

13.5

0.4

45

Ω

Rise Time Min

Between 0.4 and 2.0 V

Fall Time Max

Tr

-

1.6

nS

20pF Load

Tf

0.4

1.6

nS

Between 0.4 and 2.0 V

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,

MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571

http://www.imicorp.com

Rev 1.1

11/12/1999

Page 12 of 16

C9812

Low EMI Clock Generator for Intel 810E Chipset Systems

Approved Product

Output Buffer Characteristics (Cont.)

Buffer Characteristics for PCI, 3V66 and DOT

Characteristic

Symbol

Min

Typ

-58

-54

18

Max

-194

Units

mA

Conditions

Vout =VDDC - 1.0 V

Pull-Up Current

IOH₁

IOH₂

IOL₁

Z0

-33

-30

9.4

28

Pull-Up Current

-184

38

mA

Vout = 1. 5 V

Vout = 0.4 V

Vout = 1.5 V

Pull-Down Current

Dynamic Output Impedance

mA

55

148

55

mA

12

Ω

Rise Time Min

Between 0.4 and 2.4 V

Fall Time Max

Tr

0.5

-

2.0

nS

30pF Load

Tf

0.5

2.0

nS

Between 0.4 and 2.4 V

Buffer Characteristics for USB and REF

Characteristic

Symbol

Min

Typ

-46

-43

13

Max

Units

mA

Conditions

Pull-Up Current

IOH₁

IOH₂

IOL₁

Z0

-29

-27

9

-99

-92

27

Vout =VDD - 1.0 V

Vout = 1. 5 V

Vout = 0.4 V

Pull-Up Current

mA

Pull-Down Current

Dynamic Output Impedance

mA

26

20

1.0

39

79

mA

Vout = 1.5 V

60

Ω

Rise Time Min

Between 0.4 and 2.4 V

Fall Time Max

Tr

-

4.0

nS

20pF Load

Tf

1.0

4.0

nS

Between 0.4 and 2.4 V

Buffer Characteristics for IOAPIC

Characteristic

Symbol

IOH₁

IOH₂

IOL₁

Z0

Min

-28

-26

12

Typ

-61

-58

24

Max

Units

mA

Ω

Conditions

Pull-Up Current

-107

40

Vout =VDDI - 0.5V

Vout = 1. 0 V

Vout = 0.4 V

Pull-Up Current

Pull-Down Current

Dynamic Output Impedance

28

60

100

45

Vout = 1.4 V

13.5

0.4

Rise Time Min

Between 0.4 and 2.0 V

Tr

-

1.6

nS

20pF Load

Fall Time Max

Tf

0.4

1.6

nS

Between 0.4 and 2.0 V

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,

MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571

http://www.imicorp.com

Rev 1.1

11/12/1999

Page 13 of 16

C9812

Low EMI Clock Generator for Intel 810E Chipset Systems

Approved Product

Output Buffer Characteristics (Cont.)

Buffer Characteristics for SDRAM

Characteristic

Symbol

IOH₁

IOH₂

IOL₁

Z0

Min

-72

-68

23

Typ

-116

-110

34

Max

-198

Units

mA

Ω

Conditions

Vout =VDD - 1. 0 V

Pull-Up Current

-188

53

Vout = 1. 4 V

Vout = 0.4 V

Vout = 1.5 V

Pull-Down Current

Dynamic Output Impedance

64

98

159

24

10

Rise Time Min

Between 0.4 and 2.4 V

Tr

0.4

-

1.6

nS

30pF Load

Fall Time Max

Tf

0.4

1.6

nS

Between 0.4 and 2.4 V

VDD=VDDS=3.3V ±5%, VDDC=VDDI=2.5±5%, TA=0 to 70ºC

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,

MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571

http://www.imicorp.com

Rev 1.1

11/12/1999

Page 14 of 16

C9812

Low EMI Clock Generator for Intel 810E Chipset Systems

Approved Product

Suggested Crystal Oscillator Parameters

Characteristic

Frequency

Symbol

F_o

Min

Typ

Max

Units

MHz

PPM

Conditions

12.00

14.31818

16.00

Tolerance

TC

-

+/-100

Note 1

TS

+/- 100

Stability (Ta -10 to +60C) Note 1

Aging (first year @ 25C) Note 1

Parallel Resonant, Note 1

The crystal’s rated load. Note 1

Note 1

TA

-

5

-

Mode

OM

CL

-

Load Capacitance

18

40

-

pF

Effective Series

resistance (ESR)

R1

-

Ohms

Power Dissipation

Shunt Capacitance

DL

-

0.10

8

mW

pF

Note 1

Crystal’s internal package

capacitance (total)

CO

--

Note1: For best performance and accurate Center frequencies of this device, It is recommended but not mandatory that

the chosen crystal meets these specifications

For maximum accuracy, the total circuit loading capacitance should be equal to CL. This loading capacitance is the

effective capacitance across the crystal pins and includes the device pin capacitance (CP) in parallel with any circuit

traces, the clock generator and any onboard discrete load capacitors.

Budgeting Calculations

Device pin capacitance: Cxtal = 34pF

In order to meet the specification for CL = 18pF following the formula:

C_XINxC_XOUT

C_L

=

C_XIN

C

XOUT

+

Then the board trace capacitance between Xin and the crystal should be no more than 2pF. (same is applicable to the

trace between Xout and the crystal)

In this case the total capacitance from the crystal to Xin will be 36pF. Similarly the total capacitance between the crystal

and Xout will be 36pF. Hence using the above formula:

36pFx36pF

C_L

=

18pF

36pF + 36pF

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,

MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571

http://www.imicorp.com

Rev 1.1

11/12/1999

Page 15 of 16

C9812

Low EMI Clock Generator for Intel 810E Chipset Systems

Approved Product

Package Drawing and Dimensions

56 Pin SSOP Outline Dimensions

INCHES

MILLIMETERS

SYMBOL

A

MIN

NOM

MAX

MIN

2.41

NOM

2.59

MAX

2.79

0.095

0.102

0.012

0.090

0.010

-

0.110

C

A₁

A2

B

0.008

0.088

0.008

0.005

.720

0.016

0.092

0.0135

0.010

.730

0.20

2.24

0.31

2.29

0.41

2.34

L

H

E

0.203 0.254 0.343

0.127 0.254

18.29 18.42 18.54

C

D

E

-

.725

D

0.292

0.296

0.025 BSC

0.406

0.032

5º

0.299

7.42

7.52

7.59

a

e

0.635 BSC

A₂

A

H

L

0.400

0.024

0º

0.410

0.040

8º

10.16 10.31 10.41

A₁

0.61

0º

0.81

5º

1.02

8º

e

B

a

X

0.085

0.093

0.100

2.16

2.36

2.54

Ordering Information

Part Number

Package Type

Production Flow

C9812DYB

56 PIN SSOP

Commercial, 0 to 70ºC

Marking: Example: IMI

C9812

Date Code, Lot #

IMIC9812DYB

Flow

B = Commercial, 0 to 70ºC

Package

Y = SSOP

Revision

IMI Device Number

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,

MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571

http://www.imicorp.com

Rev 1.1

11/12/1999

Page 16 of 16


型号：	IMIC9812DYB
厂家：	CYPRESS
描述：	Clock Generator, PDSO56 光电二极管
文件：	总16页 (文件大小：273K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IMIC9812DYB [CYPRESS]

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