IMIC9806IAT [CYPRESS]
Processor Specific Clock Generator, 16MHz, CMOS, PDSO48, TSSOP-48;
| 型号： | IMIC9806IAT |
| 厂家： | 
CYPRESS |
| 描述： | Processor Specific Clock Generator, 16MHz, CMOS, PDSO48, TSSOP-48 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总14页 (文件大小：217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
C9806I
I2C Frequency Clock Generator for Mobile Pentium® II Applications.
Preliminary
Product Features
Frequency Table (MHz)
S1
S0
CPU(0:1)
PCI(_F,0:5)
30
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Supports Pentium® & Pentium® II CPUs.
2 CPU clocks.
7 independent SDRAM clocks for 3 SO DIMMs.
Power Management hardware support.
7 PCI synchronous clocks.
< 175 pS skew CPU and SDRAM clocks.
< 175 pS skew among PCI clocks.
I2C 2-Wire serial interface
Programmable registers featuring:
Individual clock enable/disable
Mode as Tri-state, test, or normal
24/48 MHz selections
0
0
60
0
1
66.6
33.3
1
0
133.3
100
33.3
1
1
33.3
Table 1
Enable/Disable SST
Available in 48-pin SSOP and TSSOP packages
Spread Spectrum Technology (SST)
Dial-a-Frequency™ Feature
Block Diagram
Pin Configuration
XIN
36pF
36pF
500K
REF1
REF0
VSS
XIN
XOUT
S1
VDD
PCI_F
PCI0
VSS
PCI1
PCI2
PCI3
PCI4
VDD
PCI5
VSS
S0
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD
REF3
VDD
REF2
PWR_DWN#
VSS
CPU0
CPU1
VDDC
SDRAM_IN
SDRAM_FB
VSS
SDRAM0
SDRAM1
VDDS
SDRAM2
SDRAM3
VSS
SDRAM4
SDRAM5
VDDS
VDD
XOUT
4
2
REF(0:3)
CPU(0:1)
VDDC
Rin
cpu
9
VDD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
S1
S0
S1
S0
PCI(_F,0:5)
pci
7
7
PLL1
VDDS
SDRAM_IN
SDRAM(_FB,0:5)
CPU_STP#
PCI_STP#
PWR_DWN#
CS#
PS#
PD#
SCLK
SDATA
C
D
VDD
VDD
SDATA
SCLK
VDD
I2CPMU
24/48 MHz
24/48 MHz
1
1
Rin
24/48 MHz
24/48 MHz
VSS
CPU_STOP#
PCI_STP#
VDD
48/24
PLL2
Fig.1
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
http://www.imicorp.com
Rev.1.0
4/25/2000
Page 1 of 14
C9806I
I2C Frequency Clock Generator for Mobile Pentium® II Applications.
Preliminary
Pin Description
Pin No.
1,2,45, 47
4
Pin Name
PWR
VDD
VDD
I/O
O
I
TYPE
OSC
Description
Buffer output clocks of the reference signal at Xin.
REF(0:3)
Xin
On-chip reference oscillator input pin. Requires either an
external parallel resonant crystal (nominally 14.318 MHz) or
externally generated reference signal
5
VDD
O
OSC
On-chip reference oscillator output pin. Drives an external
parallel resonant crystal. When an externally generated
reference signal is used at Xin, this pin remains unconnected.
Input for selecting CPU//PCI frequencies (see table 1,p.1).
Input for selecting CPU//PCI frequencies (see table 1,p.1).
PCI clock outputs, synchronous to the CPU clocks. If PCI_STP#
is asserted low, PCI (0:5) stop in a low state, PCI_F does NOT.
Serial data input pin. Conforms to the Philips I2C specification of
a Slave Receiver device. This pin is an input when receiving
data. It is an open drain output when acknowledging. See I2C
function description, p.5.
Xout
6
18
8,9,11,12,
13,14,16
19
I
I
O
PD
PU
S1
S0
PCI_F,
PCI(0:5)
SDATA
VDD
VDD
I/O PU
20
VDD
VDD
VDD
VDD
I
O
I
PU
Serial clock input pin. Conforms to the Philips I2C 100KHz
Specification.
Programmable Peripheral clock outputs. Default to 48mhz for
USB, but can be programmed to 24MHz through I2C bus.
Input pin for stopping PCI (0:5) when active low. Default high.
(see power management description p.3 )
Input pin for stopping CPU (0:1) when active low. Default high.
(see power management description p.3 ). If Byte1, Bit2 and I2C
is low (0), then CPU0 DOES NOT STOP.
SCLK
22,23
26
24/48M
PU
PU
PCI_STP#
CPU_STP#
27
I
29,30,32,
33, 35, 36,
38
VDDS
O
SDRAM clock outputs. They are buffered outputs of the signal
applied at SDRAM_IN, pin39.
SDRAM
(FB,0:5)
41,42
VDDC
VDD
O
I
Host (CPU) Clock outputs. See Table 1,p.1 for frequency
selection.
Input pin for shutting down the device when asserted low. All
outputs with the exception of SDRAM (FB,0:5), PLL’s and crystal
are stopped for minimum power consumption.
3.3 Volt common power supply pins.
CPU(0:1)
44
PU
PWR_DWN#
7,15,21,25
46, 48
28,34
-
-
P
P
-
-
VDD
3.3 Volt power supply pins for SDRAM_IN, SDRAM (FB, 0:5)
outputs.
VDDS
40
-
-
P
P
-
-
3.3 or 2.5 Volt power supply pins for the CPU (0:1), outputs.
Common Ground pins.
VDDC
VSS
3,10,17,
24, 31, 37,
43
39
VDD
I
-
Input to SDRAM buffers.
Table 2
SDRAM_IN
A bypass capacitor (0.1 uF) should be placed as close as possible to each Vdd, Vddc, and Vdds pins. If these
bypass capacitors are not close to the pins, their high frequency filtering characteristic will be canceled by the
lead inductance of the traces.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
http://www.imicorp.com
Rev.1.0
4/25/2000
Page 2 of 14
C9806I
I2C Frequency Clock Generator for Mobile Pentium® II Applications.
Preliminary
Power Management Functions
All clocks can be individually enabled or stopped via the 2-wire control interface. All clocks are stopped in the low state.
All clocks maintain a valid high period on transitions from running to stopped and on transitions from stopped to running
when the chip was not powered down. On power up, the VCOs will stabilize to the correct pulse widths within about 0.5
mS. The CPU, SDRAM, and PCI clocks transition between running and stopped by waiting for one positive edge on
PCICLK_F followed by a negative edge on the clock of interest, after which high levels of the output are either enabled
or disabled.
Pins 26 and 27 are inputs PCI_STOP# and CPU_STOP# respectively. A particular output is enabled only when both the
serial interface and these pins indicate that it should be enabled. The device clocks may be disabled according to the
following table in order to reduce power consumption. All clocks are stopped in the low state. All clocks maintain a valid
high period on transitions from running to stopped. On low to high transitions of PWR_DWN#, external circuitry should
allow 0.5 mS for the VCOs to stabilize prior to assuming the clock periods are correct. The CPU and PCI clocks
transition between running and stopped by waiting for one positive edge on PCICLK_F followed by a negative edge on
the clock of interest, after which high levels of the output are either enabled or disabled.
CPU_STOP#
PCI_STOP#
PWR_DWN#
CPU*
LOW
LOW
PCI
LOW
LOW
Running
LOW
Running
OTHER CLKs XTAL & VCOs
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
LOW
OFF
RUNNING
RUNNING
RUNNING
RUNNING
RUNNING
RUNNING
RUNNING
RUNNING
LOW
Running
Running
Table 3
*If Byte1, bit2 is programmed to a “0”, then CPU0 is not affected by CPU_STP#, and keeps running when CPU-STP# is
asserted low.
Power Management Timing
PCI_F
PCI_STP#
1 PCI_F clock
wait
Stop on next falling edge
PCI(0:5)
CPU_STP#
CPU(0:1)
wait 1 CPU clock
Stop on next falling edge
Fig.2
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
http://www.imicorp.com
Rev.1.0
4/25/2000
Page 3 of 14
C9806I
I2C Frequency Clock Generator for Mobile Pentium® II Applications.
Preliminary
2-Wire I2C Control Interface
The 2-wire control interface implements a read/write slave only interface according to Philips I2C specification. (See
fig3). The device can be read back by using standard I2C command bytes. Sub addressing is not supported, thus all
preceding bytes must be sent in order to change one of the control bytes. The 2-wire control interface allows each clock
output to be individually enabled or disabled. 100 Kbits/second (standard mode) data transfer is supported. It also allows
24/48 MHz frequency selection and test mode enable as well as Spread Spectrum programmability.
During normal data transfer, the SDATA signal only changes when the SCLK signal is low, and is stable when SCLK is
high. There are two exceptions to this. A high to low transition on SDATA while SCLK is high is used to indicate the
start of a data transfer cycle. A low to high transition on SDATA while SCLK is high indicates the end of a data transfer
cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer
cycle is a 7-bit address with a Read/Write bit (R/W#) as the LSB. R/W# = 1 in read mode (see note1, below). R/W# = 0
in write mode.
The device will respond to writes to 10 bytes (max) of data to address D2 by generating the acknowledge (low) signal on
the SDATA wire following reception of each byte. If the device should be read then an address D3 must be sent. Data
is transferred MSB first at a max rate of 100kbits/S. The device will not respond to any other control interface conditions,
and previously set control registers are retained.
IMI Device
ACK
ACK
ACK
ACK
ACK
Master Device
SDATA
COMMAND BYTE
(Don't Care)
BYTE COUNT
(Don't Care)
BYTE 0
(Valid)
BYTE N
(Valid)
1
1
0
1
0
0
1
0
MSB
LSB
8
8
8
8
SCLK
STOP CONDITION
Fig.3a (WRITE)
IMI Device
0 1
ACK BYTE COUNT
BYTE 0
(Valid)
BYTE1
(Valid)
BYTE N
(Valid)
Master Device
SDATA
NO ACK
ACK
ACK
ACK
1
1
0
1
0
1
(Valid)
MSB
LSB
8
8
8
8
SCLK
START CONDITION
STOP CONDITION
Fig.3b (READ)
Fig.3
Note1: Should the device be read, the address must be D3, therefore, the address’ LSB is a 1 (for READ). After the device receives
the address it will generate an acknowledge then immediately starts outputting data on the SDATA line. Data is transmitted
following the Philips I2C standard. After each full byte is transmitted the device will wait for an acknowledge from the receiver before
transmitting the next byte. The transmission will end when the device detects a Stop condition generated by the receiver.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
http://www.imicorp.com
Rev.1.0
4/25/2000
Page 4 of 14
C9806I
I2C Frequency Clock Generator for Mobile Pentium® II Applications.
Preliminary
Serial Control Registers
NOTE: The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true
power up. Bytes are set to the values shown only on true power up, and not when the PWR_DWN# pin is activated.
Following the acknowledge of the Address Byte (D2), two additional bytes must be sent:
1) “Command Code “ byte, and
2) “Byte Count” byte.
Although the data (bits) in these two bytes are considered “don’t care”; they must be sent and will be acknowledged.
Byte 0: Function Select Register
Bit
@Pup
Pin#
Description
7
6
5
4
3
2
1
0
0
1
1
1
1
1
0
0
Reserved
*
*
*
*
22
23
SST2* (see table5, p.7)
SST1* (see table5, p.7)
SST0* (see table5, p.7)
24/48M, 1 selects 48mhz, 0 selects 24MHz.
24/48M, 1 selects 48mhz, 0 selects 24MHz.
Bit1 Bit0
1
1
0
0
1 Tri-State (all outputs)
Spread Spectrum enabled
1 Test Mode
NON spread spectrum operating mode
0
0
Byte 1: CPU, AGP, 48/24 MHz Register (1 = Enable, 0
= Stopped)
Byte 2: PCI Register (1 = Enable, 0 = Stopped)
Bit
7
6
5
4
3
2
@Pup
Pin#
22
23
-
-
38
39
Description
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
-
8
16
14
13
12
11
9
Description
Reserved
1
1
x
x
1
1
48/24 MHz Enable/Stopped
48/24 MHz Enable/Stopped
Reserved
x
1
1
1
1
1
1
1
PCICLK_F Enable/Stopped
PCICLK5 Enable/Stopped
PCICLK4 Enable/Stopped
PCICLK3 Enable/Stopped
PCICLK2 Enable/Stopped
PCICLK1 Enable/Stopped
PCICLK0 Enable/Stopped
Reserved
SDRAM_FB Enable/Stopped
If programmed to 0, CPU0
will be independent of
CPU_STP# condition
CPU1 Enable/Stopped
CPU0 Enable/Stopped
1
0
1
1
41
42
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
http://www.imicorp.com
Rev.1.0
4/25/2000
Page 5 of 14
C9806I
I2C Frequency Clock Generator for Mobile Pentium® II Applications.
Preliminary
Serial Control Registers (Continued)
Byte 3: SDRAM Register (1 = Enable, 0 = Stopped)
* SST (0:2) are soft select pins used for setting the
Spread Spectrum width options. See Spread
Spectrum description next section.
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
26
27
29
30
32
33
35
36
Description
Reserved
Reserved
SDRAM5 Enable/Stopped
SDRAM4 Enable/Stopped
SDRAM3 Enable/Stopped
SDRAM2 Enable/Stopped
SDRAM1 Enable/Stopped
SDRAM0 Enable/Stopped
1
1
1
1
1
1
1
1
Byte 6: Dial-a-Frequency™ Register
Bit
@Pup
Pin#
Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
N7, MSB
N6
N5
N4
N3
N2
N1
N0, LSB
Byte 4: SDRAM Register (1 = Enable, 0 = Stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
x
x
x
x
x
x
x
x
-
-
-
-
-
-
-
-
Byte 7: Dial-a-Frequency™ Register
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
Description
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
Reserved
Reserved
R5
R4
R3
R2
R1
R0
Byte 5: Peripheral Control (1 = Enable, 0 = Stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
-
-
47
45
-
-
1
2
Description
Reserved
Reserved
REF3 Enable/Stopped
REF2 Enable/Stopped
Reserved
Reserved
REF1 Enable/Stopped
REF0 Enable/Stopped
Byte 8: Dial-a-Frequency™ Register
x
x
1
1
x
x
1
1
Bit
7
@Pup
Pin#
Description
Enable I2C N values
Enable I2C R values
Reserved
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
6
5
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
Reserved
Dial-a-Frequency™ Feature
I2C Dial-a-frequency feature is available in this device via bytes 6, 7 and 8.
These bytes allow the user to enter the N and R values that will enable them to program any CPU frequency desired
following the formula:
P × N
Fcpu =
Equ.(1)
R
Where N and R values are programmed in binary into bytes 6 & 7 for N and byte 8 for R. See table below for min and
max allowed values.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
http://www.imicorp.com
Rev.1.0
4/25/2000
Page 6 of 14
C9806I
I2C Frequency Clock Generator for Mobile Pentium® II Applications.
Preliminary
Dial-a-Frequency™ Feature (Cont.)
R
Min N
44
45
46
47
48
49
50
51
Max N
87
90
92
94
96
98
100
102
104
107
42
43
44
45
46
47
48
49
50
51
52
53
P is a large value PLL constant that depends on the last frequency selection achieved through the hardware selectors
(S3, S2, S1, S0) or through the software selectors (byte0, bits7,6,5,4). P value may be determined from the following
table:
S(3:0)
P
0000
0001, 1011
0010, 0011, 0101,1001, 1010
0110, 0111, 1000, 11xx
32005333
48008000
64010666
96016000
Therefore, if a 145MHz (use 145x106 )value is desired, then we should apply 145 into equation 1, and start by choosing
R to be 47 (assume the last frequency selection has the value P = 96016000):
145X106 = 96016000 X N
47
=> N = 70.97775371
Since this N number must be entered in Binary, it can only be an integer, so it must be rounded up or down. Here we
can rounded it up to 71, which will give us an exact CPU frequency of:
Fcpu = 96016000 X N = 145.045 MHz (accuracy + 310 ppm)
47
If the above frequency is not accurate enough, then you must choose another R value and start from the beginning. For
example choose R = 49 and this will yield an N = 73.99808365, which is rounded to 74. If the 74 is applied in the
formula 1, then Fcpu = 145.0038 MHz(accuracy + 26 ppm).
Other R values within the above limits may also be evaluated.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
http://www.imicorp.com
Rev.1.0
4/25/2000
Page 7 of 14
C9806I
I2C Frequency Clock Generator for Mobile Pentium® II Applications.
Preliminary
Reducing Clock Noise with Power Bypassing
RX
25
3.3 Volt VDD
.I nF
Figure 4
The C9806I produces many different frequency clocks simultaneously. If these clocks are allowed to couple back into
the Internal Analog circuitry that may cause a destablizing noise injection condition. To eliminate this potential problem
and produce the cleanest design and clock outputs, IMI recommends bypassing the 3.3V VDD supply to the Analog
Power Pin (pin 25) with the circuitry shown in Figure 4. This will effectively isolate the device’s Analog Power Supply from
any noise that is present on it that will cause increased jitter and phase noise within it internal analog circuitry.
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is a modulation technique applied here for maximum efficiency in minimizing Electro-Magnetic
Interference radiation generated from repetitive digital signals mainly clocks. A clock accumulates EM energy at the
center frequency it is generating. Spread Spectrum distributes this energy over a small frequency bandwidth therefore
spreading the same amount of energy over a spectrum. This technique is achieved by modulating the clock down from
or around the center of its resting frequency by a certain percentage (which also determines the energy distribution
bandwidth). In this device, Spread Spectrum is enabled by setting I2C byte0, bit1 = 1, and bit0 = 0. The default of the
device at power up keeps the Spread Spectrum disabled, it is therefore, important to have I2C accessibility to turn-on the
Spread Spectrum function. Once the Spread Spectrum is enabled, the spread bandwidth option is selected by SST (0:2)
in I2C byte 0, bits 4, 5 & 6 following table 4 below.
Down Spread
Center Spread
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
http://www.imicorp.com
Rev.1.0
4/25/2000
Page 8 of 14
C9806I
I2C Frequency Clock Generator for Mobile Pentium® II Applications.
Preliminary
Spread Spectrum Bandwidth Selection Table.
SST2 SST1 SST0 Bandwidth
Direction
Center
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
+/- 0.75%
+/- 0.5%
+/-0.35%
+/-0.25%
-1.5%
Center
Center
Center
Down
-1%
Down
- 0.7%
Down
- 0.5%
Down (default)
Table 4.
Maximum Ratings
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Maximum Input Voltage Relative to VSS: VSS - 0.3V
Maximum Input Voltage Relative to VDD: VDD + 0.3V
Storage Temperature:
Operating Temperature:
Maximum ESD protection
Maximum Power Supply:
-65°C to + 150°C
0°C to +85°C
2000V
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
5.5V
DC Parameters
Characteristic
Symbol Min Typ
Max
0.8
-
Units
Vdc
Vdc
Vdc
Vdc
µA
Conditions
S(0:1), PCI_STP#,
Input Low Voltage
VIL
VIH
-
-
-
-
-
Input High Voltage
2.0
-
CPU_STOP#, PWR_DWN#
Input Low Voltage
VIL
1
SDATA
SCLK
Input High Voltage
VIH
2.2
-
Input Low Current, Vin = VSS
Input High Current, Vin = VDD
Input Low Current, Vin = VSS
Input High Current, Vin = VDD
Tri-State leakage Current
Dynamic Supply Current, 3.3V
Dynamic Supply Current, 2.5V
Static Supply Current
IIL1
-66
5
Pull-up at S1, PCI_STP#,
CPU_STP#, PWR_DWN#
IIH1
IIL2
µA
5
µA
Pull-own at S0.
IIH2
Ioz
66
10
185
30
200
µA
-
-
-
-
-
-
-
-
µA
Idd3.3
Idd2.5
Isdd
mA
mA
µA
CPU = 100 MHz, Note 1
CPU = 100 MHz, Note 1
PWR_DWN# = 0
Note 1: All outputs are loaded as per Table 5. CPU(0:1) outputs are measure at 1.25V. SDRAM (FB, 0:5), PCI(F,0:5), REF (0:2),
24/48M outputs are measured at 1.5V.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
http://www.imicorp.com
Rev.1.0
4/25/2000
Page 9 of 14
C9806I
I2C Frequency Clock Generator for Mobile Pentium® II Applications.
Preliminary
AC Parameters
Characteristic
Symbol Mi
n
Typ Max Units
Conditions
Output Duty Cycle
CPU to PCI Offset
-
45
1
50
-
55
4
%
Note 1,
Note 1
Note 1
tOFF
nS
pS
Skew: (CPU-CPU), (PCI-PCI),
(SDRAM-SDRAM)
tSKEW1
-
-
175
-
-
250
pS
Note 1
∆Period Adjacent Cycles
∆P
VDD = VDDP = VDDF = VDDR = VDDA = 3.3V ± 5%, VDDC = 2.5 ± 5%, TA = 0ºC to +70ºC
Note 1: All outputs are loaded as per Table 5. CPU (0:1) outputs are measured at 1.25V.
SDRAM (FB, 0:5), PCI (F, 0:5), REF (0:2), 24/48M outputs are measured at 1.5V.
Signal Name
Load, (max), pF
CPU(0:1), 24/48mhz, REF(0:2)
SDRAM(FB,0:5), PCI(_F,0:5)
20
30
Table 5
Buffer Characteristics for CPU (0:1),
Characteristic
Symbol
Min
-15
-30
12
Typ
Max
Units
Conditions
Vout =VDDC - 0.5V
Pull-Up Current
IOH1
-
-
-
-
-
-
-
-
-
mA
mA
mA
mA
nS
Pull-Up Current
IOH2
Vout = VDDC/2
Vout = 0.4 V
Vout = VDDC/2
Note1
Pull-Down Current
Pull-Down Current
Rise/Fall Time, @ 0.4V-2.0V
IOL1
IOL2
24
Tr, Tf
0.4
1.3
Buffer Characteristics for PCI(0:5, _F)
Characteristic
Symbol
IOH1
Min
-14
-35
13
Typ
Max
Units
mA
mA
mA
mA
nS
Conditions
Pull-Up Current
-
-
-
-
-
-
-
Vout =VDD - 0.5V
Vout = VDD/2
Vout = 0.4 V
Vout = VDD/2
Note1
Pull-Up Current
IOH2
Pull-Down Current
Pull-Down Current
Rise/Fall Time, @ 0.4V-2.4V
IOL1
-
IOL2
40
-
Tr, Tf
0.4
2
Buffer Characteristics for 24/48 MHz , REF(0:2)
Characteristic
Symbol
IOH1
Min
-6
Typ
Max
Units
mA
mA
mA
mA
nS
Conditions
Pull-Up Current
-
-
-
-
-
-
-
Vout =VDD - 0.5V
Vout = VDD/2
Vout = 0.4 V
Vout = VDD/2
Note1
Pull-Up Current
IOH2
-15
6
Pull-Down Current
Pull-Down Current
Rise/Fall Time, @ 0.4V-2.4V
IOL1
-
IOL2
22
0.4
-
Tr, Tf
4
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
http://www.imicorp.com
Rev.1.0
4/25/2000
Page 10 of 14
C9806I
I2C Frequency Clock Generator for Mobile Pentium® II Applications.
Preliminary
Buffer Characteristics for SDRAM(0:5)
Characteristic
Symbol
Min
-20
-56
19
Typ
Max
Units
mA
mA
mA
mA
nS
Conditions
Vout =VDD - 0.5V
Pull-Up Current
IOH1
-
-
-
-
-
-
-
-
-
Pull-Up Current
IOH2
Vout = VDD/2
Vout = 0.4 V
Vout = VDD/2
Note1
Pull-Down Current
Pull-Down Current
Rise/Fall Time, @ 0.4V-2.4V
IOL1
IOL2
63
Tr, Tf
0.4
1.3
VDD = VDDS =3.3V ±5%, VDDC = 2.5 + 5%, TA = 0ºC to +70ºC
Note 1: All outputs are loaded as per Table 6. CPU(0:1) outputs are measure at 1.25V. SDRAM (FB, 0:5), PCI(F,0:5), REF (0:2),
24/48M outputs are measured at 1.5V.
Crystal and Reference Oscillator Parameters
Characteristic
Symbol
Min
Typ
Max
16.00
+/-100
+/- 100
5
Units
MHz
PPM
PPM
PPM
Conditions
Frequency
Fo
12.00
14.31818
Tolerance
TC
-
-
-
-
-
-
-
Calibration note 1
TS
Stability (Ta -10 to +60C) Note 1
Aging (first year @ 25C) Note 1
Parallel Resonant
TA
Mode
OM
CP
-
-
Pin Capacitance
36
pF
Capacitance of XIN and Xout pins to
ground (each)
DC Bias Voltage
Startup time
VBIAS
Ts
0.3Vdd
Vdd/2
0.7Vdd
V
µS
-
-
-
-
20
-
30
-
Load Capacitance
CL
pF
The crystal’s rated load. Note 1
Note 1
Effective Series
resistance (ESR)
R1
40
Ohms
Power Dissipation
Shunt Capacitance
DL
-
-
-
0.10
8
mW
pF
Crystal’s internal package
capacitance (total)
CO
--
For maximum accuracy, the total circuit loading capacitance should be equal to CL. This loading capacitance is the
effective capacitance across the crystal pins and includes the device pin capacitance (CP) in parallel with any circuit
traces, the clock generator and any onboard discrete load capacitors.
Budgeting Calculations
Typical trace capacitance, (< half inch) is 4 pF, Load to the crystal is therefore
Clock generator internal pin capacitance of 36 pF, Load to the crystal is therefore
The total parasitic capacitance would therefore be
=
=
2.0 pF
18.0 pF
= 20.0 pF.
Note 1: It is recommended but not mandatory that a crystal meets these specifications.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
http://www.imicorp.com
Rev.1.0
4/25/2000
Page 11 of 14
C9806I
I2C Frequency Clock Generator for Mobile Pentium® II Applications.
Preliminary
PCB Layout Suggestion
Via to VDD Island
Via to GND Plane
IMIC9806I
VCC3.3V
FB1
C12
C11
48
47
1
2
3
4
5
6
46
45
44
43
42
41
40
FB2
C3
22µF
CC2.5V
C4
7
8
C10
C9
C14
22µF
9
39
38
37
36
35
10
11
12
13
14
C5
C6
34
15
33
32
31
30
29
16
17
18
19
20
C8
RX
28
27
26
21
22
23
24
25
C7
This is only a layout recommendation for best performance and lower EMI. The designer may choose a
different approach but C4, C5, C6, C7, C8, C9, C10; C11and C12 (all are 0.1µf) should always be used and
placed close to their VDD pins.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
http://www.imicorp.com
Rev.1.0
4/25/2000
Page 12 of 14
C9806I
I2C Frequency Clock Generator for Mobile Pentium® II Applications.
Preliminary
Package Drawing and Dimensions
48 Pin SSOP Outline Dimensions
INCHES
MILLIMETERS
C
SYMBOL
MIN
NOM
MAX
MIN
2.41
NOM
2.59
MAX
2.79
L
A
A1
A2
B
0.095
0.008
0.088
0.008
0.005
0.620
0.291
0.102
0.110
0.016
0.092
0.0135
0.010
0.630
0.299
H
E
0.012
0.203 0.305 0.406
-
2.24
0.203
0.127
-
-
-
2.34
-
0.343
0.254
C
D
E
-
D
a
0.625
15.75 15.88 16.00
A2
A
0.295
7.39
7.49
7.60
e
0.025 BSC
0.635 BSC
A1
H
L
0.395
0.020
0º
-
-
-
0.420
0.040
8º
10.03
0.508
0º
-
-
-
10.67
1.016
8º
e
B
a
48 Pin TSSOP Outline Dimensions
INCHES
MILLIMETERS
SYMBOL
MIN
NOM
MAX
MIN
-
NOM
MAX
1.20
0.15
1.05
0.27
0.20
A
A1
A2
B
-
-
0.047
0.006
0.041
0.011
0.008
0.496
0.244
-
0.002
0.031
0.007
0.004
0.488
0.236
-
0.039
-
0.05
0.80
0.17
0.09
-
1.00
-
-
C
D
E
-
0.492
0.240
0.02 BSC
0.319
0.024
-
12.40 12.50 12.60
6.00
6.10
0.50 BSC
8.10
6.20
e
H
L
0.315
0.018
0º
0.323
0.030
8º
8.00
0.45
0º
8.20
0.75
8º
0.60
a
-
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
http://www.imicorp.com
Rev.1.0
4/25/2000
Page 13 of 14
C9806I
I2C Frequency Clock Generator for Mobile Pentium® II Applications.
Preliminary
Ordering Information
Part Number
IMIC9806IAY
IMIC9806IAT
Package Type
Production Flow
48 PIN SSOP
Commercial, 0ºC to +70ºC
Commercial, 0ºC to +70ºC
48 PIN TSSOP
Note:
The ordering part number is formed by a combination of device number, device revision, package style, and
screening as shown below.
Marking: Example: IMI
C9806IAY
Date Code, Lot #
IMIC9806IAY
Package
Y = SSOP
T = TSSOP
Revision
IMI Device Number
Purchase of I2C components of International Microcircuits, Inc. or one of its sublicensed Associated Companies
conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the
system conforms to the I2C Standard Specification as defined by Philips.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
http://www.imicorp.com
Rev.1.0
4/25/2000
Page 14 of 14
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