CY7C185D-15PXC [CYPRESS]
64K (8K x 8) Static RAM; 64K （ 8K ×8 ）静态RAM
| 型号： | CY7C185D-15PXC |
| 厂家： | 
CYPRESS |
| 描述： | 64K (8K x 8) Static RAM |
| 文件： | 总10页 (文件大小：182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
CY7C185D
64K (8K x 8) Static RAM
Features
Functional Description[1]
• Pin- and function-compatible with CY7C185
• High speed
The CY7C185D is a high-performance CMOS static RAM
organized as 8192 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE1), an active
HIGH chip enable (CE2), and active LOW output enable (OE)
and three-state drivers. This device has an automatic
power-down feature (CE1 or CE2), reducing the power
consumption when deselected.
— tAA = 10 ns
• Low active power
— ICC = 60 mA @ 10 ns
• Low CMOS standby power
— ISB2 = 3 mA
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE1 and WE
inputs are both LOW and CE2 is HIGH, data on the eight data
input/output pins (I/O0 through I/O7) is written into the memory
location addressed by the address present on the address
pins (A0 through A12). Reading the device is accomplished by
selecting the device and enabling the outputs, CE1 and OE
active LOW, CE2 active HIGH, while WE remains inactive or
HIGH. Under these conditions, the contents of the location
addressed by the information on address pins are present on
the eight data input/output pins.
• CMOS for optimum speed/power
• Data Retention at 2.0V
• Easy memory expansion with CE1, CE2, and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• Available in Lead (Pb)-Free Packages
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.The CY7C185D is in a standard 28-pin
300-mil-wide DIP, SOJ, or SOIC Pb-Free package.
Logic Block Diagram
Pin Configurations
DIP/SOJ/SOIC
Top View
NC
V
CC
1
2
3
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
WE
CE
4
A
5
2
I/O
I/O
0
A
A
3
6
4
5
INPUT BUFFER
A
A
2
A
1
OE
7
1
A
8
A
9
6
7
8
9
10
11
12
13
14
A
A
0
10
11
12
A
1
I/O
I/O
2
A
A
CE
1
A
2
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
A
3
3
I/O
0
I/O
1
I/O
2
A
256 x 32 x 8
ARRAY
4
A
5
I/O
I/O
I/O
I/O
4
5
6
7
A
GND
6
A
7
A
8
POWER
DOWN
CE
1
COLUMN DECODER
CE
2
WE
OE
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05466 Rev. *C
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised January 10, 2005
CY7C185D
PRELIMINARY
Selection Guide
CY7C185D-10
CY7C185D-12
CY7C185D-15
Unit
ns
Maximum Access Time
10
60
3
12
50
3
15
40
3
Maximum Operating Current
Maximum Standby Current
mA
mA
Document #: 38-05466 Rev. *C
Page 2 of 10
CY7C185D
PRELIMINARY
DC Input Voltage[2].................................... −0.5V to VCC + 0.5V
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage to Ground Potential............... –0.5V to +7.0V
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
VCC
DC Voltage Applied to Outputs
5V ± 10%
5V ± 10%
in High-Z State[2] ....................................... −0.5V to VCC + 0.5V
–40°C to +85°C
Electrical Characteristics Over the Operating Range
7C185D-10
7C185D-12
Parameter
VOH
VOL
VIH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[2]
Input Load Current
Test Conditions
Min.
2.4
Max.
Min.
Max.
Unit
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
2.4
V
V
0.4
0.4
2.0 VCC + 0.3V 2.0 VCC + 0.3V
V
VIL
–0.5
–1
0.8
+1
–0.5
–1
0.8
+1
V
IIX
GND ≤ VI ≤ VCC
µA
µA
mA
mA
mA
IOZ
Output Leakage Current
Output Short Circuit Current[3] VCC = Max., VOUT = GND
GND ≤ VI ≤ VCC, Output Disabled
–1
+1
–1
+1
IOS
–300
60
–300
50
ICC
VCC Operating Supply Current VCC = Max., IOUT = 0 mA
ISB1
Automatic Power-down Current Max. VCC, CE1 ≥ VIH or CE2 ≤ VIL
10
10
Min. Duty Cycle = 100%
ISB2
Automatic Power-down Current Max. VCC, CE1 ≥ VCC – 0.3V,
or CE2 ≤ 0.3V
3.0
3.0
mA
VIN ≥ VCC – 0.3V or VIN ≤ 0.3V
7C185D-15
Parameter
VOH
VOL
VIH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[2]
Input Load Current
Test Conditions
VCC = Min., IOH = –4.0 mA
Min.
2.4
Max.
Unit
V
VCC = Min., IOL = 8.0 mA
0.4
V
2.0 VCC + 0.3V
V
VIL
–0.5
–1
0.8
+1
V
IIX
GND ≤ VI ≤ VCC
µA
µA
mA
mA
mA
IOZ
Output Leakage Current
Output Short Circuit Current[3] VCC = Max., VOUT = GND
GND ≤ VI ≤ VCC, Output Disabled
–1
+1
IOS
–300
40
ICC
VCC Operating Supply Current VCC = Max., IOUT = 0 mA
ISB1
Automatic Power-down Current Max. VCC, CE1 ≥ VIH or CE2 ≤ VIL
10
Min. Duty Cycle = 100%
ISB2
Automatic Power-down Current Max. VCC, CE1 ≥ VCC – 0.3V or CE2 ≤ 0.3V
VIN ≥ VCC – 0.3V or VIN ≤ 0.3V
3.0
mA
Capacitance[4]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Max.
Unit
CIN
TA = 25°C, f = 1 MHz,
CC = 5.0V
7
7
pF
pF
V
COUT
Notes:
2. V (min.) = –2.0V and V (max) = V + 2V for pulse durations of less than 20 ns.
IL
IH
CC
3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05466 Rev. *C
Page 3 of 10
CY7C185D
PRELIMINARY
Thermal Resistance[4]
Parameter
ΘJA
Description
Test Conditions
All-Packages
Unit
Thermal Resistance
Still Air, soldered on a 3 × 4.5 inch, two-layer
printed circuit board
TBD
°C/W
(Junction to Ambient)[4]
ΘJC
Thermal Resistance
(Junction to Case)[4]
TBD
°C/W
AC Test Loads and Waveforms
10-ns Device
ALL INPUT PULSES
90%
Z = 50Ω
3.0V
GND
OUTPUT
90%
10%
10%
50Ω
1.5V
30 pF*
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
≤ 3 ns
R1 481Ω
≤ 3 ns
12, 15-ns Devices
High-Z characteristics:
R1 481Ω
5V
OUTPUT
(a)
5V
OUTPUT
Equivalent to:
THÉVENIN EQUIVALENT
30 pF
R2
255Ω
5 pF
R2
255Ω
INCLUDING
JIG AND
SCOPE
INCLUDING
JIGAND
167Ω
OUTPUT
1.73V
SCOPE
(b)
(c)
Switching Characteristics Over the Operating Range [6]
7C185D-10
7C185D-12
7C185D-15
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle
[5]
tpower
VCC(typical) to the first access
Read Cycle Time
100
10
100
12
100
15
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
tAA
Address to Data Valid
Data Hold from Address Change
CE1 LOW to Data Valid
CE2 HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z[7]
CE1 LOW to Low Z[8]
CE2 HIGH to Low Z
10
12
15
tOHA
3
3
3
tACE1
tACE2
tDOE
10
10
5
12
12
6
15
15
8
tLZOE
tHZOE
tLZCE1
tLZCE2
tHZCE
3
3
3
5
5
6
6
7
7
3
3
3
3
3
3
CE1 HIGH to High Z[7, 8]
CE2 LOW to High Z
tPU
CE1 LOW to Power-Up
CE2 to HIGH to Power-Up
0
0
0
ns
ns
tPD
CE1 HIGH to Power-Down
CE2 LOW to Power-Down
10
12
15
Notes:
5. t
gives the minimum amount of time that the power supply should be at typical V values until the first memory access can be performed.
CC
POWER
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I and 30-pF load capacitance.
OL OH
7. t
t
, and t
are specified with C = 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady state voltage.
HZOE, HZCE
HZWE L
8. At any given temperature and voltage condition, t
is less than t
and t
for any given device.
HZCE
LZCE1
LZCE2
Document #: 38-05466 Rev. *C
Page 4 of 10
CY7C185D
PRELIMINARY
Switching Characteristics Over the Operating Range (continued)[6]
7C185D-10
7C185D-12
Min. Max.
7C185D-15
Parameter
Write Cycle[9]
tWC
Description
Min.
Max.
Min.
Max.
Unit
Write Cycle Time
10
8
12
10
10
10
0
15
12
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE1
tSCE2
tAW
CE1 LOW to Write End
CE2 HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
8
7
tHA
0
tSA
0
0
0
tPWE
7
10
7
12
8
tSD
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z[7]
6
tHD
0
0
0
tHZWE
tLZWE
6
6
7
WE HIGH to Low Z
3
3
3
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
ICCDR
Description
VCC for Data Retention
Data Retention Current
Conditions
Min.
Max.
Unit
V
2.0
VCC = VDR = 2.0V,
CE > VCC – 0.3V,
IN > VCC – 0.3V or
3
mA
mA
ns
Non-L, Com’l / Ind’l
L-Version Only
1.2
V
[4]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
VIN < 0.3V
0
[10]
tR
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
4.5V
4.5V
VDR > 2V
V
CC
t
t
R
CDR
CE
Switching Waveforms
Read Cycle No.1[11,12]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Notes:
9. The internal write time of the memory is defined by the overlap of CE LOW, CE HIGH, and WE LOW. All 3 signals must be active to initiate a write and either
1
2
signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
10. Full device operation requires linear V ramp from V to V > 50 µs or stable at V > 50 µs.
CC
DR
CC(min.)
CC(min.)
11. Device is continuously selected. OE, CE = V . CE = V .
1
IL
2
IH
12. WE is HIGH for read cycle.
Document #: 38-05466 Rev. *C
Page 5 of 10
CY7C185D
PRELIMINARY
Switching Waveforms (continued)
Read Cycle No.2[13,14]
t
RC
CE
1
CE
2
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
ICC
V
CC
SUPPLY
CURRENT
50%
50%
ISB
Write Cycle No. 1 (WE Controlled)[12,14]
t
WC
ADDRESS
t
CE
1
SCEI
t
t
HA
AW
t
CE
SCE2
2
t
SA
t
PWE
WE
OE
t
SD
t
HD
DATA VALID
IN
NOTE 15
DATA I/O
t
HZOE
Write Cycle No. 2 (CE Controlled)[14,15,16]
t
WC
ADDRESS
t
CE
1
SCE1
t
SA
t
SCE2
CE
2
t
t
HA
AW
WE
t
t
HD
SD
DATA VALID
DATA I/O
IN
Notes:
13. Data I/O is High Z if OE = V , CE = V , WE = V , or CE =V .
IL
IH
1
IH
IL
2
14. The internal write time of the memory is defined by the overlap of CE LOW, CE HIGH and WE LOW. CE and WE must be LOW and CE must be HIGH to
1
2
1
2
initiate write. A write can be terminated by CE or WE going HIGH or CE going LOW. The data input set-up and hold timing should be referenced to the rising
1
2
edge of the signal that terminates the write.
15. During this period, the I/Os are in the output state and input signals should not be applied.
16. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
and t
.
HZWE
SD
Document #: 38-05466 Rev. *C
Page 6 of 10
CY7C185D
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[14,15,16,17]
t
WC
ADDRESS
t
CE
SCE1
1
t
CE
SCE2
2
t
t
HA
AW
t
SA
WE
t
t
HD
SD
DATA I/O
NOTE 15
DATA VALID
IN
t
t
LZWE
HZWE
Truth Table
CE1
H
CE2
X
WE
X
OE
X
Input/Output
Mode
High Z
High Z
Deselect/Power-down
Deselect/Power-down
Read
X
L
X
X
L
H
H
L
Data Out
Data In
High Z
L
H
L
X
Write
L
H
H
H
Deselect
Ordering Information
Speed
Package
Operating
Range
(ns)
Ordering Code
CY7C185D-10PXC
CY7C185D-10SXC
CY7C185D-10VXC
CY7C185D-10VXI
CY7C185D-12PXC
CY7C185D-12SXC
CY7C185D-12VXC
CY7C185D-12VXI
CY7C185D-15PXC
CY7C185D-15SXC
CY7C185D-15VXC
CY7C185D-15VXI
Name
P21
S21
V21
V21
P21
S21
V21
V21
P21
S21
V21
V21
Package Type
10
28-Lead (300-Mil) Molded DIP (Pb-Free)
28-Lead Molded SOIC (Pb-Free)
28-Lead Molded SOJ (Pb-Free)
28-Lead Molded SOJ (Pb-Free)
28-Lead (300-Mil) Molded DIP (Pb-Free)
28-Lead Molded SOIC (Pb-Free)
28-Lead Molded SOJ (Pb-Free)
28-Lead Molded SOJ (Pb-Free)
28-Lead (300-Mil) Molded DIP (Pb-Free)
28-Lead Molded SOIC (Pb-Free)
28-Lead Molded SOJ (Pb-Free)
28-Lead Molded SOJ (Pb-Free)
Commercial
Industrial
12
15
Commercial
Industrial
Commercial
Industrial
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Note:
17. If CE goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
1
2
Document #: 38-05466 Rev. *C
Page 7 of 10
CY7C185D
PRELIMINARY
Package Diagrams
28-Lead (300-Mil) PDIP P21
SEE LEAD END OPTION
14
1
MIN.
DIMENSIONS IN INCHES [MM]
MAX.
REFERENCE JEDEC MO-095
PACKAGE WEIGHT: 2.15 gms
0.260[6.60]
0.295[7.49]
15
28
0.030[0.76]
0.080[2.03]
SEATING PLANE
1.345[34.16]
1.385[35.18]
0.290[7.36]
0.325[8.25]
0.120[3.05]
0.140[3.55]
0.140[3.55]
0.190[4.82]
0.009[0.23]
0.012[0.30]
0.115[2.92]
0.160[4.06]
3° MIN.
0.015[0.38]
0.060[1.52]
0.055[1.39]
0.065[1.65]
0.310[7.87]
0.385[9.78]
0.090[2.28]
0.110[2.79]
0.015[0.38]
0.020[0.50]
SEE LEAD END OPTION
51-85014-*D
LEAD END OPTION
(LEAD #1, 14, 15 & 28)
28-Lead (300-Mil) Molded SOIC S21
PIN 1 ID
14
1
MIN.
DIMENSIONS IN INCHES[MM]
MAX.
*
0.394[10.01]
0.419[10.64]
REFERENCE JEDEC MO-119
PACKAGE WEIGHT 0.85gms
0.291[7.39]
0.300[7.62]
PART #
15
28
0.026[0.66]
0.032[0.81]
S28.3 STANDARD PKG.
SZ28.3 LEAD FREE PKG.
SEATING PLANE
0.697[17.70]
0.713[18.11]
0.092[2.33]
0.105[2.67]
*
0.004[0.10]
0.0091[0.23]
0.050[1.27]
TYP.
0.015[0.38]
0.050[1.27]
0.013[0.33]
0.019[0.48]
*
0.004[0.10]
0.0125[3.17]
0.0118[0.30]
51-85026-*C
Document #: 38-05466 Rev. *C
Page 8 of 10
CY7C185D
PRELIMINARY
Package Diagrams (continued)
28-Lead (300-Mil) Molded SOJ V21
51-85031-*B
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05466 Rev. *C
Page 9 of 10
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C185D
PRELIMINARY
Document History Page
Document Title: CY7C185D 64K (8K x 8) Static RAM (Preliminary)
Document Number: 38-05466
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
201560
233715
See ECN
See ECN
SWI
RKF
Advance Datasheet for C9 IPP
*A
DC parameters are modified as per EROS (Spec # 01-2165)
Pb-free offering in Ordering Information
*B
262950
307593
See ECN
See ECN
RKF
RKF
Added Tpower Spec in Switching Characteristics table
Added Data Retention Characteristics table and waveforms
Shaded Ordering Information
*C
1) Reduced Speed bins to -10, -12 and -15 ns
2) Added ‘Industrial’ grade parts to the Ordering Info on Page #6
Document #: 38-05466 Rev. *C
Page 10 of 10
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