CY7C185_11 [CYPRESS]
64-Kbit (8 K × 8) Static RAM CMOS for optimum speed/power; 64千位（为8K × 8 ）静态CMOS RAM以获得最佳速度/功耗
| 型号： | CY7C185_11 |
| 厂家： | 
CYPRESS |
| 描述： | 64-Kbit (8 K × 8) Static RAM CMOS for optimum speed/power |
| 文件： | 总15页 (文件大小：380K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C185
64-Kbit (8 K × 8) Static RAM
Features
Functional Description
■ High speed
❐ 15 ns
The CY7C185[1] is a high-performance CMOS static RAM
organized as 8192 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE1), an active HIGH
chip enable (CE2), and active LOW output enable (OE) and
tri-state drivers. This device has an automatic power-down
feature (CE1 or CE2), reducing the power consumption by 70%
when deselected. The CY7C185 is in a standard 300-mil-wide
DIP, SOJ, or SOIC package.
■ Fast tDOE
■ Low active power
❐ 715 mW
■ Low standby power
❐ 85 mW
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE1 and WE
inputs are both LOW and CE2 is HIGH, data on the eight data
input/output pins (I/O0 through I/O7) is written into the memory
location addressed by the address present on the address pins
(A0 through A12). Reading the device is accomplished by
selecting the device and enabling the outputs, CE1 and OE
active LOW, CE2 active HIGH, while WE remains inactive or
HIGH. Under these conditions, the contents of the location
addressed by the information on address pins are present on the
eight data input or output pins.
■ CMOS for optimum speed/power
■ Easy memory expansion with CE1, CE2 and OE features
■ TTL-compatible inputs and outputs
■ Automatic power-down when deselected
■ Available in non Pb-free 28-pin (300-Mil) Molded SOJ, 28-pin
(300-Mil) Molded SOIC and Pb-free 28-pin (300-Mil) Molded
DIP
The input or output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable (WE)
is HIGH. A die coat is used to insure alpha immunity.
Logic Block Diagram
I/O
I/O
0
INPUT BUFFER
1
A
1
I/O
I/O
2
A
2
A
3
3
A
8K x 8
ARRAY
4
A
5
I/O
I/O
I/O
I/O
4
5
6
A
6
A
7
A
8
POWER
DOWN
CE
1
7
COLUMN DECODER
CE
2
WE
OE
Selection Guide
Description
-15
15
-20
20
-35
35
Maximum Access Time (ns)
Maximum Operating Current (mA)
130
15
110
15
100
15
Maximum CMOS Standby Current (mA)
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05043 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 20, 2011
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CY7C185
Contents
Pin Configuration .............................................................3
Maximum Ratings .............................................................3
Operating Range ...............................................................3
Electrical Characteristics .................................................3
Capacitance ......................................................................4
Switching Characteristics
,Over the Operating Range .................................................5
Switching Waveforms ......................................................6
Typical DC and AC Characteristics ................................9
Truth Table ......................................................................10
Address Designators .....................................................10
Ordering Information ......................................................10
Ordering Code Definitions .........................................10
Package Diagrams ..........................................................11
Acronyms ........................................................................13
Document Conventions .................................................13
Units of Measure .......................................................13
Document History Page .................................................14
Sales, Solutions, and Legal Information ......................15
Worldwide Sales and Design Support .......................15
Products ....................................................................15
PSoC Solutions .........................................................15
Document #: 38-05043 Rev. *E
Page 2 of 15
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CY7C185
Pin Configuration
DIP/SOJ
Top View
NC
V
CC
1
2
3
4
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
WE
CE
4
A
5
2
A
A
3
6
A
A
2
A
1
OE
7
5
A
8
6
7
8
9
10
11
12
13
14
A
9
A
A
A
A
0
10
11
12
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
0
I/O
1
I/O
2
GND
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Static discharge voltage........................................... >2001 V
(per MIL-STD-883, Method 3015)
Storage temperature .................................. –65°C to +150°C
Latch-up current ..................................................... >200 mA
Ambient temperature with
power applied ............................................. –55°C to +125°C
Operating Range
Supply voltage to ground potential ...............–0.5 V to +7.0 V
Ambient
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
VCC
DC voltage applied to outputs
in High Z State[2]...........................................–0.5 V to +7.0 V
5 V ± 10%
5 V ± 10%
DC input voltage[2]........................................–0.5 V to +7.0 V
Output current into outputs (LOW) .............................. 20 mA
Electrical Characteristics
Over the Operating Range
–15
–20
–35
Parameter
VOH
Description
Test Conditions
VCC = Min.,
OH = –4.0 mA
VCC = Min.,
OL = 8.0 mA
Min
Max
Min
Max
Min
Max
Unit
Output HIGH
Voltage
2.4
2.4
2.4
V
I
VOL
VIH
VIL
IIX
Output LOW
Voltage
0.4
0.4
0.4
V
V
I
Input HIGH
Voltage
2.2
–0.5
–5
VCC + 0.3
V
2.2
–0.5
–5
VCC + 0.3 V
2.2
–0.5
–5
VCC + 0.3 V
Input LOW
Voltage[2]
0.8
0.8
+5
0.8
+5
V
Input Leakage GND ≤ VI ≤ VCC
Current
+5
μA
μA
mA
IOZ
ICC
ISB1
Output Leakage GND ≤ VI ≤ VCC
Current Output Disabled
,
–5
+5
–5
+5
–5
+5
VCC Operating VCC = Max.,
Supply Current IOUT = 0 mA
130
40
110
20
100
20
Automatic
Power-down
Current
Max. VCC,
CE1 ≥ VIH or CE2 ≤ VIL
Min. Duty Cycle =100%
mA
mA
ISB2
Automatic
Power-down
Current
Max. VCC
,
15
15
15
CE1 ≥ VCC – 0.3 V,
or CE2 ≤ 0.3 V
VIN ≥ VCC – 0.3 V or
VIN ≤ 0.3 V
Document #: 38-05043 Rev. *E
Page 3 of 15
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CY7C185
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Max
7
Unit
pF
CIN
TA = 25°C, f = 1 MHz,
CC = 5.0 V
V
COUT
7
pF
Figure 1. AC Test Loads and Waveforms
R1 481Ω
R1 481Ω
ALL INPUT PULSES
90%
5 V
OUTPUT
5 V
OUTPUT
3.0 V
GND
90%
10%
10%
30 pF
5 pF
R2
255Ω
R2
255Ω
≤ 5 ns
≤ 5 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIGAND
SCOPE
Equivalent to:
OUTPUT
THÉVENIN EQUIVALENT
(a)
(b)
167Ω
1.73 V
Notes
2. Minimum voltage is equal to –3.0 V for pulse durations less than 30 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05043 Rev. *E
Page 4 of 15
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CY7C185
Switching Characteristics Over the Operating Range[4]
-15
-20
-35
Parameter
Read Cycle
tRC
Description
Min
15
3
Max
Min
20
5
Max
Min
35
5
Max
Unit
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE1 LOW to Data Valid
CE2 HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z[5]
CE1 LOW to Low Z[6]
CE2 HIGH to Low Z
15
20
35
tOHA
tACE1
15
15
8
20
20
9
35
35
15
tACE2
tDOE
tLZOE
3
3
3
tHZOE
tLZCE1
tLZCE2
tHZCE
7
7
8
8
10
10
3
3
5
3
5
3
CE1 HIGH to High Z[5, 6]
CE2 LOW to High Z
tPU
tPD
CE1 LOW to Power-up
CE2 to HIGH to Power-up
0
0
0
ns
ns
CE1 HIGH to Power-down
CE2 LOW to Power-down
15
20
20
Write Cycle[7]
tWC
Write Cycle Time
15
12
12
12
0
20
15
15
15
0
35
20
20
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE1
tSCE2
tAW
CE1 LOW to Write End
CE2 HIGH to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
tHA
tSA
0
0
0
tPWE
tSD
12
8
15
10
0
20
12
0
Data Setup to Write End
Data Hold from Write End
WE LOW to High Z[5]
WE HIGH to Low Z
tHD
0
tHZWE
tLZWE
7
7
8
3
5
5
Notes
4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified I /I
OL OH
and 30-pF load capacitance.
5. t , and t are specified with C = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
t
HZOE, HZCE
HZWE
L
6. At any temperature and voltage condition, t
is less than t
and t
for any given device.
HZCE
LZCE1
LZCE2
7. The internal write time of the memory is defined by the overlap of CE LOW, CE HIGH, and WE LOW. All 3 signals must be active to initiate a write and either signal
1
2
can terminate a write by going HIGH. The data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05043 Rev. *E
Page 5 of 15
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CY7C185
Switching Waveforms
Figure 2. Read Cycle No.1[8,9]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 3. Read Cycle No.2[10,11]
t
RC
CE
1
CE
2
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
ICC
ISB
V
CC
SUPPLY
CURRENT
50%
50%
Notes
8. Device is continuously selected. OE, CE = V . CE = V .
IH
1
IL
2
9. WE is HIGH for read cycle.
10. Data I/O is High Z if OE = V , CE = V , WE = V , or CE =V .
IL
IH
1
IH
IL
2
11. The internal write time of the memory is defined by the overlap of CE LOW, CE HIGH and WE LOW. CE and WE must be LOW and CE must be HIGH to initiate
1
2
1
2
write. A write can be terminated by CE or WE going HIGH or CE going LOW. The data input setup and hold timing must be referenced to the rising edge of the
1
2
signal that terminates the write.
Document #: 38-05043 Rev. *E
Page 6 of 15
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CY7C185
Switching Waveforms (continued)
Figure 4. Write Cycle No. 1 (WE Controlled)[9,11]
t
WC
ADDRESS
t
CE
SCEI
1
t
AW
t
HA
t
CE
SCE2
2
t
SA
t
PWE
WE
OE
t
SD
t
HD
DATA VALID
NOTE 12
t
IN
DATA I/O
HZOE
Figure 5. Write Cycle No. 2 (CE Controlled)[11,12,13]
t
WC
ADDRESS
t
CE
SCE1
1
t
SA
t
SCE2
CE
2
t
t
HA
AW
WE
t
t
HD
SD
DATA VALID
DATA I/O
IN
Notes
12. During this period, the I/Os are in the output state and input signals must not be applied.
13. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
and t
.
HZWE
SD
Document #: 38-05043 Rev. *E
Page 7 of 15
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CY7C185
Switching Waveforms (continued)
Figure 6. Write Cycle No. 3 (WE Controlled, OE LOW)[11,12,13,14]
t
WC
ADDRESS
CE
t
SCE1
1
t
CE
SCE2
2
t
t
HA
AW
t
SA
WE
t
t
HD
SD
DATA I/O
NOTE 12
DATA VALID
IN
t
t
LZWE
HZWE
Note
14. If CE goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
1
2
Document #: 38-05043 Rev. *E
Page 8 of 15
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CY7C185
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
120
100
80
1.4
1.2
1.0
1.2
1.0
0.8
I
I
CC
CC
0.8
0.6
0.4
V
T
A
=5.0 V
=25°C
CC
0.6
0.4
60
40
V
V
=5.0 V
=5.0 V
CC
IN
0.2
0.0
20
0
I
0.2
0.0
SB
I
SB
–55
25
125
0.0
1.0
2.0
3.0
4.0
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
140
120
1.6
1.4
1.4
1.3
1.2
100
80
V
=5.0 V
CC
1.2
1.0
T =25°C
A
1.1
1.0
60
T =25°C
A
V
CC
=5.0 V
40
0.8
20
0
0.9
0.8
0.6
–55
0.0
1.0
2.0
3.0
4.0
25
125
4.0
4.5
5.0
5.5
6.0
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
NORMALIZED I vs. CYCLE TIME
CC
3.0
2.5
2.0
1.5
30.0
25.0
20.0
15.0
1.25
1.00
0.75
0.50
V
=5.0 V
CC
T =25°C
A
V
CC
=0.5 V
1.0
0.5
0.0
10.0
5.0
V
=4.5 V
CC
T =25°C
A
0.0
0.0
1.0
2.0
3.0
4.0
5.0
0
200 400
600 800 1000
10
20
30
40
SUPPLY VOLTAGE (V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
Document #: 38-05043 Rev. *E
Page 9 of 15
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CY7C185
Truth Table
Address Designators
Address
Name
Address
Pin
Input/Out-
put
Function
Number
CE1 CE2 WE OE
Mode
Deselect/
Power-down
A4
A5
X3
2
3
H
X
X
X
High Z
X4
X
L
X
X
High Z
Deselect/
Power-down
A6
X5
4
A7
X6
5
L
L
L
H
H
H
H
L
L
X
H
Data Out
Data In
High Z
Read
A8
X7
6
Write
A9
Y1
7
H
Deselect
A10
A11
A12
A0
Y4
8
Y3
9
Y0
10
21
23
24
25
Y2
A1
X0
A2
X1
A3
X2
Ordering Information
Speed
Package
Operating
Range
(ns)
Ordering Code
Name
Package Type
28-pin (300-Mil) Molded SOJ
15
CY7C185-15VI
CY7C185-20PXC
CY7C185-35SC
51-85031
51-85014
51-85026
Industrial
Commercial
Commercial
20
28-pin (300-Mil) Molded DIP (Pb-free)
28-pin (300-Mil) Molded SOIC
35
Ordering Code Definitions
CY 7 1 85 - XX XX
C
X
Temperature Range: X = C or I
C = Commercial; I = Industrial
Package Type: XX = V or PX or S
V = 28-pin Molded SOJ
PX = 28-pin Molded DIP (Pb-free)
S = 28-pin Molded SOIC
Speed: 15 ns or 20 ns or 35 ns
85 = 64 Kbit density with datawidth × 8 bits
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
7 = SRAM
CY = Cypress
Document #: 38-05043 Rev. *E
Page 10 of 15
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CY7C185
Package Diagrams
Figure 7. 28-pin (300-Mil) PDIP (51-85014)
51-85014 *E
Figure 8. 28-pin (300-Mil) Molded SOIC (51-85026)
51-85026 *F
Document #: 38-05043 Rev. *E
Page 11 of 15
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CY7C185
Package Diagrams (continued)
Figure 9. 28-pin (300-Mil) Molded SOJ (51-85031)
51-85031 *D
Document #: 38-05043 Rev. *E
Page 12 of 15
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CY7C185
Acronyms
Document Conventions
Units of Measure
Acronym
CE
Description
chip enable
Symbol
ns
Unit of Measure
CMOS
I/O
Complementary metal oxide semiconductor
Input/output
nano seconds
Volts
V
OE
output enable
µA
mA
mV
mW
MHz
pF
micro Amperes
milli Amperes
milli Volts
SRAM
SOJ
Static random access memory
Small Outline J-Lead
TSOP
VFBGA
Thin Small Outline Package
Very Fine-Pitch Ball Grid Array
milli Watts
Mega Hertz
pico Farad
degree Celcius
Watts
°C
W
Document #: 38-05043 Rev. *E
Page 13 of 15
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CY7C185
Document History Page
Document Title: CY7C185, 64-Kbit (8 K × 8) Static RAM
Document Number: 38-05043
Submission
Date
Orig. of
Change
Revision
ECN
Description of Change
**
107145
116470
486744
09/10/01
09/16/02
See ECN
SZV
CEA
NXR
Change from Spec number: 38-00037 to 38-05043
Add applications foot note to data sheet
Changed Low standby power from 220mW to 85mW
*A
*B
Changed the description of IIX from Input Load Current to Input Leakage
Current in DC Electrical Characteristics table
Removed IOS parameter from DC Electrical Characteristics table
Updated the Ordering Information table
*C
*D
*E
2263686
3105329
3235800
See ECN
12/09/2010
04/20/2011
VKN/AESA Removed 25 ns speed bin
Updated the Ordering Information table as per the current product offerings
AJU
Added Ordering Code Definitions.
Updated Package Diagrams.
PRAS
Template changes.
Added Acronyms and Units of Measure.
Updated package diagram spec 51-85026 to *F.
Document #: 38-05043 Rev. *E
Page 14 of 15
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CY7C185
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2001-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05043 Rev. *E
Revised April 20, 2011
Page 15 of 15
All products and company names mentioned in this document may be the trademarks of their respective holders.
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