CY7C185_06 [CYPRESS]
8K x 8 Static RAM; 8K ×8静态RAM
| 型号： | CY7C185_06 |
| 厂家： | 
CYPRESS |
| 描述： | 8K x 8 Static RAM |
| 文件： | 总12页 (文件大小：306K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1bCY7C185
CY7C185
8K x 8 Static RAM
Features
Functional Description[1]
• High speed
The CY7C185 is a high-performance CMOS static RAM
organized as 8192 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE1), an active
HIGH chip enable (CE2), and active LOW output enable (OE)
and tri-state drivers. This device has an automatic
power-down feature (CE1 or CE2), reducing the power
consumption by 70% when deselected. The CY7C185 is in a
standard 300-mil-wide DIP, SOJ, or SOIC package.
— 15 ns
• Fast tDOE
• Low active power
— 715 mW
• Low standby power
— 85 mW
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE1 and WE
inputs are both LOW and CE2 is HIGH, data on the eight data
input/output pins (I/O0 through I/O7) is written into the memory
location addressed by the address present on the address
pins (A0 through A12). Reading the device is accomplished by
selecting the device and enabling the outputs, CE1 and OE
active LOW, CE2 active HIGH, while WE remains inactive or
HIGH. Under these conditions, the contents of the location
addressed by the information on address pins are present on
the eight data input/output pins.
• CMOS for optimum speed/power
• Easy memory expansion with CE1, CE2 and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• Available in non Pb-free 28-pin (300-Mil) Molded SOJ,
28-pin (300-Mil) Molded SOIC and both Pb-free and non
Pb-free in 28-pin (300-Mil) Molded DIP
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to insure alpha immunity.
Logic Block Diagram
Pin Configurations
DIP/SOJ
Top View
I/O
I/O
0
INPUT BUFFER
NC
A
4
V
CC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
WE
CE
2
3
4
5
A
5
2
A
1
I/O
I/O
A
A
3
2
6
A
2
A
A
2
7
A
8
A
1
A
3
6
7
8
9
3
A
9
OE
A
8K x 8
ARRAY
4
A
A
A
A
0
A
10
11
12
5
I/O
4
I/O
5
I/O
6
I/O
7
CE
1
A
6
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
10
11
12
13
14
A
A
8
7
I/O
0
I/O
1
I/O
2
GND
POWER
DOWN
CE
1
COLUMN DECODER
CE
2
WE
OE
Selection Guide
-15
-20
20
-25
-35
Maximum Access Time (ns)
15
130
15
25
100
15
35
Maximum Operating Current (mA)
110
15
100
15
Maximum CMOS Standby Current (mA)
Notes:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05043 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 24, 2006
[+] Feedback
CY7C185
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Ambient
Supply Voltage to Ground Potential............... –0.5V to +7.0V
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
VCC
DC Voltage Applied to Outputs
5V ± 10%
5V ± 10%
in High Z State[2] ............................................ –0.5V to +7.0V
DC Input Voltage[2]......................................... –0.5V to +7.0V
Electrical Characteristics Over the Operating Range
–15
–20
–25, -35
Parameter Description
Test Conditions
VCC = Min.,
OH = –4.0 mA
Min.
Max.
Min.
Max.
Min.
Max.
Unit
VOH
VOL
VIH
VIL
Output HIGH
Voltage
2.4
2.4
2.4
V
I
Output LOW
Voltage
VCC = Min.,
IOL = 8.0 mA
0.4
VCC + 0.3V
0.8
0.4
0.4
V
V
Input HIGH
Voltage
2.2
–0.5
–5
2.2
–0.5
–5
VCC + 0.3V
2.2
–0.5
–5
VCC + 0.3V
Input LOW
Voltage[2]
0.8
+5
0.8
+5
V
IIX
Input Leakage GND ≤ VI ≤ VCC
Current
+5
µA
µA
mA
IOZ
ICC
ISB1
Output Leakage GND ≤ VI ≤ VCC
,
–5
+5
–5
+5
–5
+5
Current Output Disabled
VCC Operating VCC = Max.,
Supply Current IOUT = 0 mA
130
110
20
100
20
Automatic
Power-Down
Current
Max. VCC
,
40
mA
mA
CE1 ≥ VIH or CE2 ≤ VIL
Min. Duty Cycle =100%
ISB2
Automatic
Power-Down
Current
Max. VCC
,
15
15
15
CE1 ≥ VCC – 0.3V,
or CE2 ≤ 0.3V
VIN ≥ VCC – 0.3V or
VIN ≤ 0.3V
Capacitance[3]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
CC = 5.0V
Max.
Unit
pF
CIN
7
7
V
COUT
pF
Notes:
2. Minimum voltage is equal to –3.0V for pulse durations less than 30 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05043 Rev. *B
Page 2 of 12
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CY7C185
AC Test Loads and Waveforms
R1 481Ω
R1 481Ω
ALL INPUT PULSES
5V
OUTPUT
5V
OUTPUT
3.0V
GND
90%
10%
90%
10%
30 pF
5 pF
R2
255Ω
R2
255Ω
≤ 5 ns
≤ 5 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIGAND
SCOPE
Equivalent to:
OUTPUT
THÉVENIN EQUIVALENT
(a)
(b)
167Ω
1.73V
Switching Characteristics Over the Operating Range[4]
-15
-20
-25
-35
Parameter
Read Cycle
tRC
Description
Min.
15
3
Max.
Min.
20
5
Max.
Min.
25
5
Max.
Min.
35
5
Max.
Unit
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE1 LOW to Data Valid
CE2 HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z[5]
CE1 LOW to Low Z[6]
CE2 HIGH to Low Z
15
20
25
35
tOHA
tACE1
15
15
8
20
20
9
25
25
12
35
35
15
tACE2
tDOE
tLZOE
3
3
3
3
tHZOE
tLZCE1
tLZCE2
tHZCE
7
7
8
8
10
10
10
10
3
3
5
3
5
3
5
3
CE1 HIGH to High Z[5, 6]
CE2 LOW to High Z
tPU
tPD
CE1 LOW to Power-Up
CE2 to HIGH to Power-Up
0
0
0
0
ns
ns
CE1 HIGH to Power-Down
CE2 LOW to Power-Down
15
20
20
20
Write Cycle[7]
tWC
Write Cycle Time
15
12
12
12
0
20
15
15
15
0
25
20
20
20
0
35
20
20
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE1
tSCE2
tAW
CE1 LOW to Write End
CE2 HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
tHA
tSA
0
0
0
0
tPWE
tSD
12
8
15
10
0
15
10
0
20
12
0
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z[5]
tHD
0
tHZWE
7
7
7
8
tLZWE
WE HIGH to Low Z
3
5
5
5
Notes:
4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I and 30-pF load capacitance.
OL OH
5. t
t
, and t
are specified with C = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
HZOE, HZCE
HZWE L
6. At any given temperature and voltage condition, t
is less than t
and t
for any given device.
LZCE2
HZCE
LZCE1
7. The internal write time of the memory is defined by the overlap of CE LOW, CE HIGH, and WE LOW. All 3 signals must be active to initiate a write and either
1
2
signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05043 Rev. *B
Page 3 of 12
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CY7C185
Switching Waveforms
Read Cycle No.1[8,9]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No.2[10,11]
t
RC
CE
1
CE
2
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
ICC
V
CC
SUPPLY
CURRENT
50%
50%
ISB
Notes:
8. Device is continuously selected. OE, CE = V . CE = V .
IH
1
IL
2
9. WE is HIGH for read cycle.
10. Data I/O is High Z if OE = V , CE = V , WE = V , or CE =V .
IL
IH
1
IH
IL
2
11. The internal write time of the memory is defined by the overlap of CE LOW, CE HIGH and WE LOW. CE and WE must be LOW and CE must be HIGH
1
2
1
2
to initiate write. A write can be terminated by CE or WE going HIGH or CE going LOW. The data input set-up and hold timing should be referenced to the
1
2
rising edge of the signal that terminates the write.
Document #: 38-05043 Rev. *B
Page 4 of 12
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CY7C185
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[9,11]
t
WC
ADDRESS
t
CE
SCEI
1
t
AW
t
HA
t
CE
SCE2
2
t
SA
t
PWE
WE
OE
t
SD
t
HD
DATA VALID
NOTE 12
t
IN
DATA I/O
HZOE
Write Cycle No. 2 (CE Controlled)[11,12,13]
t
WC
ADDRESS
t
CE
SCE1
1
t
SA
t
SCE2
CE
2
t
t
HA
AW
WE
t
t
HD
SD
DATA VALID
DATA I/O
IN
Notes:
12. During this period, the I/Os are in the output state and input signals should not be applied.
13. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
and t
.
HZWE
SD
Document #: 38-05043 Rev. *B
Page 5 of 12
[+] Feedback
CY7C185
Switching Waveforms (continued)
Write Cycle No. 3(WE Controlled, OE LOW)[11,12,13,14]
t
WC
ADDRESS
t
CE
SCE1
1
t
CE
SCE2
2
t
t
HA
AW
t
SA
WE
t
t
HD
SD
DATA I/O
NOTE 12
DATA VALID
IN
t
t
LZWE
HZWE
Note:
14. If CE goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
1
2
Document #: 38-05043 Rev. *B
Page 6 of 12
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CY7C185
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
120
100
80
1.4
1.2
1.0
1.2
1.0
0.8
I
I
CC
CC
0.8
0.6
0.4
V
T
A
=5.0V
=25°C
CC
0.6
0.4
60
40
V
V
=5.0V
=5.0V
CC
IN
0.2
0.0
20
0
I
0.2
0.0
SB
I
SB
–55
25
125
0.0
1.0
2.0
3.0
4.0
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
140
120
1.6
1.4
1.4
1.3
1.2
100
80
V
=5.0V
CC
1.2
1.0
T =25°C
A
1.1
1.0
60
T =25°C
A
V
CC
=5.0V
40
0.8
20
0
0.9
0.8
0.6
–55
0.0
1.0
2.0
3.0
4.0
25
125
4.0
4.5
5.0
5.5
6.0
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
NORMALIZED I vs. CYCLE TIME
CC
3.0
2.5
2.0
1.5
30.0
25.0
20.0
15.0
1.25
1.00
0.75
0.50
V
=5.0V
CC
T =25°C
A
V
CC
=0.5V
1.0
0.5
0.0
10.0
5.0
V
=4.5V
CC
T =25°C
A
0.0
0.0
1.0
2.0
3.0
4.0
5.0
0
200 400
600 800 1000
10
20
30
40
SUPPLY VOLTAGE (V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
Document #: 38-05043 Rev. *B
Page 7 of 12
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CY7C185
Truth Table
CE1
H
CE2
X
WE
X
OE
X
Input/Output
Mode
Deselect/Power-Down
High Z
High Z
X
L
X
X
Deselect/Power-Down
L
H
H
L
Data Out
Data In
High Z
Read
L
H
L
X
Write
L
H
H
H
Deselect
Address Designators
Address
Name
Address
Function
Pin
Number
A4
A5
X3
X4
X5
X6
X7
Y1
Y4
Y3
Y0
Y2
X0
X1
X2
2
3
A6
4
A7
5
A8
6
A9
7
A10
A11
A12
A0
8
9
10
21
23
24
25
A1
A2
A3
Ordering Information
Speed
Package
Operating
Range
(ns)
Ordering Code
CY7C185-15VC
Name
Package Type
15
51-85031
28-pin (300-Mil) Molded SOJ
28-pin (300-Mil) Molded SOJ
28-pin (300-Mil) Molded DIP
28-pin (300-Mil) Molded DIP (Pb-free)
28-pin (300-Mil) Molded SOJ
28-pin (300-Mil) Molded DIP
28-pin (300-Mil) Molded SOJ
28-pin (300-Mil) Molded DIP
28-pin (300-Mil) Molded SOIC
Commercial
Industrial
CY7C185-15VI
CY7C185-20PC
CY7C185-20PXC
CY7C185-20VC
CY7C185-25PC
CY7C185-25VC
CY7C185-35PC
CY7C185-35SC
20
51-85014
Commercial
51-85031
51-85014
51-85031
51-85014
51-85026
25
35
Commercial
Commercial
Document #: 38-05043 Rev. *B
Page 8 of 12
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CY7C185
Package Diagrams
28-pin (300-Mil) PDIP (51-85014)
SEE LEAD END OPTION
14
1
MIN.
DIMENSIONS IN INCHES [MM]
MAX.
REFERENCE JEDEC MO-095
PACKAGE WEIGHT: 2.15 gms
0.260[6.60]
0.295[7.49]
15
28
0.030[0.76]
0.080[2.03]
SEATING PLANE
1.345[34.16]
1.385[35.18]
0.290[7.36]
0.325[8.25]
0.120[3.05]
0.140[3.55]
0.140[3.55]
0.190[4.82]
0.009[0.23]
0.012[0.30]
0.115[2.92]
0.160[4.06]
3° MIN.
0.015[0.38]
0.060[1.52]
0.055[1.39]
0.065[1.65]
0.310[7.87]
0.385[9.78]
0.090[2.28]
0.110[2.79]
0.015[0.38]
0.020[0.50]
SEE LEAD END OPTION
51-85014-*D
LEAD END OPTION
(LEAD #1, 14, 15 & 28)
Document #: 38-05043 Rev. *B
Page 9 of 12
[+] Feedback
CY7C185
Package Diagrams (continued)
28-pin (300-Mil) Molded SOIC (51-85026)
NOTE :
PIN 1 ID
1. JEDEC STD REF MO-119
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT
DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE.
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE
14
1
MIN.
3. DIMENSIONS IN INCHES
MAX.
0.291[7.39]
0.300[7.62]
4. PACKAGE WEIGHT 0.85gms
*
0.394[10.01]
0.419[10.64]
PART #
15
28
0.026[0.66]
0.032[0.81]
S28.3 STANDARD PKG.
SZ28.3 LEAD FREE PKG.
SEATING PLANE
0.697[17.70]
0.713[18.11]
0.092[2.33]
0.105[2.67]
*
0.004[0.10]
0.0091[0.23]
0.0125[3.17]
0.015[0.38]
0.050[1.27]
0.013[0.33]
0.019[0.48]
*
0.004[0.10]
0.050[1.27]
TYP.
0.0118[0.30]
51-85026-*D
Document #: 38-05043 Rev. *B
Page 10 of 12
[+] Feedback
CY7C185
Package Diagrams (continued)
28-pin (300-Mil) Molded SOJ (51-85031)
NOTE :
1. JEDEC STD REF MO088
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE
MIN.
3. DIMENSIONS IN INCHES
MAX.
DETAIL
A
PIN 1 ID
EXTERNAL LEAD DESIGN
14
1
0.291
0.300
0.330
0.350
0.026
0.032
0.013
0.019
15
28
0.014
0.020
OPTION 1
OPTION 2
0.697
0.713
SEATING PLANE
0.120
0.140
0.007
0.013
0.004
A
0.262
0.272
0.050
TYP.
0.025 MIN.
51-85031-*C
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05043 Rev. *B
Page 11 of 12
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C185
Document History Page
Document Title: CY7C185 8K x 8 Static RAM
Document Number: 38-05043
Issue
Orig. of
Change
REV.
**
ECN NO. Date
Description of Change
107145
116470
486744
09/10/01
SZV
CEA
NXR
Change from Spec number: 38-00037 to 38-05043
Add applications foot note to data sheet
Changed Low standby power from 220mW to 85mW
*A
*B
09/16/02
See ECN
Changed the description of IIX from Input Load Current to Input Leakage
Current in DC Electrical Characteristics table
Removed IOS parameter from DC Electrical Characteristics table
Updated the Ordering Information table
Document #: 38-05043 Rev. *B
Page 12 of 12
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