CY7C1019CV33-10VI [CYPRESS]
128K x 8 Static RAM; 128K ×8静态RAM
| 型号： | CY7C1019CV33-10VI |
| 厂家： | 
CYPRESS |
| 描述： | 128K x 8 Static RAM |
| 文件： | 总8页 (文件大小：196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1019CV33
128K x 8 Static RAM
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
Features
• Pin and function compatible with CY7C1019BV33
• High speed
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location
specified on the address pins (A0 through A16).
— tAA = 8, 10, 12, 15 ns
• CMOS for optimum speed/power
• Data retention at 2.0V
• Center power/ground pinout
• Automatic power-down when deselected
• Easy memory expansion with CE and OE options
• Available in 32-pin TSOP II and 400-mil SOJ package
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
Functional Description
The CY7C1019CV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers. This
The CY7C1019CV33 is available in a standard 32-pin TSOP
II and 400-mil-wide SOJ.
Logic Block Diagram
Pin Configuration
SOJ/TSOP II
Top View
A
A
A
A
A
32
1
0
1
16
31
30
2
3
4
5
6
15
2
A
14
A
13
I/O
A
29
28
3
0
INPUT BUFFER
CE
OE
I/O
I/O
I/O
27
26
1
I/O
A
0
0
1
7
A
A
2
1
I/O
V
7
8
9
6
I/O
2
25
24
23
22
21
V
CC
A
SS
3
V
A
I/O
V
CC
I/O
4
SS
3
512 x 256 x 8
ARRAY
A
5
I/O
I/O
10
11
12
13
2
3
5
4
A
6
I/O
I/O
A
4
A
7
A
8
WE
12
I/O
A
A
5
4
11
20
19
A
A
A
A
10
5
14
15
16
I/O
6
POWER
DOWN
A
9
A
8
COLUMN
DECODER
6
18
17
CE
7
I/O
WE
7
OE
Selection Guide
7C1019CV33-8 7C1019CV33-10 7C1019CV33-12 7C1019CV33-15 Unit
Maximum Access Time
8
85
5
10
80
5
12
75
5
15
70
5
ns
Maximum Operating Current
Maximum Standby Current
mA
mA
Cypress Semiconductor Corporation
Document #: 38-05130 Rev. *D
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised December 16, 2002
CY7C1019CV33
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current......................................................>200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Ambient
Supply Voltage on VCC to Relative GND[1] ... –0.5V to + 4.6V
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
VCC
DC Voltage Applied to Outputs
3.3V ± 10%
3.3V ± 10%
in High-Z State[1] ....................................–0.5V to VCC + 0.5V
DC Input Voltage[1].................................–0.5V to VCC + 0.5V
Electrical Characteristics Over the Operating Range
7C1019CV33 7C1019CV33 7C1019CV33 7C1019CV33
-8 -10 -12 -15
Parameter
Description
Test Conditions
Min. Max. Min. Max. Min. Max. Min. Max. Unit
VOH
Output HIGH Voltage VCC = Min.,
2.4
2.4
2.4
2.4
V
V
V
IOH = –4.0 mA
VOL
VIH
Output LOW Voltage VCC = Min.,
IOL = 8.0 mA
0.4
0.4
0.4
0.4
Input HIGH Voltage
2.0
VCC
2.0
VCC
2.0
VCC
2.0
VCC
+ 0.3
+ 0.3
+ 0.3
+ 0.3
VIL
IIX
Input LOW Voltage[1]
–0.3
–1
0.8
+1
+1
–0.3
–1
0.8
+1
+1
–0.3
–1
0.8
+1
+1
–0.3
–1
0.8
+1
+1
V
Input Load Current
GND < VI < VCC
µA
µA
IOZ
Output Leakage
Current
GND < VI < VCC
,
–1
–1
–1
–1
Output Disabled
[2.]
IOS
Output Short
Circuit Current
VCC = Max.,
VOUT = GND
–300
–300
–300
–300 mA
ICC
VCC Operating
Supply Current
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
85
80
75
70
15
5
mA
mA
mA
ISB1
Automatic CE
Power-down Current VIN > VIH or
—TTL Inputs
Max. VCC, CE > VIH
15
5
15
5
15
5
VIN < VIL, f = fMAX
ISB2
Automatic CE
Max. VCC
,
Power-down Current CE > VCC – 0.3V,
—CMOS Inputs
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
Capacitance[3]
Parameter
CIN
Description
Test Conditions
Max.
Unit
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
VCC = 5.0V
8
8
pF
pF
COUT
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05130 Rev. *D
Page 2 of 8
CY7C1019CV33
AC Test Loads and Waveforms[4]
10-, 12-, 15-ns devices:
8-ns devices:
R 317Ω
Ω
Z = 50
3.3V
OUTPUT
OUTPUT
30 pF
50Ω
30pF*
R2
351Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5V
(b)
(a)
High-Z characteristics:
ALL INPUT PULSES
3.0V
R 317Ω
90%
10%
90%
10%
3.3V
OUTPUT
5 pF
GND
351
(c)
Fall Time: 1 V/ns
Rise Time: 1 V/ns
R2
Ω
(d)
Switching Characteristics[5] Over the Operating Range
7C1019CV33-8 7C1019CV33-10 7C1019CV33-12 7C1019CV33-15
Parameter
Read Cycle
tRC
Description
Min.
Max.
Min.
10
3
Max.
Min.
12
3
Max.
Min.
15
3
Max. Unit
Read Cycle Time
8
3
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z[6, 7]
CE LOW to Low Z[7]
CE HIGH to High Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
8
10
12
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOHA
tACE
8
5
10
5
12
6
15
7
tDOE
tLZOE
0
3
0
0
3
0
0
3
0
0
3
0
tHZOE
tLZCE
4
4
8
5
5
6
6
7
7
tHZCE
[8]
tPU
[8]
tPD
10
12
15
Write Cycle[9, 10]
tWC
tSCE
tAW
tHA
Write Cycle Time
8
7
7
0
0
6
5
0
3
10
8
12
9
15
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
8
9
0
0
tSA
0
0
0
tPWE
tSD
7
8
10
8
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[7]
5
6
tHD
0
0
0
tLZWE
3
3
3
tHZWE
WE LOW to High Z[6, 7]
4
5
6
7
Notes:
4. AC characteristics (except High-Z) for all 8-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin
load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6.
tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. This parameter is guaranteed by design and is not tested.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
Document #: 38-05130 Rev. *D
Page 3 of 8
CY7C1019CV33
Switching Waveforms
Read Cycle No. 1[11, 12]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[12, 13]
ADDRESS
t
RC
CE
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
t
PU
V
CC
50%
50%
SUPPLY
CURRENT
ISB
Write Cycle No. 1 (CE Controlled)[14, 15]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
SCE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
Notes:
11. Device is continuously selected. OE, CE = VIL.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
14. Data I/O is high impedance if OE = VIH
.
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05130 Rev. *D
Page 4 of 8
CY7C1019CV33
Switching Waveforms (continued)
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
NOTE 16
t
HZOE
Write Cycle No. 3 (WE Controlled, OE LOW)[15]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 16
DATA I/O
DATA VALID
t
t
LZWE
HZWE
Truth Table
CE
H
L
OE
WE
X
I/O0–I/O7
Mode
Power
X
L
High Z
Power-Down
Read
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
)
H
Data Out
Data In
High Z
)
L
X
H
L
Write
)
L
H
Selected, Outputs Disabled
)
Note:
16. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05130 Rev. *D
Page 5 of 8
CY7C1019CV33
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
32-Lead 400-Mil Molded SOJ
8
CY7C1019CV33-8VC
CY7C1019CV33-8VI
CY7C1019CV33-10VC
CY7C1019CV33-10ZC
CY7C1019CV33-10VI
CY7C1019CV33-10ZI
CY7C1019CV33-12VC
CY7C1019CV33-12ZC
CY7C1019CV33-12VI
CY7C1019CV33-12ZI
CY7C1019CV33-15VC
CY7C1019CV33-15ZC
CY7C1019CV33-15VI
CY7C1019CV33-15ZI
V33
V33
Commercial
Industrial
32-Lead 400-Mil Molded SOJ
32-Lead 400-Mil Molded SOJ
32-Lead TSOP II
10
12
15
V33
Commercial
ZS32
V33
32-Lead 400-Mil Molded SOJ
32-Lead TSOP II
Industrial
Commercial
Industrial
ZS32
V33
32-Lead 400-Mil Molded SOJ
32-Lead TSOP II
ZS32
V33
32-Lead 400-Mil Molded SOJ
32-Lead TSOP II
ZS32
V33
32-Lead 400-Mil Molded SOJ
32-Lead TSOP II
Commercial
Industrial
ZS32
V33
32-Lead 400-Mil Molded SOJ
32-Lead TSOP II
ZS32
Package Diagram
32-lead (400-Mil) Molded SOJ V33
51-85033-A
51-85033-*B
Document #: 38-05130 Rev. *D
Page 6 of 8
CY7C1019CV33
Package Diagram (continued)
32-lead
TSOP II ZS32
51-85095-**
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05130 Rev. *D
Page 7 of 8
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1019CV33
Document History Page
Document Title: CY7C1019CV33 128K x 8 Static RAM
Document Number: 38-05130
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
109245
113431
115047
119796
123030
Description of Change
12/16/01
04/10/02
08/01/02
10/11/02
12/17/02
HGK
NSL
HGK
DFP
DFP
New Data Sheet
AC Test Loads split based on speed.
*A
*B
Added TSOP II Package and I Temp. Improved ICC limits.
Updated standby current from 5 nA to 5 mA.
*C
*D
Updated Truth Table to reflect single Chip Enable option.
Document #: 38-05130 Rev. *D
Page 8 of 8
相关型号：
CY7C1019CV33-12BVXIT
128KX8 STANDARD SRAM, 12ns, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
ROCHESTER
©2020 ICPDF网 联系我们和版权申明