CY7C1019CV33-10ZXAT [CYPRESS]
1-Mbit (128 K × 8) Static RAM Center Power/Ground Pinout; 1兆位（ 128千× 8 ）静态RAM中心电源/接地引脚
| 型号： | CY7C1019CV33-10ZXAT |
| 厂家： | 
CYPRESS |
| 描述： | 1-Mbit (128 K × 8) Static RAM Center Power/Ground Pinout |
| 文件： | 总13页 (文件大小：442K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1019CV33
1-Mbit (128 K × 8) Static RAM
1-Mbit (128
K × 8) Static RAM
Features
Functional Description
■ Temperature Ranges
❐ Industrial: –40 °C to 85 °C
❐ Automotive-A: –40 °C to 85 °C
The CY7C1019CV33 is a high performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE), an active LOW
Output Enable (OE), and tristate drivers. This device has an
automatic power down feature that significantly reduces power
consumption when deselected.
■ Pin and Function compatible with CY7C1019BV33
■ High Speed
❐ tAA = 10 ns
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. Data on the eight I/O pins
(I/O0 through I/O7) is then written into the location specified on
the address pins (A0 through A16).
■ CMOS for optimum Speed and Power
■ Data Retention at 2.0 V
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O pins.
■ Center Power/Ground Pinout
■ Automatic Power Down when deselected
■ Easy Memory Expansion with CE and OE Options
■ Available in Pb-free 32-pin TSOP II package
The eight input/output pins (I/O0 through I/O7) are placed in a
high impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), or during a write operation
(CE LOW, and WE LOW).
Logic Block Diagram
I/O
0
INPUT BUFFER
I/O
1
A
0
A
A
2
1
I/O
2
A
3
A
I/O
3
4
128K x 8
ARRAY
A
5
A
6
I/O
4
A
7
A
8
I/O
5
I/O
6
POWER
DOWN
COLUMN
DECODER
CE
I/O
WE
7
OE
Cypress Semiconductor Corporation
Document #: 38-05130 Rev. *K
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 8, 2011
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CY7C1019CV33
Contents
Selection Guide ................................................................3
Pin Configuration .............................................................3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
Electrical Characteristics .................................................4
Capacitance ......................................................................4
AC Test Loads and Waveforms .......................................5
Switching Characteristics ................................................6
Switching Waveforms ......................................................7
Truth Table ........................................................................9
Ordering Information ........................................................9
Ordering Code Definitions ...........................................9
Package Diagram ............................................................10
Acronyms ........................................................................11
Document Conventions .................................................11
Units of Measure .......................................................11
Document History Page .................................................12
Sales, Solutions, and Legal Information ......................13
Worldwide Sales and Design Support .......................13
Products ....................................................................13
PSoC Solutions .........................................................13
Document #: 38-05130 Rev. *K
Page 2 of 13
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CY7C1019CV33
Selection Guide
-10 (Industrial/
Unit
Description
Auto-A)
Maximum Access Time
10
80
5
ns
Maximum Operating Current
Maximum Standby Current
mA
mA
Pin Configuration
Figure 1. 32-pin TSOP II (Top View) [1]
A
A
1
A
A
32
1
0
16
31
30
2
3
4
5
6
15
A
A
14
A
13
2
A
29
28
3
CE
OE
I/O
I/O
27
26
I/O
0
1
7
I/O
V
7
8
9
10
11
12
13
6
25
24
23
22
21
V
CC
SS
V
V
CC
I/O
SS
I/O
I/O
2
3
5
4
I/O
A
WE
A
4
12
A
11
20
19
A
5
A
10
14
15
16
A
6
A
9
A
8
18
17
A
7
Note
1. NC pins are not connected on the die.
Document #: 38-05130 Rev. *K
Page 3 of 13
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CY7C1019CV33
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
Static Discharge Voltage ...........................................>2001V
(per MIL-STD-883, Method 3015)
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Latch up Current .....................................................>200 mA
Storage Temperature ............................... –65 °C to +150 °C
Operating Range
Ambient Temperature with
Power Applied ......................................... –55 °C to +125 °C
Range
Commercial
Industrial
Ambient Temperature
0 °C to +70 °C
VCC
Supply Voltage on
3.3 V 10%
3.3 V 10%
3.3 V 10%
V
CC to Relative GND[2] ................................–0.5 V to +4.6 V
–40 C to +85 C
–40 C to +85 C
DC Voltage Applied to Outputs
in High Z State[2] .................................–0.5 V to VCC + 0.5 V
Automotive-A
DC Input Voltage[2] .............................–0.5 V to VCC + 0.5 V
Electrical Characteristics
Over the Operating Range
-10 (Industrial/Auto-A)
Parameter
VOH
Description
Test Conditions
Unit
Min
2.4
–
Max
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[2]
Input Leakage Current
Output Leakage Current
VCC Operating Supply Current
VCC = Min, IOH = –4.0 mA
–
0.4
V
V
VOL
VIH
VIL
IIX
VCC = Min, IOL = 8.0 mA
2.0
–0.3
–1
VCC + 0.3
0.8
V
V
GND < VI < VCC
+1
A
A
mA
mA
IOZ
ICC
ISB1
GND < VI < VCC, Output Disabled
–1
+1
VCC = Max, IOUT = 0 mA, f = fMAX = 1/tRC
–
–
80
Automatic CE Power down
Current —TTL Inputs
Max VCC, CE > VIH,
VIN > VIH or VIN < VIL, f = fMAX
15
ISB2
Automatic CE Power down
Current —CMOS Inputs
Max VCC, CE > VCC – 0.3 V,
–
5
mA
VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0
Capacitance
Parameter[3]
Description
Test Conditions
Max
8
Unit
pF
CIN
Input Capacitance
TA = 25 °C, f = 1 MHz, VCC = 5.0 V
COUT
Output Capacitance
8
pF
Notes
2.
V
(min.) = –2.0 V for pulse durations of less than 20 ns.
IL
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05130 Rev. *K
Page 4 of 13
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CY7C1019CV33
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms [4]
High-Z characteristics:
R 317
ALL INPUT PULSES
R 317
3.0 V
3.3 V
90%
10%
90%
10%
3.3 V
OUTPUT
OUTPUT
GND
R2
30 pF
R2
351
351
5 pF
(b)
Fall Time: 1 V/ns
Rise Time: 1 V/ns
(a)
(c)
Note
4. AC characteristics (except High Z) for all speeds are tested using the Thevenin load shown in section (a) in Figure 2. High Z characteristics are tested for all speeds
using the test load shown in section (c) in Figure 2.
Document #: 38-05130 Rev. *K
Page 5 of 13
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CY7C1019CV33
Switching Characteristics
Over the Operating Range
-10 (Industrial/
Parameter[5]
Description
Unit
Auto-A)
Min
Max
Read Cycle
tRC
Read Cycle Time
10
–
3
–
–
0
–
3
–
0
–
–
10
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
Data Hold from Address Change
10
5
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z[6, 7]
CE LOW to Low Z[7]
CE HIGH to High Z[6, 7]
–
5
–
5
[8]
tPU
–
CE LOW to Power Up
[8]
tPD
10
CE HIGH to Power Down
Write Cycle[9, 10]
tWC
Write Cycle Time
10
8
–
–
–
–
–
–
–
–
–
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
tAW
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
8
tHA
0
tSA
0
tPWE
tSD
7
WE Pulse Width
Data Setup to Write End
5
tHD
Data Hold from Write End
0
WE HIGH to Low Z[7]
WE LOW to High Z[6, 7]
tLZWE
tHZWE
3
–
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V.
6. , t , and t are specified with a load capacitance of 5 pF as in part (d) of Figure 2 on page 5. Transition is measured 500 mV from steady-state voltage.
7. At any given temperature and voltage condition, t
t
HZOE HZCE
HZWE
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
8. This parameter is guaranteed by design and is not tested.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of
these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
and t
.
HZWE
SD
Document #: 38-05130 Rev. *K
Page 6 of 13
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CY7C1019CV33
Switching Waveforms
Figure 3. Read Cycle No. 1 [11, 12]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 4. Read Cycle No. 2 (OE Controlled) [12, 13]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
t
PU
V
CC
50%
50%
SUPPLY
CURRENT
ISB
Figure 5. Write Cycle No. 1 (CE Controlled) [14, 15]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
SCE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
Notes
11. Device is continuously selected. OE, CE = V
12. WE is HIGH for read cycle.
.
IL
13. Address valid prior to or coincident with CE transition LOW.
14. Data I/O is high impedance if OE = V
.
IH
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document #: 38-05130 Rev. *K
Page 7 of 13
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CY7C1019CV33
Switching Waveforms (continued)
Figure 6. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [16, 17]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
t
PWE
SA
WE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
NOTE 18
t
HZOE
Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) [17]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 18
DATA I/O
DATA VALID
t
t
LZWE
HZWE
Notes
16. Data I/O is high impedance if OE = V
.
IH
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
18. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05130 Rev. *K
Page 8 of 13
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CY7C1019CV33
Truth Table
I/O0–I/O7
High Z
Mode
Power
CE
H
L
OE
X
WE
X
Power Down
Read
Standby (ISB)
L
H
Data Out
Data In
High Z
Active (ICC
Active (ICC
Active (ICC
)
)
)
L
X
L
Write
L
H
H
Selected, Outputs Disabled
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Ordering Code
Package Type
10
CY7C1019CV33-10ZXA
CY7C1019CV33-10ZXAT
51-85095 32-pin TSOP II (Pb-free)
51-85095 32-pin TSOP II (Pb-free)
Automotive-A
Ordering Code Definitions
CY 7 C 1019 C V33 - 10
Z
X
A X
X = T or Blank
T = Tape and Reel; Blank = Tube
Temperature Range:
A = Automotive-A
Pb-free
Package Type:
Z = 32-pin TSOP II
Speed Grade: 10 ns
V33 = 3.3 V
Process Technology 0.16 µm
Part Identifier
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document #: 38-05130 Rev. *K
Page 9 of 13
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CY7C1019CV33
Package Diagram
Figure 8. 32-pin TSOP II (20.95 × 11.76 × 1.0 mm) ZS32
51-85095 *B
Document #: 38-05130 Rev. *K
Page 10 of 13
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CY7C1019CV33
Acronyms
Document Conventions
Units of Measure
Acronym
Description
CMOS
CE
complementary metal oxide semiconductor
chip enable
Symbol
°C
Unit of Measure
degree Celsius
Mega Hertz
micro Amperes
milli Amperes
milli meter
milli seconds
nano seconds
percent
I/O
input/output
MHz
µA
mA
mm
ms
ns
OE
output enable
SRAM
TSOP
TTL
static random access memory
thin small outline package
transistor-transistor logic
write enable
WE
%
pF
V
pico Farad
Volts
W
Watts
Document #: 38-05130 Rev. *K
Page 11 of 13
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CY7C1019CV33
Document History Page
Document Title: CY7C1019CV33, 1-Mbit (128 K × 8) Static RAM
Document Number: 38-05130
Submission
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
**
109245
113431
115047
119796
123030
419983
12/16/01
04/10/02
08/01/02
10/11/02
12/17/02
See ECN
HGK
NSL
HGK
DFP
DFP
NXR
New Data Sheet
AC Test Loads split based on speed
*A
*B
*C
*D
*E
Added TSOP II Package and I Temp. Improved ICC limits
Updated standby current from 5 nA to 5 mA
Updated Truth Table to reflect single Chip Enable option
Added 48-ball VFBGA Package
Added lead-free parts in Ordering Information Table
Replaced Package Name column with Package Diagram in the Ordering
Information Table
*F
493543
See ECN
NXR
Removed 8 ns speed bin from Product offering
Added note #1 on page #2
Changed the description of IIX from Input Load Current to
Input Leakage Current in DC Electrical Characteristics table
Removed IOS parameter from DC Electrical Characteristics table
Updated Ordering Information
*G
*H
2761448
2897691
09/09/2009
03/23/2010
VKN
Included Automotive-A information
RAME
Updated Ordering Information
Updated Package Diagrams
*I
3057593
10/13/2010
PRAS
Updated Ordering Information and added Ordering Code Definitions.
Updated Package Diagram.
*J
3072834
3277371
11/11/2010
06/08/2011
PRAS
AJU
Removed obsolete parts and package diagrams.
*K
Updated Features.
Updated Selection Guide (Removed -12 (Industrial) and -15 (Industrial)
columns).
Updated Electrical Characteristics (Removed -12 (Industrial) and -15
(Industrial) columns).
Updated Switching Characteristics (Removed -12 (Industrial) and -15
(Industrial) columns).
Updated Package Diagram.
Updated in new template.
Document #: 38-05130 Rev. *K
Page 12 of 13
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CY7C1019CV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
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© Cypress Semiconductor Corporation, 2001-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05130 Rev. *K
Revised June 8, 2011
Page 13 of 13
All products and company names mentioned in this document may be the trademarks of their respective holders.
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相关型号：
CY7C1019CV33-12BVXIT
128KX8 STANDARD SRAM, 12ns, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
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