CY7C1019CV33-10VIT [CYPRESS]
Standard SRAM, 128KX8, 10ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32;
| 型号： | CY7C1019CV33-10VIT |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 128KX8, 10ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总10页 (文件大小：520K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1019CV33
128K x 8 Static RAM
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers. This
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
Features
• Pin and function compatible with CY7C1019BV33
• High speed
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location
specified on the address pins (A0 through A16).
— tAA = 8, 10, 12, 15 ns
• CMOS for optimum speed/power
• Data retention at 2.0V
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
• Center power/ground pinout
• Automatic power-down when deselected
• Easy memory expansion with CE and OE options
• Available in 48-ball VFBGA, 32-pin TSOP II and 400-mil
SOJ package
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
• Also available in lead-free 48-ball VFBGA and 32-pin
TSOP II packages
Functional Description
The CY7C1019CV33 is available in Standard 48-ball FBGA,
32-pin TSOP II and 400-mil-wide SOJ packages.
The CY7C1019CV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
Logic Block Diagram
Pin Configuration
SOJ/TSOP II
Top View
A
A
1
A
A
32
1
0
16
31
30
2
3
4
5
6
15
A
A
14
A
13
2
I/O
A
3
29
28
0
INPUT BUFFER
CE
OE
I/O
I/O
I/O
27
26
1
I/O
A
0
0
1
7
A
A
2
1
I/O
V
7
8
9
10
11
12
13
6
I/O
2
25
24
23
22
21
V
CC
SS
A
3
V
A
I/O
V
CC
I/O
4
SS
3
512 x 256 x 8
ARRAY
A
5
I/O
I/O
2
3
5
4
A
6
I/O
I/O
A
4
A
7
A
8
WE
A
4
12
I/O
A
11
5
20
19
A
5
A
10
14
15
16
I/O
6
POWER
DOWN
A
6
A
9
A
8
COLUMN
DECODER
18
17
CE
A
7
I/O
WE
7
OE
Cypress Semiconductor Corporation
Document #: 38-05130 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 9, 2006
CY7C1019CV33
Pin Configuration (continued)
48-ball FBGA
(Top View)
1
4
2
5
3
6
A
A
7
A
NC
OE
NC
2
6
A
B
C
A
A
5
I/O NC
CE
NC
NC
NC
I/O
I/O
7
1
0
A
A
A
NC
NC
I/O
6
I/O
0
4
3
1
NC
V
CC
V
SS
D
E
F
NC
V
CC
NC
V
SS
NC
NC
A
A
11
I/O
I/O
5
14
4
2
A
A
G
H
I/O
NC
A
WE
A8
12
15
3
A
A
A13
NC
NC
9
16
10
Selection Guide
7C1019CV33-8 7C1019CV33-10 7C1019CV33-12 7C1019CV33-15 Unit
Maximum Access Time
8
85
5
10
80
5
12
75
5
15
70
5
ns
Maximum Operating Current
Maximum Standby Current
mA
mA
Document #: 38-05130 Rev. *E
Page 2 of 10
CY7C1019CV33
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current......................................................>200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Ambient
Supply Voltage on VCC to Relative GND[1] ... –0.5V to + 4.6V
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
VCC
DC Voltage Applied to Outputs
3.3V ± 10%
3.3V ± 10%
in High-Z State[1] ....................................–0.5V to VCC + 0.5V
DC Input Voltage[1].................................–0.5V to VCC + 0.5V
Electrical Characteristics Over the Operating Range
7C1019CV33
-8
7C1019CV33
-10
7C1019CV33
-12
7C1019CV33
-15
Parameter Description
Test Conditions Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
VOH
VOL
VIH
VIL
Output HIGH
Voltage
VCC = Min.,
IOH = –4.0 mA
2.4
2.4
2.4
2.4
V
Output LOW
Voltage
VCC = Min.,
0.4
0.4
0.4
0.4
V
V
IOL = 8.0 mA
Input HIGH
Voltage
2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3
Input LOW
Voltage[1]
–0.3
–1
0.8
+1
–0.3
–1
0.8
+1
–0.3
–1
0.8
+1
–0.3
–1
0.8
+1
V
IIX
Input Load
Current
GND < VI < VCC
µA
µA
mA
mA
IOZ
Output Leakage GND < VI < VCC
Current
,
–1
+1
–1
+1
–1
+1
–1
+1
Output Disabled
[2.]
IOS
Output Short
Circuit Current VOUT = GND
VCC = Max.,
–300
85
–300
80
–300
75
–300
70
ICC
VCC Operating VCC = Max.,
Supply Current IOUT = 0 mA,
f = fMAX = 1/tRC
ISB1
Automatic CE
Power-down
Current
Max. VCC, CE >
VIH
VIN > VIH or
15
5
15
5
15
5
15
5
mA
mA
—TTL Inputs
V
IN < VIL, f = fMAX
Max. VCC
CE > VCC – 0.3V,
IN > VCC – 0.3V,
ISB2
Automatic CE
Power-down
Current
,
V
—CMOS Inputs or VIN < 0.3V, f = 0
Capacitance[3]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
CC = 5.0V
Max.
Unit
CIN
8
8
pF
pF
V
COUT
Notes:
1. V (min.) = –2.0V for pulse durations of less than 20 ns.
IL
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05130 Rev. *E
Page 3 of 10
CY7C1019CV33
AC Test Loads and Waveforms[4]
10-, 12-, 15-ns devices:
8-ns devices:
R 317Ω
Ω
Z = 50
3.3V
OUTPUT
OUTPUT
30 pF
50Ω
30 pF*
R2
351Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5V
(b)
(a)
High-Z characteristics:
ALL INPUT PULSES
3.0V
R 317Ω
90%
10%
90%
10%
3.3V
OUTPUT
5 pF
GND
R2
351Ω
(c)
Fall Time: 1 V/ns
Rise Time: 1 V/ns
(d)
Switching Characteristics[5] Over the Operating Range
7C1019CV33-8 7C1019CV33-10 7C1019CV33-12 7C1019CV33-15
Parameter
Read Cycle
tRC
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit
Read Cycle Time
8
3
10
12
15
ns
tAA
Address to Data Valid
8
10
12
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOHA
Data Hold from Address Change
3
3
3
tACE
8
5
10
5
12
6
15
7
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z[6, 7]
CE LOW to Low Z[7]
CE HIGH to High Z[6, 7]
tDOE
tLZOE
0
3
0
0
3
0
0
3
0
0
3
0
tHZOE
tLZCE
4
4
8
5
5
6
6
7
7
tHZCE
[8]
tPU
CE LOW to Power-Up
[8]
tPD
10
12
15
CE HIGH to Power-Down
Write Cycle[9, 10]
tWC
tSCE
tAW
Write Cycle Time
8
7
7
0
0
6
5
0
3
10
8
12
9
15
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
8
9
tHA
0
0
tSA
0
0
0
tPWE
tSD
7
8
10
8
WE Pulse Width
Data Set-Up to Write End
5
6
tHD
Data Hold from Write End
0
0
0
WE HIGH to Low Z[7]
WE LOW to High Z[6, 7]
tLZWE
3
3
3
tHZWE
4
5
6
7
Notes:
4. AC characteristics (except High-Z) for all 8-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin load
shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6. t
, t
, and t
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
HZOE HZCE
HZWE
7. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
8. This parameter is guaranteed by design and is not tested.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any
of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
and t
.
HZWE
SD
Document #: 38-05130 Rev. *E
Page 4 of 10
CY7C1019CV33
Switching Waveforms
Read Cycle No. 1[11, 12]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[12, 13]
ADDRESS
t
RC
CE
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
t
PU
V
CC
50%
50%
SUPPLY
CURRENT
ISB
Write Cycle No. 1 (CE Controlled)[14, 15]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
SCE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
Notes:
11. Device is continuously selected. OE, CE = V
12. WE is HIGH for read cycle.
.
IL
13. Address valid prior to or coincident with CE transition LOW.
14. Data I/O is high impedance if OE = V
.
IH
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05130 Rev. *E
Page 5 of 10
CY7C1019CV33
Switching Waveforms (continued)
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
t
PWE
SA
WE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
NOTE 16
t
HZOE
Write Cycle No. 3 (WE Controlled, OE LOW)[15]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 16
DATA I/O
DATA VALID
t
t
LZWE
HZWE
Truth Table
I/O0–I/O7
Mode
Power
CE
H
L
OE
WE
X
X
L
High Z
Power-Down
Read
Standby (ISB)
H
Data Out
Data In
High Z
Active (ICC
Active (ICC
Active (ICC
)
)
)
L
X
H
L
Write
L
H
Selected, Outputs Disabled
Note:
16. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05130 Rev. *E
Page 6 of 10
CY7C1019CV33
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Ordering Code
Package Type
8
CY7C1019CV33-8VC
CY7C1019CV33-8VI
51-85033 32-pin 400-Mil Molded SOJ
51-85033 32-pin 400-Mil Molded SOJ
51-85033 32-pin 400-Mil Molded SOJ
51-85095 32-pin TSOP II
Commercial
Industrial
10
CY7C1019CV33-10VC
CY7C1019CV33-10ZC
CY7C1019CV33-10ZXC
CY7C1019CV33-10VI
CY7C1019CV33-10ZI
CY7C1019CV33-10ZXI
CY7C1019CV33-12VC
CY7C1019CV33-12ZC
CY7C1019CV33-12ZXC
CY7C1019CV33-12VI
CY7C1019CV33-12ZI
CY7C1019CV33-12BVI
CY7C1019CV33-12BVXI
CY7C1019CV33-15VC
CY7C1019CV33-15ZC
CY7C1019CV33-15ZXC
CY7C1019CV33-15VI
CY7C1019CV33-15ZI
CY7C1019CV33-15ZXI
Commercial
51-85095 32-pin TSOP II (Pb-Free)
51-85033 32-pin 400-Mil Molded SOJ
51-85095 32-pin TSOP II
Industrial
Commercial
Industrial
51-85095 32-pin TSOP II (Pb-Free)
51-85033 32-pin 400-Mil Molded SOJ
51-85095 32-pin TSOP II
12
51-85095 32-pin TSOP II (Pb-Free)
51-85033 32-pin 400-Mil Molded SOJ
51-85095 32-pin TSOP II
51-85150 48-ball VFBGA
51-85150 48-ball VFBGA (Pb-Free)
51-85033 32-pin 400-Mil Molded SOJ
51-85095 32-pin TSOP II
15
Commercial
Industrial
51-85095 32-pin TSOP II (Pb-Free)
51-85033 32-pin 400-Mil Molded SOJ
51-85095 32-pin TSOP II
51-85095 32-pin TSOP II (Pb-Free)
Package Diagrams
32-pin (400-Mil) Molded SOJ (51-85033)
51-85033-A
51-85033-*B
Document #: 38-05130 Rev. *E
Page 7 of 10
CY7C1019CV33
Package Diagrams (continued)
32-pin TSOP II ZS32 (51-85095)
51-85095-**
Document #: 38-05130 Rev. *E
Page 8 of 10
CY7C1019CV33
Package Diagrams (continued)
48-ball VFBGA (6 x 8 x 1 mm) (51-85150)
BOTTOM VIEW
A1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30 0.05ꢀ(48X
1
2
3
(
5
6
6
5
(
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.475
A
A
0.75
B
6.00 0.10
3.75
B
6.00 0.10
0.15ꢀ(8X
51-85150-*D
SEATING PLANE
C
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05130 Rev. *E
Page 9 of 10
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1019CV33
Document History Page
Document Title: CY7C1019CV33 128K x 8 Static RAM
Document Number: 38-05130
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
109245
113431
115047
119796
123030
419983
Description of Change
12/16/01
04/10/02
08/01/02
10/11/02
12/17/02
See ECN
HGK
NSL
HGK
DFP
DFP
NXR
New Data Sheet
AC Test Loads split based on speed.
*A
*B
Added TSOP II Package and I Temp. Improved ICC limits.
Updated standby current from 5 nA to 5 mA.
*C
*D
*E
Updated Truth Table to reflect single Chip Enable option.
Added 48-ball VFBGA Package
Added lead-free parts in Ordering Information Table
Replaced Package Name column with Package Diagram in the Ordering
Information table.
Document #: 38-05130 Rev. *E
Page 10 of 10
相关型号：
CY7C1019CV33-12BVXIT
128KX8 STANDARD SRAM, 12ns, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
ROCHESTER
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