CY7C1019B_06 [CYPRESS]
128K x 8 Static RAM; 128K ×8静态RAM
| 型号： | CY7C1019B_06 |
| 厂家： | 
CYPRESS |
| 描述： | 128K x 8 Static RAM |
| 文件： | 总8页 (文件大小：328K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1019B
128K x 8 Static RAM
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and tri-state drivers. This
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
Features
• High speed
— tAA = 12 ns
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location
specified on the address pins (A0 through A16).
• CMOS for optimum speed/power
• Center power/ground pinout
• Automatic power-down when deselected
• Easy memory expansion with CE and OE options
• Functionally equivalent to CY7C1019
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
• AvailableinPb-freeandnonPb-free32-pinTSOPII, non
Pb-free 400-mil-wide SOJ packages.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
Functional Description
The CY7C1019B is a high-performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory
Logic Block Diagram
Pin Configurations
/TSOPII
SOJ
Top View
A
A
1
A
A
32
1
0
16
31
30
2
3
4
5
6
15
A
A
14
A
13
2
A
29
28
3
I/O0
INPUT BUFFER
CE
OE
I/O
I/O
27
26
I/O
I/O1
I/O2
0
1
7
A
0
I/O
V
7
8
9
10
11
12
13
6
A
1
25
24
23
22
21
A
2
V
CC
SS
A
V
3
V
CC
I/O
SS
A
I/O3
I/O4
I/O5
I/O6
4
128K x 8
ARRAY
I/O
I/O
2
3
5
4
A
5
A
I/O
A
6
A
7
WE
A
4
12
A
8
A
11
20
19
A
5
A
10
14
15
16
A
6
A
9
A
8
18
17
POWER
DOWN
COLUMN
DECODER
A
7
CE
I/O7
WE
OE
Selection Guide
-12
12
-15
15
Unit
ns
Maximum Access Time
Maximum Operating Current
Maximum Standby Current
140
10
130
10
mA
mA
Cypress Semiconductor Corporation
Document #: 38-05026 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 3, 2006
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CY7C1019B
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.....................................................>200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Ambient
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V
Range
Temperature[2]
VCC
DC Voltage Applied to Outputs
Commercial
0°C to +70°C
5V ± 10%
in High Z State[1] ....................................–0.5V to VCC + 0.5V
DC Input Voltage[1].................................–0.5V to VCC + 0.5V
Electrical Characteristics Over the Operating Range
-12
-15
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[1]
Input Leakage Current
Test Conditions
Min.
Max.
Min.
Max.
Unit
VOH
VOL
VIH
VIL
VCC = Min., IOH = – 4.0 mA
VCC = Min., IOL = 8.0 mA
2.4
2.4
V
V
0.4
0.4
2.2
–0.3
–1
VCC + 0.3
2.2
–0.3
–1
VCC + 0.3
V
0.8
+1
+5
0.8
+1
+5
V
IIX
GND < VI < VCC
µA
µA
IOZ
Output Leakage Current GND < VI < VCC
,
–5
–5
Output Disabled
ICC
VCC Operating
Supply Current
VCC = Max., IOUT = 0 mA,
f = fMAX = 1/tRC
140
40
130
40
mA
mA
ISB1
Automatic CE
Max. VCC, CE > VIH
Power- Down Current
—TTL Inputs
VIN > VIH or VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-Down Current
Max. VCC, CE > VCC – 0.3V,
10
10
mA
VIN > VCC – 0.3V,
—CMOS Inputs
or VIN < 0.3V, f = 0
Capacitance[3]
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
VCC = 5.0V
6
8
pF
pF
COUT
AC Test Loads and Waveforms
R1 480Ω
ALL INPUT PULSES
90%
R1 480Ω
5V
5V
OUTPUT
3.0V
GND
90%
OUTPUT
10%
10%
R2
255Ω
R2
255Ω
30 pF
5 pF
≤ 3 ns
≤ 3 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(b)
(a)
Equivalent to: THÉVENIN EQUIVALENT
167Ω
1.73V
OUTPUT
Notes:
1. V (min.) = –2.0V for pulse durations of less than 20 ns.
IL
2. T is the “Instant On” case temperature.
A
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05026 Rev. *C
Page 2 of 8
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CY7C1019B
Switching Characteristics[4] Over the Operating Range
-12
-15
Parameter
Description
Min.
12
3
Max.
Min.
15
3
Max.
Unit
Read Cycle
tRC
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
12
15
tOHA
Data Hold from Address Change
tACE
LOW to Data Valid
LOW to Data Valid
LOW to Low Z
HIGH to High Z[5, 6]
LOW to Low Z[6]
HIGH to High Z[5, 6]
LOW to Power-Up
HIGH to Power-Down
12
6
15
7
CE
OE
OE
OE
CE
CE
CE
CE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
0
3
0
0
3
0
6
6
7
7
tPD
12
15
Write Cycle[7, 8]
tWC
Write Cycle Time
LOW to Write End
12
9
15
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE
tAW
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
8
tHA
0
tSA
0
0
tPWE
tSD
Pulse Width
8
10
8
WE
Data Set-Up to Write End
6
tHD
Data Hold from Write End
HIGH to Low Z[6]
WE
0
0
tLZWE
tHZWE
3
3
LOW to High Z[5, 6]
6
7
WE
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I and 30-pF load capacitance.
OL OH
5. t
, t
, and t
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
HZOE HZCE
HZWE
6. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any
of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
and t
.
SD
HZWE
Document #: 38-05026 Rev. *C
Page 3 of 8
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CY7C1019B
Data Retention Waveform
DATA RETENTION MODE
> 2V
3.0V
3.0V
V
V
CC
DR
t
t
R
CDR
CE
Switching Waveforms
Read Cycle No. 1[9, 10]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[10, 11]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
t
PU
V
CC
50%
50%
SUPPLY
CURRENT
ISB
Notes:
9. Device is continuously selected. OE, CE = V .
IL
10. WE is HIGH for read cycle.
11. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05026 Rev. *C
Page 4 of 8
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CY7C1019B
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[12, 13]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
SCE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[12, 13]
t
WC
ADDRESS
CE
t
SCE
t
t
AW
HA
t
t
PWE
SA
WE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
NOTE 14
t
HZOE
Notes:
12. Data I/O is high impedance if OE = V
.
IH
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
14. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05026 Rev. *C
Page 5 of 8
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CY7C1019B
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[13]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 14
DATA I/O
DATA VALID
t
t
LZWE
HZWE
Truth Table
I/O0–I/O7
Mode
Power
CE
OE
WE
H
X
L
X
High Z
Power-Down
Read
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
)
L
L
L
H
L
Data Out
Data In
High Z
)
X
H
Write
)
H
Selected, Outputs Disabled
)
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C1019B-12VC
Package Type
12
51-85033 32-pin 400-Mil Molded SOJ
51-85095 32-pin TSOP Type II
Commercial
CY7C1019B-12ZC
CY7C1019B-12ZXC
CY7C1019B-15VC
CY7C1019B-15ZXC
32-pin TSOP Type II (Pb -Free)
15
51-85033 32-pin 400-Mil Molded SOJ
51-85095 32-pin TSOP Type II (Pb -Free)
Commercial
Please contact local sales representative regarding availability of these parts
Document #: 38-05026 Rev. *C
Page 6 of 8
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CY7C1019B
Package Diagrams
32-pin (400-mil) Molded SOJ (51-85033)
51-85033-*B
32-pin TSOP II (51-85095)
51-85095-**
All product or company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05026 Rev. *C
Page 7 of 8
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1019B
Document History Page
Document Title: CY7C1019B 128K x 8 Static RAM
Document Number: 38-05026
Orig. of
REV.
**
ECN NO.
109949
116170
Issue Date
09/25/01
08/14/02
Change
Description of Change
SZV
Change from Spec number: 38-01115 to 38-05026
*A
HGK
1. SOJ (400-mil) package outline replacing incorrect SOJ package
2. Pin for pin compatible with CY7C1019
3. Industrial packages added to Ordering Information
*B
*C
397875
493543
See ECN
See ECN
NXR
NXR
Changed address of Cypress Semiconductor Corporation on Page# 1
from “3901 North First Street” to “198 Champion Court”
Updated the Ordering Information Table on page # 6
Removed CY7C10191B from product offering
Removed Industrial Operating Range
Changed the description of IIX from Input Load Current to
Input Leakage Current in DC Electrical Characteristics table
Removed IOS parameter from DC Electrical Characteristics table
Updated Ordering Information table
Document #: 38-05026 Rev. *C
Page 8 of 8
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