CY29774AIT [CYPRESS]
2.5V or 3.3V, 125-MHz, 14 Output Zero Delay Buffer; 2.5V或3.3V ， 125兆赫， 14输出零延迟缓冲器
| 型号： | CY29774AIT |
| 厂家： | 
CYPRESS |
| 描述： | 2.5V or 3.3V, 125-MHz, 14 Output Zero Delay Buffer |
| 文件： | 总9页 (文件大小：77K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74
CY29774
2.5V or 3.3V, 125-MHz, 14 Output Zero Delay Buffer
The CY29774 features two reference clock inputs and pro-
vides 14 outputs partitioned in 3 banks of 5, 5, and 4 outputs.
Features
• Output frequency range: 8.3 MHz to 125 MHz
• Input frequency range: 4.2 MHz to 62.5 MHz
• 2.5V or 3.3V operation
• Split 2.5V/3.3V outputs
• 14 Clock outputs: Drive up to 28 clock lines
• 1 Feedback clock output
• 2 LVCMOS reference clock inputs
• 150 ps max output-output skew
• PLL bypass mode
• Spread Aware™
• Output enable/disable
Bank A and Bank B divide the VCO output by 4 or 8 while Bank
C divides by 8 or 12 per SEL(A:C) settings, see Functional
Table. These dividers allow output to input ratios of 6:1, 4:1,
3:1, 2:1, 3:2, 4:3, 1:1, and 2:3. Each LVCMOS compatible out-
put can drive 50Ω series or parallel terminated transmission
lines. For series terminated transmission lines, each output
can drive one or two traces giving the device an effective
fanout of 1:28.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range
of output frequencies from 8.3 MHz to 125 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
the feedback output, FB_OUT. The internal VCO is running at
multiples of the input reference clock set by the feedback di-
vider, see Frequency Table.
• Pin compatible with MPC9774
• Industrial temperature range: –40°C to +85°C
• 52-Pin 1.0-mm TQFP package
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
Description
The CY29774 is a low-voltage high-performance 125-MHz
PLL-based zero delay buffer designed for high-speed clock
distribution applications.
Pin Configuration
Block Diagram
VCO_SEL
PLL_EN
TCLK_SEL
TCLK0
TCLK1
PLL
52 51 50 49 48 47 46 45 44 43 42 41 40
QA0
÷2
÷4
CLK
÷2
/ ÷4
STOP
200 -
VSS
VSS
MR#/OE
CLK_STP#
SELB
1
39
38
37
36
35
34
33
32
31
30
29
28
27
QA1
QA2
QA3
QA4
500MHz
QB1
FB_IN
SELA
2
3
VDDQB
QB2
4
VSS
SELC
5
QB3
PLL_EN
SELA
CLK
STOP
6
÷2
/ ÷4
QB0
QB1
QB2
QB3
QB4
VDDQB
QB4
7
CY29774
TCLK_SEL
TCLK0
TCLK1
NC
8
9
SELB
FB_IN
VSS
10
11
12
13
FB_OUT
VDDFB
NC
VDD
CLK
STOP
÷4
/ ÷6
QC0
QC1
QC2
QC3
AVDD
14 15 16 17 18 19 20 21 22 23 24 25 26
SELC
CLK_STP#
FB_OUT
÷4
/
÷6
/
÷8
/
÷12
FB_SEL(1,0)
MR#/OE
Cypress Semiconductor Corporation
Document #: 38-07479 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Revised April 28, 2003
CY29774
Pin Description[1]
Pin
Name
I/O
I, PD
I, PU
O
Type
Description
9
TCLK0
TCLK1
QA(4:0)
LVCMOS LVCMOS/LVTTL reference clock input
LVCMOS LVCMOS/LVTTL reference clock input
LVCMOS Clock output bank A
10
16, 18, 21,
23, 25
32, 34, 36,
38, 40
QB(4:0)
QC(3:0)
O
O
LVCMOS Clock output bank B
LVCMOS Clock output bank C
44, 46, 48,
50
29
31
FB_OUT
FB_IN
O
LVCMOS Feedback clock output. Connect to FB_IN for normal operation.
I, PU
LVCMOS Feedback clock input. Connect to FB_OUT for normal operation.
This input should be at the same voltage rail as input reference clock.
See Table 1.
2
MR#/OE
CLK_STP#
PLL_EN
TCLK_SEL
VCO_SEL
SEL(A:C)
FB_SEL(1,0)
VDDQA
VDDQB
VDDQC
VDDFB
AVDD
I, PU
I, PU
LVCMOS Output enable/disable input. See Table 2.
LVCMOS Clock stop enable/disable input. See Table 2.
LVCMOS PLL enable/disable input. See Table 2.
LVCMOS Reference select input. See Table 2.
3
6
I, PU
8
I, PD
52
I, PD
LVCMOS VCO divider select input. See Table 2.
LVCMOS Frequency select input, Bank (A:C). See Table 3.
LVCMOS Feedback dividers select input. See Table 4.
7, 4, 5
20, 14
17, 22, 26
33, 37, 41
45, 49
28
I, PD
I, PD
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
VDD
VDD
2.5V or 3.3V Power supply for bank A output clocks[2,3]
2.5V or 3.3V Power supply for bank B output clocks[2,3]
2.5V or 3.3V Power supply for bank C output clocks[2,3]
2.5V or 3.3V Power supply for feedback output clock[2,3]
2.5V or 3.3V Power supply for PLL[2,3]
VDD
VDD
13
VDD
12
VDD
VDD
2.5V or 3.3V Power supply for core and inputs[2,3]
15
AVSS
Ground
Ground
Analog Ground
1, 19, 24,
30, 35, 39,
43, 47, 51
VSS
Common Ground
11, 27, 42
NC
No Connection
Notes:
1. PU = Internal pull up, PD = Internal pull down
2. A 0.1-µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their
high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, VDDQC, and VDDFB power supply
pins.
Document #: 38-07479 Rev. **
Page 2 of 9
CY29774
Table 1. Frequency Table
Feedback Output
Divider
VCO
Input Frequency Range
(AVDD = 3.3V)
Input Frequency Range
(AVDD = 2.5V)
Input Clock * 8
Input Clock * 12
Input Clock * 16
Input Clock * 24
Input Clock * 32
Input Clock * 48
25 MHz to 62.5 MHz
16.6 MHz to 41.6 MHz
12.5 MHz to 31.25 MHz
8.3 MHz to 20.8 MHz
6.25 MHz to 15.625 MHz
4.2 MHz to 10.4 MHz
25 MHz to 50 MHz
÷8
16.6 MHz to 33.3 MHz
12.5 MHz to 25 MHz
8.3 MHz to 16.6 MHz
6.25 MHz to 12.5 MHz
4.2 MHz to 8.3 MHz
÷12
÷16
÷24
÷32
÷48
Table 2. Function Table (configuration controls)
Control
TCLK_SEL
VCO_SEL
PLL_EN
Default
0
1
0
0
1
TCLK0
TCLK1
VCO÷2 (high input frequency range)
VCO÷4 (low input frequency range)
Bypass mode, PLL disabled. The input clock
connects to the output dividers
PLL enabled. The VCO output
connects to the output dividers
MR#/OE
1
Outputs disabled (three-state) and reset of the
device. During reset/output disable the PLL feedback
loop is open and the VCO running at its minimum
frequency. The device is reset by the internal
power-on reset (POR) circuitry during power-up.
Outputs enabled
Outputs enabled
CLK_STP#
1
QA, QB, and QC outputs disabled in LOW state.
FB_OUT is not affected by CLK_STP#.
Table 3. Function Table (Bank A, B and C)
VCO_SEL
SELA
QA(4:0)
÷4
SELB
QB(4:0)
÷4
SELC
QC(3:0)
÷8
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
÷8
÷8
÷12
÷8
÷8
÷16
÷16
÷16
÷24
Table 4. Function Table (FB_OUT)
VCO_SEL
FB_SEL1
FB_SEL0
FB_OUT
÷8
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷16
÷12
÷24
÷16
÷32
÷24
÷48
Document #: 38-07479 Rev. **
Page 3 of 9
CY29774
.
Absolute Maximum Conditions
Parameter
VDD
VDD
VIN
Description
DC Supply Voltage
Condition
Functional
Min.
–0.3
2.375
–0.3
–0.3
–
Max.
5.5
Unit
V
DC Operating Voltage
3.465
V
DC Input Voltage
Relative to VSS
Relative to VSS
VDD + 0.3
VDD + 0.3
V
VOUT
VTT
DC Output Voltage
V
Output termination Voltage
Latch Up Immunity
V
DD ÷ 2
–
V
LU
Functional
200
–
mA
mVp-p
°C
RPS
TS
Power Supply Ripple
Ripple Frequency < 100 kHz
Non Functional
Functional
150
Temperature, Storage
–65
–40
–
+150
+85
150
23
TA
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Failure in Time
°C
TJ
Functional
°C
ØJC
ØJA
ESDH
FIT
Functional
–
°C/W
°C/W
Volts
ppm
Functional
–
55
2000
–
Manufacturing test
10
DC Electrical Specifications (VDD= 2.5V ± 5%, TA = –40°C to +85°C)
Parameter
VIL
Description
Input Voltage, Low
Condition
LVCMOS
Min.
–
Typ.
Max.
0.7
Unit
V
–
–
VIH
Input Voltage, High
LVCMOS
1.7
–
VDD+0.3
V
VOL
VOH
IIL
Output Voltage, Low[4]
Output Voltage, High[4]
Input Current, Low[5]
Input Current, High[5]
PLL Supply Current
Quiescent Supply Current
Dynamic Supply Current
Input Pin Capacitance
Output Impedance
IOL = 15 mA
–
0.6
–
V
IOH = –15 mA
VIL = VSS
1.8
–
–
V
–
–100
–
µA
µA
mA
mA
mA
pF
Ω
IIH
VIL = VDD
–
–
IDDA
IDDQ
IDD
AVDD only
–
5
10
1
All VDD pins except AVDD
Outputs loaded @ 100 MHz
–
–
–
135
4
–
CIN
–
–
ZOUT
14
18
22
DC Electrical Specifications (VDD= 3.3V ± 5%, TA = –40°C to +85°C)
Parameter
VIL
Description
Input Voltage, Low
Condition
Min.
–
Typ.
–
Max.
0.8
Unit
V
LVCMOS
LVCMOS
VIH
Input Voltage, High
2.0
–
–
VDD+0.3
0.55
0.30
–
V
VOL
Output Voltage, Low[4]
IOL = 24 mA
OL = 12 mA
–
V
I
–
–
VOH
IIL
Output Voltage, High[4]
Input Current, Low[5]
Input Current, High[5]
IOH = –24 mA
VIL = VSS
2.4
–
–
V
–
–100
100
µA
µA
IIH
VIL = VDD
–
–
Notes:
4. Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50Ω series terminated
transmission lines.
5. Inputs have pull-up or pull-down resistors that affect the input current.
Document #: 38-07479 Rev. **
Page 4 of 9
CY29774
DC Electrical Specifications (VDD= 3.3V ± 5%, TA = –40°C to +85°C) (continued)
Parameter
IDDA
Description
PLL Supply Current
Condition
AVDD only
Min.
–
Typ.
5
Max.
Unit
mA
mA
mA
pF
10
1
IDDQ
Quiescent Supply Current
Dynamic Supply Current
Input Pin Capacitance
Output Impedance
All VDD pins except AVDD
–
–
IDD
Outputs loaded @ 100 MHz
–
225
4
–
CIN
–
–
ZOUT
12
15
18
Ω
AC Electrical Specifications[6] (VDD= 2.5V ± 5%, TA = –40°C to +85°C)
Parameter Description Condition
fVCO VCO Frequency
Min.
Typ.
Max.
Unit
MHz
MHz
200
25
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
400
50
fin
Input Frequency
÷8 Feedback
÷12 Feedback
16.6
12.5
8.3
6.3
4.2
0
33.3
25
÷16 Feedback
÷24 Feedback
16.6
12.5
8.3
÷32 Feedback
÷48 Feedback
Bypass mode (PLL_EN = 0)
200
75
frefDC
tr , tf
Input Duty Cycle
25
%
ns
TCLK Input Rise/FallTime
Maximum Output Frequency
0.7V to 1.7V
÷4 Output
–
1.0
fMAX
50
100
50
MHz
÷8 Output
25
÷12 Output
÷16 Output
÷24 Output
16.6
12.5
8.3
45
33.3
25
16.6
55
DC
tr , tf
t(φ)
Output Duty Cycle
%
ns
ps
Output Rise/Fall times
0.7V to 1.8V
0.1
–100
1.0
Propagation Delay (static phase
offset)
TCLK to FB_IN, does not
include jitter
100
tsk(O)
Output-to-Output Skew
Bank-to-Bank Skew
Skew within Bank
–
–
–
–
–
–
–
–
–
–
–
–
150
150
225
10
ps
ps
tsk(B)
Banks at same frequency
Banks at different frequency
–
–
tPLZ, HZ
tPZL, ZH
BW
Output Disable Time
–
ns
ns
Output Enable Time
–
10
PLL Closed Loop Bandwidth (–3 dB)
Cycle-to-Cycle Jitter
0.5 - 1.0
–
MHz
ps
tJIT(CC)
Same frequency
–
–
–
–
–
150
300
100
150
1
Multiple frequencies
tJIT(PER)
tJIT(φ)
Period Jitter
ps
ps
I/O Phase Jitter
tLOCK
Maximum PLL Lock Time
ms
Note:
6. AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested.
Document #: 38-07479 Rev. **
Page 5 of 9
CY29774
AC Electrical Specifications[6] (VDD= 3.3V ± 5%, TA = –40°C to +85°C)
Parameter Description Condition
fVCO VCO Frequency
Min.
200
25
Typ.
–
Max.
500
Unit
MHz
MHz
fin
Input Frequency
÷8 Feedback
–
62.5
41.6
÷12 Feedback
16.6
12.5
8.3
6.25
4.2
0
–
÷16 Feedback
–
31.25
20.8
15.625
10.4
200
÷24 Feedback
–
÷32 Feedback
–
÷48 Feedback
–
Bypass mode (PLL_EN = 0)
–
frefDC
tr , tf
Input Duty Cycle
25
–
75
%
ns
TCLK Input Rise/FallTime
Maximum Output Frequency
0.8V to 2.0V
÷4 Output
–
1.0
fMAX
50
25
–
125
MHz
÷8 Output
–
62.5
41.6
31.25
20.8
55
÷12 Output
÷16 Output
÷24 Output
16.6
12.5
8.3
–
–
–
DC
tr , tf
t(φ)
Output Duty Cycle
45
–
%
ns
ps
Output Rise/Fall times
0.8V to 2.4V
0.1
–
1.0
Propagation Delay (static phase
offset)
TCLK to FB_IN, same VDD
does not include jitter
,
–100
–
100
tsk(O)
tsk(B)
Output-to-Output Skew
Bank-to-Bank Skew
Skew within Bank
–
–
–
–
150
150
ps
ps
Banks at same voltage,
same frequency
Banks at same voltage,
different frequency
–
–
225
Banks at different voltage
–
–
–
–
–
250
10
10
–
tPLZ, HZ
tPZL, ZH
BW
Output Disable Time
Output Enable Time
–
–
ns
ns
PLL Closed Loop Bandwidth
(–3dB)
0.5 - 1.0
MHz
tJIT(CC)
Cycle-to-Cycle Jitter
Same frequency
–
–
–
–
–
–
–
–
–
–
150
300
100
150
1
ps
Multiple frequencies
tJIT(PER)
tJIT(φ)
Period Jitter
ps
ps
I/O Phase Jitter
I/O at same VDD
tLOCK
Maximum PLL Lock Time
ms
Document #: 38-07479 Rev. **
Page 6 of 9
CY29774
Zo = 50 ohm
Zo = 50 ohm
Pulse
Generator
Z = 50 ohm
RT = 50 ohm
RT = 50 ohm
VTT
VTT
Figure 1. AC Test Reference for VDD = 3.3V / 2.5V
VDD
LVCMOS_CLK
VDD/2
GND
VDD
FB_IN
VDD/2
t(φ)
GND
Figure 2. Propagation Delay t(φ), Static Phase Offset
VDD
VDD/2
tP
GND
T0
DC = tP / T0 x 100%
Figure 3. Output Duty Cycle (DC)
VDD
VDD/2
GND
VDD
VDD/2
GND
tSK(O)
Figure 4. Output-to-Output Skew, tsk(O)
Document #: 38-07479 Rev. **
Page 7 of 9
CY29774
Ordering Information
Part Number
Package Type
Product Flow
CY29774AI
52-pin TQFP
52-pin TQFP -Tape and Reel
Industrial, –40°C to +85°C
Industrial, –40°C to 85°C
CY29774AIT
Package Drawing and Dimension
52-Lead Thin Plastic Quad Flat Pack (10 x 10 x 1.0 mm) A52B
51-85158-**
Spread Aware is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document
are the trademarks of their respective holders.
Document #: 38-07479 Rev. **
Page 8 of 9
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY29774
Document History Page
Document Title:CY29774 2.5V or 3.3V, 125-MHz, 14 Output Zero Delay Buffer
Document #: 38-07479
Issue
Date
Orig. of
Change
Rev.
ECN No.
Description of Change
**
125954
05/01/03
RGL
New Data Sheet
Document #: 38-07479 Rev. **
Page 9 of 9
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