CY29775AIT [CYPRESS]
2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer; 2.5V或3.3V ， 200兆赫， 14输出零延迟缓冲器
| 型号： | CY29775AIT |
| 厂家： | 
CYPRESS |
| 描述： | 2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer |
| 文件： | 总11页 (文件大小：298K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY29775
2.5V or 3.3V, 200-MHz, 14 Output Zero
Delay Buffer
Features
Description
■ Output frequency range: 8.3 MHz to 200 MHz
■ Input frequency range: 4.2 MHz to 125 MHz
■ 2.5V or 3.3V operation
The CY29775 is a low-voltage high-performance 200-MHz
PLL-based zero delay buffer designed for high-speed clock
distribution applications.
The CY29775 features two reference clock inputs and provides
14 outputs partitioned in 3 banks of 5, 5, and 4 outputs. Bank A
and Bank B divide the VCO output by 4 or 8 while Bank C divides
by 8 or 12 per SEL(A:C) settings, see Function Table (Bank A,
B, and C) on page 4. These dividers allow output to input ratios
of 6:1, 4:1, 3:1, 2:1, 3:2, 4:3, 1:1, and 2:3. Each LVCMOS
compatible output can drive 50Ω series or parallel terminated
transmission lines. For series terminated transmission lines,
each output can drive one or two traces giving the device an
effective fanout of 1:28.
■ Split 2.5V/3.3V outputs
■ 14 Clock outputs: Drive up to 28 clock lines
■ 1 Feedback clock output
■ 2 LVCMOS reference clock inputs
■ 150 ps max output-output skew
■ PLL bypass mode
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range of
output frequencies from 8.3 MHz to 200 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
the feedback output, FB_OUT. The internal VCO is running at
multiples of the input reference clock set by the feedback divider,
see Frequency Table on page 4.
■ Spread Aware™
■ Output enable/disable
■ Industrial temperature range: –40°C to +85°C
■ 52-Pin 1.0-mm TQFP package
When PLL_EN is LOW, PLL is bypassed and the reference clock
directly feeds the output dividers. This mode is fully static and the
minimum input clock frequency specification does not apply.
Block Diagram
VCO_SEL(1,0)
PLL_EN
TCLK_SEL
TCLK0
TCLK1
PLL
200 -
500MHz
CLK
STOP
÷2
QA0
÷2
/ ÷4
÷4
QA1
QA2
QA3
QA4
FB_IN
SELA
CLK
STOP
÷2
/ ÷4
QB0
QB1
QB2
QB3
QB4
SELB
CLK
STOP
÷4
/ ÷6
QC0
QC1
QC2
QC3
SELC
CLK_STP#
FB_OUT
÷4
/
÷6
/
÷8
/
÷12
FB_SEL(1,0)
MR#/OE
Cypress Semiconductor Corporation
Document #: 38-07480 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 19, 2007
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CY29775
Pinouts
Figure 1. Pin Diagram - 52-Pin 1.0-mm TQFP package
52 51 50 49 48 47 46 45 44 43 42 41 40
VSS
VSS
MR#/OE
CLK_STP#
SELB
1
2
39
38
37
36
35
34
33
32
31
30
29
28
27
QB1
VDDQB
QB2
3
4
VSS
SELC
5
QB3
PLL_EN
SELA
6
VDDQB
QB4
7
CY29775
TCLK_SEL
TCLK0
8
FB_IN
VSS
9
10
11
12
13
TCLK1
FB_OUT
VDDFB
NC
VCO_SEL1
VDD
AVDD
14 15 16 17 18 19 20 21 22 23 24 25 26
Table 1. Pin Definition - 52-Pin 1.0-mm TQFP package
Pin[1]
Name
TCLK0
IO
I, PD
I, PU
O
Type
Description
9
LVCMOS LVCMOS/LVTTL reference clock input
LVCMOS LVCMOS/LVTTL reference clock input
LVCMOS Clock output bank A
10
TCLK1
16, 18, 21,
23, 25
QA(4:0)
32, 34, 36,
38, 40
QB(4:0)
QC(3:0)
O
O
LVCMOS Clock output bank B
LVCMOS Clock output bank C
44, 46, 48,
50
29
31
FB_OUT
FB_IN
O
LVCMOS Feedback clock output. Connect to FB_IN for normal operation.
I, PU
LVCMOS Feedback clock input. Connect to FB_OUT for normal operation.
This input must be at the same voltage rail as input reference clock.
See Table 2 on page 4.
2
MR#/OE
I, PU
I, PU
LVCMOS Output enable/disable input. See Table 3 on page 4.
LVCMOS Clock stop enable/disable input. See Table 3 on page 4.
LVCMOS PLL enable/disable input. See Table 3 on page 4.
LVCMOS Reference select input. See Table 3 on page 4.
LVCMOS VCO divider select input. See Tables 3, 4 and 5.
LVCMOS Frequency select input, Bank (A:C). See Table 4 on page 4.
LVCMOS Feedback dividers select inputs. See Table 5 on page 5.
3
CLK_STP#
PLL_EN
6
I, PU
8
TCLK_SEL
VCO_SEL(1,0)
SEL(A:C)
FB_SEL(1,0)
VDDQA
I, PD
11, 52
7, 4, 5
20, 14
17, 22, 26
33, 37, 41
I, PD
I, PD
I, PD
Supply
Supply
VDD
VDD
2.5V or 3.3V Power supply for bank A output clocks[2,3]
2.5V or 3.3V Power supply for bank B output clocks[2,3]
VDDQB
Notes
1. PU = Internal pull up, PD = Internal pull down
2. A 0.1-μF bypass capacitor must be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their high
frequency filtering characteristics is cancelled by the lead inductance of the traces.
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, VDDQC, and VDDFB power supply
pins.
Document #: 38-07480 Rev. *A
Page 2 of 11
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CY29775
Table 1. Pin Definition - 52-Pin 1.0-mm TQFP package (Continued)
Pin[1]
45, 49
Name
VDDQC
IO
Type
VDD
Description
2.5V or 3.3V Power supply for bank C output clocks[2,3]
2.5V or 3.3V Power supply for feedback output clock[2,3]
2.5V or 3.3V Power supply for PLL[2,3]
2.5V or 3.3V Power supply for core and inputs[2,3]
Analog Ground
Supply
Supply
Supply
Supply
Supply
Supply
28
13
12
15
VDDFB
AVDD
VDD
VDD
VDD
VDD
AVSS
VSS
Ground
Ground
1, 19, 24,
30, 35, 39,
43, 47, 51
Common Ground
27, 42
NC
No Connection
Document #: 38-07480 Rev. *A
Page 3 of 11
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CY29775
Table 2. Frequency Table
Feedback Output
Divider
VCO
Input Frequency Range
(AVDD = 3.3V)
Input Frequency Range
(AVDD = 2.5V)
Input Clock * 8
Input Clock * 12
Input Clock * 16
Input Clock * 24
Input Clock * 32
Input Clock * 48
Input Clock * 4
Input Clock * 6
Input Clock * 8
Input Clock * 12
25 MHz to 62.5 MHz
16.6 MHz to 41.6 MHz
12.5 MHz to 31.25 MHz
8.3 MHz to 20.8 MHz
6.25 MHz to 15.625 MHz
4.2 MHz to 10.4 MHz
50 MHz to 125 MHz
25 MHz to 50 MHz
÷8
÷12
÷16
÷24
÷32
÷48
÷4
16.6 MHz to 33.3 MHz
12.5 MHz to 25 MHz
8.3 MHz to 16.6 MHz
6.25 MHz to 12.5 MHz
4.2 MHz to 8.3 MHz
50 MHz to 100 MHz
33.3 MHz to 66.6 MHz
25 MHz to 50 MHz
33.3 MHz to 83.3 MHz
25 MHz to 62.5 MHz
16.6 MHz to 41.6 MHz
÷6
÷8
16.6 MHz to 33.3 MHz
÷12
Table 3. Function Table (configuration controls)
Control
TCLK_SEL
VCO_SEL0
VCO_SEL1
PLL_EN
Default
0
1
0
0
0
1
TCLK0
TCLK1
VCO÷2 (mid input frequency range)
Gated by VCO_SEL0
VCO÷4 (low input frequency range)
VCO (high input frequency range)
Bypass mode, PLL disabled. The input clock connects PLLenabled. TheVCOoutputconnects
to the output dividers
to the output dividers
MR#/OE
1
Outputs disabled (three-state) and reset of the device.
During reset/output disable the PLL feedback loop is
open and the VCO running at its minimum frequency.
The device is reset by the internal power on reset
(POR) circuitry during power up.
Outputs enabled
CLK_STP#
1
QA, QB, and QC outputs disabled in LOW state.
FB_OUT is not affected by CLK_STP#.
Outputs enabled
Table 4. Function Table (Bank A, B, and C)
VCO_SEL1 VCO_SEL0
SELA
QA(4:0)
SELB
QB(4:0)
SELC
QC(3:0)
0
0
0
0
÷4
0
÷8
÷4
÷8
0
0
0
1
1
0
1
1
x
x
1
0
1
0
1
1
0
1
0
1
÷8
÷8
1
0
1
0
1
÷12
÷16
÷24
÷4
÷8
÷16
÷2
÷16
÷2
÷4
÷4
÷6
Document #: 38-07480 Rev. *A
Page 4 of 11
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CY29775
Table 5. Function Table (FB_OUT)
VCO_SEL1
VCO_SEL0
FB_SEL1
FB_SEL0
FB_OUT
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
x
x
x
x
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
÷8
÷16
÷12
÷24
÷16
÷32
÷24
÷48
÷4
÷8
÷6
÷12
Absolute Maximum Conditions
Parameter
VDD
VDD
VIN
Description
DC Supply Voltage
Condition
Min
Max
5.5
Unit
V
–0.3
2.375
–0.3
–0.3
–
DC Operating Voltage
Functional
3.465
VDD + 0.3
VDD + 0.3
VDD ÷ 2
–
V
DC Input Voltage
Relative to VSS
Relative to VSS
V
VOUT
VTT
DC Output Voltage
V
Output termination Voltage
Latch Up Immunity
V
LU
Functional
200
–
mA
mVp-p
°C
RPS
TS
Power Supply Ripple
Ripple Frequency < 100 kHz
Non Functional
Functional
150
Temperature, Storage
–65
–40
–
+150
+85
TA
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Failure in Time
°C
TJ
Functional
150
°C
ØJC
ØJA
ESDH
FIT
Functional
–
23
°C/W
°C/W
Volts
ppm
Functional
–
55
2000
–
Manufacturing test
10
Document #: 38-07480 Rev. *A
Page 5 of 11
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CY29775
DC Electrical Specifications (VDD= 3.3V ± 5%, TA = –40°C to +85°C)
Parameter
VIL
Description
Input Voltage, Low
Condition
Min
–
Typ.
–
Max
0.8
VDD+0.3
0.55
0.30
–
Unit
V
LVCMOS
LVCMOS
VIH
Input Voltage, High
2.0
–
–
V
VOL
Output Voltage, Low[4]
IOL = 24 mA
–
V
IOL = 12 mA
–
–
VOH
IIL
Output Voltage, High[4]
Input Current, Low[5]
Input Current, High[5]
PLL Supply Current
IOH = –24 mA
2.4
–
–
V
VIL = VSS
–
–100
100
10
μA
μA
mA
mA
mA
IIH
VIL = VDD
–
–
IDDA
IDDQ
IDD
AVDD only
–
5
Quiescent Supply Current
Dynamic Supply Current
All VDD pins except AVDD
Outputs loaded at 100 MHz
Outputs loaded at 200 MHz
–
–
1
–
225
290
4
–
–
–
CIN
Input Pin Capacitance
Output Impedance
–
–
pF
ZOUT
12
15
18
Ω
DC Electrical Specifications (VDD= 2.5V ± 5%, TA = –40°C to +85°C)
Parameter
VIL
Description
Input Voltage, Low
Condition
LVCMOS
Min
–
Typ.
–
Max
Unit
V
0.7
VIH
Input Voltage, High
LVCMOS
1.7
–
–
VDD+0.3
V
VOL
VOH
IIL
Output Voltage, Low[4]
Output Voltage, High[4]
Input Current, Low[5]
Input Current, High[5]
PLL Supply Current
IOL = 15 mA
–
0.6
–
V
IOH = –15 mA
1.8
–
–
V
VIL = VSS
–
–100
100
10
1
μA
μA
mA
mA
mA
IIH
VIL = VDD
–
–
IDDA
IDDQ
IDD
AVDD only
–
5
Quiescent Supply Current
Dynamic Supply Current
All VDD pins except AVDD
Outputs loaded at 100 MHz
Outputs loaded at 200 MHz
–
–
–
135
160
4
–
–
–
CIN
Input Pin Capacitance
Output Impedance
–
–
pF
ZOUT
14
18
22
Ω
Notes
4. Driving one 50Ω parallel terminated transmission line to a termination voltage of V . Alternatively, each output drives up to two 50Ω series terminated transmission lines.
TT
5. Inputs have pull up or pull down resistors that affect the input current
Document #: 38-07480 Rev. *A
Page 6 of 11
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CY29775
AC Electrical Specifications (VDD= 2.5V ± 5%, TA = –40°C to +85°C)
Parameter[6]
Description
VCO Frequency
Condition
Min
200
50
Typ.
–
Max
400
100
66.6
50
Unit
MHz
MHz
fVCO
fin
Input Frequency
÷4 Feedback
–
÷6 Feedback
33.3
25
–
÷8 Feedback
–
÷12 Feedback
÷16 Feedback
÷24 Feedback
÷32 Feedback
÷48 Feedback
Bypass mode (PLL_EN = 0)
16.7
12.5
8.3
6.3
4.2
0
–
33.3
25
–
–
16.7
12.5
8.3
–
–
–
200
75
frefDC
tr , tf
Input Duty Cycle
25
–
%
ns
TCLK Input Rise/FallTime
Maximum Output Frequency
0.7V to 1.7V
÷2 Output
÷4 Output
÷6 Output
÷8 Output
÷12 Output
÷16 Output
÷24 Output
–
–
1.0
fMAX
100
50
–
200
100
66.6
50
MHz
–
33.3
25
–
–
16.7
12.5
8.3
45
–
33.3
25
–
–
16.7
55
DC
tr , tf
t(φ)
Output Duty Cycle
–
%
ns
ps
Output Rise/Fall times
0.7V to 1.8V
0.1
–100
–
1.0
Propagation Delay (static phase
offset)
TCLK to FB_IN, does not
include jitter
–
100
tsk(O)
Output-to-Output Skew
Bank-to-Bank Skew
Skew within Bank
–
–
–
–
–
–
–
–
–
–
–
–
–
150
150
225
10
ps
ps
tsk(B)
Banks at same frequency
Banks at different frequency
–
–
tPLZ, HZ
tPZL, ZH
BW
Output Disable Time
Output Enable Time
–
ns
ns
–
10
PLL Closed Loop Bandwidth
(–3 dB)
VCO_SEL = 0
0.5 - 1.0
–
MHz
VCO_SEL = 1
1.0 - 2.0
–
tJIT(CC)
Cycle-to-Cycle Jitter
Same frequency
Multiple frequencies
–
–
–
–
–
150
300
100
150
1
ps
tJIT(PER)
tJIT(φ)
Period Jitter
ps
ps
IO Phase Jitter
tLOCK
Maximum PLL Lock Time
ms
Note
6. AC characteristics apply for parallel output termination of 50Ω to V . Parameters are guaranteed by characterization and are not 100% tested.
TT
Document #: 38-07480 Rev. *A
Page 7 of 11
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CY29775
AC Electrical Specifications (VDD= 3.3V ± 5%, TA = –40°C to +85°C)
Parameter[6]
Description
VCO Frequency
Condition
Min
200
50
Typ.
–
Max
500
125
83.3
62.5
41.6
31.3
20.8
15.6
10.4
200
75
Unit
MHz
MHz
fVCO
fin
Input Frequency
÷4 Feedback
–
÷6 Feedback
33.3
25
–
÷8 Feedback
–
÷12 Feedback
÷16 Feedback
÷24 Feedback
÷32 Feedback
÷48 Feedback
Bypass mode (PLL_EN = 0)
16.7
12.5
8.3
6.3
4.2
0
–
–
–
–
–
–
frefDC
tr , tf
Input Duty Cycle
25
–
%
ns
TCLK Input Rise/FallTime
Maximum Output Frequency
0.8V to 2.0V
÷2 Output
÷4 Output
÷6 Output
÷8 Output
÷12 Output
÷16 Output
÷24 Output
–
–
1.0
fMAX
100
50
–
200
125
83.3
62.5
41.6
31.3
20.8
55
MHz
–
33.3
25
–
–
16.7
12.5
8.3
45
–
–
–
DC
tr , tf
t(φ)
Output Duty Cycle
–
%
ns
ps
Output Rise/Fall times
0.8V to 2.4V
0.1
–100
–
1.0
Propagation Delay (static phase
offset)
TCLK to FB_IN, same VDD
does not include jitter
,
–
100
tsk(O)
Output-to-Output Skew
Bank-to-Bank Skew
Skew within Bank
–
–
–
–
150
150
ps
ps
tsk(B)
Banks at same voltage,
same frequency
Banks at same voltage,
different frequency
–
–
225
Banks at different voltage
–
–
–
–
–
–
–
–
–
–
–
250
10
10
–
tPLZ, HZ
tPZL, ZH
BW
Output Disable Time
Output Enable Time
–
ns
ns
–
PLL Closed Loop Bandwidth
(–3dB)
VCO_SEL = 0
0.5 - 1.0
MHz
VCO_SEL = 1
1.0 - 2.0
–
tJIT(CC)
Cycle-to-Cycle Jitter
Same frequency
Multiple frequencies
–
–
–
–
–
150
300
100
150
1
ps
tJIT(PER)
tJIT(φ)
Period Jitter
ps
ps
IO Phase Jitter
IO at same VDD
tLOCK
Maximum PLL Lock Time
ms
Document #: 38-07480 Rev. *A
Page 8 of 11
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CY29775
Figure 2. AC Test Reference for VDD = 3.3V / 2.5V
Zo = 50 ohm
Zo = 50 ohm
Pulse
Generator
Z = 50 ohm
RT = 50 ohm
RT = 50 ohm
VTT
VTT
Figure 3. Propagation Delay t(φ), Static Phase Offset
VDD
LVCMOS_CLK
VDD/2
GND
VDD
FB_IN
VDD/2
t(φ)
GND
Figure 4. Output Duty Cycle (DC)
VDD
VDD/2
tP
GND
T0
DC = tP / T0 x 100%
Figure 5. Output-to-Output Skew, tsk(O)
VDD
VDD/2
GND
VDD
VDD/2
GND
tSK(O)
Document #: 38-07480 Rev. *A
Page 9 of 11
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CY29775
Ordering Information
Part Number
Package Type
Product Flow
Status
Obsolete
CY29775AI
CY29775AIT
Pb-free
52-pin TQFP
Industrial, –40°C to +85°C
Industrial, –40°C to 85°C
52-pin TQFP -Tape and Reel
Obsolete
CY29775AXI
CY29775AXIT
52-pin TQFP
Industrial, –40°C to +85°C
Industrial, –40°C to 85°C
Active
Active
52-pin TQFP -Tape and Reel
Package Drawing and Dimension
Figure 6. 52-Lead Thin Plastic Quad Flat Pack (10 x 10 x 1.0 mm) A52B
51-85158-**
Document #: 38-07480 Rev. *A
Page 10 of 11
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CY29775
Document History Page
Document Title:CY29775 2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer
Document #: 38-07480
Orig. of
Change
Rev.
ECN No. Issue Date
Description of Change
**
125955
04/29/03
See ECN
RGL
New Data Sheet
*A
1875214
WWZ/AESA Added Pb-free part numbers and updated device status
© Cypress Semiconductor Corporation, 2003-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07480 Rev. *A
Revised December 19, 2007
Page 11 of 11
Spread Aware is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
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