CY29940AC-1T [CYPRESS]
2.5V or 3.3V, 200-MHz 1:18 Clock Distribution Buffer; 2.5V或3.3V ， 200MHz的1:18时钟分配缓冲器
| 型号： | CY29940AC-1T |
| 厂家： | 
CYPRESS |
| 描述： | 2.5V or 3.3V, 200-MHz 1:18 Clock Distribution Buffer |
| 文件： | 总7页 (文件大小：196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY29940-1
2.5V or 3.3V, 200-MHz
1:18 Clock Distribution Buffer
Description
Features
• 200-MHz clock support
The CY29940-1 is a low-voltage 200-MHz clock distribution
buffer with the capability to select either a differential LVPECL-
or a LVCMOS/LVTTL-compatible input clock. The two clock
sources can be used to provide for a test clock as well as the
primary system clock. All other control inputs are
LVCMOS/LVTTL-compatible. The eighteen outputs are 2.5V
or 3.3V LVCMOS/LVTTL-compatible and can drive 50Ω series
or parallel terminated transmission lines. For series terminated
transmission lines, each output can drive one or two traces
giving the device an effective fanout of 1:36. Low
output-to-output skews make the CY29940-1 an ideal clock
distribution buffer for nested clock trees in the most
demanding of synchronous systems.
• LVPECL or LVCMOS/LVTTL clock input
• LVCMOS/LVTTL-compatible inputs
• 18 clock outputs: drive up to 36 clock lines
• 150 ps max. output-to-output skew
• 23Ω output impedance
• Dual or single supply operation:
— 3.3V core and 3.3V outputs
— 3.3V core and 2.5V outputs
— 2.5V core and 2.5V outputs
• Pin-compatible with MPC940L, MPC9109
• Available in commercial and industrial temperature
ranges
• 32-pin TQFP package
Block Diagram
Pin Configuration
VDD
VDDC
29
32 31
28
25
27 26
30
VSS
VSS
1
Q6
24
PECL_CLK
PECL_CLK#
0
1
Q7
2
3
23
22
18
TCLK
Q8
Q0-Q17
TCLK_SEL
PECL_CLK
4
5
6
7
8
VDD
Q9
TCLK
21
20
19
18
17
CY29940-1
TCLK_SEL
PECL_CLK#
VDD
Q10
Q11
VSS
VDDC
12
9
10
13
16
14 15
11
Cypress Semiconductor Corporation
Document #: 38-07487 Rev. **
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised January 28, 2003
CY29940-1
Pin Description[1]
Pin
Name
PWR
I/O
Description
5
6
3
PECL_CLK
PECL_CLK#
TCLK
I, PU PECL Input Clock
I, PD PECL Input Clock
I, PD External Reference/Test Clock Input
Clock Outputs
9, 10, 11, 13, Q(17:0)
14, 15, 18, 19,
20, 22, 23, 24,
26, 27, 28, 30,
31, 32
VDDC
O
4
TCLK_SEL
I, PD Clock Select Input. When LOW, PECL clock is selected and when HIGH
TCLK is selected.
8, 16, 29
7, 21
VDDC
VDD
3.3V or 2.5V Power Supply for Output Clock Buffers
3.3V or 2.5V Power Supply
1, 2, 12, 17, 25 VSS
Common Ground
Note:
1. PD = Internal Pull-down; PU = Internal Pull-up.
Document #: 38-07487 Rev. **
Page 2 of 7
CY29940-1
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, Vin and Vout should be constrained to the
range:
Absolute Maximum Conditions
Maximum Input Voltage Relative to VSS: ............ VSS – 0.3V
Maximum Input Voltage Relative to VDD:.............VDD + 0.3V
Storage Temperature: ................................–65°C to + 150°C
Operating Temperature:................................–40°C to +85°C
Maximum ESD Protection...............................................2 kV
Maximum Power Supply: ................................................5.5V
Maximum Input Current: ............................................±20 mA
VSS < (Vin or Vout) < VDD
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
DC Electrical Specifications: VDD = 3.3V ±5% or 2.5V ±5%, VDDC = 3.3V ±5% or 2.5V ±5%
Parameter
VIL
Description
Input Low Voltage
Conditions
Min.
VSS
2.0
Typ.
Max.
0.8
Unit
V
VIH
IIL
Input High Voltage
Input Low Current[2]
Input High Current[2]
VDD
–200
200
V
µA
µA
mV
IIH
VPP
Peak-to-Peak Input Voltage
PECL_CLK
500
1000
VCMR
Common Mode Range[3]
PECL_CLK
VDD = 3.3V
VDD – 1.4
VDD – 1.0
VDD – 0.6
VDD – 0.6
0.5
V
V
V
VDD = 2.5V
VOL
Output Low Voltage[4,5,6]
IOL = 20 mA, VDDC = 3.3V
IOL = 16 mA, VDDC = 2.5V
IOH = –20 mA, VDDC = 3.3V
IOH = –16 mA, VDDC = 2.5V
VOH
Output High Voltage[4,5,6]
2.4
1.8
IDDQ
IDD
Quiescent Supply Current
Dynamic Supply Current
5
7
mA
mA
VDD = 3.3V, Outputs @
150 MHz, CL=10 pF
285
V
DD = 3.3V, Outputs @
335
200
240
200 MHz, CL=10 pF
VDD = 2.5V, Outputs @
150 MHz, CL=10 pF
VDD = 2.5V, Outputs @
200 MHz, CL=10 pF
Zout
Cin
Output Impedance
Input Capacitance
18
23
4
28
Ω
pF
Notes:
2. Inputs have pull-up/pull-down resistors that effect input current.
3. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR
range and the input lies within the VPP specification. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines.
4. Outputs driving 50Ω transmission lines.
5. See Figure 1 and Figure 2.
6. 50% input duty cycle.
Document #: 38-07487 Rev. **
Page 3 of 7
CY29940-1
AC Electrical Specifications (VDD = 3.3V ±5% or 2.5V ±5%, VDDC = 3.3V ±5% or 2.5V ±5%)[7]
Parameter
Fmax
Description
Input Frequency
Conditions
LVCMOS Input
LVPECL Input
Min.
Typ.
Max.
200
180
4.0
5.2
3.4
4.0
55
Unit
MHz
TPD
PECL_CLK to Q Delay[4,5,10]
</ =150 MHz
V
DD = 3.3V
DD = 2.5V
2.0
2.6
1.8
2.3
45
ns
V
LVCMOS to Q Delay[4,5,10]
</ =150 MHz
VDD = 3.3V
DD = 2.5V
V
FoutDC
Tskew
Output Duty Cycle[4,5,6]
FCLK < 134 MHz
FCLK > 134 MHz
%
40
60
Output-to-Output Skew[4,5]
Part-to-Part Skew[8]
150
1.4
2.2
1.2
1.7
850
750
ps
ns
Tskew(pp)
PECL, VDDC = 3.3V
PECL, VDDC = 2.5V
TCLK, VDDC = 3.3V
TCLK, VDDC = 2.5V
PECL_CLK
Tskew(pp)
Part-to-Part Skew[8]
ns
ps
ns
Tskew(pp)
tR/tF
Part to Part Skew[9]
TCLK
Output Clocks Rise/Fall Time[4,5]
0.7V to 2.0V,
VDDC = 3.3V
0.3
0.3
1.1
1.3
0.5V to 1.8V,
VDDC = 2.5V
CY29940-1 DUT
Zo = 50 ohm
Zo = 50 ohm
Pulse
Generator
Z = 50 ohm
RT = 50 ohm
RT = 50 ohm
VTT
VTT
Figure 1. LVCMOS_CLK CY29940-1 Test Reference for VCC = 3.3V and VCC = 2.5V
CY29940-1 DUT
Zo = 50 ohm
Differential
Pulse
Zo = 50 ohm
Generator
Z = 50 ohm
Zo = 50 ohm
RT = 50 ohm
VTT
RT = 50 ohm
VTT
Figure 2. PECL_CLK CY29940-1 Test Reference for VCC = 3.3V and VCC = 2.5V
Notes:
7. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
8. Across temperature and voltage ranges, includes output skew.
9. For a specific temperature and voltage, includes output skew.
10. Parameters tested @ 150 MHz.
Document #: 38-07487 Rev. **
Page 4 of 7
CY29940-1
VCC
PECL_CLK
PECL_CLK
VCMR
VCC /2
GND
VPP
tP
VCC
T0
DC = tP / T0 x 100%
Q
VCC /2
GND
tPD
Figure 5. Output Duty Cycle (FoutDC)
Figure 3. Propagation Delay (TPD) Test Reference
VCC
VCC
LVCMOS_CLK
VCC /2
GND
VCC /2
GND
VCC
VCC
Q
VCC /2
GND
VCC /2
tPD
tSK(0)
GND
Figure 4. LVCMOS Propagation Delay (TPD) Test
Reference
Figure 6. Output-to-Output Skew tsk(0)
Ordering Information
Part Number
CY29940AC–1
Package Type
32-pin TQFP
Production Flow
Commercial, 0°C to 70°C
CY29940AC–1T
CY29940AI–1
CY29940AI–1T
32-pin TQFP – Tape and Reel
32-pin TQFP
Commercial, 0°C to 70°C
Industrial, –40°C to +85°C
Industrial, –40°C to +85°C
32-pin TQFP – Tape and Reel
Document #: 38-07487 Rev. **
Page 5 of 7
CY29940-1
Package Drawing and Dimensions
32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.4 mm A32.14
51-85088-*B
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07487 Rev. **
Page 6 of 7
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY29940-1
Document History Page
Document Title: CY29940-1 2.5V or 3.3V, 200-MHz 1:18 Clock Distribution Buffer
Document Number: 38-07487
Issue
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
**
119820
01/29/03
BRK
New Data Sheet
Document #: 38-07487 Rev. **
Page 7 of 7
相关型号：
©2020 ICPDF网 联系我们和版权申明