CY29940AC [CYPRESS]
2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer; 2.5V或3.3V ， 200MHz的， 1:18时钟分配缓冲器
| 型号： | CY29940AC |
| 厂家： | 
CYPRESS |
| 描述： | 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer |
| 文件： | 总7页 (文件大小：192K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
40
CY29940
2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
Features
Description
• 200-MHz clock support
• LVPECL or LVCMOS/LVTTL clock input
• LVCMOS/LVTTL compatible inputs
• 18 clock outputs: drive up to 36 clock lines
• 150 ps max. output-to-output skew
• Dual or single supply operation:
— 3.3V core and 3.3V outputs
The CY29940 is a low-voltage 200-MHz clock distribution buff-
er with the capability to select either a differential LVPECL or
a LVCMOS/LVTTL compatible input clock. The two clock
sources can be used to provide for a test clock as well as the
primary system clock. All other control inputs are LVC-
MOS/LVTTL compatible. The eighteen outputs are 2.5V or
3.3V LVCMOS/LVTTL compatible and can drive 50Ω series or
parallel terminated transmission lines. For series terminated
transmission lines, each output can drive one or two traces
giving the device an effective fanout of 1:36. Low out-
put-to-output skews make the CY29940 an ideal clock distri-
bution buffer for nested clock trees in the most demanding of
synchronous systems.
— 3.3V core and 2.5V outputs
— 2.5V core and 2.5V outputs
• Pin compatible with MPC940L, MPC9109
• Available in Commercial and Industrial temperature
• 32-pin LQFP package
Block Diagram
Pin Configuration
VDD
VDDC
PECL_CLK
PECL_CLK#
VSS
VSS
TCLK
1
2
3
4
5
6
7
8
24
23
22
Q6
Q7
Q8
VDD
0
1
18
Q0-Q17
TCLK
CY29940 210 Q9
TCLK_SEL
PECL_CLK
PECL_CLK#
VDD
TCLK_SEL
19
18
17
Q10
Q11
VSS
VDDC
Cypress Semiconductor Corporation
Document #: 38-07283 Rev. *B
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Revised December 21, 2002
CY29940
Pin Description[1]
Pin
Name
PWR
I/O
Description
5
6
3
PECL_CLK
PECL_CLK#
TCLK
I, PU PECL Input Clock
I, PD PECL Input Clock
I, PD External Reference/Test Clock Input
Clock Outputs
9, 10, 11, 13, Q(17:0)
14,15,18,19,
20,22,23,24,
26,27,28,30,
31, 32
VDDC
O
4
TCLK_SEL
I, PD Clock Select Input. When LOW, PECL clock is selected and when
HIGH TCLK is selected.
8, 16, 29
7, 21
VDDC
VDD
VSS
3.3V or 2.5V Power Supply for Output Clock Buffers
3.3V or 2.5V Power Supply
1, 2, 12, 17,
25
Common Ground
Note:
1. PD = Internal Pull-Down, PU = Internal Pull-up.
Document #: 38-07283 Rev. *B
Page 2 of 7
CY29940
Maximum Ratings[2]
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any volt-
age higher than the maximum rated voltages to this circuit. For
proper operation, Vin and Vout should be constrained to the
range:
Maximum Input Voltage Relative to VSS: ............. VSS – 0.3V
Maximum Input Voltage Relative to VDD:............. VDD + 0.3V
Storage Temperature: ................................–65°C to + 150°C
Operating Temperature:................................–40°C to +85°C
Maximum ESD Protection...............................................2 kV
Maximum Power Supply: ................................................5.5V
Maximum Input Current: ............................................±20 mA
VSS < (Vin or Vout) < VDD
Unused inputs must always be tied to an appropriate logic volt-
age level (either VSS or VDD).
DC Parameters: VDD = 3.3V ±5% or 2.5V ±5%, VDDC = 3.3V ±5% or 2.5V ±5%, TA = –40°C to +85°C
Parameter
VIL
Description
Input Low Voltage
Conditions
Min.
VSS
2.0
Typ.
Max.
0.8
Unit.
V
VIH
IIL
Input High Voltage
Input Low Current[3]
Input High Current[3]
VDD
–200
200
V
µA
µA
mV
IIH
VPP
Peak-to-Peak Input
Voltage
500
1000
PECL_CLK
VCMR
Common Mode Range[4]
PECL_CLK
V
DD = 3.3V
VDD – 1.4
VDD – 1.0
VDD – 0.6
VDD – 0.6
0.5
V
V
VDD = 2.5V
VOL
VOH
Output Low Voltage[5, 6, 7]
Output High Voltage[5, 6, 7]
IOL = 20 mA
V
IOH = –20 mA, VDDC = 3.3V
IOH = –20 mA, VDDC = 2.5V
2.4
1.8
V
V
IDDQ
IDD
Quiescent Supply
Current
5
7
mA
Dynamic Supply
Current
VDD = 3.3V, Outputs @
150 MHz, CL=15 pF
285
335
200
240
mA
VDD = 3.3V, Outputs @
200 MHz, CL=15 pF
VDD = 2.5V, Outputs @
150 MHz, CL=15 pF
VDD = 2.5V, Outputs @
200 MHz, CL=15 pF
Zout
Output Impedance
Input Capacitance
VDD = 3.3V
8
12
15
4
16
20
Ω
VDD = 2.5V
10
Cin
pF
Notes:
2. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Inputs have pull-up/pull-down resistors that effect input current.
4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR
range and the input lies within the VPP specification. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines
5. Outputs driving 50Ω transmission lines.
6. See Figure 1 &2.
7. 50% input duty cycle.
Document #: 38-07283 Rev. *B
Page 3 of 7
CY29940
AC Parameters[8]: VDD = 3.3V ±5% or 2.5V ±5%, VDDC = 3.3V ±5% or 2.5V ±5%, TA = –40°C to +85°C
Parameter
Fmax
tPD
Description
Input Frequency
PECL_CLK to Q Delay[5, 6, 11]
</ =150 MHz
Conditions
Min.
Typ.
Max.
Units
MHz
ns
200
3.2
3.4
3.1
3.2
5.2
5
V
85°C
DD = 3.3V
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
2.0
2.1
1.9
2.0
2.5
2.6
2.5
2.6
1.9
2.0
1.8
1.8
2.5
2.5
2.3
2.3
VDD = 3.3V
70°C
V
85°C
DD = 2.5V
VDD = 2.5V
5
70°C
5
tPD
LVCMOS to Q Delay[5, 6, 11]
</ =150 MHz
V
85°C
DD = 3.3V
3
ns
3.2
2.9
3.1
4
V
70°C
DD = 3.3V
VDD = 2.5V
85°C
4
VDD = 2.5V
3.8
3.8
10
70°C
tJ
Total Jitter
Output Duty Cycle[5, 6, 7]
VDD = 3.3V @ 150MHz
FCLK < 134 MHz
FCLK > 134 MHz
VDD = 3.3V
ps
%
FoutDC
45
40
55
60
Tskew
Output-to-Output Skew[5, 6]
Part-to-Part Skew[9]
150
200
1.4
2.2
1.2
1.7
850
750
ps
ns
ns
ps
ns
VDD = 2.5V
Tskew(pp)
Tskew(pp)
Tskew(pp)
tR/tF
PECL, VDDC = 3.3V
PECL, VDDC = 2.5V
TCLK, VDDC = 3.3V
TCLK, VDDC = 2.5V
PECL_CLK
Part-to-Part Skew[9]
Part to Part Skew[10]
TCLK
Output Clocks Rise/Fall
Time[5, 6]
0.7V to 2.0V,
VDDC = 3.3V
0.3
0.3
1.1
1.2
0.5V to 1.8V,
VDDC = 2.5V
Notes:
8. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
9. Across temperature and voltage ranges, includes output skew.
10. For a specific temperature and voltage, includes output skew
11. Parameters tested @ 150 MHz.
Document #: 38-07283 Rev. *B
Page 4 of 7
CY29940
CY29940 DUT
Zo = 50 ohm
Zo = 50 ohm
Pulse
Generator
Z = 50 ohm
RT = 50 ohm
RT = 50 ohm
VTT
VTT
Figure 1. LVCMOS_CLK CY29940 Test Reference for VCC = 3.3V and VCC = 2.5V
CY29940 DUT
Zo = 50 ohm
Differential
Pulse
Zo = 50 ohm
Generator
Zo = 50 ohm
Z = 50 ohm
RT = 50 ohm
VTT
RT = 50 ohm
VTT
Figure 2. PECL_CLK CY29940 Test Reference for VCC = 3.3V and VCC = 2.5V
VCC
PECL_CLK
PECL_CLK
VCC /2
GND
VCMR
VPP
tP
VCC
T0
Q
VCC /2
DC = tP / T0 x 100%
tPD
GND
Figure 5. Output Duty Cycle (FoutDC)
Figure 3. Propagation Delay (TPD) Test Reference
VCC
VCC
LVCMOS_CLK
VCC /2
GND
VCC /2
GND
VCC
VCC
VCC /2
GND
Q
VCC /2
tPD
tSK(0)
GND
Figure 4. LVCMOS Propagation Delay (TPD) Test
Reference
Figure 6. Output-to-Output Skew tsk(0)
Document #: 38-07283 Rev. *B
Page 5 of 7
CY29940
Ordering Information
Part Number
CY29940AI
Package Type
32 Pin LQFP
Production Flow
Industrial, –40°C to +85°C
Industrial, –40°C to +85°C
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
CY29940AIT
CY29940AC
CY29940ACT
32 Pin LQFP – Tape and Reel
32 Pin LQFP
32 Pin LQFP – Tape and Reel
Package Drawing and Dimensions
32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.4 mm A32.14
51-85088-*B
Document #: 38-07283 Rev. *B
Page 6 of 7
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY29940
Document Title: CY29940 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
Document Number: 38-07283
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
111094
Description of Change
02/01/02
08/15/02
BRK
New data sheet
*A
116776
HWT
Incorporate results offinalcharacterization using corporate methods, added
output impedance on page 3 and added output duty cycle on page 4.
Add commercial temperature range in the ordering information on page 6.
*B
122875
12/21/02
RBI
Add power up requirements to maximum rating information
Document #: 38-07283 Rev. *B
Page 7 of 7
相关型号：
©2020 ICPDF网 联系我们和版权申明