CY223811FXI [CYPRESS]
Three-PLL General Purpose FLASH Programmable Clock Generator; 三锁相环通用闪存可编程时钟发生器
| 型号： | CY223811FXI |
| 厂家： | 
CYPRESS |
| 描述： | Three-PLL General Purpose FLASH Programmable Clock Generator |
| 文件： | 总9页 (文件大小：346K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY22381
Three-PLL General Purpose FLASH
Programmable Clock Generator
■ Improves frequency accuracy over temperature, age, process,
and initial offset
Features
■ Three integrated phase-locked loops
■ Non-volatile programming enables easy customization,
ultra-fast turnaround, performance tweaking, design timing
margin testing, inventory control, lower part count, and more
secureproductsupply. Canalsobeprogrammedmultipletimes
which reduces programming errors and provides an easy
upgrade path for existing designs
■ Ultra-wide divide counters (eight-bit Q, eleven-bit P, and
seven-bit post divide)
■ Improved linear crystal load capacitors
■ Flash programmability
■ In-house programming of samples and prototype quantities is
available using the CY3672 FTG development Kit. Production
quantities are available through Cypress’s value-added
distribution partners or by using third party programmers from
BP Microsystems, HiLo Systems, and others.
■ Field programmability
■ Low-jitter, high-accuracy outputs
■ Power-management options (Shutdown, OE, Suspend)
■ Configurable crystal drive strength
■ Frequency select option through external LVTTL Input
■ 3.3V operation
■ Performance suitable for high-end multimedia,
communications, industrial, A/D converters, and consumer
applications
■ Supports numerous low-power application schemes and
reduces EMI by allowing unused outputs to be turned off
■ Eight-pin SOIC package
■ CyClocks RT™ support
■ Adjust crystal drive strength for compatibility with virtually all
crystals
Benefits
■ External frequency select option for PLL1, CLKA, and CLKB
■ Generates up to three unique frequencies on three outputs up
to 200 MHz from an external source. Functional upgrade for
current CY2081 family.
■ Industry standard supply voltage
■ Industry standard packaging saves on board space
■ Easy-to-use software support for design entry
■ Allows for 0 ppm frequency generation and frequency
conversion under the most demanding applications
Logic Block Diagram
XTALIN
OSC.
XTALOUT
PLL1
Divider
7-BIT
CLKC
11-BIT P
8-BIT Q
CONFIGURATION
FLASH
4 × 3
Crosspoint
Switch
PLL2
Divider
7-BIT
11-BIT P
8-BIT Q
CLKB
CLKA
SHUTDOWN/OE
FS/SUSPEND
PLL3
Divider
7-BIT
11-BIT P
8-BIT Q
Cypress Semiconductor Corporation
Document #: 38-07012 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 10, 2008
[+] Feedback
CY22381
Pinouts
Figure 1. CY22381- 8-pin SOIC
CLKC
GND
XTALIN
XTALOUT
FS/SUSPEND/OE/SHUTDOWN
1
2
3
4
8
7
6
5
VDD
CLKA
CLKB
Pin Definitions
Name
CLKC
GND
Pin Number
Description
1
2
3
4
5
6
7
8
Configurable clock output C
Ground
XTALIN
XTALOUT
CLKB
Reference crystal input or external reference clock input
Reference crystal feedback (float if XTALIN is driven by external reference clock)
Configurable clock output B
Configurable clock output A
Power supply
CLKA
VDD
FS/SUSPEND/
OE/SHUTDOWN
General Purpose Input. Can be Frequency Control, Suspend mode control, Output
Enable, or full-chip shutdown.
CLKA. Any divider change as a result of switching the FS input
is guaranteed to be glitch free.
Operation
The CY22381 is an upgrade to the existing CY2081. The new
device has a wider frequency range, greater flexibility, improved
performance, and incorporates many features that reduce PLL
sensitivity to external system issues.
The general-purpose input can simultaneously control the
Suspend feature, turning off a set of PLLs and outputs
determined during programming.
When programmed as an Output Enable (OE) the input forces
all outputs to be placed in a three-state condition when LOW.
The device has three PLLs that allow each output to operate at
an independent frequencies. These three PLLs are completely
programmable.
When programmed as a Shutdown, the input forces a full chip
shutdown mode when LOW.
Configurable PLLs
Crystal Input
PLL1 generates a frequency that is equal to the reference
divided by an eight-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL1 is sent
to the crosspoint switch. The frequency of PLL1 can optionally
be changed by using the external CMOS general purpose input.
See the following section on “General-Purpose Input” for more
detail.
The input crystal oscillator is an important feature of this device
because of its flexibility and performance features.
The oscillator inverter has programmable drive strength. This
allows for maximum compatibility with crystals from various
manufacturers, processes, performances, and qualities.
The input load capacitors are placed on-die to reduce external
component cost. These capacitors are true parallel-plate
capacitors for ultra-linear performance. These were chosen to
reduce the frequency shift that occurs when non-linear load
capacitance interacts with load, bias, supply, and temperature
changes. Non-linear (FET gate) crystal load capacitors must not
be used for MPEG, POTS dial tone, communications, or other
applications that are sensitive to absolute frequency
requirements
PLL2 generates a frequency that is equal to the reference
divided by an eight-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL2 is sent
to the crosspoint switch.
PLL3 generates a frequency that is equal to the reference
divided by an eight-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL3 is sent
to the cross-point switch.
The value of the load capacitors is determined by six bits in a
programmable register. The load capacitance can be set with a
resolution of 0.375pF for a total crystal load range of 6pF to 30pF.
General-Purpose Input
The CY22381 features an output control pin (pin 8) that can be
programmed to control one of four features.
For driven clock inputs the input load capacitors may be
completely bypassed. This enables the clock chip to accept
driven frequency inputs up to 166 MHz. If the application requires
a driven input, then XTALOUT must be left floating.
When programmed as a Frequency Select (FS), the input can
select between two arbitrarily programmed frequency settings.
The Frequency Select can change the following; the frequency
of PLL1, the output divider of CLKB, and the output divider of
Document #: 38-07012 Rev. *E
Page 2 of 9
[+] Feedback
CY22381
5 μA (typical). After leaving shutdown mode, the PLLs will have
Output Configuration
to relock.
Under normal operation there are four internal frequency
sources that may be routed through a programmable crosspoint
switch to any of the three outputs through programmable
seven-bit output dividers. The four sources are: reference, PLL1,
PLL2, and PLL3. The following is a description of each output.
When configured as SUSPEND, the general-purpose input can
be configured to shut down a customizable set of outputs and/or
PLLs, when LOW. All PLLs and any of the outputs can be shut
off in nearly any combination. The only limitation is that if a PLL
is shut off, all outputs derived from it must also be shut off.
Suspending a PLL shuts off all associated logic, while
suspending an output forces a three-state condition.
CLKA’s output originates from the crosspoint switch and goes
through a programmable seven-bit post divider. The seven-bit
post divider derives its value from one of two programmable
registers controlled by FS.
Improving Jitter
CLKB’s output originates from the crosspoint switch and goes
through a programmable seven-bit post divider. The seven-bit
post divider derives its value from one of two programmable
registers controlled by FS.
Jitter Optimization Control is useful in mitigating problems
related to similar clocks switching at the same moment and
causing excess jitter. If one PLL is driving more than one output,
the negative phase of the PLL can be selected for one of the
outputs. This prevents the output edges from aligning, allowing
superior jitter performance.
CLKC’s output originates from the crosspoint switch and goes
through a programmable seven-bit post divider. The seven-bit
post divider derives its value from one programmable register.
CyClocks RT Software
The Clock outputs have been designed to drive a single point
load with a total lumped load capacitance of 15pF. While driving
multiple loads is possible with the proper termination, it is
generally not recommended.
CyClocks RT is our second-generation application that allows
users to configure this device. The easy-to-use interface offers
complete control of the many features of this family including
input frequency, PLL and output frequencies, and different
functional options. Data sheet frequency range limitations are
checked and performance tuning is automatically applied. You
can download a free copy of CyClocks RT on Cypress’s web site
at http://www.cypress.com.
Power-Saving Features
When configured as OE, the general-purpose input three-states
all outputs when pulled LOW. When configured as Shutdown, a
LOW on this pin three-states all outputs and shuts off the PLLs,
counters, the reference oscillator, and all other active
components. The resulting current on the VDD pins is less than
Document #: 38-07012 Rev. *E
Page 3 of 9
[+] Feedback
CY22381
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Data Retention at Tj = 125°C ................................> 10 years
Maximum Programming Cycles........................................100
Package Power Dissipation...................................... 250 mW
Static Discharge Voltage
Supply Voltage................................................–0.5V to +7.0V
DC Input Voltage ..............................–0.5V to + (VDD + 0.5V)
Storage Temperature.................................. –65°C to +125°C
Junction Temperature.................................................. 125°C
(per MIL-STD-883, Method 3015) ........................... ≥ 2000V
Latch up (per JEDEC 17) .................................... ≥ ±200 mA
Operating Conditions
Parameter
Description
Min
3.135
0
Typ
3.3
–
Max
3.465
+70
+85
15
Unit
V
VDD
TA
Supply Voltage
Commercial Operating Temperature, Ambient
Industrial Operating Temperature, Ambient
°C
–40
–
–
°C
CLOAD_OUT Max. Load Capacitance
–
pF
fREF
External Reference Crystal
8
–
30
MHz
MHz
MHz
ms
External Reference Clock[2], Commercial
External Reference Clock[2], Industrial
1
–
166
150
500
1
–
tPU
Power up time for all VDD's to reach minimum specified voltage (power
ramps must be monotonic)
0.05
–
Electrical Characteristics
Parameter
Description
Conditions[1]
VOH = VDD – 0.5, VDD = 3.3 V
VOL = 0.5V, VDD = 3.3 V
Capload at minimum setting
Capload at maximum setting
Except crystal pins
Min
12
12
–
Typ
24
24
6
Max
–
Unit
mA
mA
pF
Output High Current[3]
Output Low Current[3]
Crystal Load Capacitance[3]
Crystal Load Capacitance[3]
Input Pin Capacitance[3]
HIGH-level Input Voltage
LOW-level Input Voltage
Input HIGH Current
IOH
IOL
–
CXTAL_MIN
–
CXTAL_MAX
–
30
7
–
pF
CIN
VIH
VIL
IIH
–
–
pF
CMOS levels,% of VDD
CMOS levels,% of VDD
VIN = VDD – 0.3 V
70%
–
–
–
VDD
VDD
μA
–
30%
10
10
10
–
–
<1
<1
–
IIL
Input LOW Current
VIN = +0.3 V
–
μA
IOZ
IDD
Output Leakage Current
Three-state outputs
–
μA
Total Power Supply Current 3.3 V Power Supply; 3 outputs at 50 MHz
3.3 V Power Supply; 3 outputs at 166 MHz
–
35
70
5
mA
mA
μA
–
–
IDDS
Total Power Supply Current in Shutdown active
Shutdown Mode
–
20
Notes
1. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions.
2. External input reference clock must have a duty cycle between 40% and 60%, measured at V /2.
DD
3. Guaranteed by design, not 100% tested.
Document #: 38-07012 Rev. *E
Page 4 of 9
[+] Feedback
CY22381
Switching Characteristics
Parameter
Name
Output Frequency[3, 4]
Description
Clock output limit, Commercial
Clock output limit, Industrial
Min
–
Typ.
–
Max
200
166
55%
Unit
MHz
MHz
1/t1
–
–
Output Duty Cycle[3, 5]
t2
Duty cycle for outputs, defined as t2 ÷ t1,
Fout < 100 MHz, divider >= 2, measured
at VDD/2
45%
50%
Duty cycle for outputs, defined as t2 ÷ t1,
Fout > 100 MHz or divider = 1, measured
at VDD/2
40%
50%
60%
Rising Edge Slew Rate[3]
Falling Edge Slew Rate[3]
Output Three-state Timing[3]
t3
t4
t5
Output clock rise time, 20% to 80% of VDD 0.75
Output clock fall time, 20% to 80% of VDD 0.75
1.4
1.4
150
–
–
V/ns
V/ns
ns
Time for output to enter or leave
three-state mode after SHUTDOWN/OE
switches
–
300
Clock Jitter[3, 6]
Lock Time[3]
t6
t7
Peak-to-peak period jitter, CLK outputs
measured at VDD/2
–
–
200
1.0
–
3
ps
PLL Lock Time from Power up
ms
Switching Waveforms
Figure 2. All Outputs, Duty Cycle and Rise and Fall Time
t
1
t
2
OUTPUT
t
3
t
4
Figure 3. Output Three-State Timing
OE
t
5
t
5
ALL
THREE-STATE
OUTPUTS
Figure 4. CLK Output Jitter
t
6
CLK
OUTPUT
Notes
4. Guaranteed to meet 20% – 80% output thresholds and duty cycle specifications.
5. Reference Output duty cycle depends on XTALIN duty cycle.
6. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate.
Document #: 38-07012 Rev. *E
Page 5 of 9
[+] Feedback
CY22381
Switching Waveforms (continued)
Figure 5. Frequency Change
OLD SELECT
NEW SELECT STABLE
SELECT
t
7
F
new
F
old
OUTPUT
Test Circuit
V
DD
0.1 mF
OUTPUTS
CLKout
C
LOAD
GND
Document #: 38-07012 Rev. *E
Page 6 of 9
[+] Feedback
CY22381
Ordering Information
Ordering Code
Package Type
Operating Range
Commercial (TA=0°C to 70°C)
Commercial (TA=0°C to 70°C)
Operating Voltage
CY22381FC[8]
CY22381FCT[8]
CY3672-USB
8-SOIC
3.3V
3.3V
8-SOIC – Tape and Reel
FTG Programmer
CY22381F Adapter for CY3672-USB
CY3699
Pb-Free
8-SOIC with NiPdAu lead frame
8-SOIC
Industrial (TA=–40°C to 85°C)
Commercial (TA=0°C to 70°C)
Commercial (TA=0°C to 70°C)
Commercial (TA=0°C to 70°C)
Industrial (TA=–40°C to 85°C)
Industrial (TA=–40°C to 85°C)
Commercial (TA=0°C to 70°C)
Commercial (TA=0°C to 70°C)
Industrial (TA=–40°C to 85°C)
Industrial (TA=–40°C to 85°C)
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
CY223811FXI
CY22381FSZC[9]
CY22381FXC[9]
CY22381FXCT
CY22381FXI
8-SOIC
8-SOIC – Tape and Reel
8-SOIC
8-SOIC – Tape and Reel
8-SOIC
CY22381FXIT
CY22381SXC-xxx[7]
CY22381SXC-xxxT[7]
CY22381SXI-xxx[7]
CY22381SXI-xxxT[7]
8-SOIC – Tape and Reel
8-SOIC
8-SOIC – Tape and Reel
Notes
7. The CY22381SXC-xxx and CY22381SXI-xxx are factory programmed configurations. Factory programming is available for high-volume design opportunities of
100Ku/year or more in production. For more details, contact your local Cypress FAE or Cypress Sales Representative.
8. Not recommended for new designs.
9. The CY22381FSZC and CY22381FXC are identical. For new designs, use CY22381FXC.
Document #: 38-07012 Rev. *E
Page 7 of 9
[+] Feedback
CY22381
Package Drawing and Dimensions
8 Lead (150 Mil) SOIC - S08
Figure 6. 8-Pin (150-Mil) SOIC S8
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
0.150[3.810]
0.157[3.987]
3. REFERENCE JEDEC MS-012
4. PACKAGE WEIGHT 0.07gms
0.230[5.842]
0.244[6.197]
PART #
S08.15 STANDARD PKG.
SZ08.15 LEAD FREE PKG.
5
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
X 45°
SEATING PLANE
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.0075[0.190]
0.0098[0.249]
0.004[0.102]
0.0098[0.249]
0°~8°
0.016[0.406]
0.035[0.889]
0.0138[0.350]
0.0192[0.487]
51-85066-*C
Document #: 38-07012 Rev. *E
Page 8 of 9
[+] Feedback
CY22381
Document History Page
Document Title: CY22381 Three-PLL General Purpose Flash Programmable Clock Generator
Document Number: 38-07012
Orig. of Submission
REV.
ECN
Description of Change
Change
Date
**
106737
108514
TLG
07/03/01 New data sheet
*A
JWK
08/23/01 Updated based on characterization results
Removed “Preliminary” heading
Removed soldering temperature rating
Split crystal load into two typical specs representing digital settings range
Changed t5 max to 300 ns
Changed t6 typical to 200 ps
Changed t7 typical to 1.0 ms
*B
*C
*D
*E
110053
121863
279431
2584052
CKN
RBI
12/10/01 Changed from preliminary to final
12/14/02 Added power up requirements to Operating Conditions information
See ECN Added lead-free devices
RGL
AESA
10/10/08 Updated template. Added Note 8 and 9. Added part number CY22381FC,
CY22381FCT, CY3672-USB, CY3699, CY22381FSZC in ordering
information table.
Removed part number CY22381FI, CY22381FIT, CY22381SC-xxx,
CY22381SC-xxxT, CY22381SI-xxx, and CY22381SI-xxxT in Ordering
Information table.
Added CY223811FXI (NiPdAu lead frame).
Changed Lead-Free to Pb-Free.
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC
PSoC Solutions
General
psoc.cypress.com
clocks.cypress.com
wireless.cypress.com
memory.cypress.com
image.cypress.com
psoc.cypress.com/solutions
psoc.cypress.com/low-power
psoc.cypress.com/precision-analog
psoc.cypress.com/lcd-drive
psoc.cypress.com/can
Clocks & Buffers
Wireless
Low Power/Low Voltage
Precision Analog
LCD Drive
Memories
Image Sensors
CAN 2.0b
USB
psoc.cypress.com/usb
© Cypress Semiconductor Corporation, 2001-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07012 Rev. *E
Revised October 10, 2008
Page 9 of 9
CYClocks RT is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
[+] Feedback
相关型号：
©2020 ICPDF网 联系我们和版权申明