CY22381FXI [CYPRESS]

Three-PLL General Purpose FLASH Programmable Clock Generator; 三锁相环通用闪存可编程时钟发生器
CY22381FXI
型号: CY22381FXI
厂家: CYPRESS    CYPRESS
描述:

Three-PLL General Purpose FLASH Programmable Clock Generator
三锁相环通用闪存可编程时钟发生器

时钟发生器 闪存
文件: 总8页 (文件大小:145K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
CY22381  
Three-PLL General Purpose FLASH  
Programmable Clock Generator  
• Non-volatile programming enables easy customi-  
zation, ultra-fast turnaround, performance tweaking,  
design timing margin testing, inventory control, lower  
part count, and more secure product supply. Can also  
Features  
• Three integrated phase-locked loops  
• Ultra-widedividecounters(eight-bitQ,eleven-bitP,and  
be programmed multiple times which reduces  
programming errors and provides an easy upgrade  
path for existing designs  
seven-bit post divide)  
• Improved linear crystal load capacitors  
• Flash programmability  
• In-house programming of samples and prototype  
quantities is available using the CY3672 FTG devel-  
opmentKit.Productionquantitiesareavailablethrough  
Cypress’s value-added distribution partners or by  
using third party programmers from BP Microsystems,  
HiLo Systems, and others.  
• Performance suitable for high-endmultimedia, commu-  
nications, industrial, A/D converters, and consumer  
applications  
• Field programmability  
• Low-jitter, high-accuracy outputs  
• Power-management options (Shutdown, OE, Suspend)  
• Configurable crystal drive strength  
• Frequency select option via external LVTTL Input  
• 3.3V operation  
• Eight-pin SOIC package  
• CyClocks RT™ support  
• Supports numerous low-power application schemes  
and reduces EMI by allowing unused outputs to be  
turned off  
• Adjust crystal drive strength for compatibility with  
Benefits  
virtually all crystals  
• External frequency select option for PLL1, CLKA, and  
CLKB  
• Industry standard supply voltage  
• Industry standard packaging saves on board space  
• Easy-to-use software support for design entry  
• Generates up to three unique frequencies on three  
outputs up to 200 MHz from an external source.  
Functional upgrade for current CY2081 family.  
• Allows for 0 ppm frequency generation and frequency  
conversion under the most demanding applications  
• Improves frequency accuracy over temperature, age,  
process, and initial offset  
Logic Block Diagram  
XTALIN  
OSC.  
XTALOUT  
PLL1  
Divider  
CLKC  
7-BIT  
11-BIT P  
CONFIGURATION  
FLASH  
8-BIT Q  
4 × 3  
PLL2  
11-BIT P  
8-BIT Q  
Crosspoint  
Switch  
Divider  
7-BIT  
CLKB  
CLKA  
SHUTDOWN/OE  
FS/SUSPEND  
PLL3  
11-BIT P  
8-BIT Q  
Divider  
7-BIT  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-07012 Rev. *D  
Revised October 13, 2004  
CY22381  
Pin Configuration  
CY22381  
8-pin SOIC  
CLKC  
GND  
FS/SUSPEND/OE/SHUTDOWN  
1
2
3
4
8
7
6
5
VDD  
XTALIN  
XTALOUT  
CLKA  
CLKB  
Selector Guide  
Part Number Outputs  
Input Frequency Range  
Output Frequency Range  
Specifics  
CY22381FC  
3
8 MHz – 30 MHz (external crystal) Up to 200 MHz  
Commercial Temperature  
1 MHz – 166 MHz (reference clock)  
CY22381FI  
3
8 MHz – 30 MHz (external crystal) Up to 166 MHz  
1 MHz – 150 MHz (reference clock)  
Industrial Temperature  
Pin Summary  
Name  
CLKC  
GND  
XTALIN  
XTALOUT  
CLKB  
Pin Number  
Description  
Configurable clock output C  
Ground  
Reference crystal input or external reference clock input  
Reference crystal feedback (float if XTALIN is driven by external reference clock)  
Configurable clock output B  
Configurable clock output A  
Power supply  
1
2
3
4
5
6
7
8
CLKA  
VDD  
FS/SUSPEND/  
General Purpose Input. Can be Frequency Control, Suspend mode control, Output  
OE/SHUTDOWN  
Enable, or full-chip shutdown.  
General-Purpose Input  
Operation  
The CY22381 features an output control pin (pin 8) that can  
The CY22381 is an upgrade to the existing CY2081. The new  
device has a wider frequency range, greater flexibility,  
improved performance, and incorporates many features that  
reduce PLL sensitivity to external system issues.  
The device has three PLLs that allow each output to operate  
at an independent frequencies. These three PLLs are  
completely programmable.  
be programmed to control one of four features.  
When programmed as a Frequency Select (FS), the input can  
select between two arbitrarily programmed frequency settings.  
The Frequency Select can change the following; the frequency  
of PLL1, the output divider of CLKB, and the output divider of  
CLKA. Any divider change as a result of switching the FS input  
is guaranteed to be glitch free.  
Configurable PLLs  
The general-purpose input can simultaneously control the  
Suspend feature, turning off a set of PLLs and outputs deter-  
mined during programming.  
PLL1 generates a frequency that is equal to the reference  
divided by an eight-bit divider (Q) and multiplied by an 11-bit  
divider in the PLL feedback loop (P). The output of PLL1 is sent  
to the crosspoint switch. The frequency of PLL1 can optionally  
be changed by using the external CMOS general purpose  
input. See the following section on “General-Purpose Input” for  
more detail.  
PLL2 generates a frequency that is equal to the reference  
divided by an eight-bit divider (Q) and multiplied by an 11-bit  
divider in the PLL feedback loop (P). The output of PLL2 is sent  
to the crosspoint switch.  
When programmed as an Output Enable (OE) the input forces  
all outputs to be placed in a three-state condition when LOW.  
When programmed as a Shutdown, the input forces a full chip  
shutdown mode when LOW.  
Crystal Input  
The input crystal oscillator is an important feature of this device  
because of its flexibility and performance features.  
The oscillator inverter has programmable drive strength. This  
allows for maximum compatibility with crystals from various  
manufacturers, processes, performances, and qualities.  
The input load capacitors are placed on-die to reduce external  
component cost. These capacitors are true parallel-plate  
capacitors for ultra-linear performance. These were chosen to  
reduce the frequency shift that occurs when non-linear load  
PLL3 generates a frequency that is equal to the reference  
divided by an eight-bit divider (Q) and multiplied by an 11-bit  
divider in the PLL feedback loop (P). The output of PLL3 is sent  
to the cross-point switch.  
Document #: 38-07012 Rev. *D  
Page 2 of 8  
CY22381  
capacitance interacts with load, bias, supply, and temperature  
changes. Non-linear (FET gate) crystal load capacitors should  
not be used for MPEG, POTS dial tone, communications, or  
other applications that are sensitive to absolute frequency  
requirements.  
The value of the load capacitors is determined by six bits in a  
programmable register. The load capacitance can be set with  
a resolution of 0.375 pF for a total crystal load range of 6 pF  
to 30 pF.  
For driven clock inputs the input load capacitors may be  
completely bypassed. This enables the clock chip to accept  
driven frequency inputs up to 166 MHz. If the application  
requires a driven input, then XTALOUT must be left floating.  
Power-Saving Features  
When configured as OE, the general-purpose input  
three-states all outputs when pulled LOW. When configured as  
Shutdown, a LOW on this pin three-states all outputs and  
shuts off the PLLs, counters, the reference oscillator, and all  
other active components. The resulting current on the VDD  
pins will be less than 5 µA (typical). After leaving shutdown  
mode, the PLLs will have to relock.  
When configured as SUSPEND, the general-purpose input  
can be configured to shut down a customizable set of outputs  
and/or PLLs, when LOW. All PLLs and any of the outputs can  
be shut off in nearly any combination. The only limitation is that  
if a PLL is shut off, all outputs derived from it must also be shut  
off. Suspending a PLL shuts off all associated logic, while  
suspending an output forces a three-state condition.  
Output Configuration  
Under normal operation there are four internal frequency  
sources that may be routed via a programmable crosspoint  
switch to any of the three outputs via programmable seven-bit  
output dividers. The four sources are: reference, PLL1, PLL2,  
and PLL3. The following is a description of each output.  
CLKA’s output originates from the crosspoint switch and goes  
through a programmable seven-bit post divider. The seven-bit  
post divider derives its value from one of two programmable  
registers controlled by FS.  
CLKB’s output originates from the crosspoint switch and goes  
through a programmable seven-bit post divider. The seven-bit  
post divider derives its value from one of two programmable  
registers controlled by FS.  
CLKC’s output originates from the crosspoint switch and goes  
through a programmable seven-bit post divider. The seven-bit  
post divider derives its value from one programmable register.  
Improving Jitter  
Jitter Optimization Control is useful in mitigating problems  
related to similar clocks switching at the same moment and  
causing excess jitter. If one PLL is driving more than one  
output, the negative phase of the PLL can be selected for one  
of the outputs. This prevents the output edges from aligning,  
allowing superior jitter performance.  
CyClocks RT Software  
CyClocks RT is our second-generation application that allows  
users to configure this device. The easy-to-use interface offers  
complete control of the many features of this family including  
input frequency, PLL and output frequencies, and different  
functional options. Data sheet frequency range limitations are  
checked and performance tuning is automatically applied. You  
can download a free copy of CyClocks RT on Cypress’s web  
site at http://www.cypress.com.  
The Clock outputs have been designed to drive a single point  
load with a total lumped load capacitance of 15 pF. While  
driving multiple loads is possible with the proper termination,  
it is generally not recommended.  
Document #: 38-07012 Rev. *D  
Page 3 of 8  
CY22381  
Junction Temperature.................................................. 125°C  
Data Retention @ Tj = 125°C................................> 10 years  
Maximum Programming Cycles........................................100  
Package Power Dissipation...................................... 250 mW  
Static Discharge Voltage  
Maximum Ratings  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Supply Voltage............................................... –0.5V to +7.0V  
DC Input Voltage.............................. –0.5V to + (VDD + 0.5V)  
Storage Temperature ..................................65°C to +125°C  
(per MIL-STD-883, Method 3015) ........................... 2000V  
Latch up (per JEDEC 17) .................................... ±200 mA  
Operating Conditions[1]  
Parameter  
VDD  
Description  
Min.  
3.135  
0
–40  
8
1
1
0.05  
Typ.  
3.3  
Max.  
3.465  
+70  
+85  
15  
Unit  
V
°C  
°C  
pF  
MHz  
MHz  
MHz  
ms  
Supply Voltage  
TA  
Commercial Operating Temperature, Ambient  
Industrial Operating Temperature, Ambient  
Max. Load Capacitance  
CLOAD_OUT  
fREF  
External Reference Crystal  
30  
External Reference Clock[2], Commercial  
External Reference Clock[2], Industrial  
166  
150  
500  
tPU  
Power-up time for all VDD's to reach minimum specified voltage  
(power ramps must be monotonic)  
Electrical Characteristics  
Parameter  
IOH  
IOL  
CXTAL_MIN  
Description  
Output High Current[3]  
Output Low Current[3]  
Conditions  
VOH = VDD – 0.5, VDD = 3.3 V  
VOL = 0.5V, VDD = 3.3 V  
Min.  
Typ.  
Max.  
Unit  
mA  
mA  
pF  
pF  
pF  
VDD  
VDD  
µA  
µA  
µA  
12  
12  
70%  
24  
24  
6
30  
7
Crystal Load Capacitance[3] Capload at minimum setting  
CXTAL_MAX Crystal Load Capacitance[3] Capload at maximum setting  
CIN  
VIH  
VIL  
IIH  
IIL  
IOZ  
IDD  
Input Pin Capacitance[3]  
HIGH-level Input Voltage  
LOW-level Input Voltage  
Input HIGH Current  
Input LOW Current  
Output Leakage Current  
Except crystal pins  
CMOS levels,% of VDD  
CMOS levels,% of VDD  
VIN = VDD – 0.3 V  
VIN = +0.3 V  
30%  
10  
10  
10  
<1  
<1  
35  
70  
5
Three-state outputs  
Total Power Supply Current 3.3 V Power Supply; 3 outputs @ 50 MHz  
3.3 V Power Supply; 3 outputs @ 166 MHz  
mA  
mA  
µA  
20  
IDDS  
Total Power Supply Current in Shut-down active  
Shutdown Mode  
Notes:  
1. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions.  
2. External input reference clock must have a duty cycle between 40% and 60%, measured at V /2.  
DD  
3. Guaranteed by design, not 100% tested.  
Document #: 38-07012 Rev. *D  
Page 4 of 8  
CY22381  
Switching Characteristics  
Parameter  
1/t1  
Name  
Description  
Clock output limit, Commercial  
Clock output limit, Industrial  
Duty cycle for outputs, defined as t2 ÷ t1,  
Fout < 100 MHz, divider >= 2, measured  
at VDD/2  
Min.  
Typ.  
Max.  
200  
166  
Unit  
MHz  
MHz  
Output Frequency[3, 4]  
t2  
Output Duty Cycle[3, 5]  
45%  
50%  
55%  
Duty cycle for outputs, defined as t2 ÷ t1,  
Fout > 100 MHzordivider = 1,measured  
at VDD/2  
Output clock rise time, 20% to 80% of VDD 0.75  
Output clock fall time, 20% to 80% of VDD 0.75  
Time for output to enter or leave  
three-state mode after SHUTDOWN/OE  
switches  
40%  
50%  
60%  
t3  
t4  
t5  
Rising Edge Slew Rate[3]  
Falling Edge Slew Rate[3]  
Output Three-state Timing[3]  
1.4  
1.4  
150  
300  
V/ns  
V/ns  
ns  
t6  
t7  
Clock Jitter[3, 6]  
Lock Time[3]  
Peak-to-peak period jitter, CLK outputs  
200  
1.0  
3
ps  
measured at VDD/2  
PLL Lock Time from Power-up  
ms  
Switching Waveforms  
All Outputs, Duty Cycle and Rise/Fall Time  
t
1
t
2
OUTPUT  
t
3
t
4
Output Three-State Timing  
OE  
t
5
t
5
ALL  
THREE-STATE  
OUTPUTS  
CLK Output Jitter  
t
6
CLK  
OUTPUT  
Notes:  
4. Guaranteed to meet 20% – 80% output thresholds and duty cycle specifications.  
5. Reference Output duty cycle depends on XTALIN duty cycle.  
6. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate.  
Document #: 38-07012 Rev. *D  
Page 5 of 8  
CY22381  
Switching Waveforms (continued)  
Frequency Change  
OLD SELECT  
NEW SELECT STABLE  
SELECT  
t
7
F
new  
F
old  
OUTPUT  
Test Circuit  
VDD  
0.1 mF  
OUTPUTS  
CLKout  
CLOAD  
GND  
Ordering Information  
Ordering Code  
Package Type  
Operating Range  
Operating Voltage  
CY22381FC  
CY22381FCT  
CY22381FI  
CY22381FIT  
8-SOIC  
8-SOIC – Tape and Reel  
8-SOIC  
8-SOIC – Tape and Reel  
8-SOIC  
8-SOIC – Tape and Reel  
8-SOIC  
Commercial (TA=0°C to 70°C)  
Commercial (TA=0°C to 70°C)  
Industrial (TA=–40°C to 85°C)  
Industrial (TA=–40°C to 85°C)  
Commercial (TA=0°C to 70°C)  
Commercial (TA=0°C to 70°C)  
Industrial (TA=–40°C to 85°C)  
Industrial (TA=–40°C to 85°C)  
3.3V  
3.3V  
3.3V  
3.3V  
3.3V  
3.3V  
3.3V  
3.3V  
CY22381SC-xxx[7]  
CY22381SC-xxxT[7]  
CY22381SI-xxx[7]  
CY22381SI-xxxT[7]  
CY3672  
8-SOIC – Tape and Reel  
Lead-Free  
CY22381FXC  
CY22381FXCT  
CY22381FXI  
8-SOIC  
8-SOIC – Tape and Reel  
8-SOIC  
8-SOIC – Tape and Reel  
8-SOIC  
8-SOIC – Tape and Reel  
8-SOIC  
Commercial (TA=0°C to 70°C)  
Commercial (TA=0°C to 70°C)  
Industrial (TA=–40°C to 85°C)  
Industrial (TA=–40°C to 85°C)  
Commercial (TA=0°C to 70°C)  
Commercial (TA=0°C to 70°C)  
Industrial (TA=–40°C to 85°C)  
Industrial (TA=–40°C to 85°C)  
3.3V  
3.3V  
3.3V  
3.3V  
3.3V  
3.3V  
3.3V  
3.3V  
CY22381FXIT  
CY22381SXC-xxx[7]  
CY22381SXC-xxxT[7]  
CY22381SXI-xxx[7]  
CY22381SXI-xxxT[7]  
8-SOIC – Tape and Reel  
Notes:  
7. The CY22381SC-xxx and CY22381SI-xxx are factory programmed configurations. Factory programming is available for high-volume design opportunities of  
100Ku/year or more in production. For more details, contact your local Cypress FAE or Cypress Sales Representative.  
Document #: 38-07012 Rev. *D  
Page 6 of 8  
CY22381  
Package Drawing and Dimensions  
8 Lead (150 Mil) SOIC - S08  
8-lead (150-Mil) SOIC S8  
PIN 1 ID  
4
1
1. DIMENSIONS IN INCHES[MM] MIN.  
MAX.  
2. PIN 1 ID IS OPTIONAL,  
ROUND ON SINGLE LEADFRAME  
RECTANGULAR ON MATRIX LEADFRAME  
0.150[3.810]  
0.157[3.987]  
3. REFERENCE JEDEC MS-012  
4. PACKAGE WEIGHT 0.07gms  
0.230[5.842]  
0.244[6.197]  
PART #  
S08.15 STANDARD PKG.  
SZ08.15 LEAD FREE PKG.  
5
8
0.189[4.800]  
0.196[4.978]  
0.010[0.254]  
0.016[0.406]  
X 45°  
SEATING PLANE  
0.061[1.549]  
0.068[1.727]  
0.004[0.102]  
0.050[1.270]  
BSC  
0.0075[0.190]  
0.0098[0.249]  
0.004[0.102]  
0.0098[0.249]  
0°~8°  
0.016[0.406]  
0.035[0.889]  
0.0138[0.350]  
0.0192[0.487]  
51-85066-*C  
CYClocks RT is a trademark of Cypress Semiconductor Corporation. All product and company names are the trademarks of their  
respective holders.  
Document #: 38-07012 Rev. *D  
Page 7 of 8  
CY22381  
Document History Page  
Document Title: CY22381 Three-PLL General Purpose Flash Programmable Clock Generator  
Document Number: 38-07012  
Orig. of  
REV.  
**  
ECN NO. Issue Date Change  
Description of Change  
106737  
07/03/01  
TLG  
New data sheet  
*A  
108514  
08/23/01  
JWK  
Updated based on characterization results  
Removed “Preliminary” heading  
Removed soldering temperature rating  
Split crystal load into two typical specs representing digital settings range  
Changed t5 max to 300 ns  
Changed t6 typical to 200 ps  
Changed t7 typical to 1.0 ms  
*B  
*C  
*D  
110053  
121863  
279431  
12/10/01  
12/14/02  
See ECN  
CKN  
RBI  
RGL  
Changed from preliminary to final  
Added power-up requirements to Operating Conditions information  
Added lead-free devices  
Document #: 38-07012 Rev. *D  
Page 8 of 8  

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