CY22381FSZCT [CYPRESS]
Clock Generator, 200MHz, CMOS, PDSO8, 0.150 INCH, LEAD FREE, SOIC-8;
| 型号： | CY22381FSZCT |
| 厂家： | 
CYPRESS |
| 描述： | Clock Generator, 200MHz, CMOS, PDSO8, 0.150 INCH, LEAD FREE, SOIC-8 时钟发生器 闪存 |
| 文件： | 总11页 (文件大小：332K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY22381
CY223811
Three-PLL General Purpose FLASH
Programmable Clock Generator
■ 8-pin SOIC package (CY22381)
Features
■ 8-pin SOIC package with NiPdAu lead finish (CY223811)
■ CyClocks RT™ support
■ Three integrated phase-locked loops
■ Ultra-wide divide counters (eight-bit Q, eleven-bit P, and
seven-bit post divide)
Functional Description
■ Improved linear crystal load capacitors
■ Flash programmability
■ The CY22381 is the next-generation programmable Flash
programmableclockforuseinnetworking, telecommunication,
datacom, and other general-purpose applications. The
CY22381 offers up to three configurable outputs in a 8-pin
SOIC, running off a 3.3V power supply. The on-chip reference
oscillator is designed to run off an 8–30-MHz crystal, or a
1–166-MHz external clock signal. The CY22381 has a three
PLLs driving 3 programmable output clocks. The output clocks
are derived from the PLL or the reference frequency (REF).
Output post dividers are available for either. The CY223811 is
the CY22381 with NiPdAu lead finish.
■ Field programmability
■ Low-jitter, high-accuracy outputs
■ Power-management options (Shutdown, OE, Suspend)
■ Configurable crystal drive strength
■ Frequency select option through external LVTTL Input
■ 3.3V operation
Logic Block Diagram
XTALIN
OSC.
XTALOUT
PLL1
Divider
CLKC
7-BIT
11-BIT P
8-BIT Q
CONFIGURATION
FLASH
4 × 3
Crosspoint
Switch
PLL2
Divider
7-BIT
11-BIT P
8-BIT Q
CLKB
CLKA
SHUTDOWN/OE
FS/SUSPEND
PLL3
Divider
7-BIT
11-BIT P
8-BIT Q
Cypress Semiconductor Corporation
Document #: 38-07012 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 17, 2011
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CY22381
CY223811
Contents
Features .............................................................................1
Functional Description .....................................................1
Logic Block Diagram ........................................................1
Pinouts ..............................................................................3
Pin Definitions ..................................................................3
Operation ...........................................................................3
Configurable PLLs .......................................................3
General-Purpose Input ................................................3
Crystal Input ................................................................3
Crystal Drive Level and Power ....................................4
Output Configuration ...................................................4
Power-Saving Features ...............................................4
Improving Jitter ............................................................4
CyClocks RT Software .....................................................4
Maximum Ratings .............................................................5
Operating Conditions .......................................................5
Recommended Crystal Specifications ...........................5
Electrical Characteristics .................................................5
Switching Characteristics ................................................6
Switching Waveforms ......................................................6
Possible Configurations ...............................................8
Ordering Information ........................................................8
Package Drawing and Dimensions ................................9
Acronyms ..........................................................................9
Document Conventions ...................................................9
Units of Measure .........................................................9
Document History Page .................................................10
Sales, Solutions, and Legal Information ......................11
Worldwide Sales and Design Support .......................11
Products ....................................................................11
PSoC Solutions .........................................................11
Document #: 38-07012 Rev. *H
Page 2 of 11
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CY22381
CY223811
Pinouts
Figure 1. CY22381, CY223811- 8-pin SOIC
CLKC
GND
XTALIN
XTALOUT
FS/SUSPEND/OE/SHUTDOWN
1
2
3
4
8
7
6
5
VDD
CLKA
CLKB
Pin Definitions
Name
CLKC
GND
Pin Number
Description
1
2
3
4
5
6
7
8
Configurable clock output C
Ground
XTALIN
XTALOUT
CLKB
Reference crystal input or external reference clock input
Reference crystal feedback (float if XTALIN is driven by external reference clock)
Configurable clock output B
Configurable clock output A
Power supply
CLKA
VDD
FS/SUSPEND/
OE/SHUTDOWN
General Purpose Input. Can be Frequency Control, Suspend mode control, Output
Enable, or full-chip shutdown.
of PLL1, the output divider of CLKB, and the output divider of
CLKA. Any divider change as a result of switching the FS input
Operation
is guaranteed to be glitch free.
The CY22381 is an upgrade to the existing CY2081. The new
device has a wider frequency range, greater flexibility, improved
performance, and incorporates many features that reduce PLL
sensitivity to external system issues.
The general-purpose input can simultaneously control the
Suspend feature, turning off a set of PLLs and outputs
determined during programming.
The device has three PLLs that allow each output to operate at
an independent frequencies. These three PLLs are completely
programmable.
When programmed as an Output Enable (OE) the input forces
all outputs to be placed in a three-state condition when LOW.
When programmed as a Shutdown, the input forces a full chip
shutdown mode when LOW.
The CY223811 is the CY22381 with NiPdAu lead finish.
Configurable PLLs
Crystal Input
PLL1 generates a frequency that is equal to the reference
divided by an eight-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL1 is sent
to the crosspoint switch. The frequency of PLL1 can optionally
be changed by using the external CMOS general purpose input.
See the following section on “General-Purpose Input” for more
detail.
The input crystal oscillator is an important feature of this device
because of its flexibility and performance features.
The oscillator inverter has programmable drive strength. This
allows for maximum compatibility with crystals from various
manufacturers, processes, performances, and qualities.
The input load capacitors are placed on-die to reduce external
component cost. These capacitors are true parallel-plate
capacitors for ultra-linear performance. These were chosen to
reduce the frequency shift that occurs when non-linear load
capacitance interacts with load, bias, supply, and temperature
changes. Non-linear (FET gate) crystal load capacitors must not
be used for MPEG, communications, or other applications that
are sensitive to absolute frequency requirements
PLL2 generates a frequency that is equal to the reference
divided by an eight-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL2 is sent
to the crosspoint switch.
PLL3 generates a frequency that is equal to the reference
divided by an eight-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL3 is sent
to the cross-point switch.
The value of the load capacitors is determined by six bits in a
programmable register. The load capacitance can be set with a
resolution of 0.375pF for a total crystal load range of 6pF to 30pF.
General-Purpose Input
For driven clock inputs the input load capacitors may be
completely bypassed. This enables the clock chip to accept
driven frequency inputs up to 166 MHz. If the application requires
a driven input, then XTALOUT must be left floating.
The CY22381 features an output control pin (pin 8) that can be
programmed to control one of four features.
When programmed as a Frequency Select (FS), the input can
select between two arbitrarily programmed frequency settings.
The Frequency Select can change the following; the frequency
Document #: 38-07012 Rev. *H
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CY22381
CY223811
multiple loads is possible with the proper termination, it is
generally not recommended.
Crystal Drive Level and Power
Crystals are specified to accept a maximum drive level.
Generally, larger crystals can accept more power. The drive level
specification in the table below is a general upper bound for the
power driven by the oscillator circuit in the CY22381.
Power-Saving Features
When configured as OE, the general-purpose input three-states
all outputs when pulled LOW. When configured as Shutdown, a
LOW on this pin three-states all outputs and shuts off the PLLs,
counters, the reference oscillator, and all other active
components. The resulting current on the VDD pins is less than
5 μA (typical). After leaving shutdown mode, the PLLs has to
relock.
For a given voltage swing, power dissipation in the crystal is
proportional to ESR and proportional to the square of the crystal
frequency. (Note that actual ESR is sometimes much less than
the value specified by the crystal manufacturer.) Power is also
almost proportional to the square of CL.
Power can be reduced to less than the DL specification in the
table below by selecting a reduced frequency crystal with low CL
and low R1 (ESR).
When configured as SUSPEND, the general-purpose input can
be configured to shut down a customizable set of outputs and/or
PLLs, when LOW. All PLLs and any of the outputs can be shut
off in nearly any combination. The only limitation is that if a PLL
is shut off, all outputs derived from it must also be shut off.
Suspending a PLL shuts off all associated logic, while
suspending an output forces a three-state condition.
Output Configuration
Under normal operation there are four internal frequency
sources that may be routed through a programmable crosspoint
switch to any of the three outputs through programmable
seven-bit output dividers. The four sources are: reference, PLL1,
PLL2, and PLL3. The following is a description of each output.
Improving Jitter
Jitter Optimization Control is useful in mitigating problems
related to similar clocks switching at the same moment and
causing excess jitter. If one PLL is driving more than one output,
the negative phase of the PLL can be selected for one of the
outputs. This prevents the output edges from aligning, allowing
superior jitter performance.
CLKA’s output originates from the crosspoint switch and goes
through a programmable seven-bit post divider. The seven-bit
post divider derives its value from one of two programmable
registers controlled by FS.
CLKB’s output originates from the crosspoint switch and goes
through a programmable seven-bit post divider. The seven-bit
post divider derives its value from one of two programmable
registers controlled by FS.
CyClocks RT Software
CyClocks RT is our second-generation application that allows
users to configure this device. The easy-to-use interface offers
complete control of the many features of this family including
input frequency, PLL and output frequencies, and different
functional options. Data sheet frequency range limitations are
checked and performance tuning is automatically applied. You
can download a free copy of CyClocks RT on Cypress’s web site
at http://www.cypress.com.
CLKC’s output originates from the crosspoint switch and goes
through a programmable seven-bit post divider. The seven-bit
post divider derives its value from one programmable register.
The Clock outputs have been designed to drive a single point
load with a total lumped load capacitance of 15pF. While driving
Document #: 38-07012 Rev. *H
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CY22381
CY223811
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Data Retention at Tj = 125°C ................................> 10 years
Maximum Programming Cycles........................................100
Package Power Dissipation...................................... 250 mW
Static Discharge Voltage
Supply Voltage................................................–0.5V to +7.0V
DC Input Voltage ..............................–0.5V to + (VDD + 0.5V)
Storage Temperature.................................. –65°C to +125°C
Junction Temperature.................................................. 125°C
(per MIL-STD-883, Method 3015) ........................... ≥ 2000V
Latch up (per JEDEC 17) .................................... ≥ ±200 mA
Operating Conditions
Parameter
Description
Min
3.135
0
Typ
3.3
–
Max
3.465
+70
+85
15
Unit
V
VDD
TA
Supply Voltage
Commercial Operating Temperature, Ambient
Industrial Operating Temperature, Ambient
°C
–40
–
–
°C
CLOAD_OUT Max. Load Capacitance
–
pF
fREF
External Reference Crystal
8
–
30
MHz
MHz
MHz
ms
External Reference Clock[2], Commercial
External Reference Clock[2], Industrial
1
–
166
150
500
1
–
tPU
Power up time for all VDD's to reach minimum specified voltage (power
ramps must be monotonic)
0.05
–
Recommended Crystal Specifications
Parameter
FNOM
Description
Description
Min
8
Typ.
Max
30
Unit
MHz
pF
Nominal crystal frequency
Nominal load capacitance
Parallel resonance, fundamental mode
–
–
–
CLNOM
R1
8
20
Equivalent series resistance Fundamental mode
(ESR)
–
50
Ω
DL
Crystal drive level
No external series resistor assumed
–
0.5
2
mW
Electrical Characteristics
Parameter
Description
Conditions[1]
VOH = VDD – 0.5, VDD = 3.3 V
VOL = 0.5V, VDD = 3.3 V
Capload at minimum setting
Capload at maximum setting
Except crystal pins
Min
12
12
–
Typ
24
24
6
Max
–
Unit
mA
mA
pF
Output High Current[3]
Output Low Current[3]
Crystal Load Capacitance[3]
Crystal Load Capacitance[3]
Input Pin Capacitance[3]
HIGH-level Input Voltage
LOW-level Input Voltage
Input HIGH Current
IOH
IOL
–
CXTAL_MIN
–
CXTAL_MAX
–
30
7
–
pF
CIN
VIH
VIL
IIH
–
–
pF
CMOS levels,% of VDD
CMOS levels,% of VDD
VIN = VDD – 0.3 V
70%
–
–
–
VDD
VDD
μA
–
30%
10
10
10
–
<1
<1
–
IIL
Input LOW Current
VIN = +0.3 V
–
μA
IOZ
Output Leakage Current
Three-state outputs
–
μA
Notes
1. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions.
2. External input reference clock must have a duty cycle between 40% and 60%, measured at V /2.
DD
3. Guaranteed by design, not 100% tested.
Document #: 38-07012 Rev. *H
Page 5 of 11
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CY22381
CY223811
Electrical Characteristics
Parameter
Description
Conditions[1]
Min
–
Typ
35
70
5
Max
–
Unit
mA
mA
μA
IDD
Total Power Supply Current 3.3 V Power Supply; 3 outputs at 50 MHz
3.3 V Power Supply; 3 outputs at 166 MHz
–
–
IDDS
Total Power Supply Current in Shutdown active
Shutdown Mode
–
20
Switching Characteristics
Parameter
Name
Output Frequency[3, 4]
Description
Clock output limit, Commercial
Clock output limit, Industrial
Min
–
Typ.
–
Max
200
166
55%
Unit
MHz
MHz
1/t1
–
–
Output Duty Cycle[3, 5]
t2
Duty cycle for outputs, defined as t2 ÷ t1,
Fout < 100 MHz, divider >= 2, measured
at VDD/2
45%
50%
Duty cycle for outputs, defined as t2 ÷ t1,
Fout > 100 MHz or divider = 1, measured
at VDD/2
40%
50%
60%
Rising Edge Slew Rate[3]
Falling Edge Slew Rate[3]
Output Three-state Timing[3]
t3
t4
t5
Output clock rise time, 20% to 80% of VDD 0.75
Output clock fall time, 20% to 80% of VDD 0.75
1.4
1.4
150
–
–
V/ns
V/ns
ns
Time for output to enter or leave
three-state mode after SHUTDOWN/OE
switches
–
300
Clock Jitter[3, 6]
Lock Time[3]
t6
t7
Peak-to-peak period jitter, CLK outputs
measured at VDD/2
–
–
200
1.0
–
3
ps
PLL Lock Time from Power up
ms
Switching Waveforms
Figure 2. All Outputs, Duty Cycle and Rise and Fall Time
t
1
t
2
OUTPUT
t
3
t
4
Figure 3. Output Three-State Timing
OE
t
5
t
5
ALL
THREE-STATE
OUTPUTS
Notes
4. Guaranteed to meet 20% – 80% output thresholds and duty cycle specifications.
5. Reference Output duty cycle depends on XTALIN duty cycle.
6. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate.
Document #: 38-07012 Rev. *H
Page 6 of 11
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CY22381
CY223811
Switching Waveforms (continued)
Figure 4. CLK Output Jitter
t
6
CLK
OUTPUT
Figure 5. Frequency Change
OLD SELECT
NEW SELECT STABLE
SELECT
t
7
F
new
F
old
OUTPUT
Test Circuit
V
DD
0.1 mF
OUTPUTS
CLKout
C
LOAD
GND
Document #: 38-07012 Rev. *H
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CY22381
CY223811
Ordering Information
Ordering Code
Pb-Free
Package Type
Operating Range
Operating Voltage
8-SOIC with NiPdAu lead frame
8-SOIC
Industrial (TA=–40°C to 85°C)
Commercial (TA=0°C to 70°C)
Commercial (TA=0°C to 70°C)
Industrial (TA=–40°C to 85°C)
Industrial (TA=–40°C to 85°C)
3.3V
3.3V
3.3V
3.3V
3.3V
CY223811FXI
CY22381FXC[9]
CY22381FXCT
CY22381FXI
CY22381FXIT
Programmer
CY3672-USB
CY3699
8-SOIC – Tape and Reel
8-SOIC
8-SOIC – Tape and Reel
Programmer
CY22381F Adapter for CY3672-USB
Some product offerings are factory programmed customer specific devices with customized part numbers. The Possible Configura-
tions table shows the available device types, but not complete part numbers. Contact your local Cypress FAE or Sales Representative
for more information.
Possible Configurations
Ordering Code
CY22381SI-xxxT[7, 8]
Pb-Free
Package Type
Operating Range
Operating Voltage
8-SOIC – Tape and Reel
Industrial (TA=–40°C to 85°C)
3.3V
CY22381SXC-xxx[7]
CY22381SXC-xxxT[7]
CY22381SXI-xxx[7]
CY22381SXI-xxxT[7]
8-SOIC
Commercial (TA=0°C to 70°C)
Commercial (TA=0°C to 70°C)
Industrial (TA=–40°C to 85°C)
Industrial (TA=–40°C to 85°C)
3.3V
3.3V
3.3V
3.3V
8-SOIC – Tape and Reel
8-SOIC
8-SOIC – Tape and Reel
Ordering Code Definitions
(1)
(T)
(F) SX C (-xxx)
CY 22381
T = tape and reel, blank = tube
Configuration specific identifier (factory programmed)
Temperature Range: C = Commercial, I = Industrial
Package:
S = SOIC, leaded
SX = SOIC, Pb-free
X = SOIC, Pb-free
F = field programmable, blank = factory programmed
Lead finish:1 = NiPdAu, blank = unspecified
Part Identifier
Company Code: CY = Cypress Semiconductor
Notes
7. The CY22381SI-xxx, CY22381SXC-xxx and CY22381SXI-xxx are factory programmed configurations. Factory programming is available for high-volume design
opportunities of 100Ku/year or more in production. For more details, contact your local Cypress FAE or Cypress Sales Representative.
8. Not recommended for new designs.
9. The CY22381FSZC and CY22381FXC are identical. For new designs, use CY22381FXC.
Document #: 38-07012 Rev. *H
Page 8 of 11
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CY22381
CY223811
Package Drawing and Dimensions
Figure 6. 8-Pin (150-mil) SOIC
51-85066-*D
Acronyms
Document Conventions
Units of Measure
Symbol
Acronym
CMOS
Description
complementary metal oxide semiconductor
equivalent series resistance
field effect transistor
Unit of Measure
ESR
FET
°C
degree Celcius
µA
mA
ms
mW
MHz
μA
μF
ns
micro Amperes
milli Amperes
milli seconds
milli Watts
MPEG
OE
motion picture experts group
output enable
PLL
phase-locked loop
SOIC
small outline integrated circuit
Mega Hertz
micro Amps
micro Farads
nano seconds
pico Farad
pF
ps
pico seconds
Volts
V
Document #: 38-07012 Rev. *H
Page 9 of 11
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CY22381
CY223811
Document History Page
Document Title: CY22381, CY223811 Three-PLL General Purpose Flash Programmable Clock Generator
Document Number: 38-07012
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
106737
108514
TLG
JWK
07/03/01 New data sheet
*A
08/23/01 Updated based on characterization results. Removed “Preliminary” heading
Removed soldering temperature rating. Split crystal load into two typical specs
representing digital settings range. Changed t5 max to 300 ns
Changed t6 typical to 200 ps. Changed t7 typical to 1.0 ms
*B
*C
*D
*E
110053
121863
279431
2584052
CKN
RBI
12/10/01 Changed from preliminary to final
12/14/02 Added power up requirements to Operating Conditions information
See ECN Added lead-free devices
RGL
AESA
10/10/08 Updated template. Added Note 8 and 9. Added part number CY22381FC,
CY22381FCT, CY3672-USB, CY3699, CY22381FSZC in ordering information
table. Removed part number CY22381FI, CY22381FIT, CY22381SC-xxx,
CY22381SC-xxxT, CY22381SI-xxx, and CY22381SI-xxxT in Ordering
Information table. Added CY223811FXI (NiPdAu lead finish). Changed
Lead-Free to Pb-Free.
*F
*G
*H
2620588 KVM/AESA
12/11/08 Add CY223811 to the document title
Distinguish between CY22381 and CY223811 in page 1 Features section
Add part number CY22381SI-xxxT in Ordering Information table.
2897317
KVM
03/22/10 Removed obsolete parts from Ordering Information table and moved ‘xx’ parts
to Possible Configurations table
Updated package diagram
3065190 KVM/BASH
01/17/11 Add crystal parameter table, ordering code definition, acronym and units tables.
Crystal Drive Level and Power. Remove FTG from CY3672.
Removed Benefits section and replaced with Functional Description section.
Document #: 38-07012 Rev. *H
Page 10 of 11
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CY22381
CY223811
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
PSoC Solutions
Clocks & Buffers
Interface
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2001-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07012 Rev. *H
Revised January 17, 2011
Page 11 of 11
CYClocks RT is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
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