CY22313ZXCT [CYPRESS]
Two-PLL Clock Generator with Direct Rambus-TM (Lite) Support; 双PLL时钟发生器，直接Rambus公司-TM （精简版）支持
| 型号： | CY22313ZXCT |
| 厂家： | 
CYPRESS |
| 描述： | Two-PLL Clock Generator with Direct Rambus-TM (Lite) Support |
| 文件： | 总9页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY22313
Two-PLL Clock Generator with
Direct Rambus™ (Lite) Support
Benefits
Features
• Two integrated phase-locked loops (PLLs)
• Ultra-accurate PLLs
• High-performance PLL tailored for multimedia applica-
tions
• Frequency tolerance within 1 PPM on all frequencies
• Direct Rambus™ clock support
• Two input selects
• One pair of differential output drivers, identical speci-
fication to CY2212
• 3.45V core; 3.45V, 2.5V, 1.8V, and 1.675V outputs
• 24-pin TSSOP package
• Selectable 54.0-/53.946-MHz output and
294.912-/393.216-MHz Rambus® output
• Supports output voltage requirements
• Industry-standard packaging saves on board space
Block Diagram
XIN
XTAL.
OSC.
XOUT
Divide by 2
Divider
LCLK
CONFIGURATION
LOGIC
54MOUT
PLL1
PLL2
FS
S
CLK
CLKB
Pin Configuration
Frequency Select Tables
FS
0
1
54MOUT
54
53.94605395
Unit
MHz
MHz
PPM
0
–1
VDDRP
VSSRP
Xout
1
24
23
22
21
20
19
18
17
16
15
14
13
S
2
VDDR
VSSR
CLK
3
Xin
4
S
0
1
CLK, CLKB
294.912
393.216
Unit
MHz
MHz
PPM
0
0
NC
5
CLKB
VSSR
VDDR
NC
VSSVPA
VDDVPA
VSS54
54MOUT
FS
6
7
LCLK
9.216
Unit
MHz
PPM
0
8
9
VDDL
VSSL
LCLK
VSSVP
10
11
12
VDD54
VDDVP
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-07434 Rev. *E
Revised June 29, 2004
CY22313
Pin Definitions
Name
VDDRP
VSSRP
Xout
Xin
NC
VSSVPA
VDDVPA
VSS54
54MOUT
FS
VDD54
VDDVP
VSSVP
LCLK
VSSL
Pin Numbers
Pin Description
1
2
3
4
5
6
7
8
9
Power for DRCG PLL
Ground for DRCG PLL
Crystal Output
Crystal Input
Do Not Connect, Leave Floating
Analog Ground For Video PLL
Analog Power for Video PLL
Ground for 54MOUT
54-MHz/53.94605395-MHz Output
Frequency Select Pin for 54MOUT (internal pull-down resistor)
Power for 54MOUT
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Power for Video PLL
Ground for Video PLL
LCLK Output
Ground for LCLK
VDDL
NC
Power for LCLK
Do Not Connect, Leave Floating
Power for DRCG CLK/CLKB
Ground for DRCG CLK/CLKB
Output Clock to Rambus (complement)
Output Clock to Rambus
VDDR
VSSR
CLKB
CLK
VSSR
VDDR
S
Ground for DRCG CLK/CLKB
Power for DRCG CLK/CLKB
Frequency Select Pin for DRCG CLK/CLKB (internal pull-up resistor)
Document #: 38-07434 Rev. *E
Page 2 of 9
CY22313
DC Input Voltage ..............................–0.5V to + (VDD + 0.5V)
Storage Temperature.................................. –65°C to +125°C
Absolute Maximum Conditions
(Above which the useful life may be impaired. For user guide-
Static Discharge Voltage
lines; not tested.)
(per MIL-STD-883, Method 3015) ............................... 2000V
Supply Voltage............................................... –0.5V to +4.0V
Latch-up (per JEDEC 17) .................................... > ±200 mA
Recommended Operating Conditions[1]
Parameter
Description
Min.
Typ
Max. Unit
VDDRP, VDDVPA,
Supply Voltage for PLL’s, Crystal Oscillator, and 3.45V Outputs
3.15
3.45
3.6
V
VDDVP, VDDR
VDD54 (2.5V)
Supply Voltage for 2.5V Outputs
Supply Voltage for 1.675V Outputs
Supply Voltage for 1.8V Outputs
2.25
1.6
1.6
2.5
1.675
1.8
2.75
1.75
2.0
V
V
V
VDD54 (1.675V)
VDDL
tPU
Power-up time for all VDDS to reach minimum specified voltage
0.05
500
ms
(power ramps must be monotonic)
TA
Operating Temperature, Ambient
Max. Load Capacitance, CMOS Output
External Reference Crystal
0
+85
15
°C
pF
MHz
CLOAD_54MOUT
fREF
18.432
Electrical Specifications
Parameter
IOH
Description
Conditions
VOH = VDD – 0.5, VDD = 2.5V
VOH = VDD – 0.5, VDD = 1.8V
Min.
Typ. Max. Unit
[2]
Output High Current, 2.5V outputs[3]
Output High Current, 1.8V outputs[3]
8
6
5
8
6
5
16
12
10
16
12
10
11[4]
7
mA
mA
mA
mA
mA
mA
pF
Output High Current, 1.675V outputs[3] VOH = VDD – 0.5, VDD = 1.675V
[2]
IOL
Output Low Current, 2.5V outputs[3]
Output Low Current, 1.8V outputs[3]
VOL = 0.5V, VDD = 2.5V
VOL = 0.5V, VDD = 1.8V
Output Low Current, 1.675V outputs[3] VOL = 0.5V, VDD = 1.675V
CXTAL
Crystal Load Capacitance[3]
Total effective load of internal load caps
Except crystal pins
CLOAD_IN Input Pin Capacitance[3]
pF
VIH
VIL
RI_FS
RI_S
IDD
HIGH-Level Input Voltage
LOW-Level Input Voltage
FS Input Resistor
S Input Resistor
Total Power Supply Current
CMOS levels,% of VDDRP/VDDVPA/VDDVP 70%
CMOS levels,% of VDDRP/VDDVPA/VDDVP
VDD
30% VDD
Pull-down resistor on FS
Pull-up resistor on S
60
10
150
225
100
125
kΩ
kΩ
mA
Sum of all supply currents
Direct Rambus Electrical Specifications[3]
Parameter
VCM
VX
VCOS
VCOH
VCOL
Description
Min.
1.35
1.25
0.4
Typ. Max.
Unit
V
V
V
V
Differential output common-mode voltage
1.75
1.85
0.7
Differential output crossing-point voltage[5]
Output Voltage swing (p-p single-ended)[6]
Output high voltage
2.1
Output low voltage
1.0
12
V
Ω
rOUT
Output dynamic resistance (at pins)[7]
50
Notes:
1. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions.
2. LCLK and 54MOUT outputs only.
3. Guaranteed by design, not 100% tested.
4. Identical Crystal Load Capacitance as CY2212ZC-2. Use the same crystal and X / X
IN
board layout as implemented with the original crystal-driven
OUT
CY2212ZC-2.
5. Differential output crossing point voltages shown in Figure 1.
6.
7.
V
OUT
= V – V
.
COS
OH
OL
r
= ∆ V / ∆ I . This is defined at the output pins, not at the measurement point of Figure 9.
O O
Document #: 38-07434 Rev. *E
Page 3 of 9
CY22313
Switching Characteristics[3]
Parameter
FPPM
Description
Frequency Error
Conditions
Min. Typ. Max. Unit
Part to Part, does not include PCB variation[8]
Over commercial temperature range[9]
Duty cycle for all outputs, measured at VDD/2
±5
±10 PPM
±2
50
±5
55
PPM
%
DC
Output Duty Cycle
45
t3_54, 2.5
54MOUT Rising Edge Slew Rate 20% to 80% of VDD54, VDD54 = 2.5V
0.75
0.35
0.75
0.35
160
1.2
0.5
1.2
0.5
4.0
2.5
4.0
2.5
400
100
V/ns
V/ns
V/ns
V/ns
ps
t3_54, 1.675 54MOUT Rising Edge Slew Rate 20% to 80% of VDD54, VDD54 = 1.675V
t4_54, 2.5 54MOUT Falling Edge Slew Rate 80% to 20% of VDD54, VDD54 = 2.5V
t4_54, 1.675 54MOUT Falling Edge Slew Rate 80% to 20% of VDD54, VDD54 = 1.675V
CR, tCF CLK/CLKB Rise and Fall Times 20% to 80% of output voltage
tCR-CF
t
CLK/CLKB Rise and Fall
Difference[10]
20% to 80% of output voltage
PLL lock time from power-up
ps
t5
Lock Time[11]
1.0
3.0
ms
Phase Noise Specifications
Parameter
Description
Phase Noise
Phase Noise
Conditions
54 MHz at 10-kHz offset
53.946 MHz at 10-kHz offset
Min. Typ. Max. Unit
–95
dBc
–92
dBc
Jitter Specifications[3]
Parameter
t6_LCLK
t6_54, 2.5
Description
Conditions
Cycle-Cycle Jitter – 9.216 MHz
Typ. Max. Unit
LCLK Jitter[12]
250
150
150
250
250
250
400
400
50
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
54MOUT Jitter[12]
Cycle-Cycle Jitter – 54 MHz, VDD = 2.5V
Cycle-Cycle Jitter – 53.946 MHz, VDD = 2.5V
Cycle-Cycle Jitter – 54 MHz, VDD = 1.675V
Cycle-Cycle Jitter – 53.946 MHz, VDD = 1.675V
1000 Cycle Jitter – 9.216 MHz
1000 Cycle Jitter – 54 MHz,
1000 Cycle Jitter – 53.946 MHz,
Cycle-Cycle Jitter, 1–6 Cycles, 400 MHz
Cycle-Cycle Jitter, 1–6 Cycles, 300 MHz
Long-term Jitter, 400 MHz
t6_54, 1.675
t7_LCLK
t7_54
LCLK 1000 Cycle Jitter[13]
54MOUT 1000 Cycle Jitter[13]
t8
t9
CLK/CLKB 1–6 Cycle Jitter[14]
CLK/CLKB Long-term Jitter[15]
70
300
400
50
Long-term Jitter, 300 MHz
t10
CLK/CLKB Duty Cycle Error[16] Cycle-Cycle Duty Cycle Error, 400 MHz
Cycle-Cycle Duty Cycle Error, 300 MHz
70
Notes:
8. Tested across three lots on same board, PCB boards can vary more than ± 5 PPM.
9. Crystal should not be heated for this test, only IC.
10. Measured on same pin of a single device.
11. Lock Time shown in Figure 2.
12. LCLK and 54MOUT Cycle-Cycle Jitter shown in Figure 3.
13. LCLK and 54MOUT 1000 Cycle Jitter shown in Figure 4.
14. CLK/CLKB 1-6 Cycle Jitter specification is absolute value of worst case deviation, and is shown in Figure 5 and Figure 6.
15. CLK/CLKB Long Term Jitter shown in Figure 7.
16. CLK/CLKB Duty Cycle Error shown in Figure 8.
Document #: 38-07434 Rev. *E
Page 4 of 9
CY22313
CLK
Vx
CLKB
Figure 1. Direct Rambus Crossing Point Voltage
80%
VDD
Output
t5
Output stable within PPM spec.
Figure 2. PLL Lock Time
tcycle,i+1
tcycle,i
t6 = tcycle,i - cycle,i+1
t
Figure 3. 54MOUT, LCLK Cycle-to-Cycle Jitter
1000 cycles
1000 cycles
...
...
t1000cycle,i+1
t1000cycle,i
t7 = t1000cycle,i - 1000cycle,i+1
t
Figure 4. 54MOUT, LCLK 1000 Cycle Jitter
Document #: 38-07434 Rev. *E
Page 5 of 9
CY22313
CLK
CLKB
tCYCLE,i
tCYCLE,i+1
t8 = tCYLCE,i – tCYCLE,i+1 over 10000 consecutive cycles
Figure 5. CLK, CLKB Cycle-to-Cycle Jitter
CLK
CLKB
t4CYCLE,i
t4CYCLE,i+1
t = t
- t
4CYCLE,i+1 over 10000 consecutive cycles
8
4CYCLE,i
Figure 6. CLK, CLKB 4-Cycle-to-Cycle Jitter
CLK
CLKB
tCYCLE
t9 = tCYCLE,max – tCYCLE,min over 10000 cycles
Figure 7. CLK, CLKB Long-term Jitter
Cycle i
Cycle i+1
CLK
CLKB
tPW+,i
tPW+,i+1
tCYCLE,i
tCYCLE,i+1
t10 = tPW+,i – tPW+,i+1
Figure 8. CLK, CLKB Duty Cycle Error
Document #: 38-07434 Rev. *E
Page 6 of 9
CY22313
Measurement Point
R = Z
C
F
T
CH
CH
R
S
R
R
Z
P
P
CH
C
MID
22313
C
MID
R
C
R = Z
T
S
F
Z
CH
Measurement Point
Figure 9. Direct Rambus Test Circuit
All VDD
0.1 µF
OUTPUTS
CLK out
CLOAD
GND
Figure 10. LCLK, 54MOUT Output Test Circuits
Table 1. Direct Rambus Test Circuit Component Values
Parameter Description
Series Resistor
Value
68
Tolerance
±5%
Unit
Ω
RS
RP
CF
CMID
Parallel Resistor
39
15
0.01
±5%
±10%
±20%
Ω
Edge-Rate Filter Capacitor[17]
AC Ground Capacitor
pF
µF
Ordering Information
Package
Ordering Code
CY22313ZC
CY22313ZCT
Name
Z24
Package Type
24-lead TSSOP
24-lead TSSOP – Tape and Reel Commercial (TA = 0°C to 85°C)
Operating Range
Commercial (TA = 0°C to 85°C)
Operating Voltages
3.45V
Z24
3.45V
Lead Free
CY22313ZXC
CY22313ZXCT
Z24
Z24
24-lead TSSOP
Commercial (TA = 0°C to 85°C)
3.45
3.45
24-lead TSSOP − Tape and Reel Commercial (TA = 0°C to 85°C)
Notes:
17. CF is OPTIONAL filter capacitor for adjusting edge rates and EMI. No filter capacitors are used for characterization and test data.
Document #: 38-07434 Rev. *E
Page 7 of 9
CY22313
Package Drawing and Dimensions
24-Lead Thin Shrunk Small Outline Package (4.40-mm Body) Z24
PIN 1 ID
1
6.25[0.246]
6.50[0.256]
DIMENSION IN MM(INCHES)
4.30[0.169]
4.50[0.177]
24
0.65[0.025]
BSC.
0.25[0.010]
BSC
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
GAUGE
PLANE
0°-8°
0.076[0.003]
0.50[0.020]
0.70[0.027]
0.05[0.002]
0.15[0.006]
0.85[0.033]
0.95[0.037]
0.09[[0.003]
0.20[0.008]
SEATING
PLANE
7.70[0.303]
7.90[0.311]
51-85119-*A
Rambus is a registered trademark, and Direct Rambus is a trademark, of Rambus Inc. All product and company names mentioned
in this document are the trademarks of their respective holders.
Document #: 38-07434 Rev. *E
Page 8 of 9
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY22313
Document History Page
Document Title: CY22313 Two-PLL Clock Generator with Direct Rambus™ (Lite) Support
Document Number: 38-07434
Issue
Date
07/02/02
Orig. of
Change
CKN
REV.
**
*A
ECN NO.
117092
121365
Description of Change
New Data Sheet
11/15/02
CKN
Reordered Pin Description table
Changed all 3.3V references to 3.45V
Changed RI_FS min. spec to 60 KOhms
Changed note 4
Inserted max. spec for Edge Rates
Reduced min. spec for Edge Rates on 1.8V and 1.675V outputs
Inserted phase noise specifications
Created separate specs for Jitter, depending on output voltage
Correctly specified CF in Table 1
*B
*C
121773
125454
02/17/03
05/19/03
CKN
CKN
Added tPU row to the Recommended Operating Conditions table
Updated Switching Characteristics table
Added CY22313LF ordering information and corresponding note
*D
*E
127393
239051
06/12/03
See ECN
RGL
RGL
Removed “PRELIMINARY”
Rephrased Note 18 to provide clarity on marking
Corrected the Lead Free Coding in the Ordering Information table
Document #: 38-07434 Rev. *E
Page 9 of 9
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