CM1234-08DE [CALMIRCO]
PicoGuard XSTM ESD Clamp Array For High Speed Data Line Protection; 的PicoGuard XSTM ESD钳位阵列高速数据线路保护
| 型号： | CM1234-08DE |
| 厂家： | 
CALIFORNIA MICRO DEVICES CORP |
| 描述： | PicoGuard XSTM ESD Clamp Array For High Speed Data Line Protection |
| 文件： | 总10页 (文件大小：160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Issue X-2
CM1234
PicoGuard XSTM ESD Clamp Array For High Speed Data Line Protection
Features
Product Description
•
•
ESD protection for 4 pairs of differential channels
ESD protection to IEC61000-4-2 Level 4
The PicoGuard XS (Xtreme Speed) protection family is
specifically designed for next generation deep sub-
micron high speed data line protection.
•
•
15kV contact discharge
20kV air discharge
The CM1234 is ideal for protecting systems with high
data and clock rates or for circuits requiring low
capacitive loading and tightly controlled signal skews
(with channel-to-channel matching at 2% max
deviation).
•
Pass-through impedance matched clamp
architecture
Flow-through routing for high-speed signal integrity
Minimal line capacitance change with temperature
and voltage
•
•
•
100Ω matched impedance for each paired
differential channel
Each I/O pin can withstand over 1000 ESD strikes*
RoHS compliant (lead-free) TDFN-16 package
The device is particularly well-suited for protecting
systems using high-speed ports such as DVI or HDMI,
along with corresponding ports in removable storage,
digital camcorders, DVD-RW drives and other
applications where extremely low loading capacitance
with ESD protection are required.
•
•
Applications
•
The CM1234 also features easily routed "pass-
through" pinouts in a RoHS compliant (lead-free),16-
lead TDFN, small footprint package.
DVI ports, HDMI ports in notebooks, set top boxes,
digital TVs, LCD displays
General purpose high-speed data line ESD
protection
•
Electrical Schematic
Out_1+
Out_1-
In_1+
In_1-
Out_2+
Out_2-
In_2+
In_2-
Out_3+
Out_3-
In_3+
In_3-
In_4+
In_4-
Out_4+
Out_4-
= 100Ω differential
matched characteristic
impedance
Gnd
*Standard test condition is IEC61000-4-2 level 4 test circuit with each pin subjected to 8kv contact discharge for 1000 pulses. Discharges are timed at 1 second intervals and all 1000 strikes are completed in one continuous test
run. The part is then subjected to standard production test to verify that all of the tested parameters are within spec afterh the 1000 strkes.
© 2008 California Micro Devices Corp. All rights reserved.
4/24/2008
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.cmd.com
1
Issue X-2
CM1234
affect signal integrity or subsequent protection
capability. (This is known as "multi-strike" capabil-
ity.)
PicoGuard XS ESD Protection Archi-
tecture
Conceptually, an ESD protection device performs the
following actions upon an ESD strike discharge into a
protected ASIC (see Figure 1):
1. When an ESD potential is applied to the system
under test (contact or air-discharge), Kirchoff’s
Current Law (KCL) dictates that the Electrical
Overstress (EOS) currents will immediately divide
throughout the circuit, based on the dynamic
impedance of each path.
In the CM1234 PicoGuard XS architecture, the signal
line leading the connector to the ASIC routes through
the CM1234 chip which provides 100Ω matched
differential channel characteristic impedance that helps
optimize 100Ω load impedance applications such as
the HDMI high speed data lines.
Note:When each of the channels are used individually
for single-ended signal lines protection, the indi-
vidual channel provides 50Ω characteristic imped-
ance matching.
2. Ideally, the classic shunt ESD clamp will switch
within 1ns to a low-impedance path and return the
majority of the EOS current to the chassis shield/
reference ground. In actuality, if the ESD compo-
The load impedance matching feature of the CM1234
helps to simplify system designer’s PCB layout
considerations in impedance matching and also
eliminates associated passive components.
nent's response time (t
) is slower than the
CLAMP
ASIC it is protecting, or if the Dynamic Clamping
Resistance (RDYN) is not significantly lower than
the ASIC's I/O cell circuitry, then the ASIC will have
to absorb a large amount of the EOS energy, and
be more likely to fail.
The route through the PicoGuard XS architecture
enables the CM1234 to provide matched impedance
for the signal path between the connector and the
ASIC. Besides this function, this circuit arrangement
also changes the way the parasitic inductance interacts
with the ESD protection circuit and helps reduce the
3. Subsequent to the ESD/EOS event, both devices
must immediately return to their original specifica-
tions, and be ready for an additional strike. Any
deterioration in parasitics or clamping capability
should be considered a failure, since it can then
I
current to the ASIC.
RESIDUAL
ESD Strike
ESD
ESD
Protection
PROTECTION
ASIC
Device
DEVICE
I /O
Connector
ISHUNT
IRESIDUAL
Figure 1. Standard ESD Protection Device Block Diagram
© 2008 California Micro Devices Corp. All rights reserved.
2
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
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Fax: 408.263.7846
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www.cmd.com 4/24/2008
Issue X-2
CM1234
The PicoGuard XS Architecture Advantages
element. This limits the speed that the ESD pulse can
discharge through the ESD protection element.
Figure 2 illustrates a standard ESD protection device.
The inductor element represents the parasitic
inductance arising from the bond wire and the PCB
trace leading to the ESD protection diodes.
In the PicoGuard XS architecture, the inductive
elements are in series to the conduction path leading
to the protected device. The elements actually help to
limit the current and voltage striking the protected
device.
Connector
ASIC
First the reactance of the inductive element, L1, on the
connector side when an ESD strike occurs, acts in the
opposite direction of the ESD striking current. This
helps limit the peak striking voltage. Then the
reactance of the inductive element, L2, on the ASIC
side forces this limited ESD strike current to be
shunted through the ESD protection diodes. At the
same time, the voltage drop across both series
element acts to lower the clamping voltage at the
protected device terminal.
Bond Wire
Inductance
ESD
Stage
Through this arrangement, the inductive elements also
tune the impedance of the ESD protection element by
cancelling the capacitive load presented by the ESD
diodes to the signal line. This improves the signal
integrity and makes the overall ESD protection device
more transparent to the high bandwidth data signals
passing through the channel.
Figure 2. Standard ESD Protection Model
Figure 3 illustrates one of the channels. Similarly, the
inductor elements represent the parasitic inductance
arising from the bond wire and PCB traces leading to
the ESD protection diodes as well.
The innovative PicoGuard XS architecture turns the
disadvantages of the parasitic inductive elements into
useful components that help to limit the ESD current
strike to the protected device and also improves the
signal integrity of the system by balancing the
capacitive loading effects of the ESD diodes. At the
same time, this architecture provides an impedance
matched signal path for 50Ω loading applications.
Connector
ASIC
50Ω
L1
L2
ESD
Device
Board designs can take advantage of precision internal
component matching for improved signal integrity,
which is not otherwise possible with discrete
components at the system level. This helps to simplify
the PCB layout considerations by the system designer
and eliminates the associated passive components for
load matching that is normally required with standard
ESD protection circuits.
Figure 3. CM1234 PicoGuard XS ESD Protection
Model
CM1234 Inductor Elements
In the CM1234 PicoGuard XS architecture, the
inductor elements and ESD protection diodes interact
differently compared to the standard ESD model.
Each ESD channel consists of a pair of diodes in
series which steer the positive or negative ESD current
pulse to either the Zener diode or to ground. This
embedded Zener diode also serves to eliminate the
need for a separate bypass capacitor to absorb
positive ESD strikes to ground. The CM1234 protects
against ESD pulses up to 18kv contact per the IEC
61000-4-2 standard.
In the standard ESD protection device model, the
inductive element presents high impedance against
high slew rate strike voltage, i.e. during an ESD strike.
The impedance increases the resistance of the
conduction path leading to the ESD protection
© 2008 California Micro Devices Corp. All rights reserved.
4/24/2008
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.cmd.com
3
Issue X-2
CM1234
Package/Pin Information
PACKAGE / PINOUT DIAGRAMS
Bottom View (Solder Side)
Out_1+
Out_1-
Out_2+
In_1+
In_1-
In_2+
Out_2-
Out_3+
Out_3-
In_2-
In_3+
In_3-
In_4+
In_4-
Out_4+
Out_4-
Note:
1) This drawing is not to scale.
PIN DESCRIPTIONS
Pin
1
2
3
4
5
6
7
8
Name
In_1+
In_1-
In_2+
In_2-
In_3+
In_3-
In_4+
In_4-
Out_4-
Out_4+
Out_3-
Out_3+
Out_2-
Out_2+
Out_1-
Out_1+
GND
Description
Bidrectional Clamp to ASIC (inside system)
Bidrectional Clamp to ASIC (inside system)
Bidrectional Clamp to ASIC (inside system)
Bidrectional Clamp to ASIC (inside system)
Bidrectional Clamp to ASIC (inside system)
Bidrectional Clamp to ASIC (inside system)
Bidrectional Clamp to ASIC (inside system)
Bidrectional Clamp to ASIC (inside system)
Bidrectional Clamp to Connector (outside system)
Bidrectional Clamp to Connector (outside system)
Bidrectional Clamp to Connector (outside system)
Bidrectional Clamp to Connector (outside system)
Bidrectional Clamp to Connector (outside system)
Bidrectional Clamp to Connector (outside system)
Bidrectional Clamp to Connector (outside system)
Bidrectional Clamp to Connector (outside system)
Ground return to shield
9
10
11
12
13
14
15
16
PAD
Ordering Information
PART NUMBERING INFORMATION
PIN
16
PACKAGE
TDFN-16
LEAD-FREE FINISH
Part Marking
CM1234-08
CM1234-08DE
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
© 2008 California Micro Devices Corp. All rights reserved.
4
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.cmd.com 4/24/2008
Issue X-2
CM1234
Specifications
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
RATING
-40 to +85
-65 to +150
6
UNITS
°C
°C
Operating Temperature Range
Storage Temperature Range
Breakdown Voltage (Positive)
V
*Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
(SEE NOTE 1)
ELECTRICAL OPERATING CHARACTERISTICS
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
VIN
IIN
I/O Voltage Relative to GND
-0.5
5.5
V
Continuous Current through signal pins (IN
to OUT) 1000 Hr
100
mA
IF
Channel Leakage Current
TA = 25°C; VN = 0V, VTEST = 5V
±0.1
±1.0
µA
VESD
ESD Protection - Peak Discharge Voltage
at any channel input, in system:
a) Contact discharge per
IEC 61000-4-2 Standard
and
TA = 25°C; Note 2
TA = 25°C; Note 2
±±5
±20
kV
kV
b) Air discharge per IEC 61000-4-2 Stan-
dard
IRES
Residual ESD Peak Current on RDUP
(Resistance of Device Under Protection)
IEC 61000-4-2 8kV;
RDUP = 5Ω, TA = 25°C;
2.5
A
Note 2
VCL
Channel Clamp Voltage
(Channel clamp voltage per
IEC 61000-4-5 Standard)
Positive Transients
IPP = 1A, TA = 25°C,
tP = 8/20μS;
Note 2
+9
–1.5
V
V
Negative Transients
RDYN
Dynamic Resistance
Positive Transients
Negative Transients
IPP = 1A, TA = 25ºC,
tP = 8/20μS;
Note 2
0.44
0.38
Ω
Ω
Zo
Differential Channels pair characteristic
impedance
TR = 200ps;
Note 2
100
Ω
%
Ω
%
ΔZo
Channel-to-Channel Impedance Match
(Differential)
TR = 200ps;
Note 2
2
ZCHANNEL Individual Channel Characteristic Imped-
ance in Single-ended Connection
TR = 200ps
50
2
ΔZCHANNEL Channel-to-Channel Impedance Match
TR = 200ps;
Note 2
(Individual)
Note 1: All parameters specified at TA = –40°C to +85°C unless otherwise noted.
Note 2: This parameter is guaranteed by design and verified by device characterization
© 2008 California Micro Devices Corp. All rights reserved.
4/24/2008
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.cmd.com
5
Issue X-2
CM1234
Performance Information
Graphical Comparison and Test Setup
Figure 4 shows that the CM1234 (PicoGuard XS ESD protector) lowers the peak voltage and clamping voltage
by 45% across a wide range of loading conditions in comparison to a standard ESD protection device. Figure 5
also indicates that the DUP/ASIC protected by the CM1234 dissipates less energy than a standard ESD protection
device. This data was derived using the test setups shown in Figure 6.
1.2
1
0.8
CM1234-08
STD ESD
0.6
Device
0.4
0.2
0
0
2
4
6
8
10
12
14
16
18
20
RDUP (Ω)
Figure 4. V
vs. RDUP* (ASIC) – 8kV Contract Strike
CLAMP
1.2
1
0.8
0.6
0.4
0.2
0
CM1234-08
STD ESD
Device
0
2
4
6
8
10
12
14
16
18
20
RDUP (Ω)
Figure 5. I
vs RDUP* (ASIC) – 8kV Contract Strike
RESIDUAL
* RDUP is the emulated Dynamic Resistance (load) of the Device Under Protection (DUP). See Figure 6.
© 2008 California Micro Devices Corp. All rights reserved.
6
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.cmd.com 4/24/2008
Issue X-2
CM1234
Voltage
Probe
Voltage
Probe
IEC 6100-4-2
IEC 6100-4-2
Test Standards
Test Standards
CM1234
Device Under
Protection (DUP)
Device Under
Protection (DUP)
Standard
ESD Device
RVARIABLE
RVARIABLE
Current
Probe
Current
Probe
IRESIDUAL
IRESIDUAL
CM1234 Test Setup
Standard ESD
Device Test Setup
Figure 6. Test Setups: Standard Device (Left) and CM1234 (Right)
© 2008 California Micro Devices Corp. All rights reserved.
4/24/2008
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.cmd.com
7
Issue X-2
CM1234
Application Information
CM1234 Application and Guidelines
As a general rule, the CM1234 ESD protection array should be located as close as possible to the point of entry of
expected electrostatic discharges with minimum PCB trace lengths to the ground planes and between the signal
input and the ESD device to minimize stray series inductance.
VCC
CM1234
Circuitry Under
Protection
Path of ESD
current pulse
Line Being
Protected
(IESD
)
Channel
Output
Channel
Input
VCL
VN
Ground Rail
Figure 7. Application of Positive ESD Pulse Between Input Channel and Ground
Figure 8. Typical PCB Layout
Additional Information
See also California Micro Devices Application Note AP209, “Design Considerations for ESD Protection,” in the
Applications section at www.calmicro.com.
© 2008 California Micro Devices Corp. All rights reserved.
8
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.cmd.com 4/24/2008
Issue X-2
CM1234
Mechanical Details
Mechanical Package Diagrams
TDFN-16 Mechanical Specifications, 0.75mm
The 16-lead, 6.0x4.0mm, 0.75mm pitch TDFN package
dimensions are presented below.
TOP VIEW
D
16 15 14 13 12 11 10 9
PACKAGE DIMENSIONS
Package
TDFN
*
JEDEC
No.
MO-229C
E
Leads
16
Pin 1
Marking
Millimeters
Nom
Inches
Nom
Dim.
Min
0.70
0.00
Max
Min
Max
1 2 3 4 5 6 7 8
A
A1
A3
b
0.75
0.80 0.028 0.030 0.031
0.05 0.000 0.001 0.002
0.02
0.175 0.200 0.225 0.007 0.008 0.009
0.20
5.90
5.05
3.90
1.75
0.25
6.00
0.30 0.008 0.010 0.012
6.10 0.232 0.236 0.240
5.15 0.199 0.201 0.203
4.10 0.153 0.157 0.161
1.85 0.012 0.016 0.020
0.029 BSC
SIDE VIEW
D
0.10
C
D2
E
5.10
4.00
0.08
C
E2
e
1.80
A1
A3
0.75 BSC
0.70 REF
0.40
A
K
0.028 REF
L
0.35
0.45 0.014 0.016 0.018
3000 pieces
# per
tape and
reel
BOTTOM VIEW
16X
M
0.10
C A B
e
b
Controlling dimension: millimeters
E2
Pin 1
1
2
3
4
5
6
7
8
9
Locator
*
This package is compliant with JEDEC standard MO-229C with the
exception of the D, D2, E, E2, K and L dimensions as called out in
the table above.
C0.2
GND PAD
16 15 14 13 12
11 10
K
L
D2
Dimensions for 16-Lead, 0.75mm pitch
TDFN package
© 2008 California Micro Devices Corp. All rights reserved.
4/24/2008
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.cmd.com
9
Issue X-2
CM1234
Tape and Reel Specifications
PACKAGE SIZE
POCKET SIZE (mm)
B0 X A0 X K0
TAPE WIDTH
W
REEL
DIAMETER
QTY PER
REEL
P0
P1
PART NUMBER
(mm)
CM1234
6.00 X 4.00 X 0.75
6.30 X 4.30 X 1.10
12mm
330mm (13")
3000
4mm 8mm
10 Pitches Cumulative
Tolerance On Tape
0.2 mm
P
o
Top
Cover
Tape
A
o
W
B
o
K
o
For tape feeder reference
Embossment
only including draft.
P
Center Lines
of Cavity
1
Concentric around B.
User Direction of Feed
© 2008 California Micro Devices Corp. All rights reserved.
10
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.cmd.com 4/24/2008
相关型号：
CM1235-08DE
Small Footprint PicoGuard XS? ESD Clamp Array For High Speed Data Line Protection
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