CLC1605IST5X [CADEKA]
Single and Triple, 1.5GHz Amplifiers; 单路和三路， 1.5GHz的放大器
| 型号： | CLC1605IST5X |
| 厂家： | 
CADEKA MICROCIRCUITS LLC. |
| 描述： | Single and Triple, 1.5GHz Amplifiers |
| 文件： | 总20页 (文件大小：2564K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
Amplify the Human Experience
Co m l i n e a r ® CLC1605, CLC3605
Single and Triple, 1.5GHz Amplifiers
f e a t u r e s
General Description
nꢀ
0.1dB gain flatness to 120MHz
The COMLINEAR CLC1605 (single) and CLC3605 (triple) are high-perfor-
mance, current feedback amplifiers that provide 1.5GHz unity gain band-
width, ±0.1dB gain flatness to 120MHz, and 2,500V/μs slew rate. This high
performance exceeds the requirements of high-definition television (HDTV)
and other multimedia applications. These COMLINEAR high-performance am-
plifiers also provide ample output current to drive multiple video loads.
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
0.01%/0.01˚ differential gain/phase
1.2GHz -3dB bandwidth at G = 2
700MHz large signal bandwidth
2,500V/μs slew rate
3.7nV/√Hz input voltage noise
120mA output current
Triple offers disable
The COMLINEAR CLC1605 and CLC3605 are designed to operate from ±5V
or +5V supplies. The CLC3605 offers a fast enable/disable feature to save
power. While disabled, the outputs are in a high-impedance state to allow for
multiplexing applications. The combination of high-speed, low-power, and ex-
cellent video performance make these amplifiers well suited for use in many
general purpose, high-speed applications including high-definition video, im-
aging applications, and radar/communications receivers.
Fully specified at 5V and ±5V supplies
CLC1605: Pb-free SOT23-5
CLC3605: Pb-free SOIC-16
a p p l i c a t i o n s
nꢀ
RGB video line drivers
nꢀ
High definition video driver
nꢀ
Video switchers and routers
nꢀ
ADC buffer
Typical Application - Driving Dual Video Loads
nꢀ
Active filters
nꢀ
High-speed instrumentation
+Vs
nꢀ
Wide dynamic range IF amp
nꢀ
Radar/communication receivers
75Ω
Cable
75Ω
Input
Cable
75Ω
75Ω
Output A
Output B
75Ω
75Ω
75Ω
R
f
R
g
75Ω
Cable
-Vs
Ordering Information
Part Number
Package
Pb-Free
RoHS Compliant
Operating Temperature Range Packaging Method
CLC1605IST5X
CLC3605ISO16X
CLC3605ISO16
SOT23-5
SOIC-16
SOIC-16
Yes
Yes
Yes
Yes
Yes
Yes
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Reel
Reel
Rail
Moisture sensitivity level for all parts is MSL-1.
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
Data Sheet
CLC1605 Pin Assignments
CLC1605 Pin Configuration
Pin No.
Pin Name
OUT
Description
1
2
3
4
5
Output
OUT
1
2
3
5
4
+V
S
-V
Negative supply
Positive input
Negative input
Positive supply
S
+IN
-IN
-V
S
+
-
-IN
+IN
+V
S
CLC3605 Pin Configuration
Pin No.
Pin Name
-IN1
Description
Negative input, channel 1
Positive input, channel 1
Negative supply
1
2
3
4
5
6
7
8
CLC3605 Pin Configuration
+IN1
-V
S
-IN2
Negative input, channel 2
Positive input, channel 2
Negative supply
1
2
3
4
16
15
14
13
12
11
10
9
+IN2
-IN1
+IN1
-VS
DIS1
OUT1
+VS
-V
S
+IN3
-IN3
Positive input, channel 3
Negative input, channel 3
-IN2
DIS2
OUT2
+VS
Disable pin. Enabled if pin is grounded, left float-
9
DIS3
ing or pulled below V , disabled if pin is pulled
ON
5
6
7
+IN2
above V
.
OFF
-VS
10
11
12
OUT3
Output, channel 3
Positive supply
+V
S
+IN3
OUT3
DIS3
OUT2
DIS2
Output, channel 2
8
-IN3
Disable pin. Enabled if pin is grounded, left float-
13
ing or pulled below V , disabled if pin is pulled
ON
above V
.
OFF
+V
S
Positive supply
14
15
OUT1
Output, channel 1
Disable pin. Enabled if pin is grounded, left float-
16
DIS1
ing or pulled below V , disabled if pin is pulled
ON
above V
.
OFF
Disable Pin Truth Table
Pin
High
Disabled
Low*
Enabled
DIS
*Default Open State
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
2
Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device
should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper de-
vice function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the
operating conditions noted on the tables and plots.
Parameter
Min
0
Max
Unit
Supply Voltage
14
V
V
Input Voltage Range
Continuous Output Current
-V -0.5V
s
+V +0.5V
s
120
mA
Reliability Information
Parameter
Min
-65
Typ
Max
Unit
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10s)
Package Thermal Resistance
5-Lead SOT23
150
150
260
°C
°C
°C
221
68
°C/W
°C/W
16-Lead SOIC
Notes:
Package thermal resistance (q ), JDEC standard, multi-layer test boards, still air.
JA
ESD Protection
Product
SOT23-5
SOIC-16
2kV
Human Body Model (HBM)
2kV
1kV
Charged Device Model (CDM)
1kV
Recommended Operating Conditions
Parameter
Min
Typ
Max
Unit
Operating Temperature Range
-40
4.5
+85
12
°C
V
Supply Voltage Range
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
3
Data Sheet
Electrical Characteristics at +5V
T = 25°C, V = +5V, R = R =330Ω, R = 150Ω to V /2, G = 2; unless otherwise noted.
A
s
f
g
L
S
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Frequency Domain Response
UGBW
Unity Gain Bandwidth
-3dB Bandwidth
G = +1, VOUT = 0.5Vpp, Rf = 499Ω
G = +2, VOUT = 0.5Vpp
G = +2, VOUT = 1Vpp
1250
1000
825
MHz
MHz
MHz
MHz
MHz
BWSS
BWLS
Large Signal Bandwidth
0.1dB Gain Flatness
0.1dB Gain Flatness
BW0.1dBSS
BW0.1dBLS
100
G = +2, VOUT = 0.5Vpp
G = +2, VOUT = 1Vpp
100
Time Domain Response
tR, tF
tS
Rise and Fall Time
VOUT = 1V step; (10% to 90%)
VOUT = 1V step
0.6
10
ns
ns
Settling Time to 0.1%
Overshoot
OS
SR
VOUT = 0.2V step
2V step
1
%
Slew Rate
1350
V/µs
Distortion/Noise Response
HD2
HD3
THD
DG
2nd Harmonic Distortion
VOUT = 1Vpp, 5MHz
-75
-85
74
dBc
dBc
3rd Harmonic Distortion
Total Harmonic Distortion
Differential Gain
VOUT = 1Vpp, 5MHz
VOUT = 1Vpp, 5MHz
dB
0.04
0.01
37
%
NTSC (3.58MHz), AC-coupled, RL = 150Ω
NTSC (3.58MHz), AC-coupled, RL = 150Ω
VOUT = 1Vpp, 10MHz
DP
Differential Phase
°
IP3
SFDR
en
Third Order Intercept
Spurious Free Dynamic Range
Input Voltage Noise
dBm
dBc
VOUT = 1Vpp, 5MHz
61
> 1MHz
3.7
20
nV/√Hz
pA/√Hz
pA/√Hz
> 1MHz, Inverting
in
Input Current Noise
> 1MHz, Non-Inverting
Channel-to-channel 5MHz, VOUT = 2Vpp
30
XTALK
Crosstalk
60
dB
DC Performance
VIO
dVIO
Ibn
Input Offset Voltage
Average Drift
0
1.6
3
mV
µV/°C
µA
Input Bias Current - Non-Inverting
Average Drift
dIbn
Ibi
7
nA/°C
µA
Input Bias Current - Inverting
Average Drift
6
dIbi
PSRR
IS
20
58
11
nA/°C
dB
Power Supply Rejection Ratio
Supply Current
DC
per channel
mA
Disable Characteristics - CLC3605 only
TON
Turn On Time
Turn Off Time
Off Isolation
23
350
75
ns
ns
dB
TOFF
OFFIOS
5MHz, VOUT = 2Vpp
VOFF
Power Down Input Voltage
DIS pin, disabled if pin is pulled above VOFF
Disabled if DIS > 1.5V
V
DIS pin, enabled if pin is grounded, left open
or pulled below VON
VON
Enable Input Voltage
Enabled if DIS < 0.5V
V
ISD
Disable Supply Current
DIS pin is pulled to VS
0.09
mA
Input Characteristics
Non-inverting
Inverting
150
70
kΩ
Ω
RIN
CIN
Input Resistance
Input Capacitance
1.0
pF
1.5 to
3.5
CMIR
Common Mode Input Range
V
CMRR
Common Mode Rejection Ratio
DC
50
dB
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
4
Data Sheet
Electrical Characteristics at +5V continued
T = 25°C, V = +5V, R = R =330Ω, R = 150Ω to V /2, G = 2; unless otherwise noted.
A
s
f
g
L
S
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Output Characteristics
Closed Loop, DC
0.1
Ω
V
RO
Output Resistance
1.5 to
3.5
VOUT
IOUT
Output Voltage Swing
Output Current
RL = 150Ω
±120
mA
nꢀꢅꢄꢈ:
1. 100% tested at 25°C
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
5
Data Sheet
Electrical Characteristics at ±5V
T = 25°C, V = ±5V, R = R =330Ω, R = 150Ω to GND, G = 2; unless otherwise noted.
A
s
f
g
L
symbꢀꢁ
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Frequency Domain Response
UGBW
Unity Gain Bandwidth
-3dB Bandwidth
G = +1, VOUT = 0.5Vpp, Rf = 499Ω
G = +2, VOUT = 0.5Vpp
G = +2, VOUT = 2Vpp
1500
1200
700
MHz
MHz
MHz
MHz
MHz
BWSS
BWLS
Large Signal Bandwidth
0.1dB Gain Flatness
0.1dB Gain Flatness
BW0.1dBSS
BW0.1dBLS
120
G = +2, VOUT = 0.5Vpp
G = +2, VOUT = 2Vpp
120
Time Domain Response
tR, tF
tS
Rise and Fall Time
VOUT = 2V step; (10% to 90%)
VOUT = 2V step
0.65
13
ns
ns
Settling Time to 0.1%
Overshoot
OS
SR
VOUT = 0.2V step
2V step
1
%
Slew Rate
2500
V/µs
Distortion/Noise Response
HD2
HD3
THD
DG
2nd Harmonic Distortion
VOUT = 2Vpp, 5MHz
-73
-85
72
dBc
dBc
3rd Harmonic Distortion
Total Harmonic Distortion
Differential Gain
VOUT = 2Vpp, 5MHz
VOUT = 2Vpp, 5MHz
dB
0.01
0.01
42
%
NTSC (3.58MHz), AC-coupled, RL = 150Ω
NTSC (3.58MHz), AC-coupled, RL = 150Ω
VOUT = 2Vpp, 10MHz
DP
Differential Phase
°
IP3
SFDR
en
Third Order Intercept
Spurious Free Dynamic Range
Input Voltage Noise
dBm
dBc
VOUT = 1Vpp, 5MHz
73
> 1MHz
3.7
20
nV/√Hz
pA/√Hz
pA/√Hz
> 1MHz, Inverting
in
Input Current Noise
> 1MHz, Non-Inverting
Channel-to-channel 5MHz
30
XTALK
Crosstalk
60
dB
DC Performance
VIO
dVIO
Ibn
Input Offset Voltage (1)
-10
-40
-35
40
0
1.6
19
7
10
40
35
mV
µV/°C
µA
Average Drift
Input Bias Current - Non-Inverting (1)
Average Drift
dIbn
Ibi
nA/°C
µA
Input Bias Current - Inverting (1)
Average Drift
6
dIbi
PSRR
IS
20
60
12
nA/°C
dB
Power Supply Rejection Ratio (1)
Supply Current (1)
DC
per channel
18
mA
Disable Characteristics - CLC3605 only
TON
Turn On Time
Turn Off Time
Off Isolation
35
410
75
ns
ns
dB
TOFF
OFFIOS
5MHz, VOUT = 2Vpp
VOFF
Power Down Input Voltage
DIS pin, disabled if pin is pulled above VOFF
Disabled if DIS > 3V
V
DIS pin, enabled if pin is grounded, left open
or pulled below VON
VON
Enable Input Voltage
Enabled if DIS < 1V
V
ISD
Disable Supply Current (1)
per channel, DIS pin is pulled to VS
0.1
0.3
mA
Input Characteristics
Non-inverting
Inverting
150
70
kΩ
Ω
RIN
CIN
Input Resistance
Input Capacitance
1.0
pF
CMIR
Common Mode Input Range
±4.0
V
CMRR
Common Mode Rejection Ratio (1)
DC
40
55
dB
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
6
Data Sheet
Electrical Characteristics at ±5V continued
T = 25°C, V = ±5V, R = R =330Ω, R = 150Ω to GND, G = 2; unless otherwise noted.
A
s
f
g
L
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Output Characteristics
Closed Loop, DC
0.1
Ω
V
RO
Output Resistance
VOUT
IOUT
Output Voltage Swing
Output Current
RL = 150Ω (1)
±3.0
±3.8
±280
mA
nꢀꢅꢄꢈ:
1. 100% tested at 25°C
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
7
Data Sheet
Typical Performance Characteristics
T = 25°C, V = ±5V, R = R =330Ω, R = 150Ω to GND, G = 2; unless otherwise noted.
A
s
f
g
L
Non-Inverting Frequency Response
Inverting Frequency Response
1
0
G = 1
Rf = 499Ω
G = -1
G = -2
3
G = 1
Rf = 750Ω
-1
-2
-3
-4
-5
0
-3
-6
-9
G = -5
G = 2
G = 5
G = -10
G = 1 0
-6
VOUT = 0.5Vpp
VOUT = 0.5Vpp
-7
0.1
1
10
Frequency (MHz)
100
1000
0.1
1
10
Frequency (MHz)
100
1000
Frequency Response vs. C
Frequency Response vs. R
L
L
1
0
5
4
3
CL = 1000pF
-1
-2
-3
-4
-5
-6
-7
Rs = 3.3Ω
2
CL = 500pF
Rs = 5Ω
1
0
CL = 100pF
Rs = 10Ω
-1
-2
-3
-4
RL = 100Ω
CL = 50pF
Rs = 15Ω
RL = 50Ω
CL = 20pF
Rs = 20Ω
VOUT = 0.5Vpp
-5
RL = 25Ω
VOUT = 0.5Vpp
-6
0.1
1
10
100
1000
0.1
1
10
Frequency (MHz)
100
1000
Frequency (MHz)
Frequency Response vs. V
Frequency Response vs. Temperature
OUT
1
0
2
1
0
-1
-2
-3
-4
-5
-6
-7
VOUT = 4Vpp
-1
+ 25degC
- 40degC
+ 85degC
-2
-3
-4
VOUT = 2Vpp
VOUT = 1Vpp
-5
VOUT = 0.2Vpp
-6
-7
0.1
1
10
Frequency (MHz)
100
1000
0.1
1
10
100
1000
10000
Frequency (MHz)
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
8
Data Sheet
Typical Performance Characteristics
T = 25°C, V = ±5V, R = R =330Ω, R = 150Ω to GND, G = 2; unless otherwise noted.
A
s
f
g
L
Non-Inverting Frequency Response at V = 5V
Inverting Frequency Response at V = 5V
S
S
1
0
G = 1
Rf = 499Ω
G = -1
G = -2
3
G = 1
Rf = 750Ω
-1
0
G = -5
-2
G = 2
-3
-4
-5
-6
-7
G = -10
-3
G = 5
G = 1 0
-6
VOUT = 0.5Vpp
VOUT = 0.5Vpp
-9
0.1
1
10
100
1000
0.1
1
10
Frequency (MHz)
100
1000
Frequency (MHz)
Frequency Response vs. C at V = 5V
Frequency Response vs. R at V = 5V
L
S
L
S
1
0
3
2
CL = 1000pF
Rs = 3.3Ω
1
-1
-2
-3
-4
-5
-6
-7
0
CL = 500pF
Rs = 5Ω
-1
-2
-3
-4
-5
-6
RL = 100Ω
CL = 100pF
Rs = 10Ω
RL = 50Ω
CL = 50pF
Rs = 15Ω
RL = 25Ω
CL = 20pF
Rs = 20Ω
VOUT = 0.5Vpp
VOUT = 0.5Vpp
0.1
1
10
100
1000
0.1
1
10
Frequency (MHz)
100
1000
Frequency (MHz)
Frequency Response vs. V
at V = 5V
Frequency Response vs. Temperature at V = 5V
OUT
S
S
1
0
2
1
0
-1
-2
-3
-4
-5
-6
-7
VOUT = 3Vpp
-1
-2
+ 25degC
VOUT = 2Vpp
-3
- 40degC
-4
VOUT = 1Vpp
+ 85degC
-5
VOUT = 0.2Vpp
-6
-7
0.1
1
10
Frequency (MHz)
100
1000
0.1
1
10
100
1000
10000
Frequency (MHz)
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
9
Data Sheet
Typical Performance Characteristics - Continued
T = 25°C, V = ±5V, R = R =330Ω, R = 150Ω to GND, G = 2; unless otherwise noted.
A
s
f
g
L
Gain Flatness
Gain Flatness at V = 5V
S
0.1
0.1
0
-0.1
-0.2
-0.3
-0.4
0
-0.1
-0.2
-0.3
VOUT = 2Vpp
RL = 150Ω
Rf = 330Ω
VOUT = 2Vpp
RL = 150Ω
Rf = 330Ω
-0.4
-0.5
-0.5
0.1
1
10
Frequency (MHz)
100
1000
0.1
1
10
100
1000
Frequency (MHz)
-3dB Bandwidth vs. V
-3dB Bandwidth vs. V
at V = 5V
OUT S
OUT
1800
1600
1400
1200
1000
800
1200
1100
1000
900
800
700
600
500
400
300
200
600
400
200
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOUT (VPP
)
VOUT (VPP)
Closed Loop Output Impedance vs. Frequency
Input Voltage Noise
10
25
V
= ±5.0V
S
20
15
10
5
1
0.1
0.01
0
10K
100K
1M
10M
100M
0.0001 0.001
0.01
0.1
1
10
Frequency (Hz)
Frequency (MHz)
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
10
Data Sheet
Typical Performance Characteristics - Continued
T = 25°C, V = ±5V, R = R =330Ω, R = 150Ω to GND, G = 2; unless otherwise noted.
A
s
f
g
L
2nd Harmonic Distortion vs. R
3rd Harmonic Distortion vs. R
L
L
-55
-60
-65
-70
-65
RL = 150Ω
-75
-80
RL = 150Ω
-70
-75
-80
-85
-90
-85
-90
RL = 1kΩ
-95
RL = 1kΩ
-95
VOUT = 2Vpp
VOUT = 2Vpp
-100
-100
0
5
10
Frequency (MHz)
15
20
0
5
10
Frequency (MHz)
15
20
2nd Harmonic Distortion vs. V
3rd Harmonic Distortion vs. V
OUT
OUT
-60
-65
-70
-75
-80
-70
10MHz
-75
-80
10MHz
5MHz
1MHz
-85
-90
5MHz
-85
-90
1MHz
-95
-95
RL = 150Ω
0.5 0.75
RL = 150Ω
0.5 0.75
-100
-100
1
1.25
1.5
1.75
2
2.25
2.5
1
1.25
1.5
1.75
2
2.25
2.5
Output Amplitude (Vpp
)
Output Amplitude (Vpp)
CMRR vs. Frequency
PSRR vs. Frequency
-25
0
V
= ±5.0V
S
-30
-35
-40
-45
-50
-55
-10
-20
-30
-40
-50
-60
10k
100k
1M
10M
100M
10K
100K
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
11
Data Sheet
Typical Performance Characteristics - Continued
T = 25°C, V = ±5V, R = R =330Ω, R = 150Ω to GND, G = 2; unless otherwise noted.
A
s
f
g
L
Small Signal Pulse Response
Small Signal Pulse Response at V = 5V
S
0.125
0.1
2.625
2.6
0.075
0.05
2.575
2.55
2.525
2.5
0.025
0
-0.025
-0.05
-0.075
-0.1
2.475
2.45
2.425
2.4
-0.125
2.375
0
20
40
60
80
100 120 140 160 180 200
0
20
40
60
80
100 120 140 160 180 200
T im e ( n s )
T im e ( n s )
Large Signal Pulse Response
Large Signal Pulse Response at V = 5V
S
2.5
2
4
3.5
3
1.5
1
0.5
0
2.5
2
-0.5
-1
-1.5
-2
1.5
1
-2.5
0
20
40
60
80
100
120
140
160
180
200
0
20
40
60
80
100
120
140
160
180
200
T im e ( n s )
T im e ( n s )
Differential Gain & Phase AC Coupled Output
Differential Gain & Phase DC Coupled Output
0.01
0.03
0.005
0.02
0.01
0
DP
DG
DG
0
-0.005
-0.01
DP
-0.01
-0.02
-0.03
-0.015
RL = 150Ω
AC coupled
RL = 150Ω
DC coupled
-0.02
-0 .7
-0.5
-0.3
-0.1
0.1
0.3
0.5
0 .7
-0 .7
-0.5
-0.3
-0.1
0.1
0.3
0.5
0 .7
I n p u t Vo l t a g e ( V )
I n p u t Vo l t a g e ( V )
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
12
Data Sheet
Typical Performance Characteristics - Continued
T = 25°C, V = ±5V, R = R =330Ω, R = 150Ω to GND, G = 2; unless otherwise noted.
A
s
f
g
L
Differential Gain & Phase AC Coupled Output at V = ±2.5V
Differential Gain & Phase DC Coupled at V = ±2.5V
S
S
0.01
0.02
DP
0.01
0
DP
0
-0.01
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-0.07
-0.02
DG
DG
-0.03
-0.04
RL = 150Ω
AC coupled
RL = 150Ω
DC coupled
-0.05
-0.35
-0.25
-0.15
-0.05
0.05
0.15
0.25
0.35
-0.35
-0.25
-0.15
-0.05
0.05
0.15
0.25
0.35
I n p u t Vo l t a g e ( V )
I n p u t Vo l t a g e ( V )
Crosstalk vs. Frequency (CLC3605)
Crosstalk vs. Frequency at V =5V (CLC3605)
S
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
VOUT = 2Vpp
VOUT = 1Vpp
0.1
1
10
100
0.1
1
10
100
Frequency (MHz)
Frequency (MHz)
Off Isolation vs. Frequency
Off Isolation vs. Frequency at V =5V
S
-45
-50
-45
-50
-55
-55
-60
-60
-65
-65
-70
-70
-75
-75
-80
-80
-85
-85
-90
-90
-95
-95
-100
-105
-110
-100
-105
-110
VOUT = 2Vpp
VOUT = 1Vpp
0.1
1
10
100
0.1
1
10
100
Frequency (MHz)
Frequency (MHz)
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
13
Data Sheet
General Information - Current Feedback
Technology
Advantages of CFB Technology
V
OUT
x1
Z *I
err
o
I
err
The CLC1605 Family of amplifiers utilize current feedback
(CFB) technology to achieve superior performance. The
primary advantage of CFB technology is higher slew rate
performance when compared to voltage feedback (VFB)
architecture. High slew rate contributes directly to better
large signal pulse response, full power bandwidth, and
distortion.
R
R
g
f
R
L
V
IN
VOUT
Rf
1
=
−
+
Eq. 2
V
Rg
Rf
Zo(jω)
IN
1 +
CFB also alleviates the traditional trade-off between
closed loop gain and usable bandwidth that is seen with
a VFB amplifier. With CFB, the bandwidth is primarily de-
Figure 2. Inverting Gain Configuration with First Order
Transfer Function
termined by the value of the feedback resistor, R . By us-
f
ing optimum feedback resistor values, the bandwidth of a
CFB amplifier remains nearly constant with different gain
configurations.
CFB Technology - Theory of Operation
Figure 1 shows a simple representation of a current feed-
back amplifier that is configured in the traditional non-
inverting gain configuration.
When designing with CFB amplifiers always abide by these
basic rules:
• Use the recommended feedback resistor value
Instead of having two high-impedance inputs similar to a
VFB amplifier, the inputs of a CFB amplifier are connected
across a unity gain buffer. This buffer has a high imped-
ance input and a low impedance output. It can source or
• Do not use reactive (capacitors, diodes, inductors, etc.)
elements in the direct feedback path
• Avoid stray or parasitic capacitance across feedback re-
sistors
sink current (I ) as needed to force the non-inverting
err
input to track the value of Vin. The CFB architecture em-
ploys a high gain trans-impedance stage that senses Ierr
• Follow general high-speed amplifier layout guidelines
and drives the output to a value of (Z (jω) * I ) volts.
o
err
• Ensure proper precautions have been made for driving
capacitive loads
With the application of negative feedback, the amplifier
will drive the output to a voltage in a manner which tries
to drive Ierr to zero. In practice, primarily due to limita-
tions on the value of Z (jω), Ierr remains a small but
o
finite value.
V
IN
V
OUT
x1
Z *I
o err
I
err
A closer look at the closed loop transfer function (Eq.1)
shows the effect of the trans-impedance, Z (jω) on the
o
R
f
gain of the circuit. At low frequencies where Z (jω) is very
R
L
o
large with respect to R , the second term of the equation
f
R
g
approaches unity, allowing R and R to set the gain. At
f
g
higher frequencies, the value of Z (jω) will roll off, and
o
the effect of the secondary term will begin to dominate.
The -3dB small signal parameter specifies the frequency
VOUT
Rf
1
=
1 +
+
Eq. 1
where the value Z (jω) equals the value of R causing the
o
f
V
Rg
Rf
Zo(jω)
IN
1 +
gain to drop by 0.707 of the value at DC.
For more information regarding current feedback ampli-
fiers, visit www.cadeka.com for detailed application notes,
such as AN-3: The Ins and Outs of Current Feedback Am-
plifiers.
Figure 1. Non-Inverting Gain Configuration with First
Order Transfer Function
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
14
Data Sheet
CFB amplifiers can be used in unity gain configurations.
Do not use the traditional voltage follower circuit, where
the output is tied directly to the inverting input. With a
CFB amplifier, a feedback resistor of appropriate value
must be used to prevent unstable behavior. Refer to fig-
ure 5 and Table 1. Although this seems cumbersome, it
does allow a degree of freedom to adjust the passband
characteristics.
Application Information
Basic Operation
Figures 3, 4, and 5 illustrate typical circuit configurations for
non-inverting, inverting, and unity gain topologies for dual
supply applications. They show the recommended bypass
capacitor values and overall closed loop gain equations.
+Vs
6.8μF
Feedback Resistor Selection
One of the key design considerations when using a CFB
0.1μF
amplifier is the selection of the feedback resistor, R . R is
f
f
Input
+
-
used in conjunction with R to set the gain in the tradi-
Output
g
tional non-inverting and inverting circuit configurations.
Refer to figures 3 and 4. As discussed in the Current Feed-
back Technology section, the value of the feedback resis-
tor has a pronounced effect on the frequency response of
the circuit.
RL
0.1μF
6.8μF
Rf
Rg
G = 1 + (Rf/Rg)
-Vs
Table 1, provides recommended R and associated R val-
f
g
ues for various gain settings. These values produce the
optimum frequency response, maximum bandwidth with
minimum peaking. Adjust these values to optimize perfor-
mance for a specific application. The typical performance
characteristics section includes plots that illustrate how
Figure 3. Typical Non-Inverting Gain Circuit
+Vs
6.8μF
the bandwidth is directly affected by the value of R at
various gain settings.
f
R1
0.1μF
+
Output
Rg
Input
-
RL
±0.1dB BW
(MHz)
-3dB BW
(MHz)
Gain
(V/V
0.1μF
R (Ω)
f
R (Ω)
g
Rf
1
2
499
330
330
330
-
167
120
66
1500
1200
385
6.8μF
G = - (Rf/Rg)
-Vs
330
82.5
33
For optimum input offset
voltage set R1 = Rf || Rg
5
10
38
245
Figure 4. Typical Inverting Gain Circuit
Table 1: Recommended R vs. Gain
f
+Vs
6.8μF
In general, lowering the value of R from the recom-
f
mended value will extend the bandwidth at the expense
of additional high frequency gain peaking. This will cause
increased overshoot and ringing in the pulse response
0.1μF
Input
+
Output
characteristics. Reducing R too much will eventually
-
f
RL
cause oscillatory behavior.
0.1μF
Rf
Increasing the value of R will lower the bandwidth. Low-
f
6.8μF
G = 1
ering the bandwidth creates a flatter frequency response
and improves 0.1dB bandwidth performance. This is im-
portant in applications such as video. Further increase in
-Vs
Rf is required for CFB amplifiers
R will cause premature gain rolloff and adversely affect
f
Figure 5. Typical Unity Gain (G=1) Circuit
gain flatness.
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
15
Data Sheet
Driving Capacitive Loads
In general, avoid adding any additional parasitic capaci-
tance at this node. In addition, stray capacitance across
Increased phase delay at the output due to capacitive load-
ing can cause ringing, peaking in the frequency response,
and possible unstable behavior. Use a series resistance,
the R resistor can induce peaking and high frequency
f
ringing. Refer to the lꢂyꢀꢊꢅ cꢀꢆꢈꢇdꢄꢃꢂꢅꢇꢀꢆꢈ section for
additional information regarding high speed layout tech-
niques.
R , between the amplifier and the load to help improve
S
stability and settling performance. Refer to Figure 6.
Overdrive Recovery
An overdrive condition is defined as the point when either
one of the inputs or the output exceed their specified volt-
age range. Overdrive recovery is the time needed for the
amplifier to return to its normal or linear operating point.
The recovery time varies, based on whether the input or
output is overdriven and by how much the range is ex-
ceeded. The CLC1605 Family will typically recover in less
than 10ns from an overdrive condition. Figure 7 shows the
CLC1605 in an overdriven condition.
Input
+
-
Rs
Output
CL
RL
Rf
Rg
Figure 6. Addition of R for Driving
S
Capacitive Loads
Table 2 provides the recommended R for various capaci-
S
tive loads. The recommended R values result in <=0.5dB
peaking in the frequency response. The Frequency Re-
S
1.5
1
6
VIN = 2Vpp
G = 5
4
sponse vs. C plot, on page 5, illustrates the response of
L
the CLC1605 Family.
Input
0.5
0
2
Output
C (pF)
R (Ω)
-3dB BW (MHz)
L
S
0
20
50
20
15
10
5
350
235
170
75
-0.5
-1
-2
-4
-6
100
500
1000
-1.5
3.3
52
0
20
40
60
80 100 120 140 160 180 200
T im e ( n s )
Figure 7. Overdrive Recovery
Power Dissipation
Table 1: Recommended R vs. C
S
L
For a given load capacitance, adjust R to optimize the
S
tradeoff between settling time and bandwidth. In general,
Power dissipation should not be a factor when operating
under the stated 1000 ohm load condition. However, ap-
plications with low impedance, DC coupled loads should
be analyzed to ensure that maximum allowed junction
temperature is not exceeded. Guidelines listed below can
be used to verify that the particular application will not
cause the device to operate beyond it’s intended operat-
ing range.
reducing R will increase bandwidth at the expense of ad-
S
ditional overshoot and ringing.
Parasitic Capacitance on the Inverting Input
Physical connections between components create unin-
tentional or parasitic resistive, capacitive, and inductive
elements.
Parasitic capacitance at the inverting input can be espe-
cially troublesome with high frequency amplifiers. A para-
sitic capacitance on this node will be in parallel with the
Maximum power levels are set by the absolute maximum
junction rating of 150°C. To calculate the junction tem-
perature, the package thermal resistance value Theta
JA
gain setting resistor R . At high frequencies, its imped-
g
(Ө ) is used along with the total die power dissipation.
JA
ance can begin to raise the system gain by making R
appear smaller.
g
T
= T + (Ө × P )
Ambient JA D
Junction
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
16
Data Sheet
2.5
2
Where T
is the temperature of the working environment.
Ambient
SOIC-16
In order to determine P , the power dissipated in the load
D
needs to be subtracted from the total power delivered by
the supplies.
1.5
1
P = P
- P
load
D
supply
Supply power is calculated by the standard power equa-
tion.
0.5
0
SOT23-5
P
= V
× I
supply
supply RMS supply
-40
-20
0
20
40
60
80
V
= V - V
S+ S-
supply
Ambient Temperature (°C)
Power delivered to a purely resistive load is:
Figure 8. Maximum Power Derating
2
P
= ((V
)
)/Rload
eff
load
LOAD RMS
The effective load resistor (Rload ) will need to include
eff
the effect of the feedback network. For instance,
Better thermal ratings can be achieved by maximizing PC
board metallization at the package pins. However, be care-
ful of stray capacitance on the input pins.
Rload in figure 3 would be calculated as:
eff
R || (R + R )
L
f
g
In addition, increased airflow across the package can also
These measurements are basic and are relatively easy to
perform with standard lab equipment. For design purposes
however, prior knowledge of actual signal levels and load
impedance is needed to determine the dissipated power.
help to reduce the effective Ө of the package.
JA
In the event the outputs are momentarily shorted to a low
impedance path, internal circuitry and output metallization
are set to limit and handle up to 65mA of output current.
However, extended duration under these conditions may
not guarantee that the maximum junction temperature
(+150°C) is not exceeded.
Here, P can be found from
D
P = P
+ P
- P
D
Quiescent
Dynamic Load
Quiescent power can be derived from the specified I val-
S
ues along with known supply voltage, V
. Load power
Supply
Layout Considerations
can be calculated as above with the desired signal ampli-
tudes using:
General layout and supply bypassing play major roles in
high frequency performance. CaDeKa has evaluation
boards to use as a guide for high frequency layout and as
aid in device testing and characterization. Follow the steps
below as a basis for high frequency layout:
(V
)
= V
/ √2
LOAD RMS
PEAK
( I
)
= ( V
)
/ Rload
LOAD RMS
LOAD RMS eff
The dynamic power is focused primarily within the output
stage driving the load. This value can be calculated as:
• Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
P
= (V - V
)
× ( I )
LOAD RMS
DYNAMIC
S+
LOAD RMS
• Place the 6.8µF capacitor within 0.75 inches of the power pin
• Place the 0.1µF capacitor within 0.1 inches of the power pin
Assuming the load is referenced in the middle of the power
rails or V /2.
supply
• Remove the ground plane under and around the part,
especially near the input and output pins to reduce para-
sitic capacitance
Figure 8 shows the maximum safe power dissipation in
the package vs. the ambient temperature for the available
packages.
• Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more in-
formation.
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
17
Data Sheet
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of these devices:
Evaluation Board #
CEB002
CEB013
Products
CLC1605
CLC3605
Evaluation Board Schematics
Evaluation board schematics and layouts are shown in Fig-
ures 9-14. These evaluation boards are built for dual- sup-
ply operation. Follow these steps to use the board in a
single-supply application:
Figure 10. CEB002 Top View
1. Short -Vs to ground.
2. Use C3 and C4, if the -V pin of the amplifier is not
S
directly connected to the ground plane.
Figure 11. CEB002 Bottom View
Figure 9. CEB002 Schematic
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
18
Data Sheet
DIS1
IN1
16
2
1
15
12
10
RIN1
RIN2
RIN3
RF1
ROUT1
ROUT2
ROUT3
OUT1
OUT2
OUT3
RG1
RG2
RG3
DIS2
IN2
13
5
4
RF2
11,14
3,6
DIS3
IN3
9
7
8
RF3
Figure 14. CEB013 Bottom View
Board Mounting Holes
Figure 12. CEB013 Schematic
Figure 13. CEB013 Top View
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
19
Data Sheet
Mechanical Dimensions
SOT23-5 Package
SOIC-16 Package
For additional information regarding our products, please visit CADEKA at: cadeka.com
caDeKa Hꢄꢂdqꢊꢂꢃꢅꢄꢃꢈ Loveland, Colorado
T: 970.663.5452
T: 877.663.5452 (toll free)
CADEKA, the CADEKA logo design, COMLINEAR, the COMLINEAR logo design, and ARCTIC are trademarks or registered trademarks of
CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies.
CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any
responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in
writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties.
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