CLC2000 [CADEKA]
High Output Current Dual Amplifier; 高输出电流放大器双
| 型号： | CLC2000 |
| 厂家： | 
CADEKA MICROCIRCUITS LLC. |
| 描述： | High Output Current Dual Amplifier |
| 文件： | 总18页 (文件大小：2081K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
Amplify the Human Experience
®
Comlinear CLC2000
High Output Current Dual Amplifier
f e a t u r e s
General Description
nꢀ
9.4V output drive into R = 25
pp
Ω
L
The Comlinear CLC2000 is a dual voltage feedback amplifier that offers
±200mA of output current at 9.4V . The CLC2000 is capable of driving
pp
nꢀ
Using both amplifiers, 18.8V
pp
differential output drive into R = 25
Ω
L
signals to within 1V of the power rails. When connected as a differential line
driver, the dual amplifier drives signals up to 18.8Vpp into a 25Ω load, which
supports the peak upstream power levels for upstream full-rate ADSL CPE
applications.
nꢀ
nꢀ
±200mA @ V = 9.4V
o
pp
0.009%/0.06˚ differential gain/
phase error
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
250MHz -3dB bandwidth at G = 2
510MHz -3dB bandwidth at G = 1
210V/μs slew rate
The Comlinear CLC2000 can operate from single or dual supplies from 5V to
12V. It consumes only 7mA of supply current per channel. The combination
of wide bandwidth, low noise, low distortion, and high output current capabil-
ity makes the CLC2000 ideally suited for Customer Premise ADSL or video line
driving applications.
4.5nV/
√
Hz input voltage noise
Hz input current noise
2.7pA/√
7mA supply current
Fully specified at 5V and 12V supplies
Pb-free SOIC-8 package
Typical Application - ADSL Application
a p p l i c a t i o n s
nꢀ
ADSL PCI modem cards
+Vs
nꢀ
ADSL external modems
nꢀ
Cable drivers
nꢀ
Video line driver
nꢀ
Twisted pair driver/receiver
+
1/2
CLC2000
R
f+
R
=12.5Ω
=12.5Ω
o+
V
o+
1:2
R
g
V
IN
R =100Ω
L
V
OUT
V
o-
R
R
o-
f-
1/2
CLC2000
-
-Vs
Ordering Information
Part Number
CLC2000ISO8X
CLC2000ISO8
Package
SOIC-8
SOIC-8
Pb-Free
Yes
Operating Temperature Range Packaging Method
-40°C to +85°C
-40°C to +85°C
Reel
Rail
Yes
Moisture sensitivity level for all parts is MSL-1.
©2008 CADEKA Microcircuits LLC
www.cadeka.com
Data Sheet
CLC2000 Pin Configuration
1
2
3
4
8
7
+V
S
OUT1
-IN1
OUT2
-IN2
6
5
+IN1
+IN2
-V
S
CLC2000 Pin Assignments
Pin No.
Pin Name
OUT1
-IN1
Description
1
2
3
4
5
6
7
8
Output, channel 1
Negative input, channel 1
Positive input, channel 1
Negative supply
+IN1
-V
S
+IN2
-IN2
Positive input, channel 2
Negative input, channel 2
Output, channel 2
Positive supply
OUT2
+V
S
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
2
Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device should
not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device func-
tion. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating
conditions noted on the tables and plots.
Parameter
Min
0
Max
Unit
Supply Voltage
±7 or 14
V
V
Input Voltage Range
-V -0.5V
s
+V +0.5V
s
Reliability Information
Parameter
Min
-65
Typ
100
Max
Unit
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10s)
Package Thermal Resistance
8-Lead SOIC
150
150
260
°C
°C
°C
°C/W
Notes:
Package thermal resistance (q ), JDEC standard, multi-layer test boards, still air.
JA
ESD Protection
Product
SOIC-8
Human Body Model (HBM)
2.5kV
2kV
Charged Device Model (CDM)
Recommended Operating Conditions
Parameter
Min
Typ
Max
Unit
Operating Temperature Range
Supply Voltage Range
-40
+85
°C
V
±2.5
±6.5
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
3
Data Sheet
Electrical Characteristics
T = 25°C, V = 5V, R = R = 510Ω, R = 100Ω to V /2, G = 2; unless otherwise noted.
A
s
f
g
L
S
symbꢀꢁ
pꢂꢃꢂmꢄꢅꢄꢃ
cꢀꢆdꢇꢅꢇꢀꢆꢈ
Mꢇꢆ
tyꢉ
Mꢂx
uꢆꢇꢅꢈ
Frequency Domain Response
UGBW
BWSS
-3dB Bandwidth
-3dB Bandwidth
G = +1, VOUT = 0.2Vpp, Rf = 0
G = +2, VOUT = 0.2Vpp
G = +2, VOUT = 2Vpp
422
236
68
MHz
MHz
MHz
MHz
BWLS
Large Signal Bandwidth
0.1dB Gain Flatness
BW0.1dB
77
G = +2, VOUT = 0.2Vpp
Time Domain Response
tR, tF
tS
Rise and Fall Time
VOUT = 1V step; (10% to 90%)
VOUT = 2V step
3.7
20
6
ns
ns
Settling Time to 0.1%
Overshoot
OS
SR
VOUT = 0.2V step
%
Slew Rate
VOUT = 2V step
200
V/µs
Distortion/Noise Response
2Vpp, 100KHz, RL = 25Ω
2Vpp, 1MHz, RL = 100Ω
2Vpp, 100KHz, RL = 25Ω
2Vpp, 1MHz, RL = 100Ω
NTSC (3.58MHz), DC-coupled, RL = 150Ω
NTSC (3.58MHz), DC-coupled, RL = 150Ω
> 1MHz
-83
-85
-86
-82
0.01
0.05
4.2
dBc
dBc
HD2
HD3
2nd Harmonic Distortion
dBc
3rd Harmonic Distortion
dBc
DG
DP
en
in
Differential Gain
Differential Phase
Input Voltage Noise
Input Current Noise
Crosstalk
%
°
nV/√Hz
pA/√Hz
dB
> 1MHz
2.7
Channel-to-channel 5MHz
XTALK
-63
DC Performance
VIO
dVIO
IIO
Input Offset Voltage
Average Drift
0.3
0.383
0.2
mV
µV/°C
µA
Input Offset Current
Input Bias Current
Average Drift
Ib
10
µA
dIbni
PSRR
AOL
IS
2.5
nA/°C
dB
Power Supply Rejection Ratio
Open-Loop Gain
DC
81
RL = 25Ω
per channel
76
dB
Supply Current
6.75
mA
Input Characteristics
RIN
CIN
Input Resistance
Non-inverting
2.5
1
MΩ
Input Capacitance
pF
0.4 to
4.6
CMIR
Common Mode Input Range
Common Mode Rejection Ratio
V
CMRR
DC
80
dB
Output Characteristics
Closed Loop, DC
0.01
Ω
RO
Output Resistance
0.95 to
4.05
RL = 25Ω
V
VOUT
Output Voltage Swing
0.75 to
4.25
RL = 1kΩ
V
ISC
Short-Circuit Output Current
VOUT = VS / 2
1000
mA
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
4
Data Sheet
Electrical Characteristics
T = 25°C, V = 12V, R = R = 510Ω, R = 100Ω to V /2, G = 2; unless otherwise noted.
A
s
f
g
L
S
symbꢀꢁ
pꢂꢃꢂmꢄꢅꢄꢃ
cꢀꢆdꢇꢅꢇꢀꢆꢈ
Mꢇꢆ
tyꢉ
Mꢂx
uꢆꢇꢅꢈ
Frequency Domain Response
UGBW
BWSS
-3dB Bandwidth
-3dB Bandwidth
G = +1, VOUT = 0.2Vpp, Rf = 0
G = +2, VOUT = 0.2Vpp
G = +2, VOUT = 4Vpp
510
250
35
MHz
MHz
MHz
MHz
BWLS
Large Signal Bandwidth
0.1dB Gain Flatness
BW0.1dB
32
G = +2, VOUT = 0.2Vpp
Time Domain Response
tR, tF
tS
Rise and Fall Time
VOUT = 4V step; (10% to 90%)
VOUT = 2V step
13.3
20
ns
ns
Settling Time to 0.1%
Overshoot
OS
SR
VOUT = 0.2V step
2
%
Slew Rate
VOUT = 4V step
210
V/µs
Distortion/Noise Response
2Vpp, 100KHz, RL = 25Ω
2Vpp, 1MHz, RL = 100Ω
8.4Vpp, 100KHz, RL = 25Ω
8.4Vpp, 1MHz, RL = 100Ω
2Vpp, 100KHz, RL = 25Ω
2Vpp, 1MHz, RL = 100Ω
8.4Vpp, 100KHz, RL = 25Ω
8.4Vpp, 1MHz, RL = 100Ω
NTSC (3.58MHz), DC-coupled, RL = 150Ω
NTSC (3.58MHz), DC-coupled, RL = 150Ω
> 1MHz
-84
-86
-63
-82
-88
-80
-63
-83
0.009
0.06
4.5
dBc
dBc
HD2
HD3
2nd Harmonic Distortion
dBc
dBc
dBc
dBc
3rd Harmonic Distortion
dBc
dBc
DG
DP
en
in
Differential Gain
Differential Phase
Input Voltage Noise
Input Current Noise
Crosstalk
%
°
nV/√Hz
pA/√Hz
dB
> 1MHz
2.7
Channel-to-channel 5MHz
XTALK
-62
DC Performance
VIO
dVIO
IIO
Input Offset Voltage(1)
-6
-2
0.3
0.383
0.2
10
6
mV
µV/°C
µA
Average Drift
Input Offset Current(1)
Input Bias Current(1)
Average Drift
2
Ib
20
µA
dIbni
PSRR
AOL
IS
2.5
81
nA/°C
dB
Power Supply Rejection Ratio(1)
DC
73
Open-Loop Gain
Supply Current(1)
RL = 25
per channel
76
dB
7
12
mA
Input Characteristics
RIN
CIN
Input Resistance
Non-inverting
2.5
1
MΩ
Input Capacitance
pF
0.6 to
11.4
CMIR
Common Mode Input Range
V
CMRR
Common Mode Rejection Ratio(1)
DC
70
79
dB
Output Characteristics
Closed Loop, DC
0.01
Ω
RO
Output Resistance
1.2 to
10.8
RL = 25Ω (1)
1.5
10.5
V
VOUT
Output Voltage Swing
0.8 to
11.2
RL = 1kΩ
V
ISC
Short-Circuit Output Current
VOUT = VS / 2
1000
mA
nꢀꢅꢄꢈ:
1. 100% tested at 25°C
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
5
Data Sheet
Typical Performance Characteristics
T = 25°C, V = 12V, R = 510Ω, R = 100Ω to V /2, G = 2; unless otherwise noted.
A
s
f
L
S
Non-Inverting Frequency Response
Non-Inverting Frequency Response (V =5V)
S
1
0
2
G = 1
Rf = 0
1
0
-1
G = 1 0
-2
-3
-1
-2
-3
-4
-5
-6
G = 1 0
G = 2
G = 5
G = 2
G = 5
-4
-5
G = 1
Rf = 0
-6
-7
VOUT = 0.2Vpp
VOUT = 0.2Vpp
0.1
1
10
100
1000
0.1
1
10
Frequency (MHz)
100
1000
Frequency (MHz)
Inverting Frequency Response
Inverting Frequency Response (V =5V)
S
1
0
1
0
G = -1
G = -2
G = -1
G = -2
-1
-1
-2
-2
G = -10
G = -10
-3
-3
-4
-4
G = -5
G = -5
-5
-6
-7
-5
-6
VOUT = 0.2Vpp
VOUT = 0.2Vpp
-7
0.1
1
10
100
1000
0.1
1
10
100
1000
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. R
Frequency vs. R (V = 5V)
L S
L
2
1
2
1
RL = 5kΩ
RL = 1kΩ
RL = 5kΩ
RL = 1kΩ
0
0
-1
-2
-3
-4
-1
-2
-3
-4
-5
-6
RL = 150Ω
RL = 150Ω
RL = 50Ω
RL = 50Ω
-5
-6
VOUT = 0.2Vpp
VOUT = 0.2Vpp
RL = 25Ω
RL = 25Ω
0.1
1
10
Frequency (MHz)
100
1000
0.1
1
10
100
1000
Frequency (MHz)
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
6
Data Sheet
Typical Performance Characteristics
T = 25°C, V = 12V, R = 510Ω, R = 100Ω to V /2, G = 2; unless otherwise noted.
A
s
f
L
S
Frequency vs. C
Frequency vs. C (V = 5V)
L
L
S
1
0
1
0
CL = 1000pF
Rs = 5 Ω
CL = 1000pF
Rs = 5 Ω
-1
-2
-3
-4
-5
-6
-1
-2
-3
-4
-5
-6
-7
CL = 500pF
Rs = 6 Ω
CL = 500pF
Rs = 6 Ω
CL = 100pF
Rs = 1 3 Ω
CL = 100pF
Rs = 1 3 Ω
CL = 50pF
Rs = 2 0 Ω
CL = 50pF
Rs = 2 5 Ω
CL = 10pF
Rs = 3 0 Ω
CL = 10pF
Rs = 4 5 Ω
VOUT = 0.2Vpp
VOUT = 0.2Vpp
-7
0.1
1
10
100
1000
0.1
1
10
100
1000
Frequency (MHz)
Frequency (MHz)
Recommended R vs. C
Recommended R vs. C (V = 5V)
S
L
S
L
S
32
30
28
26
24
22
20
18
16
14
12
10
8
45
40
35
30
25
20
15
10
5
6
4
2
0
VOUT = 0.2Vpp
RS optimized for <1dB peaking
VOUT = 0.2Vpp
RS optimized for <1dB peaking
0
10
100
CL (pf)
1000
10
100
CL (pF)
1000
Frequency Response vs. V
Frequency Response vs. V (V = 5V)
OUT S
OUT
1
0
1
0
VOUT = 1Vpp
VOUT = 1Vpp
-1
-1
-2
-3
-4
-5
-6
-7
VOUT = 5Vpp
VOUT = 2Vpp
VOUT = 2Vpp
-2
-3
-4
-5
-6
-7
VOUT = 4Vpp
VOUT = 3Vpp
0.1
1
10
Frequency (MHz)
100
1000
0.1
1
10
100
1000
Frequency (MHz)
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
7
Data Sheet
Typical Performance Characteristics - Continued
T = 25°C, V = 12V, R = 510Ω, R = 100Ω to V /2, G = 2; unless otherwise noted.
A
s
f
L
S
Frequency Response vs. Temperature
Frequency vs. Temperature (V = 5V)
S
1
0
1
0
- 40degC
+ 25degC
+ 85degC
-1
-2
-3
-4
-5
-6
-7
-1
-2
-3
-4
-5
-6
-7
+ 25degC
- 40degC
+ 85degC
VOUT = 2V
VOUT = .2V
pp
pp
0.1
1
10
100
1000
0.1
1
10
Frequency (MHz)
100
1000
Frequency (MHz)
-3dB Bandwidth vs. Output Voltage
-3dB Bandwidth vs. Output Voltage (V =5V)
S
275
250
225
200
175
150
125
100
75
250
225
200
175
150
125
100
75
50
50
25
25
0
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOUT (VPP
)
VOUT (VPP)
Open Loop Transimpendance Gain/Phase vs. Frequency
Input Voltage Noise
50
80
70
60
50
40
30
20
10
0
0
-20
Gain
40
30
20
10
0
-40
-60
-80
Phase
-100
-120
-140
-160
-180
-200
-10
-20
1k
10k
100k
1M
10M 100M
1G
0.0001 0.001 0.01
0.1
1
10
100
Frequency (Hz)
Frequency (MHz)
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
8
Data Sheet
Typical Performance Characteristics - Continued
T = 25°C, V = 12V, R = 510Ω, R = 100Ω to V /2, G = 2; unless otherwise noted.
A
s
f
L
S
2nd Harmonic Distortion vs. R
3rd Harmonic Distortion vs. R
L
L
-20
-30
-40
-20
-30
-40
RL = 25Ω
RL = 25Ω
RL = 100Ω
RL = 100Ω
-50
-60
-50
-60
-70
-70
RL = 1kΩ
RL = 1kΩ
-80
-80
-90
-90
VOUT = 2Vpp
VOUT = 2Vpp
-100
-100
0
5
10
Frequency (MHz)
15
20
0
5
10
Frequency (MHz)
15
20
2nd Harmonic Distortion vs. V
3rd Harmonic Distortion vs. V
OUT
OUT
-20
-30
-40
-20
-30
-40
-50
-50
10MHz
10MHz
-60
-70
-80
-90
-60
-70
5MHz
5MHz
-80
-90
1MHz
1MHz
-100
-100
0.5
0.75
1
1.25 1.5
1.75
2
2.25 2.5
2.75
3
0.5
0.75
1
1.25 1.5
1.75
2
2.25 2.5
2.75
3
Output Amplitude (Vpp
)
Output Amplitude (Vpp
)
Differential Gain & Phase AC Coupled
Differential Gain & Phase DC Coupled
0.01
0.06
0.05
0.04
0.03
0.02
0.01
0
RL = 150Ω
AC coupled into 220µF
0.0075
0.005
0.0025
0
DP
DG
-0.0025
-0.005
-0.0075
-0.01
DG
-0.01
DP
RL = 150Ω
DC coupled
-0.02
-0.03
VOUT = 2Vpp
-0 .7
-0.5
-0.3
-0.1
0.1
0.3
0.5
0 .7
-0 .7
-0.5
-0.3
-0.1
0.1
0.3
0.5
0 .7
I n p u t Vo l t a g e ( V )
I n p u t Vo l t a g e ( V )
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
9
Data Sheet
Typical Performance Characteristics - Continued
T = 25°C, V = 12V, R = 510Ω, R = 100Ω to V /2, G = 2; unless otherwise noted.
A
s
f
L
S
2nd Harmonic Distortion vs. R (V =5V)
3rd Harmonic Distortion vs. R (V =5V)
L
S
L
S
-20
-30
-40
-50
-60
-70
-80
-90
-100
-20
-30
-40
-50
-60
-70
-80
-90
-100
RL = 25Ω
RL = 25Ω
RL = 100Ω
RL = 100Ω
RL = 1kΩ
RL = 1kΩ
VOUT = 2Vpp
VOUT = 2Vpp
0
5
10
15
20
0
5
10
15
20
Frequency (MHz)
Frequency (MHz)
2nd Harmonic Distortion vs. V
(V =5V)
S
3rd Harmonic Distortion vs. V
(V =5V)
OUT S
OUT
-45
-50
-45
-50
10MHz
-55
-55
10MHz
-60
-65
-70
-75
-80
-60
-65
-70
-75
5MHz
5MHz
1MHz
-80
1MHz
-85
-90
-85
-90
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
2.75
3
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
2.75
3
Output Amplitude (Vpp
)
Output Amplitude (Vpp
)
Differential Gain & Phase AC Coupled (V =5V)
Differential Gain & Phase DC Coupled (V =5V)
S
S
0.01
0.04
RL = 150Ω
AC coupled into 220µF
RL = 150Ω
DC coupled
0.0075
0.005
0.0025
0
DG
0.03
0.02
DG
0.01
-0.0025
-0.005
-0.0075
-0.01
0
DP
-0.01
DP
-0.02
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
-0.4
-0.2
0
0.2
0.4
I n p u t Vo l t a g e ( V )
I n p u t Vo l t a g e ( V )
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
10
Data Sheet
Typical Performance Characteristics - Continued
T = 25°C, V = 12V, R = 510Ω, R = 100Ω to V /2, G = 2; unless otherwise noted.
A
s
f
L
S
Small Signal Pulse Response
Large Signal Pulse Response
6.15
9.0
VOUT = 4Vpp
6.1
6.05
6
8.0
7 .0
6.0
5.0
4.0
3.0
VOUT = 2Vpp
5.95
5.9
5.85
0
20
40
60
80
100 120 140 160 180 200
T im e ( n s )
0
20
40
60
80
100
120
140
160
180
200
T im e ( n s )
Small Signal Pulse Response (V =5V)
Large Signal Pulse Response (V =5V)
S
S
2.65
2.60
2.55
2.50
2.45
2.40
2.35
4.5
VOUT = 3Vpp
4.0
3.5
VOUT = 2Vpp
3.0
2.5
2.0
1.5
1.0
0.5
0
20
40
60
80
100 120 140 160 180 200
T im e ( n s )
0
20
40
60
80
100
120
140
160
180
200
T im e ( n s )
Crosstalk vs. Frequency
Crosstalk vs. Frequency (V =5V)
S
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
VOUT = 2Vpp
VOUT = 2Vpp
-90
0.1
1
10
100
0.1
1
10
100
Frequency (MHz)
Frequency (MHz)
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
11
Data Sheet
Typical Performance Characteristics - Continued
T = 25°C, V = 12V, R = 510Ω, R = 100Ω to V /2, G = 2; unless otherwise noted.
A
s
f
L
S
Closed Loop Output Impedance vs. Frequency
CMRR vs. Frequency
10
-10
-20
-30
-40
-50
-60
-70
-80
-90
1
0.1
0.01
0.001
1k
10k
100k
1M
10M
10
100
1k
10k 100k 1M 10M 100M
100M
Frequency (Hz)
Frequency (Hz)
PSRR vs. Frequency
Input Voltage vs. Output Current
-30
-40
-50
-60
-70
-80
-90
1.25
1.00
0.75
IOUT+
0.50
0.25
0.00
-0.25
-0.50
IOUT-
-0.75
RL = 2.668Ω
G = -1
VS = ±6V
-1.00
-1.25
-100
1.0
1.5
2.0
2.5
3.0
VIN (±V)
3.5
4.0
4.5
5.0
10
100
1k
10k 100k 1M 10M 100M
Frequency (Hz)
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
12
Data Sheet
Two decoupling capacitors should be placed on each pow-
er pin with connection to a local PC board ground plane.
A large, usually tantalum, 10μF to 47μF capacitor is re-
quired to provide good decoupling for lower frequency
signals and to provide current for fast, large signal chang-
es at the CLC2000 outputs. It should be within 0.25” of
the pin. A secondary smaller 0.1μF MLCC capacitor should
located within 0.125” to reject higher frequency noise on
the power line.
Application Information
Basic Operation
Figures 1 and 2 illustrate typical circuit configurations for
non-inverting, inverting, and unity gain topologies for dual
supply applications. They show the recommended bypass
capacitor values and overall closed loop gain equations.
+Vs
6.8μF
Power Dissipation
Power dissipation is an important consideration in applica-
tions with low impedance DC, coupled loads. Guidelines
listed below can be used to verify that the particular ap-
plication will not cause the device to operate beyond its
intended operating range. Calculations below relate to a
single amplifier. For the CLC2000, both amplifiers power
contribution needs to be added for the total power dis-
sipation.
0.1μF
Input
+
-
Output
RL
0.1μF
6.8μF
Rf
Rg
G = 1 + (Rf/Rg)
-Vs
Maximum power levels are set by the absolute maximum
junction rating of 150°C. To calculate the junction tem-
Figure 1. Typical Non-Inverting Gain Circuit
perature, the package thermal resistance value Theta
JA
+Vs
6.8μF
(Ө ) is used along with the total die power dissipation.
JA
T
= T + (Ө × P )
Ambient JA D
Junction
R1
0.1μF
+
Output
Rg
Where T
ment.
is the temperature of the working environ-
Ambient
Input
-
RL
0.1μF
Rf
In order to determine P , the power dissipated in the load
D
needs to be subtracted from the total power delivered by
the supplies.
6.8μF
G = - (Rf/Rg)
-Vs
For optimum input offset
voltage set R1 = Rf || Rg
P = P
- P
load
D
supply
Figure 2. Typical Inverting Gain Circuit
Supply power is calculated by the standard power equa-
tion.
Power Supply and Decoupling
P
= V × I
supply (RMS supply)
supply
The CLC2000 can be powered with a low noise supply
anywhere in the range from +5V to +13V. Ensure ad-
equate metal connections to power pins in the PC board
layout with careful attention paid to decoupling the power
supply.
V
= V
- V
(S-)
supply
(S+)
Power delivered to a purely resistive load is:
2
P
= ((V
)
) / Rload
eff
load
LOAD RMS
The effective load resistor will need to include the effect
High quality capacitors with low equivalent series resis-
tance (ESR) such as multilayer ceramic capacitors (MLCC)
should be used to minimize supply voltage ripple and
power dissipation.
of the feedback network. For instance,
Rload in figure 1 would be calculated as:
eff
R || (R + R )
L
f
g
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
13
Data Sheet
These measurements are basic and are relatively easy to
perform with standard lab equipment. For design purposes
however, prior knowledge of actual signal levels and load
impedance is needed to determine the dissipated power.
In the event of a short circuit condition, the CLC2000 has
circuitry to limit output drive capability to ±1000mA. This
will only protect against a momentary event. Extended
duration under these conditions will cause junction tem-
peratures to exceed 150°C. Due to internal metallization
constraints, continuous output current should be limited
to ±100mA.
Here, P can be found from
D
P = P
+ P
- P
D
Quiescent
Dynamic Load
Quiescent power can be derived from the specified I val-
S
ues along with known supply voltage, V
. Load power
Supply
can be calculated as above with the desired signal ampli-
tudes using:
Driving Capacitive Loads
Increased phase delay at the output due to capacitive load-
ing can cause ringing, peaking in the frequency response,
and possible unstable behavior. Use a series resistance,
(V
)
= V
/ √2
LOAD RMS
PEAK
( I
)
= (V
)
/ Rload
LOAD RMS
LOAD RMS eff
R , between the amplifier and the load to help improve
S
stability and settling performance. Refer to Figure 4.
The dynamic power is focused primarily within the output
stage driving the load. This value can be calculated as:
Input
+
-
Rs
Output
P
= (V - V
)
× (I )
LOAD RMS
DYNAMIC
S+
LOAD RMS
CL
RL
Rf
Assuming the load is referenced in the middle of the pow-
er rails or V /2.
supply
Rg
Figure 3 shows the maximum safe power dissipation in
the package vs. the ambient temperature for the 8 Lead
SOIC packages.
Figure 4. Addition of R for Driving
S
Capacitive Loads
Table 1 provides the recommended R for various capaci-
S
2.5
tive loads. The recommended R values result in <=1dB
S
peaking in the frequency response. The Frequency Re-
2
sponse vs. C plots, on page 7, illustrates the response of
L
the CLC2000.
1.5
C (pF)
L
R (Ω)
S
-3dB BW (MHz)
SOIC-8
1
10
20
40
24.5
20
275
250
175
135
75
0.5
0
50
100
500
1000
13.5
6
-40
-20
0
20
40
60
80
Ambient Temperature (°C)
5
45
Figure 3. Maximum Power Derating
Table 1: Recommended R vs. C
S
L
Better thermal ratings can be achieved by maximizing
PC board metallization at the package pins. However, be
careful of stray capacitance on the input pins.
For a given load capacitance, adjust R to optimize the
tradeoff between settling time and bandwidth. In general,
S
reducing R will increase bandwidth at the expense of ad-
S
ditional overshoot and ringing.
In addition, increased airflow across the package can also
help to reduce the effective Ө of the package.
JA
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
14
Data Sheet
Overdrive Recovery
+Vs
An overdrive condition is defined as the point when either
one of the inputs or the output exceed their specified volt-
age range. Overdrive recovery is the time needed for the
amplifier to return to its normal or linear operating point.
The recovery time varies, based on whether the input or
output is overdriven and by how much the range is ex-
ceeded. The CLC2000 will typically recover in less than
40ns from an overdrive condition. Figure 5 shows the
CLC2000 in an overdriven condition.
+
1/2
CLC2000
R
f+
R
=12.5Ω
=12.5Ω
o+
V
o+
1:2
R
g
V
R =100Ω
L
V
OUT
IN
V
o-
R
R
o-
f-
3
2
6
VIN = 2.5Vpp
G = 5
1/2
CLC2000
-
4
Input
1
2
0
0
-Vs
-1
-2
-3
-2
-4
-6
Figure 6: Typical Differential Transmission Line Driver
Output
80
For any transmission requirement, the fundamental de-
sign parameters needed are the effective impedance of
the transmission line, the power required at the load, and
knowledge concerning the content of the transmitted sig-
nal. The basic design of such a circuit is briefly outlined
below, using the ADSL parameters as a guideline.
0
20
40
60
100 120 140 160 180 200
T im e ( n s )
Figure 5. Overdrive Recovery
Using the CLC2000 as a Differential Line Driver
Data transmission techniques, such as ADSL, utilize ampli-
tude modulation techniques which are sensitive to output
clipping. A signal’s PEAK to RMS ratio, or Crest Factor (CF),
can be used to determine the adequate peak signal levels
to insure fidelity for a given signal.
The combination of good large signal bandwidth and high
output drive capability makes the CLC2000 well suited for
low impedance line driver applications, such as the up-
stream data path for a ADSL CPE modem. The dual chan-
nel configuration of the CLC2000 provides better channel
matching than a typical single channel device, resulting For an ADSL system, the signal consists of 256 indepen-
in better overall performance in differential applications. dent frequencies with varying amplitudes. This results in
When configured as a differential amplifier as in figure 6, it a noise-like signal with a crest factor of about 5.3. If the
can easily deliver the 13dBm to a standard 100Ω twisted- driver does not have enough swing to handle the signal
pair CAT3 or CAT5 cable telephone network, as required in peaks, clipping will occur and amplitude modulated infor-
a ADSL CPE application.
mation can be corrupted, causing degradation in the sig-
nals Bit Error Rate.
Differential circuits have several advantages over single-
ended configurations. These include better rejection of To determine the required swing, first use the specified
common mode signals and improvement of power-supply load impedance to convert the RMS power to an RMS volt-
rejection. The use of differential signaling also improves age. Then, multiply the RMS voltage by the crest factor to
overall dynamic performance. Total harmonic distortion get the peak values. For example 13dBm, as referenced to
(THD) is reduced by the suppression of even signal har- 1mW, is ~20mW. 20mW into the 100Ω CAT5 impedance
monics and the larger signal swings allow for an improved yields a RMS voltage of 1.413 VRMS . Using the ADSL crest
signal to noise ratio (SNR).
factor of 5.3 yields ~ ±7.5V peak signals.
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
15
Data Sheet
Line coupling through a 1:2 transformer is used to realize Evalutaion Board Schematics
these levels. Standard back termination is used to match
Evaluation board schematics and layouts are shown in Fig-
the characteristic 100Ω impedance of the CAT5 cable. For
proper power transfer, this requires an effective 1:4 im-
pedance match of 25Ω at the inputs of the transformer. To
account for the voltage drop of the impedance matching
resistors, the signal levels at the output of the amplifier
need to be doubled. Thus each amplifier will swing ±3.75V
about a centered common mode output voltage.
ures 7-9. These evaluation boards are built for dual- sup-
ply operation. Follow these steps to use the board in a
single-supply application:
1. Short -Vs to ground.
2. Use C3 and C4, if the -V pin of the amplifier is not
S
directly connected to the ground plane.
In general, the CLC2000 can be used in any application
where an economical and local hardwired connection is
needed. For example, routing analog or digital video infor-
mation for a in-cabin entertainment system. Networking of
a local surveillance system also could be considered.
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. CADEKA has evaluation
boards to use as a guide for high frequency layout and as
aid in device testing and characterization. Follow the steps
below as a basis for high frequency layout:
• Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
• Place the 6.8µF capacitor within 0.75 inches of the power pin
• Place the 0.1µF capacitor within 0.1 inches of the power pin
• Remove the ground plane under and around the part,
especially near the input and output pins to reduce para-
sitic capacitance
Figure 7. CEB006 Schematic
• Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more in-
formation.
Evaluation Board Information
The following evaluation board is available to aid in the
testing and layout of this device:
Evaluation Board #
CEB006
Products
CLC2000
Figure 8. CEB006 Top View
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
16
Data Sheet
Figure 9. CEB006 Bottom View
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
17
Data Sheet
Mechanical Dimensions
SOIC-8 Package
For additional information regarding our products, please visit CADEKA at: cadeka.com
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CADEKA, the CADEKA logo design, and Comlinear and the Comlinear logo design, are trademarks or registered trademarks of CADEKA
Microcircuits LLC. All other brand and product names may be trademarks of their respective companies.
CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any
responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in
writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties.
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Copyright ©2008 by CADEKA Microcircuits LLC. All rights reserved.
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