CLC2005ISO8 [CADEKA]
Dual, Low Cost, +2.7V to 5.5V, 260MHz Rail-to-Rail Amplifier; 双通道，低成本， + 2.7V至5.5V ，为260MHz ，轨到轨放大器
| 型号： | CLC2005ISO8 |
| 厂家： | 
CADEKA MICROCIRCUITS LLC. |
| 描述： | Dual, Low Cost, +2.7V to 5.5V, 260MHz Rail-to-Rail Amplifier |
| 文件： | 总13页 (文件大小：2647K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
Amplify the Human Experience
®
Comlinear CLC2005
Dual, Low Cost, +2.7V to 5.5V, 260MHz
Rail-to-Rail Amplifier
F E A T U R E S
General Description
nꢀ
260MHz bandwidth
The Comlinear CLC2005 is a dual, low cost, voltage feedback amplifier.
This amplifier is designed to operate on +2.7V,+5V, or ±2.5V supplies. The
input voltage range extends 300mV below the negative rail and 1.2V below
the positive rail. The CLC2005 offers superior dynamic performance
with a 260MHz small signal bandwidth and 145V/μs slew rate. The
combination of low power, high output current drive, and rail-to-rail
performance make the Comlinear CLC2005 well suited for battery-pow-
ered communication/computing systems. The combination of low cost and
high performance make the Comlinear CLC2005 suitable for high volume
applications in both consumer and industrial applications such as wireless
phones, scanners, and color copiers.
nꢀ
nꢀ
Fully specified at +2.7V and +5V supplies
Output voltage range:
0.036V to 4.953V; Vs = +5; RL = 2kΩ
nꢀ
Input voltage range:
-0.3V to +3.8V; Vs = +5
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
145V/μs slew rate
4.2mA supply current per amplifier
±55mA linear output current
±85mA short circuit current
Directly replaces AD8052 and AD8042 in
single supply applications
nꢀ
Pb-free SOIC-8 package
A P P L I C A T I O N S
Output Swing
nꢀ
A/D driver
2.7
nꢀ
Active filters
nꢀ
CCD imaging systems
nꢀ
CD/DVD ROM
nꢀ
Coaxial cable drivers
nꢀ
High capacitive load driver
nꢀ
Portable/battery-powered applications
nꢀ
Twisted pair driver
V
R
= +2.7V
= 2kΩ
s
nꢀ
Video driver
L
G = -1
0
Time (0.5μs/div)
Ordering Information
Part Number
CLC2005ISO8
CLC2005ISO8X
Package
SOIC-8
SOIC-8
Pb-Free
Yes
Operating Temperature Range Packaging Method
-40°C to +85°C
-40°C to +85°C
Rail
Yes
Reel
Moisture sensitivity level for all parts is MSL-1.
©2007-2009 CADEKA Microcircuits LLC
www.cadeka.com
Data Sheet
Pin Configuration
Pin Assignments
SOIC-8
SOIC-8
Pin No.
Pin Name
Description
OUT1
-IN1
+IN1
-Vs
1
2
3
4
8
7
6
5
+Vs
1
2
3
4
5
6
7
8
OUT1
-IN1
Output, channel 1
Negative input, channel 1
Positive input, channel 1
Negative supply
OUT2
-IN2
+IN2
-
+
+IN1
-
-V
S
+
+IN2
-IN2
Positive input, channel 2
Negative input, channel 2
Output, channel 2
Positive supply
OUT2
+V
S
©2004-2009 CADEKA Microcircuits LLC
www.cadeka.com
2
Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device
should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper
device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect
the operating conditions noted on the tables and plots.
Parameter
Min
0
Max
+6
Unit
Supply Voltage
V
V
Input Voltage Range
-V -0.5V
s
+V +0.5V
s
Reliability Information
Parameter
Min
-65
Typ
100
Max
Unit
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10s)
Package Thermal Resistance
8-Lead SOIC
175
150
260
°C
°C
°C
°C/W
Notes:
Package thermal resistance (θ ), JDEC standard, multi-layer test boards, still air.
JA
ESD Protection
Product
SOIC-8
Human Body Model (HBM)
2.5kV
2kV
Charged Device Model (CDM)
Recommended Operating Conditions
Parameter
Min
-40
Typ
Max
+85
Unit
°C
Operating Temperature Range
©2004-2009 CADEKA Microcircuits LLC
www.cadeka.com
3
Data Sheet
Electrical Characteristics
V = +2.7V, G = 2, R = 2kΩ, R = 2kΩ to V /2; unless otherwise noted.
s
f
L
s
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Frequency Domain Response
UGBW
BWSS
BWLS
-3dB Bandwidth(2)
G = +1, VOUT = 0.05Vpp
G = +2, VOUT = 0.2Vpp
G = +2, VOUT = 2Vpp
215
85
MHz
MHz
MHz
MHz
-3dB Bandwidth
Large Signal Bandwidth
Gain Bandwidth Product
36
GBWP
86
Time Domain Response
tR, tF
tS
Rise and Fall Time(2)
VOUT = 0.2V step
VOUT = 1V step
VOUT = 0.2V step
2.7V step, G = -1
3.7
40
9
ns
ns
Settling Time to 0.1%
Overshoot
OS
SR
%
Slew Rate
130
V/μs
Distortion/Noise Response
1Vpp, 5MHz
1Vpp, 5MHz
1Vpp, 5MHz
> 1MHz
79
82
77
16
1.3
65
dBc
dBc
HD2
2nd Harmonic Distortion(2)
HD3
3rd Harmonic Distortion(2)
dB
en
in
Input Voltage Noise
Input Current Noise
Crosstalk(1)
nV/√Hz
pA/√Hz
dB
> 1MHz
10MHz
XTALK
DC Performance
VIO
dVIO
Ib
Input Offset Voltage
Average Drift
-1.6
10
3
mV
μV/°C
μA
Input Bias Current
Average Drift
dIb
IIO
7
nA/°C
μA
Input Offset Current
Power Supply Rejection Ratio(1)
Open-Loop Gain
0.1
57
75
3.9
PSRR
AOL
IS
DC
52
dB
dB
Quiescent Current
Per Amplifier
mA
Input Characteristics
RIN
Input Resistance
4.3
1.8
MΩ
pF
V
CIN
Input Capacitance
CMIR
CMRR
Common Mode Input Range
Common Mode Rejection Ratio
-0.3to1.5
87
DC, Vcm = 0V to Vs -1.5
dB
Output Characteristics
0.023 to
2.66
V
RL = 10kΩ to Vs/2
RL = 2kΩ to Vs/2
RL = 150Ω to Vs/2
0.025 to
2.653
VOUT
Output Voltage Swing
V
V
0.065 to
2.55
±55
±50
±85
2.7
mA
mA
mA
V
IOUT
Output Current
-40°C to +85°C
ISC
Vs
Short-Circuit Output Current
Power Supply Operating Range
2.5
5.5
Notes:
1. 100% tested at 25°C.
2. R = 1kΩ was used for optimal performance. (For G = +1, R = 0).
f
f
©2004-2009 CADEKA Microcircuits LLC
www.cadeka.com
4
Data Sheet
Electrical Characteristics
V = 5V, G = 2, R = 2kΩ, R = 2kΩ to V /2; unless otherwise noted.
s
f
L
s
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Frequency Domain Response
UGBW
BWSS
BWLS
-3dB Bandwidth(2)
G = +1, VOUT = 0.05Vpp
G = +2, VOUT = 0.2Vpp
G = +2, VOUT = 2Vpp
260
90
MHz
MHz
MHz
MHz
-3dB Bandwidth
Large Signal Bandwidth
Gain Bandwidth Product
40
GBWP
90
Time Domain Response
tR, tF
tS
Rise and Fall Time(2)
VOUT = 0.2V step
VOUT = 2V step
VOUT = 0.2V step
5V step, G = -1
3.6
40
7
ns
ns
Settling Time to 0.1%
Overshoot
OS
SR
%
Slew Rate
145
V/μs
Distortion/Noise Response
2Vpp, 5MHz
71
78
dBc
HD2
2nd Harmonic Distortion(2)
2Vpp, 5MHz
dBc
HD3
3rd Harmonic Distortion(2)
Differential Gain
2Vpp, 5MHz
70
dB
NTSC (3.85MHz), AC-Coupled, RL = 150Ω
NTSC (3.85MHz), DC-Coupled, RL = 150Ω
NTSC (3.85MHz), AC-Coupled, RL = 150Ω
NTSC (3.85MHz), DC-Coupled, RL = 150Ω
>1MHz
0.06
0.08
0.07
0.06
16
%
DG
DP
%
°
°
Differential Phase
en
in
Input Voltage Noise
Input Current Noise
Crosstalk(2)
nV/√Hz
pA/√Hz
dB
>1MHz
1.3
62
10MHz
XTALK
DC Performance
VIO
dVIO
Ib
Input Offset Voltage(1)
-8
-8
1.4
10
3
+8
+8
mV
μV/°C
μA
Average Drift
Input Bias Current(1)
Average Drift
dIb
IIO
7
nA/°C
μA
Input Offset Current(1)
Power Supply Rejection Ratio(1)
Open-Loop Gain(1)
Quiescent Current(1)
-0.8
52
0.1
57
78
4.2
+0.8
PSRR
AOL
IS
DC
dB
68
dB
Per Amplifier
5.2
mA
Input Characteristics
RIN
Input Resistance
4.3
1.8
MΩ
pF
V
CIN
Input Capacitance
CMIR
CMRR
Common Mode Input Range
Common Mode Rejection Ratio(1)
-0.3to3.8
87
DC, Vcm = 0V to Vs -1.5
72
dB
Output Characteristics
0.027 to
4.97
V
RL = 10kΩ to Vs/2
RL = 2kΩ to Vs/2
RL = 150Ω to Vs/2(1)
0.036 to
4.953
VOUT
Output Voltage Swing
V
V
0.12 to
4.8
0.3
2.5
4.625
5.5
±55
±50
±85
5
mA
mA
mA
V
IOUT
Output Current
-40°C to +85°C
ISC
Vs
Short-Circuit Output Current
Power Supply Operating Range
Notes:
1. 100% tested at 25°C.
2. R = 1kΩ was used for optimal performance. (For G = +1, R = 0).
f
f
©2004-2009 CADEKA Microcircuits LLC
www.cadeka.com
5
Data Sheet
Typical Performance Characteristics
V = +5V, G = 2, R = 2kΩ, R = 2kΩ to V /2; unless otherwise noted.
s
f
L
s
Non-Inverting Frequency Response V = +5V
Inverting Frequency Response V = +5V
s
s
G = -1
G = 1
f
R = 2kΩ
f
R = 0
G = 2
R = 1kΩ
f
G = -10
f
R = 2kΩ
G = 10
R = 2kΩ
f
G = -5
R = 2kΩ
f
G = 5
R = 2kΩ
f
G = -2
R = 2kΩ
f
0.1
1
0.1
1
10
100
10
100
Frequency (MHz)
Frequency (MHz)
Non-Inverting Frequency Response V = +2.7V
Inverting Frequency Response V = +2.7V
s
s
G = -1
G = 1
R = 0
f
R = 2kΩ
f
G = 2
R = 1kΩ
f
G = -10
R = 2kΩ
f
G = 10
R = 2kΩ
f
G = -5
R = 2kΩ
f
G = 5
R = 2kΩ
f
G = -2
R = 2kΩ
f
0.1
1
10
100
0.1
1
10
100
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. C
Large Signal Frequency Response
L
C
= 100pF
L
R
= 25Ω
V
V
= 1V
= 2V
s
o
pp
C
R
= 50pF
= 33Ω
L
s
o
pp
C
R
= 20pF
= 20Ω
L
s
+
-
Rs
CL
RL
1kΩ
C
= 10pF
L
R
= 0Ω
1kΩ
s
0.1
1
0.1
1
10
100
10
100
Frequency (MHz)
Frequency (MHz)
©2004-2009 CADEKA Microcircuits LLC
www.cadeka.com
6
Data Sheet
Typical Performance Characteristics
V = +5V, G = 2, R = 2kΩ, R = 2kΩ to V /2; unless otherwise noted.
s
f
L
s
Frequency Response vs. Temperature
Input Voltage Noise
100
90
80
70
60
50
40
30
20
10
0
1
10
1k
10k
100
100k
1M
Frequency (Hz)
Frequency (MHz)
2nd & 3rd Harmonic Distortion; V = +5V
2nd & 3rd Harmonic Distortion; V = +2.7V
s
s
-20
-30
-40
-50
-60
-70
-80
-90
-20
-30
-40
-50
-60
-70
-80
-90
V
= 2V
V = 1V
o pp
o
pp
R = 1kΩ
3rd
R = 1kΩ
f
f
R
= 150Ω
L
2nd
3rd
R
= 150Ω
R
= 150Ω
L
L
2nd
= 150Ω
R
L
2nd
= 2kΩ
2nd
R = 2kΩ
L
R
L
3rd
3rd
R = 2kΩ
L
R
= 2kΩ
L
0
5
0
10
15
20
5
10
15
20
Frequency (MHz)
Frequency (MHz)
2nd Harmonic Distortion vs. V
3rd Harmonic Distortion vs. V
o
o
-20
-30
-40
-50
-60
-70
-80
-90
-20
-30
-40
-50
-60
-70
-80
-90
R = 1kΩ
f
R = 1kΩ
f
20MHz
10MHz
20MHz
10MHz
5MHz
2MHz
5MHz
2MHz
0.5
1.0
1.5
2.0
2.5
0.5
1.0
1.5
2.0
2.5
Output Amplitude (V
)
Output Amplitude (V )
pp
pp
©2004-2009 CADEKA Microcircuits LLC
www.cadeka.com
7
Data Sheet
Typical Performance Characteristics
V = +5V, G = 2, R = 2kΩ, R = 2kΩ to V /2; unless otherwise noted.
s
f
L
s
PSRR
CMRR
0
-10
-20
-30
-40
-50
-60
-70
-40
-50
-60
-70
-80
-90
0.01
0.1
1k
0.01
1.0
10
100
0.1
1
100
10
Frequency (MHz)
Frequency (MHz)
Open Loop Gain & Phase vs. Frequency
Output Current
0.8
0.6
0.4
0.2
0
80
70
60
50
40
30
20
10
0
|Gain|
Linear output current ±55mA
Short circuit current ±85mA
0
-0.2
-0.4
Phase
-45
-90
-0.6
-0.8
-10
-20
-135
-180
0.01
0.1
1
10
100
-100
-50
0
50
100
Frequency (MHz)
Output Current (mA)
Small Signal Pulse Response V = +5V
Small Signal Pulse Response V = +2.7V
s
s
R = 1kΩ
R = 1kΩ
f
f
Time (20ns/div)
Time (20ns/div)
©2004-2009 CADEKA Microcircuits LLC
www.cadeka.com
8
Data Sheet
Typical Performance Characteristics
V = +5V, G = 2, R = 2kΩ, R = 2kΩ to V /2; unless otherwise noted.
s
f
L
s
Large Signal Pulse Response V = +5V
Output Swing
s
2.7
R = 1kΩ
f
V
= +2.7V
s
R
= 2kΩ
L
G = -1
0
Time (20ns/div)
Time (0.5μs/div)
Channel Matching V = +5V
s
R = 1kΩ
f
L
R
= 2kΩ
Channel 1
G = 2
Channel 2
0.1
1
10
100
Frequency (MHz)
©2004-2009 CADEKA Microcircuits LLC
www.cadeka.com
9
Data Sheet
General Description
G = 2
R
V
= 2kΩ
= +5V
L
R
= 2kΩ
f
s
The CLC2005 is a single supply, general purpose, voltage-
feedback amplifier fabricated on a complementary bipolar
process using a patent pending topography. It features a
rail-to-rail output stage and is unity gain stable. Both gain
bandwidth and slew rate are insensitive to temperature.
R
= 1kΩ
f
The common mode input range extends to 300mV below
ground and to 1.2V below V . Exceeding these values
s
1
10
100
will not cause phase reversal. However, if the input volt-
age exceeds the rails by more than 0.5V, the input ESD
devices will begin to conduct. The output will stay at the
rail during this overdrive condition.
Frequency (MHz)
Figure 2: Frequency Response vs. R
f
Power Dissipation
The design uses a Darlington output stage. The output
stage is short circuit protected and offers “soft” saturation
protection that improves recovery time.
The maximum internal power dissipation allowed is directly
related to the maximum junction temperature. If the
maximum junction temperature exceeds 150°C, some
reliability degradation will occur. If the maximum junction
temperature exceeds 175°C for an extended time, device
failure may occur.
The typical circuit schematic is shown in Figure 1.
+Vs
6.8μF
+
The CLC2005 is short circuit protected. However, this may
not guarantee that the maximum junction temperature
(+150°C) is not exceeded under all conditions. Follow the
maximum power derating curves shown in Figure 3 to
ensure proper operation.
0.1μF
+In1
+
Out1
1/2
CLC2005
-
Rf
2.0
Rg
1.5
SOIC-8 lead
Figure 1: Typical Configuration
1.0
At non-inverting gains other than G = +1, keep R below
g
0.5
0
1kΩ to minimize peaking; thus, for optimum response at a
gain of +2, a feedback resistor of 1kΩ is recommended.
Figure 2 illustrates the CLC2005 frequency response with
both 1kΩ and 2kΩ feedback resistors.
-50 -30
-10
10
30
50
70
90
Ambient Temperature ( C)
Figure 3: Power Derating Curves
Overdrive Recovery
For an amplifier, an overdrive condition occurs when the
output and/or input ranges are exceeded. The recovery
time varies based on whether the input or output is over-
driven and by how much the ranges are exceeded. The
CLC2005 will typically recover in less than 20ns from an
overdrive condition. Figure 4 shows the CLC2005 in an
overdriven condition.
©2004-2009 CADEKA Microcircuits LLC
www.cadeka.com
10
Data Sheet
Refer to the evaluation board layouts shown in Figure 7
for more information.
R
V
= 2kΩ
L
Input
=2V
in
pp
G = 5
R
= 1kΩ
f
When evaluating only one channel, complete the following
on the unused channel:
Output
1. Ground the non-inverting input.
2. Short the output to the inverting input.
Evaluation Board Information
Time (20ns/div)
The following evaluation boards are available to aid in the
testing and layout of this device:
Figure 4: Overdrive Recovery
Eval Board
CEB006
Description
Products
Driving Capacitive Loads
Dual Channel, Dual Supply
8 lead SOIC
CLC2005SO8
The Frequency Response vs. C plot on page 6, illustrates
L
the response of the CLC2005. A small series resistance
Evaluation board schematics and layouts are shown in
Figure 6 and Figure 7.
(R ) at the output of the amplifier, illustrated in Figure 5,
s
will improve stability and settling performance. R values
s
The CEB006 evaluation board is built for dual supply
operation. Follow these steps to use the board in a single
supply application:
in the Frequency Response vs. C plot were chosen to
achieve maximum bandwidth with less than 1dB of peak-
L
ing. For maximum flatness, use a larger R .
s
1. Short -V to ground.
s
2. Use C3 and C4, if the -V pin of the CLC2005 is
s
+
Rs
not directly connected to the ground plane.
-
CL
RL
Rf
Rg
Figure 5: Typical Topology for driving a capacitive load
Layout Considerations
General layout and supply bypassing play major roles
in high frequency performance. Cadeka has evaluation
boards to use as a guide for high frequency layout and to
aid in device testing and characterization. Follow the steps
below as a basis for high frequency layout:
n
Include 6.8μF and 0.1μF ceramic capacitors
n
Place the 6.8μF capacitor within 0.75 inches of the
power pin
n
Place the 0.1μF capacitor within 0.1 inches of the
power pin
n
Remove the ground plane under and around the part,
especially near the input and output pins to reduce
parasitic capacitance
n
Figure 6: Evaluation Board Schematic
Minimize all trace lengths to reduce series inductances
©2004-2009 CADEKA Microcircuits LLC
www.cadeka.com
11
Data Sheet
CLC2005 Evaluation Board Layout
Figure 7a: CEB006 (Top)
Figure 7b: CEB006 (Bottom)
©2004-2009 CADEKA Microcircuits LLC
www.cadeka.com
12
Data Sheet
Mechanical Dimensions
SOIC-8 Package
SOIC-8
SYMBOL
MIN
0.054
0.004
0.014
0.189
0.150
0.229
MAX
0.068
0.0098
0.019
0.196
0.157
0.244
A
A1
B
D
E
D
e
θ
2
X
C
L
H
e
0.050 BSC
C
C
L
0.0075
0.016
0.0098
0.034
E
H
L
X
0.0215 Ref
Gauge Plane
Seating Plane
θ
1
θ
2
0°
8°
7° BSC
Pin No. 1
B
DETAIL-A
L
NOTE:
1. All dimensions are in inches.
0.015±0.004 x 45°
DETAIL-A
2. Lead coplanarity should be 0" to 0.004" max.
3. Package surface finishing: VDI 24~27
4. All dimension excluding mold flashes.
5. The lead width, B to be determined at 0.0075"
from the lead tip.
A1
θ
1
A
C
For additional information regarding our products, please visit CADEKA at: cadeka.com
CADEKA Headquarters Loveland, Colorado
T: 970.663.5452
T: 877.663.5452 (toll free)
Amplify the Human Experience
CADEKA, the CADEKA logo design, Comlinear, and the Comlinear logo design are trademarks or registered trademarks of CADEKA
Microcircuits LLC. All other brand and product names may be trademarks of their respective companies.
CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any
responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in
writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties.
Copyright ©2007-2009 by CADEKA Microcircuits LLC. All rights reserved.
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