CLC1606ISO8X [CADEKA]
1.3GHz Current Feedback Amplifier; 1.3GHz的电流反馈放大器
| 型号： | CLC1606ISO8X |
| 厂家： | 
CADEKA MICROCIRCUITS LLC. |
| 描述： | 1.3GHz Current Feedback Amplifier |
| 文件： | 总18页 (文件大小：2386K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
Amplify the Human Experience
Co m l i n e a r ® CLC1606
1.3GHz Current Feedback Amplifier
f e a t u r e s
General Description
nꢀ
1.2GHz -3dB bandwidth at G=2
The COMLINEAR CLC1606 is a high-performance, current feedback ampli-
fier with superior bandwith and video specifications. The CLC1606 provides
1.3GHz unity gain bandwidth, ±0.1dB gain flatness to 150MHz, and provides
3,300V/μs slew rate exceeding the requirements of high-definition television
(HDTV) and other multimedia applications. The COMLINEAR CLC1606 high-
performance amplifier also provide ample output current to drive multiple
video loads.
nꢀ
nꢀ
3,300V/μs slew rate
0.01%/0.01˚ differential gain/
phase error
nꢀ
nꢀ
nꢀ
7.5mA supply current
875MHz large signal bandwidth
120mA output current (easily drives
three video loads)
nꢀ
nꢀ
nꢀ
Fully specified at 5V and ±5V supplies
CLC1606: Pb-free SOT23-5
CLC1606: Pb-free SOIC-8
The COMLINEAR CLC1606 is designed to operate from ±5V or +5V supplies.
It consumes only 7.5mA of supply current. The combination of high-speed
and excellent video performance make the CLC1606 well suited for use in
many general purpose, high-speed applications including standard definition
and high definition video. Data communications applications benefit from
the CLC1606’s total harmonic distortion of -68dBc at 10MHz and fast settling
time to 0.1%.
a p p l i c a t i o n s
nꢀ
RGB video line drivers
nꢀ
High definition video driver
nꢀ
Video switchers and routers
nꢀ
ADC buffer
nꢀ
Active filters
Typical Application - Driving Dual Video Loads
nꢀ
High-speed instrumentation
nꢀ
Wide dynamic range IF amp
Ordering Information
Part Number
Package
Pb-Free
Yes
RoHS Compliant
Operating Temperature Range Packaging Method
CLC1606IST5X
CLC1606ISO8
CLC1606ISO8X
SOT23-5
SOIC-8
SOIC-8
Yes
Yes
Yes
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Reel
Rail
Yes
Yes
Reel
Moisture sensitivity level for all parts is MSL-1.
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
Data Sheet
SOT23-5 Pin Assignments
SOT23-5 Pin Configuration
Pin No.
Pin Name
OUT
Description
1
2
3
4
Output
OUT
1
2
3
5
4
+V
S
-V
Negative supply
Positive input
Negative input
S
-V
S
+
-
+IN
-IN
-IN
+IN
5
+V
Positive supply
S
SOIC Pin Configuration
SOIC Pin Assignments
Pin No.
Pin Name
NC
Description
1
2
3
4
5
6
7
8
No connect
-IN1
Negative input, channel 1
Positive input, channel 1
Negative supply
No connect
1
8
7
NC
+V
NC
+IN1
2
3
4
-IN1
S
-V
S
NC
6
5
OUT
NC
+IN1
OUT
Output
-V
S
+V
Positive supply
No connect
S
NC
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
2
Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device
should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper de-
vice function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the
operating conditions noted on the tables and plots.
Parameter
Min
0
Max
Unit
Supply Voltage
14
V
V
Input Voltage Range
Continuous Output Current
-V -0.5V
s
+V +0.5V
s
120
mA
Reliability Information
Parameter
Min
-65
Typ
Max
Unit
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10s)
Package Thermal Resistance
5-Lead SOT23
150
150
260
°C
°C
°C
221
100
°C/W
°C/W
8-Lead SOIC
Notes:
Package thermal resistance (q ), JDEC standard, multi-layer test boards, still air.
JA
ESD Protection
Product
SOT23-5
Human Body Model (HBM)
2kV
1kV
Charged Device Model (CDM)
Recommended Operating Conditions
Parameter
Min
Typ
Max
Unit
Operating Temperature Range
Supply Voltage Range
-40
4.5
+85
°C
V
12
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
3
Data Sheet
Electrical Characteristics at +5V
T = 25°C, V = +5V, R = 270Ω, R = 150Ω to V /2, G = 2; unless otherwise noted.
A
s
f
L
S
symbꢀꢁ
pꢂꢃꢂmꢄꢅꢄꢃ
cꢀꢆdꢇꢅꢇꢀꢆꢈ
Mꢇꢆ
tyꢉ
Mꢂx
uꢆꢇꢅꢈ
Frequency Domain Response
UGBW
-3dB Bandwidth
G = +1, Rf = 390Ω, VOUT = 0.5Vpp
G = +2, VOUT = 0.5Vpp
G = +2, VOUT = 1Vpp
1000
900
800
132
140
MHz
MHz
MHz
MHz
MHz
BWSS
-3dB Bandwidth
BWLS
Large Signal Bandwidth
0.1dB Gain Flatness
0.1dB Gain Flatness
BW0.1dBSS
BW0.1dBLS
G = +2, VOUT = 0.5Vpp
G = +2, VOUT = 1Vpp
Time Domain Response
tR, tF
tS
Rise and Fall Time
VOUT = 1V step; (10% to 90%)
VOUT = 1V step
0.6
10
ns
ns
Settling Time to 0.1%
Overshoot
OS
SR
VOUT = 0.2V step
1V step
1
%
Slew Rate
1500
V/µs
Distortion/Noise Response
HD2
HD3
THD
IP3
DG
2nd Harmonic Distortion
1Vpp, 5MHz
-74
-70
68
dBc
dBc
3rd Harmonic Distortion
Total Harmonic Distortion
Third-Order Intercept
Differential Gain
1Vpp, 5MHz
1Vpp, 5MHz
dB
1Vpp, 10MHz
36
dBm
%
0.01
0.01
3
NTSC (3.58MHz), AC-coupled, RL = 150Ω
NTSC (3.58MHz), AC-coupled, RL = 150Ω
> 1MHz
DP
Differential Phase
°
en
Input Voltage Noise
nV/√Hz
pA/√Hz
pA/√Hz
> 1MHz, Inverting
> 1MHz, Non-inverting
20
ini
Input Current Noise
30
DC Performance
VIO
dVIO
Ibn
Input Offset Voltage
Average Drift
0
mV
µV/°C
µA
3.7
Input Bias Current - Non-Inverting
Average Drift
±3.0
100
±6.0
56
dIbn
Ibi
nA/°C
µA
Input Bias Current - Inverting
Average Drift
dIbi
PSRR
IS
nA/°C
dB
Power Supply Rejection Ratio
Supply Current
DC
55
6.5
mA
Input Characteristics
Non-inverting
Inverting
150
70
kΩ
Ω
RIN
CIN
Input Resistance
Input Capacitance
1.0
pF
CMIR
Common Mode Input Range
±1.5
V
CMRR
Common Mode Rejection Ratio
DC
50
dB
Output Characteristics
Closed Loop, DC
0.1
Ω
V
RO
Output Resistance
VOUT
IOUT
Output Voltage Swing
Output Current
RL = 150Ω
±1.5
±120
mA
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
4
Data Sheet
Electrical Characteristics at ±5V
T = 25°C, V = ±5V, R = 270Ω, R = 150Ω, G = 2; unless otherwise noted.
A
s
f
L
symbꢀꢁ
pꢂꢃꢂmꢄꢅꢄꢃ
cꢀꢆdꢇꢅꢇꢀꢆꢈ
Mꢇꢆ
tyꢉ
Mꢂx
uꢆꢇꢅꢈ
Frequency Domain Response
UGBW
-3dB Bandwidth
G = +1, Rf = 390Ω, VOUT = 0.5Vpp
G = +2, VOUT = 0.5Vpp
G = +2, VOUT = 2Vpp
1300
1200
875
MHz
MHz
MHz
MHz
MHz
BWSS
-3dB Bandwidth
BWLS
Large Signal Bandwidth
0.1dB Gain Flatness
0.1dB Gain Flatness
BW0.1dBSS
BW0.1dBLS
150
G = +2, VOUT = 0.5Vpp
G = +2, VOUT = 2Vpp
150
Time Domain Response
tR, tF
tS
Rise and Fall Time
VOUT = 2V step; (10% to 90%)
VOUT = 2V step
0.5
13
ns
ns
Settling Time to 0.1%
Overshoot
OS
SR
VOUT = 0.2V step
2V step
1
%
Slew Rate
3300
V/µs
Distortion/Noise Response
HD2
HD3
THD
IP3
DG
2nd Harmonic Distortion
2Vpp, 5MHz
-71
-71
-68
39
dBc
dBc
3rd Harmonic Distortion
Total Harmonic Distortion
Third-Order Intercept
Differential Gain
2Vpp, 5MHz
2Vpp, 5MHz
dB
2Vpp, 10MHz
dBm
%
0.01
0.01
3
NTSC (3.58MHz), AC-coupled, RL = 150Ω
NTSC (3.58MHz), AC-coupled, RL = 150Ω
> 1MHz
DP
Differential Phase
°
en
Input Voltage Noise
nV/√Hz
pA/√Hz
pA/√Hz
> 1MHz, Inverting
> 1MHz, Non-inverting
20
ini
Input Current Noise - Inverting
30
DC Performance
VIO
dVIO
Ibn
Input Offset Voltage(1)
-10
-45
-50
40
0.5
3.7
10
45
50
mV
µV/°C
µA
Average Drift
Input Bias Current - Non-Inverting (1)
Average Drift
±3.0
100
±7.0
56
dIbn
Ibi
nA/°C
µA
Input Bias Current - Inverting (1)
Average Drift
dIbi
PSRR
IS
nA/°C
dB
Power Supply Rejection Ratio (1)
Supply Current (1)
DC
50
7.5
9.5
mA
Input Characteristics
Non-inverting
Inverting
150
170
1.0
kΩ
k
RIN
CIN
Input Resistance
Input Capacitance
pF
CMIR
Common Mode Input Range
±4.0
V
CMRR
Common Mode Rejection Ratio (1)
DC
40
50
dB
Output Characteristics
Closed Loop, DC
0.1
Ω
V
RO
Output Resistance
VOUT
IOUT
Output Voltage Swing
Output Current
RL = 150Ω (1)
±3.0
±3.7
±280
mA
nꢀꢅꢄꢈ:
1. 100% tested at 25°C
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
5
Data Sheet
Typical Performance Characteristics
T = 25°C, V = ±5V, R = 270Ω, R = 150Ω, G = 2; unless otherwise noted.
A
s
f
L
Non-Inverting Frequency Response
Inverting Frequency Response
3
G = 1
3
Rf = 390Ω
G = -1
G = 1
Rf = 499Ω
0
-3
-6
0
-3
-6
-9
G = -2
G = -5
G = 2
G = 5
G = -10
G = 1 0
VOUT = 0.5Vpp
VOUT = 0.5Vpp
-9
0.1
1
10
100
1000
0.1
1
10
Frequency (MHz)
100
1000
Frequency (MHz)
Frequency Response vs. C
Frequency Response vs. R
L
L
1
0
6
5
4
CL = 1000pF
s = 3 . 3 Ω
-1
-2
-3
-4
-5
-6
-7
3
R
2
CL = 500pF
R
s = 5 Ω
1
0
CL = 100pF
R
s = 1 0 Ω
-1
-2
-3
-4
RL = 100Ω
RL = 50Ω
CL = 50pF
s = 1 5 Ω
R
CL = 20pF
VOUT = 0.5Vpp
RL = 25Ω
-5
VOUT = 0.5Vpp
R
s = 2 0 Ω
-6
0.1
1
10
100
1000
0.1
1
10
Frequency (MHz)
100
1000
Frequency (MHz)
Frequency Response vs. V
Frequency Response vs. Temperature
OUT
3
2
2
1
1
0
0
-1
-1
-2
-3
-4
-5
-6
-7
+ 25degC
VOUT = 1Vpp
-2
- 40degC
-3
-4
-5
-6
-7
VOUT = 2Vpp
VOUT = 4Vpp
+ 85degC
VOUT = 0.2Vpp
0.1
1
10
Frequency (MHz)
100
1000
0.1
1
10
100
1000
10000
Frequency (MHz)
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
6
Data Sheet
Typical Performance Characteristics
T = 25°C, V = ±5V, R = 270Ω, R = 150Ω, G = 2; unless otherwise noted.
A
s
f
L
Non-Inverting Frequency Response at V = 5V
Inverting Frequency Response at V = 5V
S
S
2
3
G = 1
Rf = 390Ω
1
0
G = -1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
G = 2
G = -2
G = 5
G = -5
-3
G = -10
G = 1 0
-6
VOUT = 0.5Vpp
VOUT = 0.5Vpp
-9
0.1
1
10
Frequency (MHz)
100
1000
0.1
1
10
100
1000
Frequency (MHz)
Frequency Response vs. C at V = 5V
Frequency Response vs. R at V = 5V
L
S
L
S
1
0
4
3
2
CL = 1000pF
-1
-2
-3
-4
-5
-6
-7
R
s = 3 . 3 Ω
1
CL = 500pF
R
s = 5 Ω
0
-1
-2
-3
-4
-5
-6
CL = 100pF
RL = 100Ω
R
s = 1 0 Ω
RL = 50Ω
RL = 25Ω
CL = 50pF
s = 1 5 Ω
R
CL = 20pF
VOUT = 0.5Vpp
VOUT = 0.5Vpp
R
s = 2 0 Ω
0.1
1
10
100
1000
0.1
1
10
Frequency (MHz)
100
1000
Frequency (MHz)
Frequency Response vs. V
at V = 5V
Frequency Response vs. Temperature at V = 5V
OUT
S
S
2
1
2
1
0
0
-1
-2
-3
-4
-5
-6
-7
-1
VOUT = 1Vpp
-2
+ 25degC
-3
VOUT = 2Vpp
VOUT = 3Vpp
-4
-5
-6
-7
- 40degC
+ 85degC
VOUT = 0.2Vpp
0.1
1
10
Frequency (MHz)
100
1000
0.1
1
10
100
1000
10000
Frequency (MHz)
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
7
Data Sheet
Typical Performance Characteristics - Continued
T = 25°C, V = ±5V, R = 270Ω, R = 150Ω, G = 2; unless otherwise noted.
A
s
f
L
Gain Flatness
Gain Flatness at V = 5V
S
1 .7
1.5
1.3
1.1
0.9
0 .7
0.8
0 .7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.5
0.3
0.1
-0.1
-0.3
-0.1
-0.2
VOUT = 2Vpp
RL = 150Ω
Rf = 270Ω
VOUT = 2Vpp
RL = 150Ω
Rf = 270Ω
-0.3
-0.4
-0.5
-0.5
0.1
1
10
100
1000
0.1
1
10
100
1000
Frequency (MHz)
Frequency (MHz)
-3dB Bandwidth vs. V
at G=10
-3dB Bandwidth vs. V
at G=10, V = 5V
OUT S
OUT
600
450
550
500
450
400
400
350
300
250
350
G = 10
300
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOUT (VPP
)
VOUT (VPP)
Closed Loop Output Impedance vs. Frequency
Input Voltage Noise
2.0
20
V
= ±5.0V
S
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
15
10
5
0
10K
100K
1M
10M
100M
0.0001 0.001
0.01
0.1
1
10
Frequency (Hz)
Frequency (MHz)
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
8
Data Sheet
Typical Performance Characteristics - Continued
T = 25°C, V = ±5V, R = 270Ω, R = 150Ω, G = 2; unless otherwise noted.
A
s
f
L
2nd Harmonic Distortion vs. R
3rd Harmonic Distortion vs. R
L
L
-55
-60
-55
-60
RL = 150Ω
-65
-70
-75
-80
-85
-90
-95
-100
-65
RL = 150Ω
-70
-75
-80
-85
-90
RL = 499Ω
RL = 499Ω
-95
VOUT = 2Vpp
VOUT = 2Vpp
-100
0
5
10
Frequency (MHz)
15
20
0
5
10
Frequency (MHz)
15
20
2nd Harmonic Distortion vs. V
3rd Harmonic Distortion vs. V
OUT
OUT
-60
-60
-65
-70
-75
-80
-85
-65
-70
-75
10MHz
10MHz
5MHz
5MHz
-80
-85
-90
1MHz
-90
-95
1MHz
RL = 150Ω
RL = 150Ω
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
Output Amplitude (Vpp
)
Output Amplitude (Vpp)
CMRR vs. Frequency
PSRR vs. Frequency
0
0
V
= ±5.0V
S
-10
-20
-30
-40
-50
-60
-10
-20
-30
-40
-50
-60
10k
100k
1M
10M
100M
10K
100K
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
9
Data Sheet
Typical Performance Characteristics - Continued
T = 25°C, V = ±5V, R = 270Ω, R = 150Ω, G = 2; unless otherwise noted.
A
s
f
L
Small Signal Pulse Response
Small Signal Pulse Response at V = 5V
S
0.125
0.1
2.625
2.6
0.075
0.05
2.575
2.55
2.525
2.5
0.025
0
-0.025
-0.05
-0.075
-0.1
2.475
2.45
2.425
2.4
-0.125
2.375
0
20
40
60
80
100 120 140 160 180 200
0
20
40
60
80
100 120 140 160 180 200
T im e ( n s )
T im e ( n s )
Large Signal Pulse Response
Large Signal Pulse Response at V = 5V
S
3
4
3.5
3
2
1
0
2.5
2
-1
-2
-3
1.5
1
0
20
40
60
80
100
T im e ( n s )
120
140
160
180
200
0
20
40
60
80
100
120
140
160
180
200
T im e ( n s )
Differential Gain & Phase AC Coupled Output
Differential Gain & Phase DC Coupled Output
0.02
0.015
0.01
0.06
0.05
0.04
0.03
0.02
0.01
0
DP
0.005
DG
0
DP
DG
-0.005
-0.01
RL = 150Ω
AC coupled
-0.01
-0.02
RL = 150Ω
DC coupled
-0.015
-0 .7
-0.5
-0.3
-0.1
0.1
0.3
0.5
0 .7
-0 .7
-0.5
-0.3
-0.1
0.1
0.3
0.5
0 .7
I n p u t Vo l t a g e ( V )
I n p u t Vo l t a g e ( V )
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
10
Data Sheet
Typical Performance Characteristics - Continued
T = 25°C, V = ±5V, R = 270Ω, R = 150Ω, G = 2; unless otherwise noted.
A
s
f
L
Differential Gain & Phase AC Coupled Output at V = ±2.5V
Differential Gain & Phase DC Coupled at V = ±2.5V
S
S
0.01
0.05
0.04
0.005
DP
0.03
0.02
0.01
0
DP
0
-0.005
-0.01
-0.015
-0.02
DG
-0.01
-0.02
-0.03
-0.04
DG
-0.025
-0.03
RL = 150Ω
AC coupled
RL = 150Ω
DC coupled
-0.35
-0.25
-0.15
-0.05
0.05
0.15
0.25
0.35
-0.35
-0.25
-0.15
-0.05
0.05
0.15
0.25
0.35
I n p u t Vo l t a g e ( V )
I n p u t Vo l t a g e ( V )
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
11
Data Sheet
General Information - Current Feedback
Technology
Advantages of CFB Technology
V
OUT
x1
Z *I
err
o
I
err
The CLC1606 Family of amplifiers utilize current feedback
(CFB) technology to achieve superior performance. The
primary advantage of CFB technology is higher slew rate
performance when compared to voltage feedback (VFB)
architecture. High slew rate contributes directly to better
large signal pulse response, full power bandwidth, and
distortion.
R
R
g
f
R
L
V
IN
VOUT
Rf
1
=
−
+
Eq. 2
V
Rg
Rf
Zo(jω)
IN
1 +
CFB also alleviates the traditional trade-off between
closed loop gain and usable bandwidth that is seen with
a VFB amplifier. With CFB, the bandwidth is primarily de-
Figure 2. Inverting Gain Configuration with First Order
Transfer Function
termined by the value of the feedback resistor, R . By us-
f
ing optimum feedback resistor values, the bandwidth of a
CFB amplifier remains nearly constant with different gain
configurations.
CFB Technology - Theory of Operation
Figure 1 shows a simple representation of a current feed-
back amplifier that is configured in the traditional non-
inverting gain configuration.
When designing with CFB amplifiers always abide by these
basic rules:
• Use the recommended feedback resistor value
Instead of having two high-impedance inputs similar to a
VFB amplifier, the inputs of a CFB amplifier are connected
across a unity gain buffer. This buffer has a high imped-
ance input and a low impedance output. It can source or
• Do not use reactive (capacitors, diodes, inductors, etc.)
elements in the direct feedback path
• Avoid stray or parasitic capacitance across feedback re-
sistors
sink current (I ) as needed to force the non-inverting
err
input to track the value of Vin. The CFB architecture em-
ploys a high gain trans-impedance stage that senses Ierr
• Follow general high-speed amplifier layout guidelines
and drives the output to a value of (Z (jω) * I ) volts.
o
err
• Ensure proper precautions have been made for driving
capacitive loads
With the application of negative feedback, the amplifier
will drive the output to a voltage in a manner which tries
to drive Ierr to zero. In practice, primarily due to limita-
tions on the value of Z (jω), Ierr remains a small but
o
finite value.
V
IN
V
OUT
x1
Z *I
o err
I
err
A closer look at the closed loop transfer function (Eq.1)
shows the effect of the trans-impedance, Z (jω) on the
o
R
f
gain of the circuit. At low frequencies where Z (jω) is very
R
L
o
large with respect to R , the second term of the equation
f
R
g
approaches unity, allowing R and R to set the gain. At
f
g
higher frequencies, the value of Z (jω) will roll off, and
o
the effect of the secondary term will begin to dominate.
The -3dB small signal parameter specifies the frequency
VOUT
Rf
1
=
1 +
+
Eq. 1
where the value Z (jω) equals the value of R causing the
o
f
V
Rg
Rf
Zo(jω)
IN
1 +
gain to drop by 0.707 of the value at DC.
For more information regarding current feedback ampli-
fiers, visit www.cadeka.com for detailed application notes,
such as AN-3: The Ins and Outs of Current Feedback Am-
plifiers.
Figure 1. Non-Inverting Gain Configuration with First
Order Transfer Function
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
12
Data Sheet
CFB amplifiers can be used in unity gain configurations.
Do not use the traditional voltage follower circuit, where
the output is tied directly to the inverting input. With a
CFB amplifier, a feedback resistor of appropriate value
must be used to prevent unstable behavior. Refer to fig-
ure 5 and Table 1. Although this seems cumbersome, it
does allow a degree of freedom to adjust the passband
characteristics.
Application Information
Basic Operation
Figures 3, 4, and 5 illustrate typical circuit configurations for
non-inverting, inverting, and unity gain topologies for dual
supply applications. They show the recommended bypass
capacitor values and overall closed loop gain equations.
+Vs
6.8μF
Feedback Resistor Selection
One of the key design considerations when using a CFB
0.1μF
amplifier is the selection of the feedback resistor, R . R is
f
f
Input
+
-
used in conjunction with R to set the gain in the tradi-
Output
g
tional non-inverting and inverting circuit configurations.
Refer to figures 3 and 4. As discussed in the Current Feed-
back Technology section, the value of the feedback resis-
tor has a pronounced effect on the frequency response of
the circuit.
RL
0.1μF
6.8μF
Rf
Rg
G = 1 + (Rf/Rg)
-Vs
Table 1, provides recommended R and associated R val-
f
g
ues for various gain settings. These values produce the
optimum frequency response, maximum bandwidth with
minimum peaking. Adjust these values to optimize perfor-
mance for a specific application. The typical performance
characteristics section includes plots that illustrate how
Figure 3. Typical Non-Inverting Gain Circuit
+Vs
6.8μF
the bandwidth is directly affected by the value of R at
various gain settings.
R1
f
0.1μF
+
Output
Rg
Input
-
RL
0.1μF
Rf
±0.1dB BW
(MHz)
-3dB BW
(MHz)
Gain
(V/V
R (Ω)
R (Ω)
f
g
6.8μF
G = - (Rf/Rg)
-Vs
1
2
5
390
270
270
-
136
150
115
1300
1200
750
For optimum input offset
voltage set R1 = Rf || Rg
270
67.5
Figure 4. Typical Inverting Gain Circuit
Table 1: Recommended R vs. Gain
f
+Vs
6.8μF
In general, lowering the value of R from the recom-
f
mended value will extend the bandwidth at the expense
of additional high frequency gain peaking. This will cause
increased overshoot and ringing in the pulse response
0.1μF
Input
+
Output
characteristics. Reducing R too much will eventually
-
f
RL
cause oscillatory behavior.
0.1μF
Rf
Increasing the value of R will lower the bandwidth. Low-
f
6.8μF
G = 1
ering the bandwidth creates a flatter frequency response
and improves 0.1dB bandwidth performance. This is im-
portant in applications such as video. Further increase in
-Vs
Rf is required for CFB amplifiers
R will cause premature gain rolloff and adversely affect
f
Figure 5. Typical Unity Gain (G=1) Circuit
gain flatness.
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
13
Data Sheet
Driving Capacitive Loads
ringing. Refer to the lꢂyꢀꢊꢅ cꢀꢆꢈꢇdꢄꢃꢂꢅꢇꢀꢆꢈ section for
additional information regarding high speed layout tech-
niques.
Increased phase delay at the output due to capacitive load-
ing can cause ringing, peaking in the frequency response,
and possible unstable behavior. Use a series resistance,
Overdrive Recovery
R , between the amplifier and the load to help improve
stability and settling performance. Refer to Figure 6.
S
An overdrive condition is defined as the point when either
one of the inputs or the output exceed their specified volt-
age range. Overdrive recovery is the time needed for the
amplifier to return to its normal or linear operating point.
The recovery time varies, based on whether the input or
output is overdriven and by how much the range is ex-
ceeded. The CLC1606 Family will typically recover in less
than 10ns from an overdrive condition. Figure 7 shows the
CLC1606 in an overdriven condition.
Input
+
-
Rs
Output
CL
RL
Rf
Rg
Figure 6. Addition of R for Driving
S
1.5
1
6
Capacitive Loads
VIN = 2Vpp
G = 5
4
Table 2 provides the recommended R for various capaci-
S
Input
tive loads. The recommended R values result in <=0.5dB
S
Output
0.5
0
2
peaking in the frequency response. The Frequency Re-
sponse vs. C plot, on page 5, illustrates the response of
L
0
the CLC1606 Family.
-0.5
-1
-2
-4
-6
C (pF)
L
R (Ω)
-3dB BW (MHz)
S
20
20
10
375
180
58
-1.5
100
0
20
40
60
80 100 120 140 160 180 200
1000
3.3
T im e ( n s )
Figure 7. Overdrive Recovery
Power Dissipation
Table 1: Recommended R vs. C
S
L
For a given load capacitance, adjust R to optimize the
tradeoff between settling time and bandwidth. In general,
S
Power dissipation should not be a factor when operating
under the stated 1000 ohm load condition. However, ap-
plications with low impedance, DC coupled loads should
be analyzed to ensure that maximum allowed junction
temperature is not exceeded. Guidelines listed below can
be used to verify that the particular application will not
cause the device to operate beyond it’s intended operat-
ing range.
reducing R will increase bandwidth at the expense of ad-
S
ditional overshoot and ringing.
Parasitic Capacitance on the Inverting Input
Physical connections between components create unin-
tentional or parasitic resistive, capacitive, and inductive
elements.
Maximum power levels are set by the absolute maximum
junction rating of 150°C. To calculate the junction tem-
Parasitic capacitance at the inverting input can be espe-
cially troublesome with high frequency amplifiers. A para-
sitic capacitance on this node will be in parallel with the
perature, the package thermal resistance value Theta
JA
(Ө ) is used along with the total die power dissipation.
JA
gain setting resistor R . At high frequencies, its imped-
g
ance can begin to raise the system gain by making R
g
appear smaller.
T
= T + (Ө × P )
Ambient JA D
Junction
In general, avoid adding any additional parasitic capaci-
tance at this node. In addition, stray capacitance across
Where T
is the temperature of the working environment.
the R resistor can induce peaking and high frequency
Ambient
f
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
14
Data Sheet
In order to determine P , the power dissipated in the load
needs to be subtracted from the total power delivered by
the supplies.
D
2
1.5
1
P = P
- P
load
D
supply
Supply power is calculated by the standard power equa-
SOIC-8
tion.
P
= V
× I
supply
supply RMS supply
0.5
0
SOT23-5
V
= V - V
S+ S-
supply
Power delivered to a purely resistive load is:
-40
-20
0
20
40
60
80
2
P
= ((V
)
)/Rload
eff
load
LOAD RMS
Ambient Temperature (°C)
The effective load resistor (Rload ) will need to include
eff
the effect of the feedback network. For instance,
Figure 8. Maximum Power Derating
Rload in figure 3 would be calculated as:
eff
R || (R + R )
Better thermal ratings can be achieved by maximizing PC
board metallization at the package pins. However, be care-
ful of stray capacitance on the input pins.
L
f
g
These measurements are basic and are relatively easy to
perform with standard lab equipment. For design purposes
however, prior knowledge of actual signal levels and load In addition, increased airflow across the package can also
impedance is needed to determine the dissipated power. help to reduce the effective Ө of the package.
JA
Here, P can be found from
D
In the event the outputs are momentarily shorted to a low
impedance path, internal circuitry and output metallization
are set to limit and handle up to 65mA of output current.
However, extended duration under these conditions may
not guarantee that the maximum junction temperature
(+150°C) is not exceeded.
P = P
+ P
- P
D
Quiescent
Dynamic Load
Quiescent power can be derived from the specified I val-
ues along with known supply voltage, V
can be calculated as above with the desired signal ampli-
tudes using:
S
. Load power
Supply
Layout Considerations
(V
)
= V
/ √2
LOAD RMS
PEAK
General layout and supply bypassing play major roles in
high frequency performance. CaDeKa has evaluation
boards to use as a guide for high frequency layout and as
aid in device testing and characterization. Follow the steps
below as a basis for high frequency layout:
( I
)
= ( V
)
/ Rload
LOAD RMS
LOAD RMS eff
The dynamic power is focused primarily within the output
stage driving the load. This value can be calculated as:
P
= (V - V
)
× ( I )
LOAD RMS
DYNAMIC
S+
LOAD RMS
• Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
Assuming the load is referenced in the middle of the power
rails or V /2.
supply
• Place the 6.8µF capacitor within 0.75 inches of the power pin
• Place the 0.1µF capacitor within 0.1 inches of the power pin
Figure 8 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8 and 14 lead
SOIC packages.
• Remove the ground plane under and around the part,
especially near the input and output pins to reduce para-
sitic capacitance
• Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more in-
formation.
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
15
Data Sheet
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of these devices:
Evaluation Board #
CEB002
CEB003
Products
CLC1606IST5X
CLC1606ISO8X
Evaluation Board Schematics
Evaluation board schematics and layouts are shown in Fig-
ures 9-14. These evaluation boards are built for dual- sup-
ply operation. Follow these steps to use the board in a
single-supply application:
Figure 10. CEB002 Top View
1. Short -Vs to ground.
2. Use C3 and C4, if the -V pin of the amplifier is not
S
directly connected to the ground plane.
Figure 11. CEB002 Bottom View
Figure 9. CEB002 Schematic
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
16
Data Sheet
Figure 14. CEB003 Bottom View
Figure 12. CEB003 Schematic
Figure 13. CEB003 Top View
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
17
Data Sheet
Mechanical Dimensions
SOT23-5 Package
SOIC-8 Package
For additional information regarding our products, please visit CADEKA at: cadeka.com
caDeKa Hꢄꢂdqꢊꢂꢃꢅꢄꢃꢈ Loveland, Colorado
T: 970.663.5452
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CADEKA, the CADEKA logo design, COMLINEAR, the COMLINEAR logo design, and ARCTIC are trademarks or registered trademarks of
CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies.
CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any
responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in
writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties.
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