ACPL-331J-000E [AVAGO]
1.5 Amp Output Current IGBT Gate Driver Optocoupler; 1.5安培输出电流IGBT门极驱动光电耦合器
| 型号： | ACPL-331J-000E |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | 1.5 Amp Output Current IGBT Gate Driver Optocoupler |
| 文件： | 总22页 (文件大小：300K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACPL-331J
1.5 Amp Output Current IGBT Gate Driver Optocoupler
with Integrated (V ) Desaturation Detection, UVLO,
CE
Fault Status Feedback and Active Miller Clamping
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
The ACPL-331J is an advanced 1.5 A output current, easy- • Under Voltage Lock-Out Protection (UVLO)
to-use, intelligent gate driver which makes IGBT VCE fault
protection compact, affordable, and easy-to implement.
with Hysteresis
• Desaturation Detection
• Miller Clamping
Features such as integrated
V
CE
detection, under
voltage lockout (UVLO), “soft” IGBT turn-off, isolated
open collector fault feedback and active Miller clamping
provide maximum design flexibility and circuit protec-
tion.
• Open Collector Isolated fault feedback
•
“Soft”IGBT Turn-off
• Fault Reset by next LED turn-on (low to high) after
The ACPL-331J contains a AlGaAs LED. The LED is
optically coupled to an integrated circuit with a power
output stage. ACPL-331J is ideally suited for driving
power IGBTs and MOSFETs used in motor control inverter
applications. The voltage and current supplied by these
optocouplers make them ideally suited for directly
driving IGBTs with ratings up to 1200 V and 100 A. For
IGBTs with higher ratings, the ACPL-331J can be used to
drive a discrete power stage which drives the IGBT gate.
fault mute period
• Available in SO-16 package
• Safety approvals: UL approved, 5000 V
for 1
RMS
minute, CSA approved, IEC/EN/DIN-EN 60747-5-5
approved V
= 1230 V
IORM
PEAK
Specifications
• 1.5 A maximum peak output current
• 1.0 A minimum peak output current
The ACPL-331J has an insulation voltage of V
= 1230
IORM
V
.
PEAK
• 250 ns maximum propagation delay over
temperature range
Block Diagram
13
• 100 ns maximum pulse width distortion (PWD)
• 50 kV/μs minimum common mode rejection (CMR)
VCC2
UVLO
6, 7
D
R
I
V
E
R
at V = 1500 V
CM
ANODE
11
5, 8
VOUT
• I
< 5 mA maximum supply current
CC(max)
CATHODE
DESAT
LED1
14
• Wide V operating range: 15 V to 30 V over
CC
DESAT
temperature range
9, 12
VEE
SHIELD
LED2
• 1.0 A Miller Clamp. Clamp pin short to V if not used
EE
VCLAMP
• Wide operating temperature range: –40°C to 105°C
2
10
16
VCC1
VCLAMP
VE
Applications
3
FAULT
• Isolated IGBT/Power MOSFET gate drive
• AC and brushless DC motor drives
1, 4
VS
15
VLED
• Industrial inverters and Uninterruptible Power Supply
SHIELD
(UPS)
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Pin Description
Pin
1
Symbol
VS
Description
Input Ground
1
2
3
4
5
6
7
8
VS
2
VCC1
FAULT
Positive input supply voltage. (3.3 V to 5.5 V)
VE 16
VLED 15
3
Fault output. FAULT changes from a high impedance state
to a logic low output within 5 μs of the voltage on the
DESAT pin exceeding an internal reference voltage of 6.5 V.
FAULT output is an open collector which allows the FAULT
outputs from all ACPL-331J in a circuit to be connected
together in a “wired OR” forming a single fault bus for inter-
facing directly to the micro-controller.
VCC1
FAULT
VS
DESAT 14
VCC2 13
4
VS
Input Ground
CATHODE
ANODE
ANODE
CATHODE
VEE 12
5
CATHODE Cathode
6
ANODE
ANODE
Anode
Anode
VOUT 11
7
8
CATHODE Cathode
VCLAMP 10
9
VEE
Output supply voltage.
10
11
12
13
14
VCLAMP
VOUT
VEE
Miller clamp
VEE
9
Gate drive voltage output
Output supply voltage.
Positive output supply voltage
VCC2
DESAT
Desaturation voltage input. When the voltage on DESAT
exceeds an internal reference voltage of 6.5 V while the
IGBT is on, FAULT output is changed from a high impedance
state to a logic low state within 5 μs.
15
16
VLED
LED anode. This pin must be left unconnected for guaran-
teed data sheet performance. (For optical coupling testing
only)
VE
Common (IGBT emitter) output supply voltage.
Ordering Information
ACPL-331J is UL Recognized with 5000 Vrms for 1 minute per UL1577.
Option
Surface
Mount
IEC/EN/DIN EN
60747-5-5
Part number
RoHS Compliant
-000E
Package
Tape& Reel
Quantity
ACPL-331J
SO-16
X
X
X
X
45 per tube
850 per reel
-500E
X
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACPL-331J-500E to order product of SO-16 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN
60747-5-5 Safety Approval in RoHS compliant.
Example 2:
ACPL-331J-000E to order product of SO-16 Surface Mount package in tube packaging with IEC/EN/DIN EN
60747-5-5 Safety Approval and RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and
RoHS compliant option will use ‘-XXXE‘.
2
Package Outline Drawings
ACPL-331J 16-Lead Surface Mount Package
0.0ꢀ8
(0.457ꢁ
0.050
(ꢀ.270ꢁ
LAND PATTERN RECOMMENDATION
ꢀ6 ꢀ5 ꢀ4 ꢀ3 ꢀ2 ꢀꢀ ꢀ0
9
TYPE NUMBER
DATE CODE
A 33ꢀJ
YYWW
0.458 (ꢀꢀ.63ꢁ
0.295 0.0ꢀ0
(7.493 0.254ꢁ
0.085 (2.ꢀ6ꢁ
ꢀ
2
3
4
5
6
7
8
0.406 0.ꢀ0
(ꢀ0.3ꢀ2 0.254ꢁ
0.025 (0.64ꢁ
0.345 0.0ꢀ0
(8.763 0.254ꢁ
ALL LEADS
9 °
TO BE
COPLANAR
0.002
0.ꢀ38 0.005
(3.505 0.ꢀ27ꢁ
0.0ꢀ8
(0.457ꢁ
0 - 8 °
0.008 0.003
(0.203 0.076ꢁ
STANDOFF
0.025 MIN.
0.408 0.0ꢀ0
(ꢀ0.363 0.254ꢁ
Dimensions in inches (millimeters)
Notes: Initial and continued variation in the color of the ACPL-
331J’s white mold compound is normal and does note affect device
performance or reliability.
Floating Lead Protrusion is 0.25 mm (10 mils) max.
Recommended Pb-Free IR Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
3
Regulatory Information
The ACPL-331J is approved by the following organizations:
IEC/EN/DIN EN 60747-5-5
UL
Approval under:
DIN EN 60747-5-5 (VDE 0884-5):2011-11
EN 60747-5-5:2011
Approval under UL 1577, component recognition
program up to VISO = 5000 VRMS. File E55361.
CSA
Approval under CSA Component Acceptance Notice #5,
File CA 88324.
Table 1. IEC/EN/DIN EN 60747-5-5 Insulation Characteristics*
Description
Symbol
Characteristic
Unit
Installation classification per DIN VDE 0110/39, Table 1
for rated mains voltage ≤ 150 Vrms
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 600 Vrms
for rated mains voltage ≤ 1000Vrms
I – IV
I – IV
I – IV
I – III
Climatic Classification
40/100/21
2
Pollution Degree (DIN VDE 0110/39)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b**,
VIORM
VPR
1230
2306
Vpeak
Vpeak
VIORM x 1.875=VPR, 100% Production Test with tm=1 sec, Partial discharge < 5 pC
Input to Output Test Voltage, Method a**,
VIORM x 1.6=VPR, Type and Sample Test, tm=10 sec, Partial discharge < 5 pC
VPR
1968
8000
Vpeak
Vpeak
Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec)
VIOTM
Safety-limiting values – maximum values allowed in the event of a failure
Case Temperature
TS
175
°C
Input Current
IS, INPUT
PS, OUTPUT
RS
400
mA
mW
Ω
Output Power
1200
>109
Insulation Resistance at TS, VIO = 500 V
*
Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.
Surface mount classification is class A in accordance with CECCOO802.
** Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section IEC/EN/
DIN EN 60747-5-5, for a detailed description of Method a and Method b partial discharge test profiles.
Dependence of Safety Limiting Values on Temperature. (take from DS AV01-0579EN Pg.7)
1400
PS , OUTPUT
PS , INPUT
1200
1000
800
600
400
200
0
0
25 50 75 100 125 150 175 200
TS - CASE TEMPERATURE - °C
4
Table 2. Insulation and Safety Related Specifications
Parameter
Symbol
ACPL-331J
Units
Conditions
Minimum External Air
Gap (Clearance)
L(101)
8.3
mm
Measured from input terminals to output terminals,
shortest distance through air.
Minimum External
Tracking (Creepage)
L(102)
CTI
8.3
0.5
mm
mm
Measured from input terminals to output terminals,
shortest distance path along body.
Minimum Internal
Plastic Gap (Internal
Clearance)
Through insulation distance conductor to conductor,
usually the straight line distance thickness between the
emitter and detector.
Tracking Resistance
(Comparative Tracking
Index)
>175
IIIa
V
DIN IEC 112/VDE 0303 Part 1
Isolation Group
Material Group (DIN VDE 0110, 1/89, Table 1)
Table 3. Absolute Maximum Ratings
Parameter
Symbol
Min.
-55
-40
Max.
125
105
125
25
Units
°C
Note
Storage Temperature
Operating Temperature
Output IC Junction Temperature
Average Input Current
TS
TA
°C
2
2
1
TJ
°C
IF(AVG)
IF(TRAN)
mA
A
Peak Transient Input Current
(<1 μs pulse width, 300pps)
1.0
Reverse Input Voltage
VR
5
V
“High”Peak Output Current
“Low”Peak Output Current
Positive Input Supply Voltage
FAULT Output Current
IOH(PEAK)
IOL(PEAK)
VCC1
1.5
1.5
7.0
A
3
3
A
-0.5
8.0
V
IFAULT
mA
V
FAULT Pin Voltage
VFAULT
(VCC2 - VEE
-0.5
-0.5
-0.5
-0.5
-0.5
VCC1
35
Total Output Supply Voltage
Negative Output Supply Voltage
Positive Output Supply Voltage
Gate Drive Output Voltage
Peak Clamping Sinking Current
Miller Clamping Pin Voltage
DESAT Voltage
)
V
(VE - VEE
)
15
V
6
(VCC2 - VE)
VO(PEAK)
IClamp
VClamp
VDESAT
PO
35 - (VE - VEE
VCC2
1.0
)
V
V
A
-0.5
VE
VCC2
VE + 10
600
V
V
Output IC Power Dissipation
Input IC Power Dissipation
Solder Reflow Temperature Profile
mW
mW
2
2
PI
150
See Package Outline Drawings section
Table 4. Recommended Operating Conditions
Parameter
Symbol
TA
Min.
- 40
15
0
Max.
Units
Note
Operating Temperature
Total Output Supply Voltage
Negative Output Supply Voltage
Positive Output Supply Voltage
Input Current (ON)
105
°C
V
2
7
4
(VCC2 - VEE
)
30
(VE - VEE
)
15
V
(VCC2 - VE)
IF(ON)
15
8
30 - (VE - VEE
12
)
V
mA
Input Voltage (OFF)
VF(OFF)
- 3.6
0.8
V
5
Table 5. Electrical Specifications (DC)
Unless otherwise noted, all typical values at T = 25°C, V
- V = 30 V, V - V = 0 V;
EE E EE
A
CC2
all Minimum/Maximum specifications are at Recommended Operating Conditions.
Parameter
FAULT Logic Low
Output Voltage
Symbol
VFAULTL
Min.
Typ.
0.1
Max.
0.4
Units
V
Test Conditions
Fig.
Note
IFAULT = 1.1 mA, VCC1 = 5.5V
IFAULT = 1.1 mA, VCC1 = 3.3V
VFAULT = 5.5 V, VCC1 = 5.5V
VFAULT = 3.3 V, VCC1 = 3.3V
0.1
0.4
V
FAULT Logic High
Output Current
IFAULTH
0.02
0.002
-0.75
0.5
μA
μA
A
0.3
High Level
Output Current
IOH
-0.3
-1.0
0.3
1.0
90
VO = VCC2 – 4
VO = VCC2 – 15
VO = VEE + 2.5
4, 18
5, 19
5
3
5
3
6
A
Low Level
Output Current
IOL
0.75
140
A
A
VO = VEE + 15
Low Level Output Current
During Fault Condition
IOLF
230
0.5
mA
VOUT - VEE = 14 V
High Level
Output Voltage
VOH
VOL
VCC-2.9 VCC-2.0
V
V
V
A
IO = -650 μA
2, 4,
20
7, 8, 9,
23
Low Level
Output Voltage
0.17
2.0
IO = 100 mA
3, 5,
21
Clamp Pin Threshold
Voltage
VtClamp
ICL
Clamp Low Level
Sinking Current
0.21
0.7
VO = VEE + 2.5
High Level Supply Current
Low Level Supply Current
ICC2H
ICC2L
ICHG
2.5
5
mA
mA
mA
IO = 0 mA
IO = 0 mA
VDESAT = 2 V
6, 7,
23
9
2.5
5
Blanking Capacitor
Charging Current
0.13
10
-0.24
-0.33
8, 24
25
9, 10
Blanking Capacitor
Discharge Current
IDSCHG
30
mA
VDESAT = 7.0 V
DESAT Threshold
UVLO Threshold
VDESAT
VUVLO+
VUVLO-
6
6.5
7.5
V
V
V
V
VCC2 -VE >VUVLO-
VO > 5 V
9, 27
9
10.5
9.2
11.6
10.3
1.3
12.5
11.1
7, 9, 11
7, 9, 12
VO < 5 V
UVLO Hysteresis
(VUVLO+ 0.4
- VUVLO-
)
Threshold Input Current
Low to High
IFLH
VFHL
VF
2.0
6
mA
V
IO = 0 mA, VO > 5 V
Threshold Input Voltage
High to Low
0.8
1.2
Input Forward Voltage
1.6
1.95
V
IF = 10 mA
Temperature Coefficient
of Input Forward Voltage
ΔVF/ΔTA
-1.3
mV/°C
Input Reverse Breakdown
Voltage
BVR
5
V
IR = 10 μA
Input Capacitance
CIN
70
pF
f = 1 MHz, VF = 0 V
6
Table 6. Switching Specifications (AC)
Unless otherwise noted, all typical values at T = 25°C, V
- V = 30 V, V - V = 0 V;
EE E EE
A
CC2
all Minimum/Maximum specifications are at Recommended Operating Conditions.
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Fig.
Note
Propagation Delay Time
to High Output Level
tPLH
100
180
250
ns
Rg = 20 Ω, Cg = 5 nF,
f = 10 kHz,
Duty Cycle = 50%,
IF = 10 mA, VCC2 = 30 V
1, 10,
11, 12,
13, 26
13, 15
Propagation Delay Time
to Low Output Level
tPHL
100
180
20
250
ns
Pulse Width Distortion
PWD
-100
-150
100
150
ns
ns
14, 17
17, 16
Propagation Delay Difference
Between Any Two Parts or
Channels
(tPHL - tPLH
PDD
)
Rise Time
tR
tF
50
ns
ns
μs
Fall Time
50
DESAT Sense to 90% VO Delay
tDESAT(90%)
tDESAT(10%)
tDESAT(FAULT)
0.15
0.3
1.5
0.5
CDESAT = 100pF, RF=2.1kΩ, 14, 27, 19
Rg = 20 Ω, Cg = 5 nF,
VCC2 = 30 V
34
DESAT Sense to 10% VO Delay
1.1
μs
μs
CDESAT = 100pF, RF=2.1kΩ , 15, 16,
Rg = 20 Ω, Cg = 5 nF,
VCC2 = 30 V
17, 27,
34
DESAT Sense to Low Level
FAULT Signal Delay
0.25
0.8
CDESAT = 100 pF, RF = 2.1
kΩ, CF = Open, Rg = 20 Ω,
Cg = 5 nF, VCC2 = 30 V
27, 34
18
CDESAT = 100 pF, RF = 2.1
kΩ, CF = 1 nF, Rg = 20 Ω,
Cg = 5 nF, VCC2 = 30 V
DESAT Sense to DESAT
Low Propagation Delay
tDESAT(LOW)
0.25
μs
CDESAT = 100pF, RF = 2.1
27, 34
34
19
20
kΩ, Rg = 20 Ω, Cg = 5 nF,
VCC2 = 30 V
DESAT Input Mute
tDESAT(MUTE)
5
μs
μs
RESET to High Level FAULT
Signal Delay
tRESET(FAULT) 0.3
1
2.0
2.5
CDESAT = 100pF,
RF = 2.1 kΩ,
Rg = 20 Ω, Cg = 5 nF,
VCC1 = 5.5V, VCC2 = 30 V
0.8
1.5
μs
CDESAT = 100pF,
RF = 2.1 kΩ,
Rg = 20 Ω, Cg = 5 nF,
VCC1 = 3.3V, VCC2 = 30 V
Output High Level Common
Mode Transient Immunity
|CMH|
|CML|
15
50
15
50
25
60
25
60
kV/μs TA = 25°C, IF = 10 mA
28, 29, 21
VCM = 1500 V, VCC2 = 30 V, 30, 31
RF = 2.1 kΩ, CF = 15 pF
TA = 25°C, IF = 10 mA
VCM = 1500 V, VCC2 = 30 V,
RF = 2.1 kΩ, CF = 1 nF
21, 26
Output Low Level Common
Mode Transient Immunity
kV/μs TA = 25°C, VF = 0 V
28, 29, 22
VCM = 1500 V, VCC2 = 30 V, 30, 31
RF = 2.1 kΩ, CF = 15 pF
TA = 25°C, VF = 0 V
VCM = 1500 V, VCC2 = 30 V,
RF = 2.1 kΩ, CF = 1 nF
7
Table 7. Package Characteristics
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Fig.
Note
Input-Output Momentary
Withstand Voltage
VISO
5000
Vrms
RH < 50%, t = 1 min.,
TA = 25°C
24, 25
Input-Output Resistance
Input-Output Capacitance
RI-O
> 109
1.3
Ω
V
I-O = 500 V
25
CI-O
pF
freq=1 MHz
TA = 25°C
Output IC-to-Pins 9 &10
Thermal Resistance
θ09-10
30
°C/W
Notes:
1. Derate linearly above 70°C free air temperature at a rate of 0.3 mA/°C.
2. In order to achieve the absolute maximum power dissipation specified, pins 4, 9, and 10 require ground plane connections and may require
airflow. See the Thermal Model section in the application notes at the end of this data sheet for details on how to estimate junction temperature
and power dissipation. In most cases the absolute maximum output IC junction temperature is the limiting factor. The actual power dissipation
achievable will depend on the application environment (PCB Layout, air flow, part placement, etc.). See the Recommended PCB Layout section
in the application notes for layout considerations. Output IC power dissipation is derated linearly at 10 mW/°C above 90°C. Input IC power
dissipation does not require derating.
3. Maximum pulse width = 10 μs. This value is intended to allow for component tolerances for designs with IO peak minimum = 1.0 A.
Derate linearly from 2.0 A at +25°C to 1.5 A at +105°C. This compensates for increased I
4. This supply is optional. Required only when negative gate drive is implemented.
5. Maximum pulse width = 50 μs.
due to changes in V over temperature.
OPEAK
OL
6. See the Slow IGBT Gate Discharge During Fault Condition section in the applications notes at the end of this data sheet for further details.
7. 15 V is the recommended minimum operating positive supply voltage (V - V ) to ensure adequate margin in excess of the maximum V
UVLO+
CC2
E
threshold of 12.5 V. For High Level Output Voltage testing, V is measured with a dc load current. When driving capacitive loads, V will
OH
OH
approach V as I approaches zero units.
CC
OH
8. Maximum pulse width = 1.0 ms.
9. Once V of the ACPL-331J is allowed to go high (V
- V > V
E
), the DESAT detection feature of the ACPL-331J will be the primary source of
O
CC2
UVLO+
IGBT protection. UVLO is needed to ensure DESAT is functional. Once V
is increased from 0V to above V , DESAT will remain functional
UVLO+
CC2
until V
is decreased below V . Thus, the DESAT detection and UVLO features of the ACPL-331J work in conjunction to ensure constant
UVLO-
CC2
IGBT protection.
10. See the DESAT fault detection blanking time section in the applications notes at the end of this data sheet for further details.
11. This is the “increasing”(i.e. turn-on or “positive going”direction) of V - V
CC2
E
12. This is the “decreasing”(i.e. turn-off or “negative going”direction) of V
13. This load condition approximates the gate load of a 1200 V/75A IGBT.
- V
CC2
E
14. Pulse Width Distortion (PWD) is defined as |t
- t | for any given unit.
PHL PLH
15. As measured from I to V .
F
O
16. The difference between t
and t
between any two ACPL-331J parts under the same test conditions.
PLH
PHL
17. As measured from ANODE, CATHODE of LED to V
OUT
18. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low.
19. This is the amount of time the DESAT threshold must be exceeded before VOUT begins to go low, and the FAULT output to go low. This is supply
voltage dependent.
20. Auto Reset: This is the amount of time when VOUT will be asserted low after DESAT threshold is exceeded. See the Description of Operation
(Auto Reset) topic in the application information section.
21. Common mode transient immunity in the high state is the maximum tolerable dV /dt of the common mode pulse, V , to assure that the
CM
CM
output will remain in the high state (i.e., V > 15 V or FAULT > 2 V).
O
22. Common mode transient immunity in the low state is the maximum tolerable dV /dt of the common mode pulse, V , to assure that the
CM
CM
output will remain in a low state (i.e., V < 1.0 V or FAULT < 0.8 V).
O
23. To clamp the output voltage at V - 3 , a pull-down resistor between the output and V is recommended to sink a static current of 650 μA
CC
VBE
EE
while the output is high. See the Output Pull-Down Resistor section in the application notes at the end of this data sheet if an output pull-down
resistor is not used.
24. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 Vrms for 1 second. This test is
performed before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 60747-5-5 Insulation Characteristic Table.
25. This is a two-terminal measurement: pins 1-8 are shorted together and pins 9-16 are shorted together.
26. Split resistors network with a ratio of 1:1 is needed at input LED1. See Figure 31.
8
I
F
t
t
f
r
90%
50%
10%
V
OUT
t
t
PHL
PLH
Figure 1. Timing Curve
0
-0.5
-ꢀ
0.25
0.2
____
= -650uA
I OUT
0.ꢀ5
0.ꢀ
-ꢀ.5
-2
0.05
0
-2.5
-40
-20
0
20
40
60
80
ꢀ05
-40
-20
0
20
40
60
o C
80
ꢀ05
TA - TEMPERATURE - oC
TA - TEMPERATURE -
Figure 2. VOH vs. temperature
Figure 3. VOL vs. temperature
4
30
29
28
27
26
25
_ _ _ _ ꢀ05 oC
_ _ _ _ ꢀ05 oC
______ 25 o C
--------- -40 o C
o
______ 25 C
--------- -40 oC
3
2
ꢀ
0
0.0
0.2
0.4
0.6
0.8
ꢀ.0
0
0.5
ꢀ
ꢀ.5
IOH - OUTPUT HIGH CURRENT - A
IOL - OUTPUT LOW CURRENT - A
Figure 4. VOH vs. IOH
Figure 5. VOL vs. IOL
9
2.65
2.55
2.45
2.35
2.25
3.50
3.25
3.00
2.75
2.50
2.25
2.00
--------- I
CC2
H
L
________ICC2
_
- ---- ---- I
CC2
H
I
________ CC2
L
-40
-20
0
20
40
60
o C
80
105
105
105
15
20
25
30
VCC2 - SUPPLY VOLTAGE - V
T A - TEMPERATURE -
Figure 6. ICC2 vs. temperature
Figure 7. ICC2 vs. VCC2
7.5
-0.20
7.0
6.5
6.0
-0.25
-0.30
-0.35
-40
-20
0
20
40
60
o C
80
-40
-20
0
20
40
60
o C
80
105
T A - TEMPERATURE -
T A -TEMPERATURE -
Figure 8. ICHG vs. temperature
Figure 9. DESAT threshold vs. temperature
300
300
---------- t
---------- t
PLH
PLH
_______tPHL
_______t
PHL
250
200
150
100
250
200
150
100
-40
-20
0
20
40
60
80
15
20
25
30
Vcc - SUPPLY VOLTAGE - V
o
T
- TEMPERATURE -
C
A
Figure 10. Propagation delay vs. temperature
Figure 11. Propagation delay vs. supply voltage
10
300
250
200
150
100
300
200
100
0
---------- t
_______t
PLH
---------- t
_______ t
PLH
PHL
PHL
0
10
20
30
40
50
0
10
20
30
40
50
LOAD RESISTANCE - ohm
LOAD CAPACITANCE - nF
Figure 12. Propagation delay vs. load resistance
Figure 13. Propagation delay vs. load capacitance
250
2.0
------- V CC2 =15V
_____ VCC2 =30V
1.5
200
150
100
1.0
0.5
0.0
-40
-20
0
20
40
60
80
105
-40
-20
0
20
40
60
o C
80
105
T A - TEMPERATURE - o C
T A - TEMPERATURE -
Figure 14. DESAT sense to 90% VOUT delay vs. temperature
Figure 15. DESAT sense to 10% VOUT delay vs. temperature
4.0
0.012
------- VCC2
_____ VCC2
=15V
=30V
------- V CC2 =15V
_____ V CC2 =30V
3.0
2.0
1.0
0.0
0.008
0.004
0.000
10
20
30
LOAD RESISTANCE-ohm
40
50
0
10
20
30
40
50
LOAD CAPACITANCE-nF
Figure 16. DESAT sense to 10% VOUT delay vs. load resistance
Figure 17. DESAT sense to 10% VOUT delay vs. load capacitance
11
1
2
3
4
5
6
7
8
VS
VE 16
VLED 15
VCC1
FAULT
VS
DESAT 14
VCC2 13
0.1μF
15V Pulsed
+
CATHODE
ANODE
ANODE
CATHODE
VEE 12
_
IOUT
VOUT 11
30V
0.1μF
+
_
VCLAMP 10
10mA
VEE
9
Figure 18. IOH Pulsed test circuit
1
2
3
4
5
6
7
8
VS
VE 16
VLED 15
VCC1
FAULT
VS
DESAT 14
VCC2 13
0.1μF
15V Pulsed
CATHODE
ANODE
ANODE
CATHODE
VEE 12
IOUT
VOUT 11
30V
0.1μF
+
_
VCLAMP 10
+
_
VEE
9
Figure 19. IOL Pulsed test circuit
1
2
3
4
5
6
7
8
VS
VE 16
VLED 15
VCC1
FAULT
VS
DESAT 14
VCC2 13
0.1μF
CATHODE
ANODE
ANODE
CATHODE
VEE 12
VOUT
VOUT 11
30V
0.1μF
+
_
VCLAMP 10
650μA
10mA
VEE
9
Figure 20. VOH Pulsed test circuit
12
1
2
3
4
5
6
7
8
VS
VE 16
VLED 15
VCC1
FAULT
VS
DESAT 14
VCC2 13
0.1μF
100mA
CATHODE
ANODE
ANODE
CATHODE
VEE 12
VOUT
VOUT 11
30V
30V
30V
0.1μF
+
_
VCLAMP 10
VEE
9
Figure 21. VOL Pulsed test circuit
1
2
3
4
5
6
7
8
VS
VE 16
VLED 15
VCC1
FAULT
VS
DESAT 14
VCC2 13
0.1μF
ICC2
CATHODE
ANODE
ANODE
CATHODE
VEE 12
VOUT 11
0.1μF
+
_
VCLAMP 10
10mA
VEE
9
Figure 22. ICC2H test circuit
1
2
3
4
5
6
7
8
VS
VE 16
VLED 15
VCC1
FAULT
VS
DESAT 14
VCC2 13
0.1μF
ICC2
CATHODE
ANODE
ANODE
CATHODE
VEE 12
VOUT 11
0.1μF
+
_
VCLAMP 10
VEE
9
Figure 23. ICC2L test circuit
13
1
2
3
4
5
6
7
8
VS
VE 16
VLED 15
ICHG
VCC1
FAULT
VS
DESAT 14
VCC2 13
0.1μF
CATHODE
ANODE
ANODE
CATHODE
VEE 12
VOUT 11
30V
30V
30V
0.1μF
+
_
VCLAMP 10
10mA
VEE
9
Figure 24. ICHG Pulsed test circuit
1
VS
VE 16
VLED 15
_
+
7V
2
VCC1
3
FAULT
VS
DESAT 14
VCC2 13
0.1μF
IDSCHG
4
5
CATHODE
ANODE
ANODE
CATHODE
VEE 12
6
VOUT 11
0.1μF
+
_
7
VCLAMP 10
8
VEE
9
Figure 25. IDSCHG test circuit
1
2
3
4
5
6
7
VS
VE 16
VLED 15
VCC1
FAULT
VS
DESAT 14
VCC2 13
0.1μF
CATHODE
ANODE
ANODE
CATHODE
VEE 12
VOUT
VOUT 11
0.1μF
20Ω
+
_
VCLAMP 10
5nF
8
VEE
9
10mA, 10kHz,
50% Duty Cycle
Figure 26. tPLH, tPHL, tf, tr, test circuit
14
1
2
3
4
5
6
7
8
VS
VE 16
VLED 15
VIN
VCC1
R =2.1kΩ
F
VFAULT
FAULT
VS
DESAT 14
VCC2 13
0.1μF
C
F
+
5V
_
CATHODE
ANODE
ANODE
CATHODE
VEE 12
VOUT
VOUT 11
30V
0.1μF
20Ω
+
_
VCLAMP 10
10mA
5nF
VEE
9
Figure 27. tDESAT fault test circuit
1
VS
VE 16
VLED 15
5V
2
VCC1
R =2.1kΩ
F
SCOPE
3
FAULT
VS
DESAT 14
VCC2 13
C =15pF
F
or 1nF
30V
4
5
6
7
8
0.1μF
CATHODE
ANODE
ANODE
CATHODE
VEE 12
20Ω
VOUT 11
0.1μF
360Ω
VCLAMP 10
5nF
VEE
9
VCM
Figure 28. CMR Test circuit LED2 off
1
VS
VE 16
VLED 15
5V
2
VCC1
R =2.1kΩ
F
SCOPE
3
FAULT
VS
DESAT 14
VCC2 13
C =15pF
F
or 1nF
30V
4
5
6
7
8
0.1μF
CATHODE
ANODE
ANODE
CATHODE
VEE 12
20Ω
VOUT 11
0.1μF
360Ω
VCLAMP 10
5nF
VEE
9
VCM
Figure 29. CMR Test Circuit LED2 on
15
1
2
3
4
5
6
7
8
VS
VE 16
VLED 15
5V
VCC1
R =2.1kΩ
F
DESAT 14
VCC2 13
FAULT
VS
C =15pF
F
or 1nF
30V
0.1μF
CATHODE
ANODE
ANODE
VEE 12
SCOPE
20Ω
VOUT 11
0.1μF
360Ω
VCLAMP 10
5nF
CATHODE
VEE
9
VCM
Figure 30. CMR Test circuit LED1 off
1
2
3
4
5
6
7
8
VS
VE 16
VLED 15
5V
VCC1
R =2.1kΩ
F
DESAT 14
VCC2 13
FAULT
VS
C =15pF
F
or 1nF
30V
5
6
7
8
CATHODE
ANODE
0.1μF
CATHODE
ANODE
ANODE
VEE 12
SCOPE
20Ω
ꢀꢁꢂ
ꢀꢁꢂ
5V
VOUT 11
ANODE
0.1μF
360Ω
VCLAMP 10
CATHODE
5nF
CATHODE
VEE
9
Split resistors network with a ratio of 1:1
VCM
Figure 31. CMR Test Circuit LED1 on
16
13
Application Information
VCC2
UVLO
6, 7
5, 8
Product Overview Description
D
R
I
V
E
R
ANODE
11
The ACPL-331J is a highly integrated power control
device that incorporates all the necessary components
for a complete, isolated IGBT / MOSFET gate drive circuit
with fault protection and feedback into one SO-16
package. Active Miller clamp function eliminates the
need of negative gate drive in most application and
allows the use of simple bootstrap supply for high side
driver. An optically isolated power output stage drives
IGBTs with power ratings of up to 100 A and 1200 V. A
high speed internal optical link minimizes the propaga-
tion delays between the microcontroller and the IGBT
while allowing the two systems to operate at very large
common mode voltage differences that are common
in industrial motor drives and other power switching
applications. An output IC provides local protection
for the IGBT to prevent damage during over current,
and a second optical link provides a fully isolated fault
status feedback signal for the microcontroller. A built
in “watchdog” circuit, UVLO monitors the power stage
supply voltage to prevent IGBT caused by insufficient
gate drive voltages. This integrated IGBT gate driver is
designed to increase the performance and reliability of
a motor drive without the cost, size, and complexity of a
discrete design.
VOUT
CATHODE
DESAT
LED1
14
DESAT
9, 12
VEE
SHIELD
LED2
VCLAMP
2
3
10
16
VCC1
VCLAMP
VE
FAULT
1, 4
15
VS
VLED
SHIELD
Figure 32. Block Diagram of ACPL-331J
Recommended Application Circuit
The ACPL-331J has an LED input gate control, and an
open collector fault output suitable for wired ‘OR’ ap-
plications. The recommended application circuit shown
in Figure 33 illustrates a typical gate drive implementa-
tion using the ACPL-331J. The following describes about
driving IGBT. However, it is also applicable to MOSFET.
Depending upon the MOSFET or IGBT gate threshold
requirements, designers may want to adjust the VCC
Two light emitting diodes and two integrated circuits
housed in the same SO-16 package provide the input
control circuitry, the output power stage, and two optical
channels. The output Detector IC is designed manufac-
tured on a high voltage BiCMOS/Power DMOS process.
The forward optical signal path, as indicated by LED1,
transmits the gate control signal. The return optical signal
path, as indicated by LED2, transmits the fault status
feedback signal.
supply voltage (Recommended V = 17.5V for IGBT and
12.5V for MOSFET).
CC
The two supply bypass capacitors (0.1 μF) provide the
large transient currents necessary during a switching
transition. Because of the transient nature of the
charging currents, a low current (5mA) power supply
suffices. The desaturation diode D
fast recovery type, t below 75ns (e.g. ERA34-10) and
600V/1200V
DESAT
rr
capacitor C
are necessary external components for
BLANK
Under normal operation, the LED1 directly controls the
IGBT gate through the isolated output detector IC, and
LED2 remains off. When an IGBT fault is detected, the
output detector IC immediately begins a “soft” shutdown
sequence, reducing the IGBT current to zero in a con-
trolled manner to avoid potential IGBT damage from
inductive over voltages. Simultaneously, this fault status
is transmitted back to the input via LED2, where the fault
latch disables the gate control input and the active low
fault output alerts the microcontroller.
the fault detection circuitry. The gate resistor R serves to
limit gate charge current and controls the IGBT collector
voltage rise and fall times. The open collector fault
G
output has a passive pull-up resistor R (2.1 kΩ) and a
F
1000 pF filtering capacitor, C . A 47 kΩ pull down resistor
F
R
on V
provides a predictable high level
PULL-DOWN
OUT
output voltage (V ). In this application, the IGBT gate
OH
driver will shut down when a fault is detected and fault
reset by next cycle of IGBT turn on. Application notes are
mentioned at the end of this datasheet.
During power-up, the Under Voltage Lockout (UVLO)
feature prevents the application of insufficient gate
voltage to the IGBT, by forcing the ACPL-331J’s output
low. Once the output is in the high state, the DESAT (V
)
CE
detection feature of the ACPL-331J provides IGBT pro-
tection. Thus, UVLO and DESAT work in conjunction to
provide constant IGBT protection.
17
1
2
3
4
5
6
7
8
VS
VE 16
VLED 15
0.1μF
VCC1
CBLANK
100 Ω
RF
CF
DDESAT
0.1μF
+
FAULT
VS
DESAT 14
VCC2 13
_
CATHODE
ANODE
ANODE
CATHODE
VEE 12
+ HVDC
+
_
RG
+
VCE
-
VOUT 11
VCLAMP 10
VEE
Q1
Q2
R
3-PHASE
AC
RPULL-DOWN
+
_
+
VCE
-
9
- HVDC
Figure 33. Recommended application circuit (Single Supply) with desaturation detection and active Miller Clamp
Description of Operation
Normal Operation
During normal operation, V
trolled by input LED current I (pins 5, 6, 7 and 8), with
the IGBT collector-to-emitter voltage being monitored
through DESAT. The FAULT output is high. See Figure 34.
of the ACPL-331J is con-
is an internal feedback channel which brings the FAULT
output low for the purpose of notifying the micro-con-
troller of the fault condition.
OUT
F
Fault Reset
Fault Condition
Once fault is detected, the output will be muted for 5 ꢀs
(minimum). All input LED signals will be ignored during
the mute period to allow the driver to completely soft
The DESAT pin monitors the IGBT Vce voltage. When the
voltage on the DESAT pin exceeds 6.5 V while the IGBT
is on, VOUT is slowly brought low in order to “softly” shut-down the IGBT. The fault mechanism can be reset by
turn-off the IGBT and prevent large di/dt induced
voltages. Also Figure 34. Fault Timing diagram activated
the next LED turn-on after the 5us (minimum) mute time.
See Figure 34.
tDESAT(LOW)
IF
Reset done
during the next
LED turn-on
6.5V
VDESAT
tBLANK
tDESAT(10%)
90%
VOUT
10%
tRESET(FAULT)
tDESAT(90%)
FAULT
50%
50%
tDESAT(FAULT)
tDESAT(MUTE)
Figure 34. Fault Timing diagram
18
Output Control
Slow IGBT Gate Discharge during Fault Condition
The outputs (V
trolled by the combination of I , UVLO and a detected
IGBT Desat condition. Once UVLO is not active (V
and FAULT) of the ACPL-331J are con-
When a desaturation fault is detected, a weak pull-down
device in the ACPL-331J output drive stage will turn on
to ‘softly’ turn off the IGBT. This device slowly discharges
the IGBT gate to prevent fast changes in drain current
that could cause damaging voltage spikes due to lead
and wire inductance. During the slow turn off, the large
output pull-down device remains off until the output
OUT
F
-
CC2
V > V
), V
UVLO
is allowed to go high, and the DESAT
E
OUT
(pin 14) detection feature of the ACPL-331J will be the
primary source of IGBT protection. Once V is increased
from 0V to above V
CC2
, DESAT will remain functional
UVLO+
until V
is decreased below V
. Thus, the DESAT
voltage falls below V + 2 Volts, at which time the large
pull down device clamps the IGBT gate to V .
EE
CC2
UVLO-
EE
detection and UVLO features of the ACPL-331J work in
conjunction to ensure constant IGBT protection.
DESAT Fault Detection Blanking Time
Desaturation Detection and High Current Protection
The DESAT fault detection circuitry must remain disabled
for a short time period following the turn-on of the IGBT
to allow the collector voltage to fall below the DESAT
threshold. This time period, called the DESAT blanking
time is controlled by the internal DESAT charge current,
the DESAT voltage threshold, and the external DESAT
capacitor.
The ACPL-331J satisfies these criteria by combining a
high speed, high output current driver, high voltage
optical isolation between the input and output, local
IGBT desaturation detection and shut down, and an
optically isolated fault status feedback signal into a single
16-pin surface mount package.
The fault detection method, which is adopted in the
ACPL-331J is to monitor the saturation (collector)
voltage of the IGBT and to trigger a local fault shutdown
sequence if the collector voltage exceeds a predeter-
mined threshold. A small gate discharge device slowly
reduces the high short circuit IGBT current to prevent
damaging voltage spikes. Before the dissipated energy
can reach destructive levels, the IGBT is shut off. During
the off state of the IGBT, the fault detect circuitry is simply
disabled to prevent false ‘fault’signals.
The nominal blanking time is calculated in terms of
external capacitance (C
BLANK
(V
), and DESAT charge current (I
DESAT
C
x V
/ I
. The nominal blanking time with
BLANK
DESAT
CHG
the recommended 100pF capacitor is 100pF * 6.5 V / 240
μA = 2.7 μsec.
The capacitance value can be scaled slightly to adjust the
blanking time, though a value smaller than 100 pF is not
recommended. This nominal blanking time represents
the longest time it will take for the ACPL-331J to respond
to a DESAT fault condition. If the IGBT is turned on while
the collector and emitter are shorted to the supply rails
(switching into a short), the soft shut-down sequence
will begin after approximately 3 μsec. If the IGBT collector
and emitter are shorted to the supply rails after the IGBT
is already on, the response time will be much quicker due
to the parasitic parallel capacitance of the DESAT diode.
The recommended 100pF capacitor should provide
adequate blanking as well as fault response times for
most applications.
The alternative protection scheme of measuring IGBT
current to prevent desaturation is effective if the short
circuit capability of the power device is known, but
this method will fail if the gate drive voltage decreases
enough to only partially turn on the IGBT. By directly
measuring the collector voltage, the ACPL-331J limits
the power dissipation in the IGBT even with insufficient
gate drive voltage. Another more subtle advantage of the
desaturation detection method is that power dissipation
in the IGBT is monitored, while the current sense method
relies on a preset current threshold to predict the safe
limit of operation. Therefore, an overly conservative over
current threshold is not needed to protect the IGBT.
I
UVLO(V -V )
DESAT Function
Not Active
Pin 3 (FAULT) Output
High
V
OUT
F
CC2
E
ON
ON
ON
OFF
OFF
Active
Low
Low
High
Low
Low
Not Active
Not Active
Active
Active (with DESAT fault)
Active (no DESAT fault)
Not Active
Low (FAULT)
High (or no fault)
High
Not Active
Not Active
High
19
Under Voltage Lockout
1
2
3
4
5
6
7
8
VS
VE 16
VLED 15
The ACPL-331J Under Voltage Lockout (UVLO) feature is
designed to prevent the application of insufficient gate
voltage to the IGBT by forcing the ACPL-331J output
low during power-up. IGBTs typically require gate
voltages of 15 V to achieve their rated V
At gate voltages below 13 V typically, the V
increases dramatically, especially at higher currents.
At very low gate voltages (below 10 V), the IGBT may
operate in the linear region and quickly overheat.
The UVLO function causes the output to be clamped
VCC1
FAULT
VS
DESAT 14
VCC2 13
VCC
voltage.
voltage
CE(ON)
CE(ON)
CATHODE
ANODE
ANODE
CATHODE
VEE 12
RG
VOUT 11
VCLAMP 10
RPULL-DOWN
whenever insufficient operating supply (V ) is applied.
CC2
Once V
exceeds V
(the positive-going UVLO
CC2
UVLO+
VEE
9
threshold), the UVLO clamp is released to allow the
device output to turn on in response to input signals. As
V
is increased from 0 V (at some level below V
),
CC2
UVLO+
Figure 35. Output pull-down resistor.
first the DESAT protection circuitry becomes active. As
is further increased (above V ), the UVLO clamp
V
CC2
UVLO+
DESAT Pin Protection Resistor
is released. Before the time the UVLO clamp is released,
the DESAT protection is already active. Therefore, the
UVLO and DESAT Fault detection feature work together
to provide seamless protection regardless of supply
The freewheeling of flyback diodes connected across
the IGBTs can have large instantaneous forward voltage
transients which greatly exceed the nominal forward
voltage of the diode. This may result in a large negative
voltage spike on the DESAT pin which will draw substan-
tial current out of the driver if protection is not used. To
limit this current to levels that will not damage the driver
IC, a 100 ohm resistor should be inserted in series with
the DESAT diode. The added resistance will not alter the
DESAT threshold or the DESAT blanking time.
voltage (V ).
CC2
Active Miller Clamp
A Miller clamp allows the control of the Miller current
during a high dV/dt situation and can eliminate the use
of a negative supply voltage in most of the applications.
During turn-off, the gate voltage is monitored and the
clamp output is activated when gate voltage goes below
2V (relative to V ). The clamp voltage is V +2.5V typ
for a Miller current up to 1100mA. The clamp is disabled
when the LED input is triggered again.
1
2
3
4
5
6
7
8
VS
VE 16
VLED 15
EE
OL
100pF
100 Ω
VCC1
DDESAT
FAULT
VS
DESAT 14
VCC2 13
Other Recommended Components
VCC
The application circuit in Figure 33 includes an output
pull-down resistor, a DESAT pin protection resistor, a
FAULT pin capacitor, and a FAULT pin pullup resistor and
Active Miller Clamp connection.
CATHODE
ANODE
ANODE
CATHODE
VEE 12
RG
VOUT 11
Output Pull-Down Resistor
VCLAMP 10
During the output high transition, the output voltage
VEE
9
rapidly rises to within 3 diode drops of V . If the output
CC2
current then drops to zero due to a capacitive load, the
output voltage will slowly rise from roughly V -3(V
)
CC2
BE
Figure 36. DESAT pin protection.
to V
within a period of several microseconds. To limit
CC2
the output voltage to V -3(V ), a pull-down resistor,
CC2
BE
R
between the output and V is recommend-
PULL-DOWN
EE
ed to sink a static current of several 650 μA while the
output is high. Pull-down resistor values are dependent
on the amount of positive supply and can be adjusted
according to the formula, R
650 μA.
= [V -3 * (V )] /
pull-down
CC2 BE
20
Capacitor on FAULT Pin for High CMR
Pull-up Resistor on FAULT Pin
Rapid common mode transients can affect the fault pin
voltage while the fault output is in the high state. A 1000
pF capacitor should be connected between the fault pin
and ground to achieve adequate CMOS noise margins at
the specified CMR value of 50 kV/μs.
The FAULT pin is an open collector output and therefore
requires a pull-up resistor to provide a high-level signal.
Also the FAULT output can be wire ‘OR’ed together with
other types of protection (e.g. over-temperature, over-
voltage, over-current ) to alert the microcontroller.
Other Possible Application Circuit (Output Stage)
1
2
3
4
5
6
7
8
VS
VE 16
VLED 15
DESAT 14
VCC2 13
VEE 12
0.1μF 0.1μF
VCC1
FAULT
VS
Optional R2
0.1μF
CATHODE
ANODE
ANODE
CATHODE
+ HVDC
+
_
RG
Optional R1
+
VCE
-
VOUT 11
Q1
Q2
3-PHASE
AC
10
VCLAMP
+
RPULL-DOWN
_
+
VCE
-
*
VEE
9
- HVDC
Figure 37. IGBT drive with negative gate drive, external booster and desaturation detection (VCLAMP should be connected to VEE when it is not used) VCLAMP is
used as secondary gate discharge path. * indicates component required for negative gate drive topology
1
2
3
4
5
6
7
8
VS
VE 16
VLED 15
DESAT 14
VCC2 13
VEE 12
0.1μF 0.1μF
VCC1
FAULT
VS
Optional R2
0.1μF
CATHODE
ANODE
ANODE
CATHODE
+ HVDC
+
_
RG
Optional R1
+
VCE
-
VOUT 11
Q1
Q2
3-PHASE
AC
10
VCLAMP
RPULL-DOWN
+
VCE
-
*
VEE
9
- HVDC
R3
Figure 38. Large IGBT drive with negative gate drive, external booster. VCLAMP control secondary discharge path for higher power application.
21
Thermal Model
where P = power into input IC and P = power into
The ACPL-331J is designed to dissipate the majority of
the heat through pins 1, 4, 5 & 8 for the input IC and pins
i
o
output IC. Since θ and θ
are dependent on PCB
5A
9,12A
layout and airflow, their exact number may not be
available. Therefore, a more accurate method of calcu-
lating the junction temperature is with the following
equations:
9 & 12 for the output IC. (There are two V pins on the
EE
output side, pins 9 and 12, for this purpose.) Heat flow
through other pins or through the package directly into
ambient are considered negligible and not modeled
here.
T = P θ + T
ji
i
i5
P5
In order to achieve the power dissipation specified in
the absolute maximum specification, it is imperative
that pins 5, 9, and 12 have ground planes connected to
them. As long as the maximum power specification is
not exceeded, the only other limitation to the amount
of power one can dissipate is the absolute maximum
junction temperature specification of 125°C. The junction
temperatures can be calculated with the following
equations:
T
= P θ
+ T
jo
o
o9,12 P9,12
These equations, however, require that the pin 5 and pins
9, 12 temperatures be measured with a thermal couple
on the pin at the ACPL-331J package edge.
If the calculated junction temperatures for the thermal
model in Figure 39 is higher than 125°C, the pin tem-
perature for pins 9 and 12 should be measured (at the
package edge) under worst case operating environment
for a more accurate estimate of the junction tempera-
tures.
T = P (θ + θ ) + T
ji
i
i5
5A
A
T
jo
= Po (θ
+ θ
) + T
9,12A A
o9,12
Tji = junction temperature of input side IC
Tjo = junction temperature of output side IC
Tji
Tjo
T
T
P5 = pin 5 temperature at package edge
P9,12 = pin 9 and 12 temperature at package edge
TI1 = 60°C/W
Tl9, 12 = 30°C/W
θI5 = input side IC to pin 5 thermal resistance
θ
θ
θ
o9,12 = output side IC to pin 9 and 12 thermal resistance
5A = pin 5 to ambient thermal resistance
9,12A = pin 9 and 12 to ambient thermal resistance
TP9, 12
9, 12A = 50°C/W*
TP1
T
1A = 50°C/W*
T
*The θ5A and θ9,12A values shown here are for PCB layouts with reasonable air flow.
This value may increase or decrease by a factor of 2 depending on PCB layout and/or airflow.
TA
Figure 39. ACPL-331J Thermal Model
Related Application Notes
AN5314 – Active Miller Clamp
AN5324 - Desaturation Fault Detection
AN5315 – “Soft”Turn-off Feature
AN1043 – Common-Mode Noise : Sources and Solutions
AN02-0310EN - Plastics Optocoupler Product ESD and Moisture Sensitivity
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved.
AV02-0119EN - October 25, 2012
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