ACPL-333J-000E [AVAGO]
2.5 Amp Output Current IGBT Gate Driver Optocoupler with Integrated; 2.5安培输出电流IGBT栅极驱动光电耦合器与集成型号: | ACPL-333J-000E |
厂家: | AVAGO TECHNOLOGIES LIMITED |
描述: | 2.5 Amp Output Current IGBT Gate Driver Optocoupler with Integrated |
文件: | 总23页 (文件大小:304K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ACPL-333J
2.5 Amp Output Current IGBT Gate Driver Optocoupler
with Integrated (V ) Desaturation Detection, UVLO
CE
Fault Status Feedback, Active Miller Clamp and Auto-Fault Reset
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
The ACPL-333J is an advanced 2.5 A output current, easy- • 2.5 A maximum peak output current
to-use, intelligent gate drivers which make IGBT V fault
protection compact, affordable, and easy-to implement.
CE
• 2.0 A minimum peak output current
• 250 ns maximum propagation delay over temperature
Features such as integrated V detection, under voltage
CE
range
lockout (UVLO), “soft” IGBT turn-off, isolated open
collector fault feedback, active Miller clamping and Auto- • 1.7A Active Miller Clamp.Clamp pin short to V if not
EE
fault reset provide maximum design flexibility and circuit
protection.
used
• Desaturation Detection
The ACPL-333J contains a AlGaAs LED. The LED is optically
coupled to an integrated circuit with a power output
stage. ACPL-333J are ideally suited for driving power IGBTs
and MOSFETs used in motor control inverter applications.
The voltage and current supplied by these optocouplers
make them ideally suited for directly driving IGBTs with
ratings up to 1200 V and 150 A. For IGBTs with higher
ratings, the ACPL-333J can be used to drive a discrete
power stage which drives the IGBT gate. The ACPL-333J
• Under Voltage Lock-Out Protection (UVLO) with
Hysteresis
• Open Collector Isolated fault feedback
•
“Soft”IGBT Turn-off
• Automatic Fault Reset after fixed mute time , typical
26μs
• Available in SO-16 package
• 100 ns maximum pulse width distortion (PWD)
have an insulation voltage of V
= 1230 V
.
IORM
PEAK
• 50 kV/μs minimum common mode rejection (CMR) at
Block Diagram
V
= 1500 V
CM
13
• I
< 5 mA maximum supply current
VCC2
CC(max)
UVLO
• Wide V operating range: 15 V to 30 V over
CC
6, 7
5, 8
D
R
I
V
E
R
temperature range
ANODE
11
VOUT
• Wide operating temperature range: –40°C to 105°C
CATHODE
DESAT
LED1
14
• Safety approvals: UL approval, 5000 V
for 1 minute,
RMS
DESAT
CSA approval, IEC/EN/DIN-EN 60747-5-5 approval
= 1230 V
9, 12
VEE
V
IORM
PEAK
SHIELD
LED2
VCLAMP
Applications
2
3
10
16
VCC1
VCLAMP
VE
• Isolated IGBT/Power MOSFET gate drive
• AC and brushless DC motor drives
FAULT
• Industrial inverters and Uninterruptible Power Supply
(UPS)
1, 4
15
VS
VLED
SHIELD
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Pin Description
Pin
1
Symbol
VS
Description
Input Ground
1
2
3
4
5
6
7
8
VS
VE 16
VLED 15
2
VCC1
FAULT
Positive input supply voltage. (3.3 V to 5.5 V)
3
Fault output. FAULT changes from a high impedance state
to a logic low output within 5 μs of the voltage on the
DESAT pin exceeding an internal reference voltage of 6.5 V.
FAULT output is an open collector which allows the FAULT
outputs from all ACPL-333J in a circuit to be connected
together in a “wired OR”forming a single fault bus for inter-
facing directly to the micro-controller.
VCC1
FAULT
VS
DESAT 14
VCC2 13
4
VS
Input Ground
CATHODE
ANODE
ANODE
CATHODE
VEE 12
5
CATHODE Cathode
6
ANODE
ANODE
Anode
Anode
VOUT 11
7
8
CATHODE Cathode
VCLAMP 10
9
VEE
Output supply voltage.
VEE
9
10
11
12
13
14
VCLAMP
VOUT
VEE
Miller clamp
Gate drive voltage output
Output supply voltage.
Positive output supply voltage
VCC2
DESAT
Desaturation voltage input. When the voltage on DESAT
exceeds an internal reference voltage of 6.5 V while
the IGBT is on, FAULT output is changed from a high
impedance state to a logic low state within 5 μs.
15
16
VLED
LED anode. This pin must be left unconnected for guaran-
teed data sheet performance. (For optical coupling testing
only)
VE
Common (IGBT emitter) output supply voltage.
Ordering Information
ACPL-333J is UL Recognized with 5000 Vrms for 1 minute per UL1577.
Option
Surface
Mount
IEC/EN/DIN EN
60747-5-5
Part number
RoHS Compliant
-000E
Package
Tape& Reel
Quantity
ACPL-333J
SO-16
45 per tube
850 per reel
X
X
X
X
-500E
X
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACPL-333J-500E to order product of SO-16 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN
60747-5-5 Safety Approval in RoHS compliant.
Example 2:
ACPL-333J-000E to order product of SO-16 Surface Mount package in tube packaging with IEC/EN/DIN EN
60747-5-5 Safety Approval and RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and
RoHS compliant option will use ‘-XXXE‘.
2
Package Outline Drawings
ACPL-333J 16-Lead Surface Mount Package
0.018
(0.457)
0.050
(1.270)
LAND PATTERN RECOMMENDATION
16 15 14 13 12 11 10
9
TYPE NUMBER
DATE CODE
A 333J
YYWW
0.458 (11.63)
0.295 ± 0.010
(7.493 ± 0.254)
0.085 (2.16)
1
2
3
4
5
6
7
8
0.406 ± 0.10
(10.312 ± 0.254)
0.025 (0.64)
0.345 ± 0.010
(8.763 ± 0.254)
ALL LEADS
TO BE
9°
COPLANAR
± 0.002
0.138 ± 0.005
(3.505 ± 0.127)
0.018
(0.457)
0- 8°
0.008 ± 0.003
(0.203 ± 0.076)
STANDOFF
0.025 MIN.
0.408 ± 0.010
(10.363 ± 0.254)
Dimensions in inches (millimeters)
Notes: Initial and continued variation in the color of the ACPL-333J’s white mold compound is normal and does note affect device performance or
reliability.
Floating Lead Protrusion is 0.25 mm (10 mils) max.
Recommended Pb-Free IR Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
3
Regulatory Information
The ACPL-333J is approved by the following organizations:
IEC/EN/DIN EN 60747-5-5
UL
Approval under:
Approval under UL 1577, component recognition
DIN EN 60747-5-5 (VDE 0884-5):2011-11
EN 60747-5-5:2011
program up to V = 5000 V . File E55361.
ISO
RMS
CSA
Approval under CSA Component Acceptance Notice #5,
File CA 88324.
Table 1. IEC/EN/DIN EN 60747-5-5 Insulation Characteristics*
Description
Symbol
Characteristic
Unit
Installation classification per DIN VDE 0110/39, Table 1
for rated mains voltage ≤ 150 Vrms
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 600 Vrms
for rated mains voltage ≤ 1000Vrms
I – IV
I – IV
I – IV
I – III
Climatic Classification
40/100/21
2
Pollution Degree (DIN VDE 0110/39)
Maximum Working Insulation Voltage
VIORM
VPR
1230
2306
Vpeak
Vpeak
Input to Output Test Voltage, Method b**,
VIORM x 1.875=VPR, 100% Production Test with tm=1 sec, Partial discharge < 5 pC
Input to Output Test Voltage, Method a**,
VPR
1968
8000
Vpeak
Vpeak
V
IORM x 1.6=VPR, Type and Sample Test, tm=10 sec, Partial discharge < 5 pC
Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec)
VIOTM
Safety-limiting values – maximum values allowed in the event of a failure.
Case Temperature
TS
175
°C
Input Current
IS, INPUT
PS, OUTPUT
RS
400
mA
mW
Ω
Output Power
1200
>109
Insulation Resistance at TS, VIO = 500 V
*
Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.
Surface mount classification is class A in accordance with CECCOO802.
** Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section IEC/EN/
DIN EN 60747-5-5, for a detailed description of Method a and Method b partial discharge test profiles.
Dependence of Safety Limiting Values on Temperature. (take from DS AV01-0579EN Pg.7)
4
Table 2. Insulation and Safety Related Specifications
Parameter
Symbol
ACPL-333J Units
Conditions
Minimum External Air
Gap (Clearance)
L(101)
8.3
8.3
0.5
mm
mm
mm
Measured from input terminals to output terminals, shortest
distance through air.
Minimum External
Tracking (Creepage)
L(102)
CTI
Measured from input terminals to output terminals, shortest
distance path along body.
Minimum Internal
Plastic Gap (Internal
Clearance)
Through insulation distance conductor to conductor, usually the
straight line distance thickness between the emitter and detector.
Tracking Resistance
(Comparative Tracking
Index)
>175
IIIa
V
DIN IEC 112/VDE 0303 Part 1
Isolation Group
Material Group (DIN VDE 0110, 1/89, Table 1)
Table 3. Absolute Maximum Ratings
Parameter
Symbol
Min.
-55
-40
Max.
125
105
Units
°C
Note
Storage Temperature
Operating Temperature
TS
TA
°C
2
Output IC Junction Temperature
Average Input Current
TJ
125
25
°C
mA
A
2
1
IF(AVG)
IF(TRAN)
Peak Transient Input Current,
(<1 μs pulse width, 300pps)
1.0
Reverse Input Voltage
VR
5
V
“High”Peak Output Current
“Low”Peak Output Current
Positive Input Supply Voltage
FAULT Output Current
IOH(PEAK)
IOL(PEAK)
VCC1
2.5
A
3
3
2.5
A
-0.5
7.0
V
IFAULT
VFAULT
8.0
mA
V
FAULT Pin Voltage
-0.5
-0.5
-0.5
-0.5
-0.5
VCC1
33
Total Output Supply Voltage
Negative Output Supply Voltage
Positive Output Supply Voltage
Gate Drive Output Voltage
Peak Clamping Sinking Current
Miller Clamping Pin Voltage
DESAT Voltage
(VCC2 - VEE)
(VE - VEE)
(VCC2 - VE)
VO(PEAK)
IClamp
V
15
V
6
33 - (VE - VEE)
VCC2
1.7
V
V
A
VClamp
VDESAT
PO
-0.5
VE
VCC2
VE + 10
600
V
V
Output IC Power Dissipation
Input IC Power Dissipation
Solder Reflow Temperature Profile
mW
mW
2
2
PI
150
See Package Outline Drawings section
Table 4. Recommended Operating Conditions
Parameter
Symbol
TA
Min.
- 40
15
Max.
105
Units
°C
V
Note
Operating Temperature
Total Output Supply Voltage
Negative Output Supply Voltage
Positive Output Supply Voltage
Input Current (ON)
2
7
4
(VCC2 - VEE)
(VE - VEE)
(VCC2 - VE)
IF(ON)
30
0
15
V
15
30 - (VE - VEE)
V
8
12
mA
V
Input Voltage (OFF)
VF(OFF)
- 3.6
0.8
5
Table 5. Electrical Specifications (DC)
Unless otherwise noted, all typical values at T = 25°C, V
- V = 30 V, V - V = 0 V;
EE E EE
A
CC2
all Minimum/Maximum specifications are at Recommended Operating Conditions. Positive Supply Voltage used.
Parameter
Symbol
Min.
Typ.
0.1
Max.
0.4
Units
V
Test Conditions
Fig.
Note
FAULT Logic Low
Output Voltage
VFAULTL
IFAULT = 1.1 mA, VCC1 = 5.5V
IFAULT = 1.1 mA, VCC1 = 3.3V
VFAULT = 5.5 V, VCC1 = 5.5V
0.1
0.4
V
FAULT Logic High
Output Current
IFAULTH
0.02
0.002
-1.5
0.5
μA
μA
A
0.3
VFAULT = 3.3 V, VCC1 = 3.3V
High Level Output Current
IOH
-0.5
-2.0
0.5
VO = VCC2 - 4
2, 6,
21
5
3
5
3
6
A
VO = VCC2 – 15
VO = VEE + 2.5
VO = VEE + 15
VOUT - VEE = 14 V
Low Level Output Current
IOL
1.5
A
3, 7,
22
2.0
A
Low Level Output Current
During Fault Condition
IOLF
VOH
140
mA
High Level Output Voltage
VCC-2.9 VCC-2.0
V
IO = -650 μA
IO = 100 mA
4,
23
7, 8, 9
23
Low Level Output Voltage
VOL
0.17
2.0
0.5
V
V
5, 24
Clamp Pin Threshold
Voltage
VtClamp
Clamp Low Level Sinking
Current
ICL
0.35
1.1
A
VO = VEE + 2.5
8
High Level Supply Current
Low Level Supply Current
ICC2H
ICC2L
2.5
2.5
5
5
mA
mA
IO = 0 mA
IO = 0 mA
9, 10,
25,
26
9
Blanking Capacitor
Charging Current
ICHG
-0.13
10
-0.24
30
-0.33
mA
mA
VDESAT = 2 V
11, 27 9, 10
Blanking Capacitor
Discharge Current
IDSCHG
VDESAT = 7.0 V
28
DESAT Threshold
UVLO Threshold
VDESAT
VUVLO+
6
6.5
7.5
V
V
VCC2 -VE >VUVLO-
VO > 5 V
12
9
10.5
11.6
12.5
7, 9,
11
VUVLO-
9.2
0.4
10.3
1.3
11.1
6
V
VO < 5 V
7, 9,
12
UVLO Hysteresis
(VUVLO+
- VUVLO-
V
)
Threshold Input Current
Low to High
IFLH
2.0
mA
V
IO = 0 mA, VO > 5 V
Threshold Input Voltage
High to Low
VFHL
0.8
1.2
Input Forward Voltage
VF
1.6
1.95
V
IF = 10 mA
Temperature Coefficient
of Input Forward Voltage
ΔVF/ΔTA
-1.3
mV/°C
Input Reverse Breakdown
Voltage
BVR
CIN
5
V
IR = 10 μA
Input Capacitance
70
pF
f = 1 MHz, VF = 0 V
6
Table 6. Switching Specifications (AC)
Unless otherwise noted, all typical values at T = 25°C, V
- V = 30 V, V - V = 0 V;
EE E EE
A
CC2
all Minimum/Maximum specifications are at Recommended Operating Conditions. Only Positive Supply Voltage used.
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Fig.
Note
Propagation Delay Time
to High Output Level
tPLH
100
180
250
ns
Rg = 10 Ω,
1, 13,
14, 15,
16, 29
13, 15
Cg = 10 nF,
f = 10 kHz,
Duty Cycle = 50%,
IF = 10 mA,
VCC2 = 30 V
Propagation Delay Time
to Low Output Level
tPHL
100
180
20
250
ns
1, 13,
14, 15,
16, 29
Pulse Width Distortion
PWD
-100
-150
100
150
ns
ns
14, 17
17, 16
Propagation Delay
(tPHL - tPLH
)
Difference Between Any
Two Parts or Channels
PDD
Rise Time
Fall Time
tR
tF
50
ns
ns
μs
50
DESAT Sense to
90% VO Delay
tDESAT(90%)
0.15
0.5
3
CDESAT = 100pF, Rg = 10 Ω,
17, 30
19
18
Cg = 10 nF, VCC2 = 30 V
DESAT Sense to
10% VO Delay
tDESAT(10%)
2
μs
μs
CDESAT = 100pF, Rg = 10 Ω,
Cg = 10 nF, VCC2 = 30 V
18, 19,
20, 30
DESAT Sense to Low Level tDESAT(FAULT)
FAULT Signal Delay
0.25
0.5
CDESAT = 100 pF, RF = 2.1 kΩ, 30
CF = Open, Rg = 10 Ω,
Cg = 10 nF, VCC2 = 30 V
0.8
CDESAT = 100 pF, RF = 2.1 kΩ,
CF = 1 nF, Rg = 10 Ω,
Cg = 10 nF, VCC2 = 30 V
DESAT Sense to DESAT
Low Propagation Delay
tDESAT(LOW)
0.25
μs
CDESAT = 100pF, RF = 2.1 kΩ, 30
Rg = 10 Ω, Cg = 10 nF,
VCC2 = 30 V
19
20
DESAT Input Mute
tDESAT(MUTE) 15
26
25
60
25
60
40
μs
CDESAT = 100pF, RF = 2.1 kΩ,
Rg = 10 Ω, Cg = 10 nF,
VCC1 = 5.5V, VCC2 = 30 V
Output High Level
Common Mode Transient
Immunity
|CMH|
15
50
15
50
kV/μs
TA = 25°C, IF = 10 mA
VCM = 1500 V, VCC2 = 30 V, RF 33, 34
= 2.1 kΩ, CF = 15 pF
31, 32, 21
TA = 25°C, IF = 10 mA
VCM = 1500 V, VCC2 = 30 V, RF
= 2.1 kΩ, CF = 1 nF
21,26
Output Low Level
Common Mode Transient
Immunity
|CML|
kV/μs
TA = 25°C, VF = 0 V
VCM = 1500 V, VCC2 = 30 V, RF 33, 34
= 2.1 kΩ, CF = 15 pF
31, 32, 22
TA = 25°C, VF = 0 V
VCM = 1500 V, VCC2 = 30 V, RF
= 2.1 kΩ, CF = 1 nF
7
Table 7. Package Characteristics
Parameter
Symbol Min.
Typ.
Max. Units
Test Conditions
Fig.
Note
Input-Output Momentary
Withstand Voltage
VISO
5000
Vrms
RH < 50%, t = 1 min., TA = 25°C
24, 25
Input-Output Resistance
Input-Output Capacitance
RI-O
> 109
1.3
Ω
V
I-O = 500 V
25
CI-O
pF
freq=1 MHz
TA = 25°C
Output IC-to-Pins 9 &10
Thermal Resistance
θ09-10
30
°C/W
Notes:
1. Derate linearly above 70°C free air temperature at a rate of 0.3 mA/°C.
2. In order to achieve the absolute maximum power dissipation specified, pins 4, 9, and 10 require ground plane connections and may require
airflow. See the Thermal Model section in the application notes at the end of this data sheet for details on how to estimate junction temperature
and power dissipation. In most cases the absolute maximum output IC junction temperature is the limiting factor. The actual power dissipation
achievable will depend on the application environment (PCB Layout, air flow, part placement, etc.). See the Recommended PCB Layout section
in the application notes for layout considerations. Output IC power dissipation is derated linearly at 10 mW/°C above 90°C. Input IC power
dissipation does not require derating.
3. Maximum pulse width = 10 μs. This value is intended to allow for component tolerances for designs with I peak minimum = 2.0 A. Derate
O
linearly from 3.0 A at +25°C to 2.5 A at +105°C. This compensates for increased I
due to changes in V over temperature.
OPEAK
OL
4. This supply is optional. Required only when negative gate drive is implemented.
5. Maximum pulse width = 50 μs.
6. See the Slow IGBT Gate Discharge During Fault Condition section in the applications notes at the end of this data sheet for further details.
7. 15 V is the recommended minimum operating positive supply voltage (V - V ) to ensure adequate margin in excess of the maximum V
UVLO+
CC2
E
threshold of 12.5V. For High Level Output Voltage testing, V is measured with a dc load current. When driving capacitive loads, V will
OH
OH
approach V as I approaches zero units.
CC
OH
8. Maximum pulse width = 1.0 ms.
9. Once V of the ACPL-333J is allowed to go high (V
- V > V
), the DESAT detection feature of the ACPL-333J will be the primary source of
O
CC2
E
UVLO+
IGBT protection. UVLO is needed to ensure DESAT is functional. Once V
is increased from 0V to above V , DESAT will remain functional
UVLO+
CC2
until V
is decreased below V . Thus, the DESAT detection and UVLO features of the ACPL-333J work in conjunction to ensure constant
UVLO-
CC2
IGBT protection.
10. See the DESAT fault detection blanking time section in the applications notes at the end of this data sheet for further details.
11. This is the “increasing”(i.e. turn-on or “positive going”direction) of V - V
CC2
E
12. This is the “decreasing”(i.e. turn-off or “negative going”direction) of V
- V
CC2
E
13. This load condition approximates the gate load of a 1200 V/150A IGBT.
14. Pulse Width Distortion (PWD) is defined as |t - t | for any given unit.
PHL PLH
15. As measured from I to V .
F
O
16. The difference between t
and t
between any two ACPL-333J parts under the same test conditions.
PLH
PHL
17. As measured from ANODE, CATHODE of LED to V
OUT
18. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low.
19. This is the amount of time the DESAT threshold must be exceeded before V
voltage dependent.
begins to go low, and the FAULT output to go low. This is supply
OUT
20. Fault Reset: This is the amount of time when V
will be asserted low after DESAT threshold is exceeded. See the Description of Operation
OUT
(Fault Reset) topic in the application information section.
21. Common mode transient immunity in the high state is the maximum tolerable dV /dt of the common mode pulse, V , to assure that the
CM
CM
output will remain in the high state (i.e., V > 15 V or FAULT > 2 V).
O
22. Common mode transient immunity in the low state is the maximum tolerable dV /dt of the common mode pulse, V , to assure that the
CM
CM
output will remain in a low state (i.e., V < 1.0 V or FAULT < 0.8 V).
O
23. To clamp the output voltage at V - 3 V , a pull-down resistor between the output and V is recommended to sink a static current of 650 μA
CC
BE
EE
while the output is high. See the Output Pull-Down Resistor section in the application notes at the end of this data sheet if an output pull-down
resistor is not used.
24. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 Vrms for 1 second. This test is
performed before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 60747-5-5 Insulation Characteristic Table.\
25. This is a two-terminal measurement: pins 1-8 are shorted together and pins 9-16 are shorted together.
26. Split resistors network with a ratio of 1:1 is needed at input LED1. See Figure 34.
8
I
F
t
t
f
r
90%
50%
10%
V
OUT
t
t
PHL
PLH
Figure 1. VOUT propagation delay waveforms
3.0
2.5
2.0
1.5
1.0
5
4
3
2
1
0
-----V
___V
=VEE +15V
=VEE +2.5V
OUT
OUT
-40
-20
0
20
40
60
80
105
-40
-20
0
20
40
60
80
105
o
TA - TEMPERATURE - o C
TA - TEMPERATURE -
C
Figure 2. IOH vs. temperature
Figure 3. IOL vs. temperature
0
0.25
0.2
0.15
0.1
0.05
0
____IOUT = -650uA
-0.5
-1
-1.5
-2
-2.5
-40
-20
0
20
40
60
80
105
-40
-20
0
20
40
60
80
100
TA - TEMPERATURE - o C
T A - TEMPERATURE - o C
Figure 4. VOH vs. temperature
Figure 5. VOL vs. temperature
9
30
29
28
27
26
25
8
7
6
5
4
3
2
1
0
_ _ _ _ 105 oC
______ 25 o C
--------- -40 o C
o
_ _ _ _ 100
C
______ 25 o C
o
--------- -40
C
0.0
0.2
0.4
0.6
0.8
1.0
0
0.5
1
1.5
2
2.5
IOH - OUTPUT HIGH CURRENT - A
I
OL - OUTPUT LOW CURRENT - A
Figure 6. VOH vs. IOH
Figure 7. VOL vs. IOL
4
3
2
1
0
3.50
3.25
3.00
2.75
2.50
2.25
2.00
ICC2
H
ICC2L
-40
-20
0
20
40
60
80
105
-40
-20
0
20
40
60
80
105
TA - TEMPERATURE - oC
TA - TEMPERATURE - oC
Figure 8. ICL vs. temperature
Figure 9. ICC2 vs. temperature
2.65
-0.20
ICC2H
I
CC2L
2.55
2.45
-0.25
-0.30
-0.35
2.35
2.25
15
20
25
30
-40
-20
0
20
40
60
80
105
V
CC2 - OUTPUR SUPPLY VOLTAGE - V
TA - TEMPERATURE - qC
Figure 11. ICHG vs. temperature
Figure 10. ICC2 vs. VCC2
10
7.5
7.0
6.5
6.0
300
250
200
150
100
t PLH
t PHL
-40
-20
0
20
40
60
80
105
-40
-20
0
20
40
60
80
105
TA - TEMPERATURE - qC
TA - TEMPERATURE - qC
Figure 13. Propagation delay vs. temperature
Figure 12. DESAT threshold vs. temperature
300
300
t PLH
t PHL
t PLH
t PHL
250
200
150
100
250
200
150
100
0
10
20
30
40
50
15
20
25
30
LOAD RESISTANCE - ohm
Vcc - SUPPLY VOLTAGE - V
Figure 14. Propagation delay vs. supply voltage
Figure 15. Propagation delay vs. load resistance
300
t PLH
t PHL
200
100
0
0
10
20
30
40
50
LOAD CAPACITANCE - nF
Figure 16. Propagation delay vs. load capacitance
11
3.0
2.5
2.0
1.5
1.0
300
250
200
150
100
VCC2 = 15V
CC2 = 30V
V
-40
-20
0
20
40
60
80
105
-40
-20
0
20
40
60
80
105
TA - TEMPERATURE - qC
TA - TEMPERATURE - qC
Figure 17. DESAT sense to 90% VOUT delay vs. temperature
Figure 18. DESAT sense to 10% VOUT delay vs. temperature
4.0
0.012
VCC2 = 15V
VCC2 = 15V
VCC2 = 30V
V
CC2 = 30V
3.0
0.008
0.004
0.000
2.0
1.0
0.0
0
10
20
30
40
50
10
20
30
40
50
LOAD CAPACITANCE - nF
LOAD RESISTANCE - ohm
Figure 19. DESAT sense to 10% VOUT delay vs. load resistance
Figure 20. DESAT sense to 10% VOUT delay vs. load capacitance
12
FAULT
0.1μF
1
2
3
4
5
6
7
8
VS
VE 16
VLED 15
VCC1
DESAT 14
VCC2 13
VS
15V Pulsed
+
CATHODE
ANODE
ANODE
CATHODE
VEE 12
_
IOUT
VOUT 11
30V
30V
30V
0.1μF
+
_
VCLAMP 10
10mA
VEE
9
Figure 21. IOH Pulsed test circuit
1
VS
VE 16
VLED 15
2
VCC1
3
DESAT 14
VCC2 13
FAULT
VS
0.1μF
4
15V Pulsed
5
CATHODE
ANODE
ANODE
VEE 12
IOUT
6
VOUT 11
0.1μF
+
_
7
VCLAMP 10
+
_
8
CATHODE
VEE
9
Figure 22. IOL Pulsed test circuit
1
2
3
4
5
6
VS
VE 16
VLED 15
VCC1
FAULT
VS
DESAT 14
VCC2 13
0.1μF
CATHODE
ANODE
ANODE
CATHODE
VEE 12
VOUT
VOUT 11
0.1μF
+
_
7
VCLAMP 10
650μA
10mA
8
VEE
9
Figure 23. VOH Pulsed test circuit
13
1
2
3
4
5
6
7
8
VS
VE 16
VLED 15
VCC1
FAULT
VS
DESAT 14
VCC2 13
0.1μF
100mA
CATHODE
ANODE
ANODE
CATHODE
VEE 12
VOUT
VOUT 11
30V
30V
30V
0.1μF
+
_
VCLAMP 10
VEE
9
Figure 24. VOL Pulsed test circuit
1
2
3
4
5
6
7
8
VS
VE 16
VLED 15
VCC1
FAULT
VS
DESAT 14
VCC2 13
0.1μF
ICC2
CATHODE
ANODE
ANODE
CATHODE
VEE 12
VOUT 11
0.1μF
+
_
VCLAMP 10
10mA
VEE
9
Figure 25. ICC2H test circuit
1
2
3
4
5
6
7
8
VS
VE 16
VLED 15
VCC1
FAULT
VS
DESAT 14
VCC2 13
0.1μF
I CC2
CATHODE
ANODE
ANODE
CATHODE
VEE 12
VOUT 11
0.1μF
+
_
VCLAMP 10
VEE
9
Figure 26. ICC2L test circuit
14
1
2
3
4
5
6
7
8
VS
VE 16
VLED 15
ICHG
VCC1
FAULT
VS
DESAT 14
VCC2 13
0.1μF
CATHODE
ANODE
ANODE
CATHODE
VEE 12
VOUT 11
30V
0.1μF
+
_
VCLAMP 10
10mA
VEE
9
Figure 27. ICHG Pulsed test circuit
1
2
3
4
5
6
7
8
VS
VE 16
VLED 15
_
+
7V
VCC1
FAULT
VS
DESAT 14
VCC2 13
0.1μF
IDSCHG
CATHODE
ANODE
ANODE
CATHODE
VEE 12
VOUT 11
30V
0.1μF
+
_
VCLAMP 10
VEE
9
Figure 28. IDSCHG test circuit
1
2
3
4
5
6
7
VS
VE 16
VLED 15
VCC1
FAULT
VS
DESAT 14
VCC2 13
0.1μF
CATHODE
ANODE
ANODE
CATHODE
VEE 12
VOUT
VOUT 11
30V
0.1μF
10Ω
+
_
VCLAMP 10
10nF
8
VEE
9
10mA, 10kHz,
50% Duty Cycle
Figure 29. tPLH, tPHL, tf, tr, test circuit
15
1
2
3
4
5
6
7
8
VS
VE 16
VLED 15
VIN
VCC1
R =2.1kΩ
F
VFAULT
FAULT
VS
DESAT 14
VCC2 13
0.1μF
C
F
+
5V
_
CATHODE
ANODE
ANODE
CATHODE
VEE 12
VOUT
VOUT 11
30V
0.1μF
10Ω
+
_
VCLAMP 10
10mA
10nF
VEE
9
Figure 30. tDESAT fault test circuit
1
2
3
4
5
6
7
8
VS
VE 16
VLED 15
5V
VCC1
R =2.1kΩ
SCOPE
F
DESAT 14
VCC2 13
FAULT
VS
C =15pF
F
or 1nF
30V
0.1μF
CATHODE
ANODE
ANODE
VEE 12
10Ω
VOUT 11
0.1μF
360Ω
VCLAMP 10
10nF
CATHODE
VEE
9
VCM
Figure 31. CMR Test circuit LED2 off
1
VS
VE 16
VLED 15
5V
2
VCC1
R =2.1kΩ
F
SCOPE
3
DESAT 14
VCC2 13
FAULT
VS
C =15pF
F
or 1nF
30V
4
5
6
7
8
0.1μF
CATHODE
ANODE
ANODE
VEE 12
10Ω
VOUT 11
0.1μF
360Ω
VCLAMP 10
10nF
CATHODE
VEE
9
VCM
Figure 32. CMR Test Circuit LED2 on
16
1
2
3
4
5
6
7
8
VS
VE 16
VLED 15
5V
VCC1
R =2.1kΩ
F
DESAT 14
VCC2 13
FAULT
C =15pF
F
or 1nF
30V
VS
0.1μF
CATHODE
ANODE
ANODE
CATHODE
VEE 12
SCOPE
10Ω
VOUT 11
0.1μF
360Ω
VCLAMP 10
10nF
VEE
9
VCM
Figure 33. CMR Test circuit LED1 off
1
2
3
4
5
6
7
8
VS
VE 16
VLED 15
5V
VCC1
R =2.1kΩ
F
DESAT 14
VCC2 13
FAULT
VS
C =15pF
F
or 1nF
30V
5
6
7
8
CATHODE
ANODE
0.1μF
CATHODE
ANODE
ANODE
VEE 12
SCOPE
10Ω
VOUT 11
ꢀꢁꢂ
ꢀꢁꢂ
0.1μF
5V
ANODE
Ω
360
VCLAMP 10
10nF
CATHODE
CATHODE
VEE
9
Split resistors network with a ratio of 1:1
VCM
Figure 34. CMR Test Circuit LED1 on
17
Application Information
Product Overview Description
status feedback signal.
The ACPL-333J are highly integrated power control
devices that incorporate all the necessary components
for a complete, isolated IGBT / MOSFET gate drive circuit
with fault protection and feedback into one SO-16
package. Active Miller clamp function eliminates the
need of negative gate drive in most application and
allows the use of simple bootstrap supply for high side
driver. An optically isolated power output stage drives
IGBTs with power ratings of up to 150 A and 1200 V. A
high speed internal optical link minimizes the propaga-
tion delays between the microcontroller and the IGBT
while allowing the two systems to operate at very large
common mode voltage differences that are common
in industrial motor drives and other power switching
applications. An output IC provides local protection
for the IGBT to prevent damage during over current,
and a second optical link provides a fully isolated fault
status feedback signal for the microcontroller. A built
in “watchdog” circuit, UVLO monitors the power stage
supply voltage to prevent IGBT caused by insufficient
gate drive voltages. This integrated IGBT gate driver is
designed to increase the performance and reliability of
a motor drive without the cost, size, and complexity of a
discrete design.
Under normal operation, the LED1 directly controls the
IGBT gate through the isolated output detector IC, and
LED2 remains off. When an IGBT fault is detected, the
output detector IC immediately begins a “soft” shutdown
sequence, reducing the IGBT current to zero in a con-
trolled manner to avoid potential IGBT damage from
inductive over voltages. Simultaneously, this fault status
is transmitted back to the input via LED2, where the fault
latch disables the gate control input and the active low
fault output alerts the microcontroller.
During power-up, the Under Voltage Lockout (UVLO)
feature prevents the application of insufficient gate
voltage to the IGBT, by forcing the ACPL-333J ’s output
low. Once the output is in the high state, the DESAT (VCE)
detection feature of the ACPL-333J provides IGBT pro-
tection. Thus, UVLO and DESAT work in conjunction to
provide constant IGBT protection.
Recommended Application Circuit
The ACPL-333J have an LED input gate control, and an
open collector fault output suitable for wired ‘OR’ appli-
cations. The recommended application circuit shown in
Figure 36 (page 21) illustrates a typical gate drive imple-
mentation using the ACPL-333J. The following describes
about driving IGBT. However, it is also applicable to
MOSFET. Depending upon the MOSFET or IGBT gate
threshold requirements, designers may want to adjust
Two light emitting diodes and two integrated circuits
housed in the same SO-16 package provide the input
control circuitry, the output power stage, and two optical
channels. The output Detector IC is designed manufac-
tured on a high voltage BiCMOS/Power DMOS process.
The forward optical signal path, as indicated by LED1,
transmits the gate control signal. The return optical
signal path, as indicated by LED2, transmits the fault
the VCC supply voltage (Recommended V = 17.5V for
IGBT and 12.5V for MOSFET).
CC
The two supply bypass capacitors (0.1 μF) provide the
large transient currents necessary during a switching
transition. Because of the transient nature of the
charging currents, a low current (5mA) power supply
13
VCC2
UVLO
6, 7
5, 8
D
R
I
V
E
R
suffices. The desaturation diode D
600V/1200V
DESAT
ANODE
11
fast recovery type, t below 75ns (e.g. ERA34-10) and
rr
VOUT
CATHODE
capacitor C
are necessary external components for
DESAT
BLANK
LED1
14
the fault detection circuitry. The gate resistor R serves to
G
DESAT
limit gate charge current and controls the IGBT collector
voltage rise and fall times. The open collector fault
9, 12
VEE
SHIELD
LED2
output has a passive pull-up resistor R (2.1 kΩ) and a
F
VCLAMP
1000 pF filtering capacitor, C . A 47 kΩ pull down resistor
F
2
3
10
16
VCC1
VCLAMP
VE
R
on V
provides a predictable high level
PULL-DOWN
OUT
output voltage (V ). In this application, the IGBT gate
OH
FAULT
driver will shut down when a fault is detected and fault
reset by next cycle of IGBT turn on. Application notes are
mentioned at the end of this datasheet.
1, 4
15
VS
VLED
SHIELD
Figure 35. Block Diagram of ACPL-333J
18
1
2
3
4
5
6
7
8
VS
VE 16
VLED 15
0.1μF
VCC1
CBLANK
100 Ω
RF
CF
DDESAT
0.1μF
+
FAULT
VS
DESAT 14
VCC2 13
_
CATHODE
ANODE
ANODE
CATHODE
VEE 12
+ HVDC
+
_
RG
+
VCE
-
VOUT 11
VCLAMP 10
VEE
Q1
Q2
R
3-PHASE
AC
RPULL-DOWN
+
_
+
VCE
-
9
- HVDC
Figure 36. Recommended application circuit (Single Supply) with desaturation detection and active Miller Clamp
Description of Operation
Fault Reset
Normal Operation
Once fault is detected, the output will be soft-shut down
to low. All input LED signals will be ignored during
the fault period to allow the driver to completely soft
shut-down the IGBT. For ACPL-333J, the driver will auto-
matically reset the FAULT pin after a fixed mute time of
25μs (typical). See Figure 37.
During normal operation, V
of the ACPL-333J is con-
OUT
trolled by input LED current IF (pins 5, 6, 7 and 8), with
the IGBT collector-to-emitter voltage being monitored
through DESAT. The FAULT output is high. See Figure 37.
Fault Condition
The DESAT pin monitors the IGBT V voltage. When the
ce
voltage on the DESAT pin exceeds 6.5 V while the IGBT is
on, V
is slowly brought low in order to “softly” turn-off
OUT
the IGBT and prevent large di/dt induced voltages. Also
activated is an internal feedback channel which brings
the FAULT output low for the purpose of notifying the
micro-controller of the fault condition.
tDESAT(LOW)
IF
6.5V
Automatic Reset
after mute time
VDESAT
tBLANK
tDESAT(10%)
90%
VOUT
10%
tDESAT(90%)
FAULT
50%
50%
tDESAT(FAULT)
tDESAT(MUTE)
Figure 37. Fault Timing diagram (ACPL-333J)
19
Output Control
Slow IGBT Gate Discharge during Fault Condition
The outputs (V
trolled by the combination of I , UVLO and a detected
IGBT Desat condition. Once UVLO is not active (V
and FAULT) of the ACPL-333J are con-
When a desaturation fault is detected, a weak pull-down
device in the ACPL-333J output drive stage will turn on
to ‘softly’ turn off the IGBT. This device slowly discharges
the IGBT gate to prevent fast changes in drain current
that could cause damaging voltage spikes due to lead
and wire inductance. During the slow turn off, the large
output pull-down device remains off until the output
OUT
F
-
CC2
V > V
), VOUT is allowed to go high, and the DESAT
UVLO
E
(pin 14) detection feature of the ACPL-333J will be the
primary source of IGBT protection. Once V is increased
from 0V to above V
CC2
, DESAT will remain functional
UVLO+
until V
is decreased below V
.
Thus, the DESAT
voltage falls below V + 2 Volts, at which time the large
pull down device clamps the IGBT gate to V .
EE
CC2
UVLO-
EE
detection and UVLO features of the ACPL-333J work in
conjunction to ensure constant IGBT protection.
DESAT Fault Detection Blanking Time
Desaturation Detection and High Current Protection
The DESAT fault detection circuitry must remain disabled
for a short time period following the turn-on of the IGBT
to allow the collector voltage to fall below the DESAT
threshold. This time period, called the DESAT blanking
time is controlled by the internal DESAT charge current,
the DESAT voltage threshold, and the external DESAT
capacitor.
The ACPL-333J satisfies these criteria by combining a
high speed, high output current driver, high voltage
optical isolation between the input and output, local
IGBT desaturation detection and shut down, and an
optically isolated fault status feedback signal into a single
16-pin surface mount package.
The fault detection method, which is adopted in the
ACPL-333J, is to monitor the saturation (collector)
voltage of the IGBT and to trigger a local fault shutdown
sequence if the collector voltage exceeds a predeter-
mined threshold. A small gate discharge device slowly
reduces the high short circuit IGBT current to prevent
damaging voltage spikes. Before the dissipated energy
can reach destructive levels, the IGBT is shut off. During
the off state of the IGBT, the fault detect circuitry is simply
disabled to prevent false ‘fault’signals.
The nominal blanking time is calculated in terms of
external capacitance (C
BLANK
(V
), and DESAT charge current (I
DESAT
C
x V
/ I
. The nominal blanking time with
BLANK
DESAT
CHG
the recommended 100pF capacitor is 100pF * 6.5 V / 240
μA = 2.7 μsec.
The capacitance value can be scaled slightly to adjust the
blanking time, though a value smaller than 100 pF is not
recommended. This nominal blanking time represents
the longest time it will take for the ACPL-333J to respond
to a DESAT fault condition. If the IGBT is turned on while
the collector and emitter are shorted to the supply rails
(switching into a short), the soft shut-down sequence
will begin after approximately 3 μsec. If the IGBT collector
and emitter are shorted to the supply rails after the IGBT
is already on, the response time will be much quicker due
to the parasitic parallel capacitance of the DESAT diode.
The recommended 100pF capacitor should provide
adequate blanking as well as fault response times for
most applications.
The alternative protection scheme of measuring IGBT
current to prevent desaturation is effective if the short
circuit capability of the power device is known, but
this method will fail if the gate drive voltage decreases
enough to only partially turn on the IGBT. By directly
measuring the collector voltage, the ACPL-333J limits the
power dissipation in the IGBT even with insufficient gate
drive voltage. Another more subtle advantage of the de-
saturation detection method is that power dissipation in
the IGBT is monitored, while the current sense method
relies on a preset current threshold to predict the safe
limit of operation. Therefore, an overly conservative over
current threshold is not needed to protect the IGBT.
I
UVLO(V -V )
DESAT Function
Not Active
Pin 3 (FAULT) Output
High
V
OUT
F
CC2
E
ON
ON
ON
OFF
OFF
Active
Low
Low
High
Low
Low
Not Active
Not Active
Active
Active (with DESAT fault)
Active (no DESAT fault)
Not Active
Low (FAULT)
High (or no fault)
High
Not Active
Not Active
High
20
Under Voltage Lockout
1
2
3
4
5
6
7
8
VS
VE 16
VLED 15
The ACPL-333J Under Voltage Lockout (UVLO) feature is
designed to prevent the application of insufficient gate
voltage to the IGBT by forcing the ACPL-333J output
low during power-up. IGBTs typically require gate
voltages of 15 V to achieve their rated V
At gate voltages below 13 V typically, the V
increases dramatically, especially at higher currents.
At very low gate voltages (below 10 V), the IGBT may
operate in the linear region and quickly overheat.
The UVLO function causes the output to be clamped
VCC1
FAULT
VS
DESAT 14
VCC2 13
VCC
voltage.
voltage
CE(ON)
CE(ON)
CATHODE
ANODE
ANODE
CATHODE
VEE 12
RG
VOUT 11
VCLAMP 10
RPULL-DOWN
whenever insufficient operating supply (V ) is applied.
CC2
Once V
exceeds V
(the positive-going UVLO
CC2
UVLO+
VEE
9
threshold), the UVLO clamp is released to allow the
device output to turn on in response to input signals. As
V
is increased from 0 V (at some level below V
),
CC2
UVLO+
Figure 38. Output pull-down resistor.
first the DESAT protection circuitry becomes active. As
is further increased (above V ), the UVLO clamp
V
CC2
UVLO+
is released. Before the time the UVLO clamp is released,
the DESAT protection is already active. Therefore, the
UVLO and DESAT Fault detection feature work together
to provide seamless protection regardless of supply
DESAT Pin Protection Resistor
The freewheeling of flyback diodes connected across
the IGBTs can have large instantaneous forward voltage
transients which greatly exceed the nominal forward
voltage of the diode. This may result in a large negative
voltage spike on the DESAT pin which will draw substan-
tial current out of the driver if protection is not used. To
limit this current to levels that will not damage the driver
IC, a 100 ohm resistor should be inserted in series with
the DESAT diode. The added resistance will not alter the
DESAT threshold or the DESAT blanking time.
voltage (V ).
CC2
Active Miller Clamp
A Miller clamp allows the control of the Miller current
during a high dV/dt situation and can eliminate the use
of a negative supply voltage in most of the applications.
During turn-off, the gate voltage is monitored and the
clamp output is activated when gate voltage goes below
2V (relative to V ). The clamp voltage is V +2.5V typ
EE
OL
for a Miller current up to 1100mA. The clamp is disabled
when the LED input is triggered again.
1
2
3
4
5
6
7
8
VS
VE 16
VLED 15
100pF
100 Ω
VCC1
Other Recommended Components
DDESAT
FAULT
VS
DESAT 14
VCC2 13
The application circuit in Figure 36 includes an output
pull-down resistor, a DESAT pin protection resistor, a
FAULT pin capacitor, and a FAULT pin pullup resistor and
Active Miller Clamp connection.
VCC
CATHODE
ANODE
ANODE
CATHODE
VEE 12
RG
Output Pull-Down Resistor
VOUT 11
During the output high transition, the output voltage
VCLAMP 10
rapidly rises to within 3 diode drops of V . If the output
CC2
current then drops to zero due to a capacitive load, the
VEE
9
output voltage will slowly rise from roughly V -3(V
)
CC2
BE
to V
within a period of several microseconds. To limit
CC2
the output voltage to V -3(V ), a pull-down resistor,
CC2
BE
Figure 39. DESAT pin protection.
R
between the output and V is recommend-
PULL-DOWN
EE
ed to sink a static current of several 650 μA while the
output is high. Pull-down resistor values are dependent
on the amount of positive supply and can be adjusted
according to the formula, R
650 μA.
= [V -3 * (V )] /
pull-down
CC2 BE
21
Capacitor on FAULT Pin for High CMR
Pull-up Resistor on FAULT Pin
Rapid common mode transients can affect the fault pin The FAULT pin is an open collector output and therefore
voltage while the fault output is in the high state. A 1000 requires a pull-up resistor to provide a high-level signal.
pF capacitor should be connected between the fault pin
Also the FAULT output can be wire ‘OR’ed together with
and ground to achieve adequate CMOS noise margins at other types of protection (e.g. over-temperature, over-
the specified CMR value of 50 kV/μs.
voltage, over-current ) to alert the microcontroller.
Other Possible Application Circuit (Output Stage)
1
2
3
4
5
6
7
8
VS
VE 16
VLED 15
DESAT 14
VCC2 13
VEE 12
0.1μF 0.1μF
VCC1
FAULT
VS
Optional R2
0.1μF
CATHODE
ANODE
ANODE
CATHODE
+ HVDC
+
_
RG
Optional R1
+
VCE
-
VOUT 11
Q1
Q2
3-PHASE
AC
10
VCLAMP
*
+
_
RPULL-DOWN
+
VCE
-
VEE
9
- HVDC
Figure 40. IGBT drive with negative gate drive, external booster and desaturation detection (VCLAMP should be connected to VEE when it is not used)
VCLAMP is used as secondary gate discharge path. * indicates component required for negative gate drive topology
1
2
3
4
5
6
7
8
VS
VE 16
VLED 15
DESAT 14
VCC2 13
VEE 12
0.1μF 0.1μF
VCC1
FAULT
VS
Optional R2
0.1μF
CATHODE
ANODE
ANODE
CATHODE
+ HVDC
+
_
RG
Optional R1
+
VCE
-
VOUT 11
Q1
Q2
3-PHASE
AC
10
VCLAMP
*
RPULL-DOWN
+
VCE
-
VEE
9
- HVDC
R3
Figure 41. Large IGBT drive with negative gate drive, external booster. VCLAMP control secondary discharge path for higher power application.
22
Thermal Model
where P = power into input IC and P = power into
The ACPL-333J is designed to dissipate the majority of
the heat through pins 1, 4, 5 & 8 for the input IC and pins
i
o
output IC. Since θ and θ
are dependent on PCB
5A
9,12A
layout and airflow, their exact number may not be
available. Therefore, a more accurate method of calcu-
lating the junction temperature is with the following
equations:
9 & 12 for the output IC. (There are two V pins on the
EE
output side, pins 9 and 12, for this purpose.) Heat flow
through other pins or through the package directly into
ambient are considered negligible and not modeled
here.
T = P θ + T
ji
i
i5
P5
In order to achieve the power dissipation specified in
the absolute maximum specification, it is imperative
that pins 5, 9, and 12 have ground planes connected to
them. As long as the maximum power specification is
not exceeded, the only other limitation to the amount
of power one can dissipate is the absolute maximum
junction temperature specification of 125°C. The junction
temperatures can be calculated with the following
equations:
T
= P θ
+ T
jo
o
o9,12 P9,12
These equations, however, require that the pin 5 and pins
9, 12 temperatures be measured with a thermal couple
on the pin at the ACPL-333J package edge.
If the calculated junction temperatures for the thermal
model in Figure 42 is higher than 125°C, the pin tem-
perature for pins 9 and 12 should be measured (at the
package edge) under worst case operating environment
for a more accurate estimate of the junction tempera-
tures.
T = P (θ + θ ) + T
ji
i
i5
5A
A
T
jo
= Po (θ
+ θ
) + T
9,12A A
o9,12
Tji = junction temperature of input side IC
Tjo = junction temperature of output side IC
Tji
Tjo
T
T
P5 = pin 5 temperature at package edge
P9,12 = pin 9 and 12 temperature at package edge
TI1 = 60°C/W
Tl9, 12 = 30°C/W
θI5 = input side IC to pin 5 thermal resistance
θ
θ
θ
o9,12 = output side IC to pin 9 and 12 thermal resistance
5A = pin 5 to ambient thermal resistance
9,12A = pin 9 and 12 to ambient thermal resistance
TP9, 12
9, 12A = 50°C/W*
TP1
T
1A = 50°C/W*
T
*The θ5A and θ9,12A values shown here are for PCB layouts with reasonable air flow.
This value may increase or decrease by a factor of 2 depending on PCB layout and/or airflow.
TA
Figure 42. ACPL-333J Thermal Model
Related Application Notes
AN5314 – Active Miller Clamp
AN5315 – “Soft”Turn-off Feature
AN1043 – Common-Mode Noise : Sources and Solutions
AV02-0310EN - Plastic Optocouplers Product ESD and Moisture Sensitivity
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved. Obsoletes AV02-0726EN
AV02-1087EN - October 25, 2012
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