ACPL-38JT-000E [AVAGO]
Automotive Gate Drive Optocoupler with R2Coupler⢠Isolation, 2.5 Amp Output Current, Integrated Desaturation (VCE) Detection and Fault Status Feedback; 汽车栅极驱动光电耦合器与R2Couplerâ ?? ¢隔离， 2.5安培输出电流，集成去饱和（ VCE）检测和故障状态反馈
| 型号： | ACPL-38JT-000E |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | Automotive Gate Drive Optocoupler with R2Coupler⢠Isolation, 2.5 Amp Output Current, Integrated Desaturation (VCE) Detection and Fault Status Feedback |
| 文件： | 总33页 (文件大小：561K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACPL-38JT
2
Automotive Gate Drive Optocoupler with R Coupler™ Isolation,
2.5 Amp Output Current, Integrated Desaturation (V ) Detection
CE
and Fault Status Feedback
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
Avago’s automotive 2.5 Amp Gate Drive Optocoupler with 2.5 A maximum peak output current
Integrated Desaturation (V ) Detection and Fault Status
CE
Drive IGBTs up to I = 150 A, V = 1200 V
C
CE
Feedback makes automotive IGBT V fault protection
compact, affordable, and easy-to-implement while satis-
CE
Optically isolated, FAULT status feedback
fying automotive AEC-Q100 Grade 1 semiconductor re- SO-16 package
quirement.
CMOS/TTL compatible
2
Avago R Coupler isolation products provide the rein-
500 ns max. switching speeds
“Soft”IGBT turn-off
forced insulation and reliability needed for critical in auto-
motive and high temperature industrial applications
Integrated fail-safe IGBT protection
Functional Diagram
– Desat (VCE) detection
– Under Voltage Lock-Out protection (UVLO) with
hysteresis
VLED1+ VLED1–
7
8
13
VCC2
VC
User configurable: inverting, noninverting, auto-reset,
UVLO
11
10
auto-shutdown
D
R
I
V
E
R
Wide operating V range: 15 to 30 Volts
LED1
CC
VOUT
DESAT
2
3
VIN+
VIN–
-40°C to +125°C operating temperature range
14
DESAT
15 kV/s min. Common Mode Rejection (CMR) at V
=
CM
9, 12
VEE
1500 V
SHIELD
LED2
4
Qualified to AEC-Q100 Grade 1 Test Guidelines
VCC1
Regulatory approvals:
– UL1577, CSA
5
6
VE
RESET
FAULT
16
15
FAULT
– IEC/EN/DIN EN 60747-5-5
1
GND1
VLED2+
SHIELD
Applications
Figure 1. ACPL-38JT Functional Diagram
Automotive Isolated IGBT/MOSFET Inverter gate drive
Automotive DC-DC Converter
AC and brushless dc motor drives
Industrial inverters for power supplies and motor
controls
Un-interruptible Power Supplies
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information
ACPL-38JT is UL Recognized with 5000 Vrms for 1 minute per UL1577.
Part Number
RoHS Compliant
-000E
Package
Surface Mount
Tape & Reel
Quantity
X
X
45 per tube
850 per reel
ACPL-38JT
SO-16
-500E
X
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACPL-38JT-500E to order product of SO-16 Surface Mount RoHS compliant package in Tape and Reel packaging.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Typical Fault Protected IGBT Gate Drive Circuit
The ACPL-38JT is an easy-to-use, intelligent gate driver which makes IGBT V fault protection compact, affordable, and
CE
easy-to-implement. Features such as user configurable inputs, integrated V detection, under voltage lockout (UVLO),
CE
“soft”IGBT turn-off and isolated fault feedback provide maximum design flexibility and circuit protection.
Boundary
Isolation
Boundary
Isolation
Boundary
Isolation
DC-DC
Converter
Battery
Boundary
Isolation
Boundary
Isolation
Boundary
Isolation
Boundary
Isolation
FAULT
Micro-Controller
Typical Application Block Diagram of a motor control system.
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND1
VIN+
VIN
VE
VLED2+
DESAT
VCC2
0.1μF 0.1μF
CBLANK
*
0.1μF
DDESAT
100 Ω
+ VF
μC
VCC1
0.1μF
*
RF
RESET
FAULT
VLED+
VEE
+
RG
+
VCE
VC
Q1
Q2
VOUT
VEE
RPULL-DOWN
+
*
VLED
Typical de-saturation protected gate drive circuit, non-inverting.
Description of Operation during Fault Condition
Output Control
1. DESAT terminal monitors the IGBT V voltage through The outputs (V
and FAULT) of the ACPL-38JT are con-
CE
OUT
D
.
trolled by the combination of V , UVLO and a detected
IGBT Desat condition. As indicated in the below table, the
ACPL-38JT can be configured as inverting or non-invert-
DESAT
IN
2. When the voltage on the DESAT terminal exceeds 7
volts, the IGBT gate voltage (V ) is slowly lowered.
OUT
ing using the V
or V inputs respectively. When an
IN+
IN-
3. FAULT output goes low, notifying the microcontroller
of the fault condition.
inverting configuration is desired, V must be held high
IN+
and V toggled. When a non-inverting configuration
IN-
4. Microcontroller takes appropriate action.
is desired, V must be held low and V toggled. Once
IN- IN+
UVLO is not active (V
- V > V
), V
UVLO
is allowed
OUT
CC2
E
to go high, and the DESAT (pin 14) detection feature of
the ACPL-38JT will be the primary source of IGBT protec-
tion. UVLO is needed to ensure DESAT is functional. Once
V
> 11.6 V, DESAT will remain functional until V
UVLO+
UVLO-
< 12.4 V. Thus, the DESAT detection and UVLO features of
the ACPL-38JT work in conjunction to ensure constant
IGBT protection.
Desat
Pin 6
Condition (FAULT)
UVLO
(V - V )
CC2
Detected
on Pin 14
Output
V
IN+
V
V
OUT
IN-
E
X
X
Low
X
X
X
Active
X
X
X
Yes
X
X
Low
X
Low
Low
Low
X
High
Low
X
X
X
Low
High
Not Active
No
High
High
3
Product Overview Description
manufactured on a high voltage BiCMOS/Power DMOS
process. The forward optical signal path, as indicated by
LED1, transmits the gate control signal. The return optical
signal path, as indicated by LED2, transmits the fault
status feedback signal. Both optical channels are com-
pletely controlled by the input and output ICs respective-
ly, making the internal isolation boundary transparent to
the microcontroller.
The ACPL-38JT (shown in Figure 1) is a highly integrated
power control device that incorporates all the necessary
components for a complete, isolated IGBT gate drive
circuit with fault protection and feedback into one SO-16
package. TTL input logic levels allow direct interface with
a microcontroller, and an optically isolated power output
stage drives IGBTs with power ratings of up to 150 A and
1200 V. A high speed internal optical link minimizes the
propagation delays between the microcontroller and
the IGBT while allowing the two systems to operate at
very large common mode voltage differences that are
common in industrial motor drives and other power
switching applications. An output IC provides local pro-
tection for the IGBT to prevent damage during overcur-
rents, and a second optical link provides a fully isolated
fault status feedback signal for the microcontroller. A built
in “watchdog” circuit monitors the power stage supply
voltage to prevent IGBT caused by insufficient gate drive
voltages. This integrated IGBT gate driver is designed to
increase the performance and reliability of a motor drive
without the cost, size, and complexity of a discrete design.
Under normal operation, the input gate control signal
directly controls the IGBT gate through the isolated output
detector IC. LED2 remains off and a fault latch in the input
buffer IC is disabled. When an IGBT fault is detected, the
output detector IC immediately begins a “soft” shutdown
sequence, reducing the IGBT current to zero in a controlled
manner to avoid potential IGBT damage from inductive
over-voltages. Simultaneously, this fault status is transmit-
ted back to the input buffer IC via LED2, where the fault
latch disables the gate control input and the active low
fault output alerts the microcontroller.
During power-up, the Under Voltage Lockout (UVLO)
feature prevents the application of insufficient gate
voltage to the IGBT, by forcing the ACPL-38JT’s output
Two light emitting diodes and two integrated circuits
housed in the same SO-16 package provide the input
control circuitry, the output power stage, and two
optical channels. The input Buffer IC is designed on a
bipolar process, while the output Detector IC is designed
low. Once the output is in the high state, the DESAT (V
)
CE
detection feature of the ACPL-38JT provides IGBT pro-
tection. Thus, UVLO and DESAT work in conjunction to
provide constant IGBT protection.
4
Package Pin Out
1
2
3
4
5
6
7
8
GND1
VE 16
VLED2+ 15
DESAT 14
VCC2 13
VEE 12
VIN+
VIN
VCC1
RESET
FAULT
VLED1+
VLED1
VC 11
VOUT 10
VEE
9
Pin Descriptions
Symbol Description
Symbol Description
VIN+
Noninverting gate drive voltage output (VOUT
control input.
)
VE
Common (IGBT emitter) output supply voltage.
VIN-
Inverting gate drive voltage output (VOUT
control input.
)
VLED2+
LED 2 anode. This pin must be left unconnected
for guaranteed data sheet performance.
(For optical coupling testing only.)
VCC1
Positive input supply voltage. (4.5 V to 5.5 V)
DESAT
Desaturation voltage input. When the voltage
on DESAT exceeds an internal reference voltage
of 7V while the IGBT is on, FAULT output is changed
from a high impedance state to a logic low state
within 5 s. See Note 25.
GND1
RESET
Input Ground.
VCC2
VC
Positive output supply voltage.
FAULT reset input. A logic low input for at least
0.1 s, asynchronously resets FAULT output high
and enables VIN. Synchronous control of RESET
relative to VIN is required. RESET is not affected
by UVLO. Asserting RESET while VOUT is high does
Collector of output pull-up triple-darlington
transistor. It is connected to VCC2 directly or through
a resistor to limit output turn-on current.
not affect VOUT
.
FAULT
Fault output. FAULT changes from a high impedance VOUT
state to a logic low output within 5 s of the voltage
on the DESAT pin exceeding an internal reference
voltage of 7V. FAULT output remains low until RESET
is brought low. FAULT output is an open collector
which allows the FAULT outputs from all HCPL-316Js
in a circuit to be connected together in a “wired OR”
forming a single fault bus for interfacing directly to
the micro-controller.
Gate drive voltage output.
VLED1+
LED 1 anode. This pin must be left unconnected
for guaranteed data sheet performance.
(For optical coupling testing only.)
VEE
Output supply voltage.
VLED1-
LED 1 cathode. This pin must be connected to
ground.
5
Package Outline Drawings
16-Lead Surface Mount
0.018
(0.457)
0.050
(1.270)
LAND PATTERN RECOMMENDATION
16 15 14 13 12 11 10 9
TYPE NUMBER
DATE CODE
A 38JT
YYWW
EE
0.458 (11.63)
0.295 0.010
(7.493 0.254)
0.085 (2.16)
1
2 3 4 5 6 7 8
0.406 0.10
(10.312 0.254)
EXTENDED
DATECODE FOR
LOT TRACKING
0.025 (0.64)
0.345 0.010
(8.763 0.254)
ALL LEADS
9°
TO BE
COPLANAR
0.002
0.138 0.005
(3.505 0.127)
0.018
(0.457)
0–8°
0.008 0.003
(0.203 0.076)
STANDOFF
0.025 MIN.
0.408 0.010
(10.363 0.254)
Package Characteristics
All specifications and figures are at the nominal (typical) operating conditions of V = 5 V, V - V = 30 V, V - V = 0 V,
CC1
CC2 EE
E
EE
and T = +25°C.
A
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Note
Input-Output Momentary Withstand
Voltage
VISO
5000
VRMS
RH < 50%, t = 1 min.
TA = 25°C
1, 2, 3
Resistance (Input-Output)
Capacitance (Input-Output)
RI-O
1014
1.3
VI-O = 500 Vdc
3
CI-O
pF
f = 1 MHz
Output IC-to-Pins 9 & 12
Thermal Resistance
O9-12
30
°C/W
TA = 100°C
Input IC-to-Pin 1 Thermal Resistance
I1
60
°C/W
TA = 100°C
Recommended Pb-Free IR Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
The ACPL-38JT is approved by the following organizations:
UL
IEC/EN/DIN EN 60747-5-5
Approved under UL 1577, component recognition Approved under:
program up to V = 5000 V
release.
expected prior to product
ISO
RMS
IEC 60747-5-5
EN 60747-5-5
CSA
DIN EN 60747-5-5
Approved under CSA Component Acceptance Notice #5,
File CA 88324.
6
IEC/EN/DIN EN 60747-5-5 Insulation Characteristics
Description
Symbol
Characteristic
Unit
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 450 Vrms
I - IV
I - III
I - II
for rated mains voltage ≤ 600 Vrms
Climatic Classification
55/125/21
2
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b[2] VIORM x 1.875 = VPR
VIORM
VPR
1230
2306
VPEAK
VPEAK
,
100% Production Test with tm = 10sec, Partial discharge < 5 pC
Input to Output Test Voltage, Method a[2] VIORM x 1.6 = VPR
Type and Sample Test, tm = 60 sec, Partial discharge < 5 pC
,
VPR
1968
8000
VPEAK
VPEAK
Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec)
VIOTM
Safety-limiting values – maximum values allowed in the event of a failure
TS
175
400
1200
°C
mA
mW
Case Temperature
Input Current[3]
Output Power[3]
IS, INPUT
PS, OUTPUT
Insulation Resistance at TS, VIO = 500 V
RS
>109
Notes:
1. Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.
Surface Mount Classification is Class A in accordance with CECCOO802.
2. Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/EN/
DIN EN 60747-5-5) for a detailed description of Method a and Method b partial discharge test profiles.
3. Refer to the following figure for dependence of P and I on ambient temperature.
S
S
1400
1200
1000
PS, OUTPUT
PS, INPUT
800
600
400
200
0
0
25
50
75
100 125 150 175 200
TS – CASE TEMPERATURE – °C
Figure 2. Dependence of safety limiting values on temperature.
7
Insulation and Safety Related Specifications
Parameter
Symbol
Value
Units
Conditions
Minimum External Air Gap (Clearance)
L(101)
8.3
mm
Measured from input terminals to output terminals,
shortest distance through air.
Minimum External Tracking (Creepage)
L(102)
8.3
0.5
mm
mm
Measured from input terminals to output terminals,
shortest distance path along body.
Minimum Internal Plastic Gap
(Internal Clearance)
Through insulation distance conductor to conductor,
usually the straight line distance thickness between
the emitter and detector.
Tracking Resistance
(Comparative Tracking Index)
CTI
>175
IIIa
Volts
DIN IEC 112/VDE 0303 Part 1
Isolation Group
Material Group (DIN VDE 0110)
Absolute Maximum Ratings
Parameter
Symbol
Min.
-55
-40
Max.
150
125
150
2.5
Units
°C
Note
Storage Temperature
Operating Temperature
Output IC Junction Temperature
Peak Output Current
Fault Output Current
Positive Input Supply Voltage
Input Pin Voltages
TS
TA
°C
TJ
°C
4
5
|IO(peak)
IFAULT
VCC1
|
A
8
mA
Volts
Volts
-0.5
-0.5
5.5
VIN+, VIN- and
VRESET
VCC1
Total Output Supply Voltage
Negative Output Supply Voltage
Positive Output Supply Voltage
Gate Drive Output Voltage
Collector Voltage
(VCC2 - VEE
(VE - VEE
)
-0.5
-0.5
-0.5
-0.5
VEE + 5
VE
35
Volts
Volts
Volts
Volts
Volts
Volts
mW
)
15
6
4
(VCC2 - VE)
Vo(peak)
VC
35 - (VE - VEE
VCC2
)
VCC2
DESAT Voltage
VDESAT
PO
VE + 10
600
Output IC Power Dissipation
Input IC Power Dissipation
Solder Reflow Temperature Profile
PI
150
mW
See Package Outline Drawings section
Recommended Operating Conditions
Parameter
Symbol
VCC1
Min.
4.5
Max.
5.5
30
Units
Volts
Volts
Volts
Volts
Volts
°C
Notes
Input Supply Voltage
28
9
Total Output Supply Voltage
Negative Output Supply Voltage
Positive Output Supply Voltage
Collector Voltage
(VCC2 - VEE
)
15
(VE - VEE
)
0
15
6
(VCC2 - VE)
15
30 – (VE - VEE
VCC2
)
VC
TA
VEE + 6
-40
Operating Temperature
125
8
Electrical Specifications
Recommended operating conditions unless otherwise specified: T = -40°C to +125°C, all typical values at T = 25°C,
A
A
V
= 5 V, and V
- V = 30 V, V - V = 0 V; all Minimum/Maximum specifications are at Recommended Operating
CC1
CC2
EE
E
EE
Conditions.
Parameter
Symbol
Min.
Typ.*
Max.
Units Test Conditions
Fig.
Note
Logic Low Input Voltages
VIN+L, VIN-L
VRESETL
,
0.8
V
Logic High Input Voltages
Logic Low Input Currents
VIN+H, VIN-H
VRESETH
,
2.0
-0.5
5.0
-40
V
IIN+L, IIN-L
,
-0.4
12
mA
mA
A
A
VIN = 0.4 V
IRESETL
FAULT Logic Low Output
Current
IFAULTL
IFAULTH
IOH
VFAULT = 0.4 V
VFAULT = VCC1
29
30
FAULT Logic High Output
Current
High Level Output Current
-0.5
-2.0
-1.5
2.3
VOUT = VCC2 - 4 V
VOUT = VCC2 - 15 V
3, 8,
31
7
5
Low Level Output Current
IOL
0.5
2.0
A
VOUT = VEE + 2.5 V
4, 9,
32
7
5
V
OUT = VEE + 15 V
Low Level Output Current
High Level Output Voltage
IOLF
VOH
90
160
230
mA
V
VOUT - VEE = 14 V
IOUT = -100 mA
IOUT = -650 A
IOUT = 0
5, 33
6, 8,
34
8
VC - 3.5
VC -2.9
VC - 2.5
VC - 2.0
VC - 1.5
VC - 1.2
VC
9, 10, 11
V
V
Low Level Output Voltage
VOL
0.17
17
0.5
V
IOUT = 100 mA
7, 9, 35 26
High Level Input Supply
Current
ICC1H
22
mA
VIN+ = VCC1 = 5.5 V, 10, 36
VIN- = 0 V
Low Level Input Supply
Current
ICCIL
ICC2
6
11
5
mA
mA
VIN+ = VIN- = 0 V,
VCC1 = 5.5 V,
10, 37
Output Supply Current
2.5
VOUT open
11, 12,
38, 39
11
Low Level Collector Current
High Level Collector Current
ICL
0.3
1.0
1.3
3.0
0
mA
mA
mA
mA
mA
IOUT = 0
15, 58
15, 57
15, 56
14, 60
14, 59
13, 40
27
27
27
ICH
0.3
IOUT = 0
1.8
IOUT = -650 A
VE Low Level Supply Current
IEL
-0.7
-0.5
-0.4
-0.14
VE High Level Supply Current IEH
0
25
Blanking Capacitor Charging ICHG
Current
-0.13
-0.18
-0.25
-0.25
-0.33
-0.33
mA
mA
VDESAT = 0 - 6 V
11, 12
VDESAT = 0 - 6 V,
TA = 25°C - 125°C
Blanking Capacitor Discharge IDSCHG
Current
10
50
mA
VDESAT = 7 V
41
UVLO Threshold
UVLO Hysteresis
DESAT Threshold
VUVLO+
VUVLO-
11.6
0.4
6.5
12.3
11.1
13.5
12.4
V
V
VOUT > 5 V
VOUT < 5 V
42
9, 11, 13
9, 11, 14
(VUVLO+
1.2
V
42
VUVLO-
)
VDESAT
7.0
7.5
V
VCC2 - VE > VUVLO-
16, 43
11
9
Switching Specifications
Unless otherwise noted, all typical values at T = 25°C, V
= 5 V, and V - V = 30 V, V - V = 0 V; all Minimum/
CC2 EE E EE
A
CC1
Maximum specifications are at Recommended Operating Conditions.
Parameter
Symbol
Min.
Typ.*
Max.
Units Test Conditions
Fig.
Note
VIN to High Level Output
Propagation Delay Time
tPLH
0.10
0.30
0.50
s
Rg = 10
Cg = 10 nF
f = 10 kHz
17,18,19,
20,21,22,
44, 53, 54
15
VIN to Low Level Output
Propagation Delay Time
tPHL
0.10
0.32
0.02
0.5
s
Duty Cycle = 50%
Pulse Width Distortion
PWD
-0.30
0.30
0.35
s
s
16,17
17,18
Propagation Delay Difference (tPHL-tPLH) PDD -0.35
Between Any 2 Parts
10% to 90% Rise Time
90% to 10% Fall Time
tr
0.1
0.1
0.3
s
s
s
44
tf
44
DESAT Sense to 90% VOUT
Delay
tDESAT(90%)
0.5
3.0
5
Rg = 10
23, 55
19
Cg = 10 nF
DESAT Sense to 10% VOUT
Delay
tDESAT(10%)
tDESAT(FAULT)
tDESAT(LOW)
tRESET(FAULT)
2.0
1.8
0.25
7
s
s
s
s
VCC2 - VEE = 30 V
24, 26, 27
45, 55
DESAT Sense to Low Level
FAULT Signal Delay
25, 46, 55
20
21
22
DESAT Sense to DESAT Low
Propagation Delay
55
RESET to High Level FAULT
Signal Delay
3
20
28, 47, 55
RESET Signal Pulse Width
UVLO to VOUT High Delay
UVLO to VOUT Low Delay
PWRESET
tUVLO ON
tUVLO OFF
0.1
s
s
s
4.0
6.0
30
VCC2 = 1.0 ms ramp 48
13
14
23
Output High Level Common |CMH|
Mode Transient Immunity
15
15
kV/s TA = 25°C,
VCM = 1500 V,
CC2 = 30 V
49, 50, 51,
52
V
Output Low Level Common
Mode Transient Immunity
|CML|
30
kV/s TA = 25°C,
24
V
CM = 1500 V,
VCC2 = 30 V
10
Notes:
1.
2.
In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥6000 Vrms for 1 second.
The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to your equipment level safety specification or IEC/EN/DIN EN 60747-5-5 Insulation
Characteristics Table.
3.
4.
Device considered a two terminal device: pins 1 - 8 shorted together and pins 9 - 12 shorted together.
In order to achieve the absolute maximum power dissipation specified, pins 1, 9, and 12 require ground plane connections and may require
airflow. See the Thermal Model section in the application notes at the end of this data sheet for details on how to estimate junction temperature
and power dissipation. In most cases the absolute maximum output IC junction temperature is the limiting factor. The actual power dissipation
achievable will depend on the application environment (PCB Layout, air flow, part placement, etc.). See the Recommended PCB Layout section
in the application notes for layout considerations. Output IC power dissipation is derated linearly at 10 mW/°C above 90°C. Input IC power
dissipation does not require de-rating.
5.
Maximum pulse width = 10 μs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO
peak minimum = 2.0 A. See Applications section for additional details on I peak. De-rate linearly from 3.0 A at +25°C to 2.5 A at +125°C. This
OH
compensates for increased I
This supply is optional. Required only when negative gate drive is implemented.
Maximum pulse width = 50 s, maximum duty cycle = 0.5%.
See the Slow IGBT Gate Discharge During Fault Condition section in the applications notes at the end of this data sheet for further details.
due to changes in V over temperature.
OPEAK
OL
6.
7.
8.
9.
15 V is the recommended minimum operating positive supply voltage (V
- V ) to ensure adequate margin in excess of the maximum V
CC2
E UVLO+
threshold of 13.5 V. For High Level Output Voltage testing, V is measured with a dc load current. When driving capacitive loads, V will
OH
OH
approach V as I approaches zero units.
CC
OH
10. Maximum pulse width = 1.0 ms, maximum duty cycle = 20%.
11. Once V of the ACPL-38JT is allowed to go high (V - V > V ), the DESAT detection feature of the ACPL-38JT will be the primary source of
UVLO
OUT
CC2
E
IGBT protection. UVLO is needed to ensure DESAT is functional. Once V
> 11.6 V, DESAT will remain functional until V
- < 12.4 V. Thus, the
UVLO+
UVLO
DESAT detection and UVLO features of the ACPL-38JT work in conjunction to ensure constant IGBT protection.
12. See the Blanking Time Control section in the applications notes at the end of this data sheet for further details.
13. This is the “increasing”(i.e. turn-on or “positive going”direction) of V
14. This is the “decreasing”(i.e. turn-off or “negative going”direction) of V
15. This load condition approximates the gate load of a 1200 V/75A IGBT.
- V .
CC2
E
- V .
E
CC2
16. Pulse Width Distortion (PWD) is defined as |t
- t | for any given unit.
PHL PLH
17. As measured from V , V to V
.
IN+ IN-
OUT
18. The difference between t
and t between any two ACPL-38JT parts under the same test conditions.
PHL
PLH
19. Supply Voltage Dependent.
20. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low.
21. This is the amount of time the DESAT threshold must be exceeded before V begins to go low, and the FAULT output to go low.
OUT
22. This is the amount of time from when RESET is asserted low, until FAULT output goes high. The minimum specification of 3 μs is the guaranteed
minimum FAULT signal pulse width when the ACPL-38JT is configured for Auto-Reset. See the Auto-Reset section in the applications notes at the
end of this data sheet for further details.
23. Common mode transient immunity in the high state is the maximum tolerable dV /dt of the common mode pulse, V , to assure that the
CM
CM
output will remain in the high state (i.e., V > 15 V or FAULT > 2 V). A 100 pF and a 3K pull-up resistor is needed in fault detection mode.
O
24. Common mode transient immunity in the low state is the maximum tolerable dV /dt of the common mode pulse, V , to assure that the
CM
CM
output will remain in a low state (i.e., V < 1.0 V or FAULT < 0.8 V).
O
25. Does not include LED2 current during fault or blanking capacitor discharge current.
26. To clamp the output voltage at V - 3 V , a pull-down resistor between the output and V is recommended to sink a static current of 650 A
CC
BE
EE
while the output is high. See the Output Pull-Down Resistor section in the application notes at the end of this data sheet if an output pull-down
resistor is not used.
27. The recommended output pull-down resistor between V
and V does not contribute any output current when V
= V .
OUT EE
OUT
EE
28. In most applications V will be powered up first (before V ) and powered down last (after V ). This is desirable for maintaining control of the
CC1
CC2
CC2
IGBT gate. In applications where V
voltage (minimum 4.5 V) to avoid any momentary instability at the output during V
is powered up first, it is important to ensure that Vin+ remains low until V
reaches the proper operating
CC2
CC1
ramp-up or ramp-down.
CC1
11
2.0
1.8
1.6
1.4
1.2
1.0
7
6
5
4
3
2
1
0
VOUT=VEE + 2.5V
VOUT=VEE + 15V
-40 -20
0
20
40
60
80 100 120 140
-40 -20
0
20
40
60
80 100 120 140
TA - TEMPERATURE - °C
TA - TEMPERATURE - °C
Figure 3. IOH vs. temperature.
Figure 4. IOL vs. temperature.
200
175
150
0
Iout = -100mA
-1
-2
-3
-4
125
100
75
-40°C
25°C
50
100°C
25
0
5
10
15
20
25
30
-40 -20
0
20
40
60
80 100 120 140
VOUT – OUTPUT VOLTAGE – V
TA - TEMPERATURE - °C
Figure 5. IOLF vs. VOUT
.
Figure 6. VOH vs. Temperature.
29.0
28.5
28.0
27.5
27.0
26.5
0.25
0.20
0.15
0.10
0.05
-40°C
+25°C
+125°C
0.00
-40
10
60
110
160
0
0.2
0.4
0.6
0.8
TA - TEMPERATURE - °C
I
OH - OUTPUT HIGH CURRENT - A
Figure 7. VOL vs. Temperature.
Figure 8. VOH vs. IOH.
12
6
5
4
3
2
1
0
20
15
10
5
-40°C
+25°C
+125°C
Icc1H
Icc1L
0
0
0.5
1
1.5
2
2.5
-40 -20
0
20
40
60
80 100 120 140
I
OL - OUTPUT LOW CURRENT - A
TA - TEMPERATURE - °C
Figure 9. VOL vs. IOL
.
Figure 10. ICC1 vs. temperature.
2.60
2.55
2.50
2.45
2.40
3.0
2.9
2.8
ICC2H
ICC2L
Icc2H
2.35
15
2.7
-40 -20
0
20
40
60
80 100 120 140
20
25
30
VCC2 – OUTPUT SUPPLY VOLTAGE – V
TA - TEMPERATURE - °C
Figure 11. ICC2 vs. temperature.
Figure 12. ICC2 vs. VCC2.
-0.15
-0.2
-0.10
-0.15
-0.20
-0.25
-0.30
-0.35
-0.40
-0.45
IEH
IEL
-0.25
-0.3
-0.50
-40 -20
0
20 40 60 80 100 120 140
-40 -20
0
20 40 60 80 100 120 140
TA - TEMPERATURE - °C
TEMPERATURE - °C
Figure 13. ICHG vs. temperature.
Figure 14. IE vs. temperature.
13
4
3
7.5
7.0
6.5
6.0
2
1
0
-40°C
+25°C
+100°C
0
0.5
1.0
1.5
2.0
-40 -20
0
20 40
60 80 100 120 140
IOUT (mA)
TEMPERATURE - °C
Figure 15. IC vs. IOUT
.
Figure 16. DESAT threshold vs. temperature.
0.40
0.50
0.40
0.30
0.20
TpLH
TpHL
tPHL
tPLH
0.35
0.30
0.25
0.20
-40 -20
0
20
40
60
80 100 120 140
15
20
25
30
VCC – SUPPLY VOLTAGE – V
TEMPERATURE - °C
Figure 17. Propagation delay vs. temperature.
Figure 18. Propagation delay vs. supply voltage.
0.50
0.40
VCC1=4.5V
VCC1=5.0V
VCC1=4.5V
VCC1=5.0V
VCC1=5.5V
0.45
0.40
0.35
0.30
0.25
0.20
VCC1=5.5V
0.35
0.30
0.25
0.20
-50
0
50
100
150
-50
0
50
100
150
TEMPERATURE - °C
TEMPERATURE - °C
Figure 19. VIN to high propagation delay vs. temperature.
Figure 20. VIN to low propagation delay vs. temperature.
14
0.40
0.35
0.30
0.25
0.20
0.40
0.35
0.30
0.25
0.20
tPLH
tPHL
tPLH
tPHL
0
20
40
60
80
100
0
10
20
30
40
50
LOAD RESISTANCE –
LOAD CAPACITANCE – nF
Figure 21. Propagation delay vs. load capacitance.
Figure 22. Propagation delay vs. load resistance.
3.0
2.5
2.0
1.5
1.0
0.45
0.40
0.35
0.30
0.25
-50
-50
0
50
100
150
0
50
100
150
TEMPERATURE - °C
TEMPERATURE - °C
Figure 23. DESAT sense to 90% Vout delay vs. temperature.
Figure 24. DESAT sense to 10% Vout delay vs. temperature.
0.008
3.6
3.2
2.8
2.4
2.0
1.6
VCC2 = 15 V
VCC2 = 30 V
0.006
0.004
0.002
0
0
10
20
30
40
50
-50
0
50
100
150
TEMPERATURE - °C
LOAD CAPACITANCE – nF
Figure 25. DESAT sense to low level fault signal delay vs. temperature.
Figure 26. DESAT sense to 10% Vout delay vs. load capacitance.
15
0.0030
0.0025
0.0020
0.0015
0.0010
12
10
8
Vcc1 = 4.5V
Vcc1 = 5.0V
Vcc1 = 5.5V
VCC2 = 15 V
VCC2 = 30 V
6
4
10
20
30
40
50
-50
0
50
100
150
LOAD RESISTANCE – Ω
TEMPERATURE – °C
Figure 27. DESAT sense to 10% Vout delay vs. load resistance.
Figure 28. RESET to high level fault signal delay vs. temperature.
Test Circuit Diagrams
0.1μF
0.1μF
0.1μF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
GND1
VIN+
VIN
VE
VLED2+
DESAT
VCC2
GND1
VIN+
VIN
16
15
14
13
12
11
10
9
VE
VLED2+
DESAT
VCC2
_
_
+
+
2
3
4
5
6
7
8
4.5V
4.5V
10mA
_
+
_
VCC1
VCC1
+
0.4V
0.4V
VEE
VEE
RESET
FAULT
VLED+
RESET
FAULT
VLED+
VC
VC
IFAULT
IFAULT
VOUT
VEE
VOUT
VEE
VLED
VLED
Figure 29. IFAULTL test circuit.
Figure 30. IFAULTH test circuit.
0.1
1
2
3
4
5
6
7
8
GND1
VIN+
VIN
VCC1
VE
16
15
14
13
12
11
10
9
1
GND1
VE 16
_
+
0.1μF
30V
0.1μF
_
_
VLED2+
DESAT
VIN+
VIN
VCC1
VLED2+
2
3
4
5
6
7
8
15
14
13
12
11
10
9
+
5V
+
DESAT
30V
VCC2
VEE
VCC2
VEE
+
_
15V
0.1μF
RESET
FAULT
VLED+
0.1μF
RESET
FAULT
VLED+
Pulsed
IOUT
30V
30V
VC
VC
+
_
+
_
15V
+
_
Pulsed
IOUT
VOUT
VOUT
0.1μF
0.1μF
VLED
VEE
VLED
VEE
Figure 31. IOH pulsed test circuit.
Figure 32. IOL pulsed test circuit.
16
0.1μF
0.1μF
1
2
3
4
5
6
7
8
GND1
VIN+
VIN
VE 16
VLED2+ 15
DESAT 14
VCC2 13
VEE 12
1
2
3
4
5
6
7
8
GND1
VIN+
VIN
VE 16
VLED2+ 15
DESAT 14
VCC2 13
VEE 12
_
+
0.1μF
30V
_
+
0.1μF
30V
_
_
+
5V
+
5V
VCC1
VCC1
0.1μF
0.1μF
RESET
FAULT
VLED+
RESET
FAULT
VLED+
IOUT
14V
+
_
VOUT
30V
30V
2V
Pulsed
VC 11
VC 11
+
_
+
_
VOUT 10
VOUT 10
0.1μF
0.1μF
VEE
9
VLED
VEE 9
VLED
Figure 33. IOLF test circuit.
Figure 34. VOH pulsed test circuit.
0.1μF
GND1
VIN+
VIN
VCC1
VE
16
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
GND1
VIN+
VIN
VCC1
VE
16
_
+
_
+
0.1μF
30V
_
VLED2+
DESAT
VCC2
15
14
13
VLED2+ 15
DESAT 14
+
5V
0.1μF
5.5V
ICC1
13
VCC2
0.1μF
VEE 12
VC 11
10
12
VEE
RESET
FAULT
VLED+
RESET
FAULT
VLED+
30V
100mA
11
VC
+
_
VOUT
10
9
VOUT
VEE
0.1μF
VOUT
9
VLED
VEE
VLED
Figure 35. VOL test circuit.
Figure 36. ICC1H test circuit.
1
16
1
GND1
VE
16
15
14
13
12
11
10
9
GND1
VE
VLED2+
DESAT
_
_
0.1μF
30V
_
+
2
3
4
5
6
7
8
VIN+
VIN
VCC1
VLED2+ 15
+
2
3
4
5
6
7
8
VIN+
VIN
VCC1
+
14
13
12
11
10
9
DESAT
5.5V
5V
0.1μF
0.1μF
VCC2
VEE
VCC2
VEE
VC
ICC1
0.1μF
RESET
FAULT
VLED+
RESET
FAULT
30V
VC
+
_
VOUT
VLED+
VLED
VOUT
VEE
0.1μF
VLED
VEE
Figure 37. ICC1L test circuit.
Figure 38. ICC2H test circuit.
17
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
16
VE
16
15
14
GND1
VIN+
GND1
VIN+
VE
VLED2+
DESAT
_
30V
_
0.1μF
30V
_
0.1μF
0.1μF
+
VLED2+ 15
+
+
ICHG
VIN
DESAT
VIN
0.1μF
14
5V
VCC1
VCC2
VEE
13
12
VCC1
VCC2 13
ICC2
VEE
0.1μF
0.1μF
RESET
FAULT
VLED+
VLED
12
RESET
FAULT
VLED+
VLED
30V
30V
VC
VC 11
11
+
_
+
_
VOUT
VEE
10
9
VOUT 10
0.1μF
9
VEE
Figure 39. ICC2L test circuit.
Figure 40. ICHG pulsed test circuit.
GND1
VIN+
VE
VLED2+
DESAT
1
2
3
4
5
6
7
8
1
16
15
14
13
12
11
10
9
GND1
VE 16
7V
30V
_
_
_
0.1μF
+
2
3
4
5
6
7
8
VIN+
VLED2+
15
14
13
12
11
10
9
+
+
ICHG
IDSCHG
VIN
VIN
DESAT
5V
0.1μF
VCC1
VCC2
VEE
VCC1
VCC2
VEE
RESET
FAULT
VLED+
VLED
0.1μF
RESET
FAULT
VLED+
VLED
30V
Sweep
0.1μF
VC
VOUT
VEE
0.1μF
VC
VOUT
VEE
+
_
+
_
VOUT
Figure 41. IDSCHG test circuit.
Figure 42. UVLO threshold test circuit.
1
1
GND1
VE 16
16
15
14
13
12
GND1
VE
7V
30V
_
15V
_
_
0.1μF
0.1μF
VIN
2
3
4
5
6
7
8
VIN+
VLED2+
15
2
3
4
5
6
7
8
VIN+
VLED2+
DESAT
+
+
+
VIN
VIN
DESAT 14
_
SWEEP
5V
+
VCC1
VCC2
VCC1
VCC2
VEE
13
0.1μF
VEE
0.1μF
0.1μF
RESET
FAULT
VLED+
VLED
12
RESET
FAULT
VLED+
VLED
VOUT
30V
15V
0.1μF
VC
VOUT
VEE
0.1μF
11
10
9
10mA
VC 11
+
_
+
_
10Ω
3 k
VOUT
10
9
10nF
0.1μF
VEE
Figure 43. DESAT threshold test circuit.
Figure 44. tPLH, tPHL, tr, tf test circuit.
18
1
2
1
2
GND1
VIN+
VE
GND1
VIN+
VE
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
30V
0.1μF
0.1μF
30V
_
0.1μF
0.1μF
VLED2+
VLED2+
VIN
IN
+
+
3 VIN
VCC1
DESAT
VCC2
VEE
3 VIN
VCC1
DESAT
VCC2
VEE
5V
5V
_
3 k
4
4
0.1μF
0.1μF
VOUT
VOUT
5 RESET
5 RESET
0.1μ
0.1μF
30V
30V
VC
VOUT
VEE
VC
VOUT
VEE
6
6
FAULT
FAULT
+
+
VFAULT
3 k
10Ω
10Ω
10nF
_
VLED+
VLED+
7
7
10nF
8 VLED
8 VLED
Figure 45. tDESAT(10%) test circuit.
Figure 46. tDESAT(FAULT) test circuit.
1 GND1
VIN+
VE
1
16
16
GND1
VE
+
5V
0.1μF
+
5V
_
0.1μF
30V
+
0.1μF
0.1μF
_
VLED2+
2
2 VIN+
VLED2+
15
14
13
12
11
10
9
15
STROBE 8V
VOUT
_
3 VIN
DESAT
VCC2
VEE
3
VIN
4 VCC1
5
DESAT 14
3 k
3 k
VCC1
4
5
6
7
8
VCC2
VEE
13
12
11
10
9
VIN HIGH TO LOW
VFAULT
VOUT
RESET
FAULT
VLED+
VLED
0.1μF
RESET
30V
0.1μF
VC
VOUT
VEE
6
VC
VOUT
VEE
FAULT
+
10Ω
10Ω
10nF
_
7 VLED+
10nF
8
VLED
Figure 47. tRESET(FAULT) test circuit.
Figure 48. UVLO delay test circuit.
1
1
16
VE
GND1
VE 16
GND1
5V
5V
2 VIN+
VLED2+
2
3
4
5
6
7
8
15
VIN+
VLED2+ 15
25V
VOUT
10Ω
25V
3
4
5
6
VIN
DESAT 14
14
13
12
VIN
DESAT
VCC2
VEE
VCC1
VCC2
VCC1
13
3 kΩ
3 kΩ
0.1μF
0.1μF
0.1μF
0.1μF
VEE
RESET
FAULT
12
RESET
FAULT
VLED+
VLED
VC
VOUT
VEE
SCOPE
0.1μF
SCOPE
0.1μF
11
10
9
VC 11
10Ω
7 VLED+
8 VLED
VOUT 10
10nF
10nF
9
VEE
750Ω
_
9V
+
Figure 49. CMR test circuit, LED2 off.
Figure 50. CMR test circuit, LED2 on.
19
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
GND1
VIN+
VE 16
16
15
14
GND1
VIN+
VE
VLED2+
DESAT
5V
5V
VLED2+
15
25V
0.1μF
25V
VIN
DESAT 14
VIN
VCC1
VCC2
13
VCC1
VCC2 13
0.1μF
3 kΩ
3 kΩ
100pF
0.1μF
0.1μF
VEE
VEE
RESET
FAULT
VLED+
VLED
12
12
RESET
FAULT
VLED+
VLED
SCOPE
10Ω
VC
VOUT
VEE
11
10
9
11
VC
100pF
VOUT 10
SCOPE
10nF
10Ω
10nF
9
VEE
VCM
VCM
Figure 51. CMR test circuit, LED1 off.
Figure 52. CMR test circuit, LED1 on.
VIN-
VIN-
0 V
2.5 V
2.5 V
VIN+
2.5 V
2.5 V
VIN+
5.0 V
tr
tf
tr
tf
90%
90%
50%
10%
50%
10%
VOUT
VOUT
tPLH
tPHL
tPLH
tPHL
Figure 53. VOUT propagation delay waveforms, noninverting configuration.
Figure 54. VOUT propagation delay waveforms, inverting configuration.
tDESAT (FAULT)
tDESAT (10%)
tDESAT (LOW)
7 V
VDESAT
50%
tDESAT (90%)
VOUT
90%
10%
FAULT
RESET
50% (2.5 V)
tRESET (FAULT)
50%
Figure 55. Desat, VOUT, fault, reset delay waveforms.
20
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
GND1
VIN+
VE 16
GND1
VIN+
VE
VLED2+
DESAT
16
15
14
13
12
11
10
9
_
30V
_
30V
0.1μF
0.1μF
0.1μF
0.1μF
_
_
+
+
VLED2+ 15
+
+
5V
5V
0.1μF
VIN
DESAT
VIN
14
13
12
11
10
9
0.1μF
VCC1
VCC2
VEE
VCC1
VCC2
VEE
0.1μF
0.1μF
RESET
FAULT
VLED+
VLED
RESET
FAULT
VLED+
VLED
IC
IC
30V
30V
VC
VOUT
VEE
VC
VOUT
VEE
+
_
+
_
650μF
Figure 56. ICH test circuit.
Figure 57. ICH test circuit.
IE
1
2
3
4
5
6
7
8
1
GND1
VIN+
VE
VLED2+
DESAT
16
15
16
15
14
13
12
11
10
9
GND1
VE
_
+
30V
30V
0.1μF
0.1μF
0.1μF
0.1μF
_
_
2
3
4
5
6
7
8
VIN+
VLED2+
+
+
5V
VIN
0.1μF
VIN
DESAT 14
VCC2 13
VCC1
VCC2
VEE
VCC1
VEE
0.1μF
0.1μF
RESET
FAULT
VLED+
VLED
RESET
FAULT
VLED+
VLED
12
IC
30V
30V
VC
VOUT
VEE
VC
11
+
_
+
_
VOUT
10
VEE
9
Figure 58. ICL test circuit.
Figure 59. IEH test circuit.
IE
1
2
3
4
5
6
7
8
GND1
VE
VLED2+
DESAT
16
15
14
13
12
11
10
9
_
30V
0.1μF
0.1μF
_
+
VIN+
+
5V
VIN
0.1μF
VCC1
VCC2
VEE
0.1μF
RESET
FAULT
VLED+
VLED
30V
VC
VOUT
VEE
+
_
Figure 60. IEL test circuit.
21
Typical Application/Operation
Introduction to Fault Detection and Protection
The alternative protection scheme of measuring IGBT
current to prevent desaturation is effective if the short
circuit capability of the power device is known, but this
method will fail if the gate drive voltage decreases enough
to only partially turn on the IGBT. By directly measuring
the collector voltage, the ACPL-38JT limits the power
dissipation in the IGBT even with insufficient gate drive
voltage. Another more subtle advantage of the desatu-
ration detection method is that power dissipation in the
IGBT is monitored, while the current sense method relies
on a preset current threshold to predict the safe limit of
operation. Therefore, an overly- conservative overcurrent
threshold is not needed to protect the IGBT.
The power stage of a typical three phase inverter is sus-
ceptible to several types of failures, most of which are
potentially destructive to the power IGBTs. These failure
modes can be grouped into four basic categories: phase
and/or rail supply short circuits due to user misconnect or
bad wiring, control signal failures due to noise or compu-
tational errors, overload conditions induced by the load,
and component failures in the gate drive circuitry. Under
any of these fault conditions, the current through the
IGBTs can increase rapidly, causing excessive power dis-
sipation and heating. The IGBTs become damaged when
the current load approaches the saturation current of the
device, and the collector to emitter voltage rises above the
saturation voltage level. The drastically increased power
dissipation very quickly overheats the power device and
destroys it. To prevent damage to the drive, fault protec-
tion must be implemented to reduce or turn--off the over-
currents during a fault condition.
Recommended Application Circuit
The ACPL-38JT has both inverting and non-inverting gate
control inputs, an active low reset input, and an open
collector fault output suitable for wired ‘OR’applications.
A circuit providing fast local fault detection and shutdown
is an ideal solution, but the number of required compo-
nents, board space consumed, cost, and complexity have
until now limited its use to high performance drives. The
features which this circuit must have are high speed, low
cost, low resolution, low power dissipation, and small size.
The recommended application circuit shown in Figure 61
illustrates a typical gate drive implementation using the
ACPL-38JT.
The four supply bypass capacitors (0.1 F) provide the
large transient currents necessary during a switching
transition. Because of the transient nature of the charging
currents, a low current (5 mA) power supply suffices.
The desat diode and 100pF capacitor are the necessary
external components for the fault detection circuitry. The
gate resistor (10 ) serves to limit gate charge current and
indirectly control the IGBT collector voltage rise and fall
times. The open collector fault output has a passive 3.3 k
pull-up resistor and a 330 pF filtering capacitor.
Applications Information
The ACPL-38JT satisfies these criteria by combining a high
speed, high output current driver, high voltage optical
isolation between the input and output, local IGBT de-
saturation detection and shut down, and an optically
isolated fault status feedback signal into a single 16-pin
surface mount package.
The fault detection method, which is adopted in the
ACPL-38JT, is to monitor the saturation (collector) voltage
of the IGBT and to trigger a local fault shutdown sequence
A clamping diode between V
positive going voltage noises affecting the FAULT status.
and RESET will prevent
CC1
A 47 k pulldown resistor on V
predictable high level output voltage (V ). In this appli-
cation, the IGBT gate driver will shut down when a fault is
detected and will not resume switching until the micro-
controller applies a reset signal.
provides a more
OUT
if the collector voltage exceeds
a predetermined
OH
threshold. A small gate discharge device slowly reduces
the high short circuit IGBT current to prevent damaging
voltage spikes. Before the dissipated energy can reach de-
structive levels, the IGBT is shut off. During the off state
of the IGBT, the fault detect circuitry is simply disabled to
prevent false ‘fault’signals.
22
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND1
VE
100pF
0.1μF
0.1μF
VIN+
VIN-
VLED2+
DESAT
DDESAT
0.1μF
100Ω
−
+
+ V
−
F
5V
μC
V
VCC2
VEE
CC1
VCC2 =18V
RESET
FAULT
VLED+
VLED-
0.1μF
+
V−CE
+
Q1
Q2
RG
3.3kΩ
−
VC
VOUT
VEE
3-Phase
Output
330pF
47kΩ
+
−
+
V−CE
= -5V
VEE
Figure 61. Recommended application circuit.
Description of Operation/Timing
Fault Condition
Figure 62 illustrates input and output waveforms under When the voltage on the DESAT pin exceeds 7 V while
the conditions of normal operation, a desat fault condition, the IGBT is on, V is slowly brought low in order to
OUT
and normal reset behavior.
“softly” turn-off the IGBT and prevent large di/dt induced
voltages. Also activated is an internal feedback channel
which brings the FAULT output low for the purpose of
notifying the micro-controller of the fault condition. See
Figure 62.
Normal Operation
During normal operation, V
of the ACPL-38JT is con-
OUT
trolled by either V
or V , with the IGBT collector-to-
IN+
IN-
emitter voltage being monitored through D
FAULT output is high and the RESET input should be held
high. See Figure 62.
. The
DESAT
Reset
The FAULT output remains low until RESET is brought
low. See Figure 62. While asserting the RESET pin (LOW),
the input pins must be asserted for an output low state
(V
is LOW or V is HIGH). This may be accomplished
IN+
IN-
either by software control (i.e. of the microcontroller) or
hardware control (see Figures 71 and 72).
NORMAL
OPERATION
FAULT
CONDITION
RESET
VIN-
0 V
5 V
NON-INVERTING
CONFIGURED
INPUTS
VIN+
VIN-
5 V
5 V
INVERTING
CONFIGURED
INPUTS
VIN+
7 V
VDESAT
VOUT
FAULT
RESET
Figure 62. Timing diagram.
23
Slow IGBT Gate Discharge During Fault Condition
is applied. Once V
UVLO threshold), the UVLO clamp is released to allow the
device output to turn on in response to input signals. As
exceeds V
(the positive-going
UVLO+
When a desaturation fault is detected, a weak pull-down
device in the ACPL-38JT output drive stage will turn on
to ‘softly’ turn off the IGBT. This device slowly discharges
the IGBT gate to prevent fast changes in drain current that
could cause damaging voltage spikes due to lead and
wire inductance. During the slow turn off, the large output
pull-down device remains off until the output voltage falls
CC2
V
CC2
is increased from 0 V (at some level below V
),
UVLO+
first the DESAT protection circuitry becomes active.
As V is further increased (above V ), the UVLO
CC2
UVLO+
clamp is released. Before the time the UVLO clamp is
released, the DESAT protection is already active. Therefore,
the UVLO and DESAT FAULT DETECTION features work
together to provide seamless protection regardless of
below V + 2 Volts, at which time the large pull down
EE
device clamps the IGBT gate to V
.
EE
DESAT Fault Detection Blanking Time
supply voltage (V ).
CC2
The DESAT fault detection circuitry must remain disabled
for a short time period following the turn-on of the IGBT
to allow the collector voltage to fall below the DESAT
theshold. This time period, called the DESAT blanking
time, is controlled by the internal DESAT charge current,
the DESAT voltage threshold, and the external DESAT
capacitor.The nominal blanking time is calculated in terms
Behavioral Circuit Schematic
The functional behavior of the ACPL-38JT is represented
by the logic diagram in Figure 63 which fully describes the
interaction and sequence of internal and external signals
in the ACPL-38JT.
Input IC
of external capacitance (C
), FAULT threshold voltage
BLANK
(V
), and DESAT charge current (ICHG) as t
=
DESAT
BLANK
In the normal switching mode, no output fault has been
detected, and the low state of the fault latch allows the
input signals to control the signal LED. The fault output is
in the open-collector state, and the state of the Reset pin
does not affect the control of the IGBT gate. When a fault
is detected, the FAULT output and signal input are both
latched. The fault output changes to an active low state,
and the signal LED is forced off (output LOW). The latched
condition will persist until the Reset pin is pulled low.
C
x V
/ I
. The nominal blanking time with the
BLANK
DESAT CHG
recommended 100 pF capacitor is 100 pF * 7 V / 250 A =
2.8 sec. The capacitance value can be scaled slightly to
adjust the blanking time, though a value smaller than 100
pF is not recommended.
This nominal blanking time also represents the longest
time it will take for the ACPL-38JT to respond to a DESAT
fault condition. If the IGBT is turned on while the collector
and emitter are shorted to the supply rails (switching into
a short), the soft shut-down sequence will begin after ap-
proximately 3 sec. If the IGBT collector and emitter are
shorted to the supply rails after the IGBT is already on, the
response time will be much quicker due to the parasitic
parallel capacitance of the DESAT diode. The recommend-
ed 100 pF capacitor should provide adequate blanking as
well as fault response times for most applications.
Output IC
Three internal signals control the state of the driver
output: the state of the signal LED, as well as the UVLO and
Fault signals. If no fault on the IGBT collector is detected,
and the supply voltage is above the UVLO threshold, the
LED signal will control the driver output state. The driver
stage logic includes an interlock to ensure that the pull-up
and pull-down devices in the output stage are never on at
the same time. If an undervoltage condition is detected,
the output will be actively pulled low by the 50x DMOS
device, regardless of the LED state. If an IGBT desaturation
fault is detected while the signal LED is on, the Fault signal
will latch in the high state. The triple darlington AND the
50x DMOS device are disabled, and a smaller 1x DMOS
pull-down device is activated to slowly discharge the
IGBT gate. When the output drops below two volts, the
50x DMOS device again turns on, clamping the IGBT gate
firmly to Vee. The Fault signal remains latched in the high
state until the signal LED turns off.
Under Voltage Lockout
The ACPL-38JT Under Voltage Lockout (UVLO) feature is
designed to prevent the application of insufficient gate
voltage to the IGBT by forcing the ACPL-38JT output low
during power-up. IGBTs typically require gate voltages of
15V to achieve their ratedV
voltage. At gate voltages
CE(ON)
below 13V typically, their on-voltage increases dramatical-
ly, especially at higher currents. At very low gate voltages
(below 10V), the IGBT may operate in the linear region and
quickly overheat. The UVLO function causes the output to
be clamped whenever insufficient operating supply (V
)
CC2
24
250 μA
VE (16)
DESAT (14)
+
–
VIN+ (2)
VIN– (3)
LED
7 V
VCC1 (4)
GND (1)
VCC2 (13)
VC (11)
–
+
UVLO
DELAY
Q
12 V
FAULT (6)
VOUT (10)
VEE (9,12)
R
S
50 x
RESET (5)
FAULT
1 x
Figure 63. Behavioral circuit schematic
16
1
2
3
4
5
6
7
8
GND1
VIN+
VE
16
1
2
3
4
5
6
7
8
GND1
VE
VLED2+
DESAT
100pF
100pF
15
VLED2+
15
14
13
12
11
10
9
VIN+
DDESAT
100Ω
VIN
DESAT 14
VCC2 13
VIN
MJD44H11 or
VCC1
VCC1
VCC2
VEE
D44VH10
Rg
VEE
4.5Ω
RESET
FAULT
VLED+
VLED
12
RESET
FAULT
VLED+
VLED
VC
VOUT
VEE
11
10
9
VC
VOUT
VEE
10Ω
2.5Ω
10nF
MJD45H11 or
D45VH10
15V
-5V
Figure 64. Output pull-down resistor.
Figure 65. DESAT pin protection.
1
2
3
4
5
6
7
8
GND1
VIN+
VE
16
15
14
VLED2+
DESAT
0.1μF
VIN
5V
μC
VCC1
VCC2 13
3.3kΩ
VEE
RESET
FAULT
VLED+
VLED
12
VC
11
330pF
VOUT 10
9
VEE
Figure 66. FAULT Pin CMR protection.
25
Other Recommended Components
Driving with Standard CMOS/TTL for High CMR
The application circuit in Figure 61 includes an output pull- Capacitive coupling from the isolated high voltage
down resistor, a DESAT pin protection resistor, a FAULT pin
capacitor (330 pF), and a FAULT pin pull-up resistor.
circuitry to the input referred circuitry is the primary CMR
limitation. This coupling must be accounted for to achieve
high CMR performance. The input pins V and V must
IN+
IN-
Output Pull-Down Resistor
have active drive signals to prevent unwanted switching
of the output under extreme common mode transient
conditions. Input drive circuits that use pull-up or pull-
down resistors, such as open collector configurations,
should be avoided. Standard CMOS or TTL drive circuits
are recommended.
During the output high transition, the output voltage
rapidly rises to within 3 diode drops of V . If the output
CC2
current then drops to zero due to a capacitive load, the
output voltage will slowly rise from roughly V -3(V
)
CC2
BE
to V
within a period of several microseconds. To limit
CC2
the output voltage to V -3(V ), a pull-down resistor
CC2
BE
User-Configuration of the ACPL-38JT Input Side
between the output and V is recommended to sink a
EE
static current of several 650 A while the output is high. The V , V , FAULT and RESET input pins make a wide
IN+ IN-
Pull-down resistor values are dependent on the amount variety of gate control and fault configurations possible,
of positive supply and can be adjusted according to the
formula, R = [V -3 * (V )] / 650 A.
depending on the motor drive requirements. The
ACPL-38JT has both inverting and nonninverting gate
control inputs, an open collector fault output suitable for
wired ‘OR’applications and an active low reset input.
pull-down
CC2
BE
DESAT Pin Protection
The freewheeling of flyback diodes connected across the
IGBTs can have large instantaneous forward voltage tran-
sients which greatly exceed the nominal forward voltage
of the diode. This may result in a large negative voltage
spike on the DESAT pin which will draw substantial current
out of the IC if protection is not used. To limit this current
to levels that will not damage the IC, a 100 ohm resistor
should be inserted in series with the DESAT diode. The
added resistance will not alter the DESAT threshold or the
DESAT blanking time.
Driving Input of ACPL-38JT in Non-Inverting/
Inverting Mode
The Gate Drive Voltage Output of the ACPL-38JT can be
configured as inverting or non-inverting using the V
IN–
and V
inputs. As shown in Figure 67, when a non-in-
IN+
verting configuration is desired, V is held low by con-
IN–
necting it to GND1 and V is toggled. As shown in Figure
IN+
68, when an inverting configuration is desired, V is held
IN+
high by connecting it to V
and V is toggled.
CC1
IN–
Pull-up Resistor on FAULT Pin
Local Shutdown, Local Reset
The FAULT pin is an open-collector output and therefore
requires a pull-up resistor to provide a high-level signal.
As shown in Figure 69, the fault output of each ACPL-38JT
gate driver is polled separately, and the individual reset
lines are asserted low independently to reset the motor
controller after a fault condition.
Capacitor on FAULT Pin for High CMR
Rapid common mode transients can affect the fault pin
voltage while the fault output is in the high state. A 330 pF
capacitor (Fig. 66) should be connected between the fault
pin and ground to achieve adequate CMOS noise margins
at the specified CMR value of 15 kV/s. The added capaci-
tance does not increase the fault output delay when a de-
saturation condition is detected.
Global-Shutdown, Global Reset
As shown in Figure 70, when configured for inverting
operation, the ACPL-38JT can be configured to shutdown
automatically in the event of a fault condition by tying the
FAULT output to V . For high reliability drives, the open
IN+
collector FAULT outputs of each ACPL-38JT can be wire
‘OR’ed together on a common fault bus, forming a single
fault bus for interfacing directly to the micro-controller.
Protection on RESET Pin for High CMR
Large voltage spike on RESET due to excessive switching
noise coupling could trigger false FAULT output signal. In
such cases connecting a 330pF filtering capacitor between
RESET and GROUND or a clamping diode between RESET
When any of the six gate drivers detects a fault, the fault
output signal will disable all six ACPL-38JT gate drivers
simultaneously and thereby provide protection against
further catastrophic failures.
to V
will eliminate the false FAULT signal.
CC1
26
GND1
VIN+
VE
VLED2+
DESAT
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND1
VIN+
VE 16
VLED2+ 15
DESAT 14
VIN
VIN
μC
VCC1
VCC2
VEE
μC
13
12
11
10
9
VCC1
VCC2
VEE
RESET
FAULT
VLED+
VLED
RESET
FAULT
VLED+
VLED
VC
VOUT
VEE
VC
VOUT
VEE
Figure 67. Typical input configuration, noninverting.
Figure 68. Typical Input Configuration, Inverting.
GND1
VIN+
VE
VLED2+
DESAT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VIN
μC
VCC1
VCC2
VEE
RESET
FAULT
VLED+
VLED
VC
VOUT
VEE
Figure 69. Local shutdown, local reset configuration.
Auto-Reset
Resetting Following a Fault Condition
As shown in Figure 71, when the inverting V input is
To resume normal switching operation following a fault
IN-
connected to ground (non-inverting configuration), the condition (FAULT output low), the RESET pin must first be
ACPL-38JT can be configured to reset automatically by asserted low in order to release the internal fault latch and
connecting RESET to V . In this case, the gate control reset the FAULT output (high). Prior to asserting the RESET
IN+
signal is applied to the non-inverting input as well as the
pin low, the input (V ) switching signals must be config-
IN
reset input to reset the fault latch every switching cycle. ured for an output (V ) low state. This can be handled
OL
During normal operation of the IGBT, asserting the reset
directly by the microcontroller or by hardwiring to syn-
input low has no effect. Following a fault condition, the chronize the RESET signal with the appropriate input
gate driver remains in the latched fault state until the gate signal. Figure 72a shows how to connect the RESET to the
control signal changes to the ‘gate low’ state and resets
V
signal for safe automatic reset in the non-inverting
IN+
the fault latch. If the gate control signal is a continuous input configuration. Figure 72b shows how to configure
PWM signal, the fault latch will always be reset by the the V /RESET signals so that a RESET signal from the
IN+
next time the input signal goes high. This configuration microcontroller causes the input to be in the “output-
protects the IGBT on a cycle-by-cycle basis and automati- off” state. Similarly, Figures 72c and 72d show automatic
cally resets before the next‘on’cycle. The fault outputs can RESET and microcontroller RESET safe configurations for
be wire ‘OR’ed together to alert the microcontroller, but the inverting input configuration.
this signal would not be used for control purposes in this
(Auto-Reset) configuration. When the ACPL-38JT is con-
figured for Auto-Reset, the guaranteed minimum FAULT
signal pulse width is 3 s.
27
1
2
3
4
5
6
7
8
GND1
VIN+
VE
16
1
2
3
4
5
6
7
8
GND1
VIN+
VE
VLED2+
DESAT
16
15
14
13
12
11
VLED2+ 15
DESAT 14
VCC2 13
VIN
VIN
C
C
VCC1
VCC2
VEE
VCC1
VEE
RESET
FAULT
VLED+
VLED
RESET
FAULT
VLED+
VLED
12
VC
VC
11
VOUT 10
VOUT 10
9
9
VEE
VEE
CONNECT TO CONNECT TO
OTHER
RESETS
OTHER
FAULTS
Figure 70. Global-shutdown, global reset configuration.
Figure 71. Auto-reset configuration.
GND1
VIN+
VE
VLED2+
DESAT
1
2
3
4
5
6
7
8
GND1
VE
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VIN+
VIN+
VLED2+
DESAT
VIN
VIN
VCC
VCC
VIN+
RESET
/
C
VCC1
VCC2
VEE
C
VCC1
VCC2
VEE
RESET
FAULT
RESET
FAULT
VLED+
VLED
RESET
FAULT
VLED+
VLED
FAULT
VC
VOUT
VEE
VC
VOUT
VEE
Figure 72a. Safe hardware reset for non-inverting input configuration
(automatically resets for every VIN+ input).
Figure 72b. Safe hardware reset for non-inverting input configuration.
VCC
VCC
GND1
VIN+
VE
VLED2+
DESAT
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
GND1
VIN+
VE
16
15
14
13
12
11
10
9
16
15
VLED2+
VIN
RESET
FAULT
VIN
VIN
VIN
DESAT 14
VCC2 13
C
C
VCC1
VCC2
VEE
VCC1
RESET
FAULT
VEE
RESET
FAULT
VLED+
VLED
RESET
FAULT
VLED+
VLED
12
VC
VOUT
VEE
VC
11
VOUT 10
9
VEE
Figure 72c. Safe hardware reset for inverting input configuration.
Figure 72d. Safe hardware reset for inverting input configuration
(automatically resets for every VIN- input).
28
16
15
14
13
12
11
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
GND1
VIN+
VE
VLED2+
DESAT
VE
VLED2+
DESAT
100pF
100pF
VIN
MJD44H11 or
VCC1
VCC2
VEE
VCC2
VEE
D44VH10
RC8Ω
4.5Ω
RESET
FAULT
VLED+
VLED
VC
VC
VOUT
VEE
10Ω
10Ω
2.5Ω
VOUT 10
10nF
10nF
MJD45H11 or
D45VH10
9
VEE
15V
15V
-5V
-5V
Figure 73. Use of RC to further limit ION,PEAK
.
Figure 74. Current buffer for increased drive current
Higher Output Current Using an External Current Buffer: DESAT Diode and DESAT Threshold
To increase the IGBT gate drive current, a non-inverting The DESAT diode’s function is to conduct forward current,
current buffer (such as the npn/pnp buffer shown in Figure
74) may be used. Inverting types are not compatible with emitter voltage, V
allowing sensing of the IGBT’s saturated collector-to-
, (when the IGBT is “on”) and to
CESAT
the de-saturation fault protection circuitry and should be block high voltages (when the IGBT is “off”). During the
avoided. To preserve the slow IGBT turn-off feature during short period of time when the IGBT is switching, there is
a fault condition, a 10 nF capacitor should be connected commonly a very high dV /dt voltage ramp rate across
CE
from the buffer input to V and a 10 W resistor inserted the IGBT’s collector-to-emitter. This results in I
(=
EE
CHARGE
between the output and the common npn/pnp base. The
MJD44H11/MJD45H11 pair is appropriate for currents up
C
x dV /dt) charging current which will charge
D-DESAT CE
the blanking capacitor, C
. In order to minimize this
BLANK
to 8A maximum. The D44VH10/ D45VH10 pair is appropri- charging current and avoid false DESAT triggering, it
ate for currents up to 15 A maximum.
is best to use fast response diodes. Listed in the below
table are fast-recovery diodes that are suitable for use as
a DESAT diode (D
). In the recommended application
DESAT
circuit shown in Figure 61, the voltage on pin 14 (DESAT)
is V = V + V , (where V is the forward ON voltage
DESAT
F
CE
F
of D
and V is the IGBT collector-to-emitter voltage).
DESAT
CE
The value of V which triggers DESAT to signal a FAULT
CE
condition, is nominally 7V – V . If desired, this DESAT
F
threshold voltage can be decreased by using multiple
DESAT diodes in series. If n is the number of DESAT diodes
then the nominal threshold value becomes V
=
CE,FAULT(TH)
7 V – n x V . In the case of using two diodes instead of one,
F
diodes with half of the total required maximum reverse-
voltage rating may be chosen.
Max. Reverse Voltage Rating
Part Number
MUR1100E
MURS160T3G
UF4007
Manufacturers
t (ns)
V
(Volts)
Package Type
rr
RRM
ON Semiconductor
ON Semiconductor
Vishay General Semi.
Vishay General Semi.
75
75
75
75
1000
600
59-04 (axial leaded)
Case 403A (surface mount)
DO-204AL (axial leaded)
SOD57 (axial leaded)
1000
1000
BYV26E
29
Power Considerations
Operating Within the Maximum Allowable Power Ratings (Adjusting Step 2: Calculate total power dissipation in the ACPL-38JT:
Value of R ):
G
The ACPL-38JT total power dissipation (P ) is equal to the
T
When choosing the value of R , it is important to confirm
sum of the input-side power (P ) and output-side power
G
I
that the power dissipation of the ACPL-38JT is within the (P ):
O
maximum allowable power rating.
P = P + P
T
I
O
P = I
* V
I
CC1
CC1
The steps for doing this are:
P
= I
= P
+ P
O
O(BIAS) O(SWTICH)
1. Calculate the minimum desired R ;
G
* (V –V ) + E * f
SWITCH SWITCH
CC2
CC2 EE
2. Calculate total power dissipation in the part referring
where,
PO (BIAS) = steady-state power dissipation in the ACPL-38JT
to Figure 76. (Average switching energy supplied to
ACPL-38JT per cycle vs. R plot);
G
3. Compare the input and output power dissipation due to biasing the device.
calculated in step #2 to the maximum recommended
PO (SWITCH) = transient power dissipation in the ACPL-38JT
due to charging and discharging power device gate.
dissipation for the ACPL-38JT. (If the maximum rec-
ommended level has been exceeded, it may be nec-
essary to raise the value of R to lower the switching
power and repeat step #2.)
ESWITCH = Average Energy dissipated in ACPL-38JT due to
switching of the power device over one switching cycle
(J/cycle).
G
Asanexample,thetotalinputandoutputpowerdissipation
can be calculated given the following conditions:
fSWITCH = average carrier signal frequency.
I
~ 2.0 A
ON, MAX
V
V = -5 V
= 18 V
CC2
MAX. ION, IOFF vs. GATE RESISTANCE (VCC2 / VEE2 = 25 V / 5 V)
4
EE
f
= 10 kHz
CARRIER
3
2
1
Step 1: Calculate R minimum from I peak specification:
G
OL
To find the peak charging l assume that the gate is
initially charged the steady-state value of V . Therefore
OL
IOFF (MAX.)
EE
apply the following relationship:
0
-1
-2
-3
ION (MAX.)
[V @650 A – (V +V )]
OH
OL EE
R
G
=
=
=
I
OL, PEAK
[V – 1 – (V + V )]
CC2
OL
EE
0
20 40 60 80 100 120 140 160 180 200
I
Rg (Ω)
OL, PEAK
Figure 75. Typical peak ION and IOFF currents vs. Rg (for ACPL-38JT output
driving an IGBT rated at 600 V/100 A).
18 V – 1 V – (1.5 V + (-5 V))
2.0 A
=
≈
10.25
For RG = 10.5, the value read from Figure 76 is ESWITCH
=
10.5 (for a 1% resistor)
6.05 J. Assume a worst-case average ICC1 = 16.5 mA
(which is given by the average of ICC1H and ICC1L). Similarly
the average ICC2 = 5.5 mA.
(Note from Figure 75 that the real value of I may vary
from the value calculated from the simple model shown.)
OL
P
P
= 16.5 mA * 5.5 V = 90.8 mW
= P + P
I
O
O(BIAS)
O(SWITCH)
= 5.5 mA * (18 V – (–5 V)) + 6.051 J * 10 kHz
= 126.5 mW + 60.51 mW
= 187.01 mW
30
Step 3: Compare the calculated power dissipation with the absolute As long as the maximum power specification is not
maximum values for the ACPL-38JT:
exceeded, the only other limitation to the amount of
power one can dissipate is the absolute maximum junction
temperature specification of 140°C. The junction tempera-
tures can be calculated with the following equations:
For the example,
P = 90.8 mW < 150 mW (abs. max.) OK
I
P
= 187.01 mW < 600 mW (abs. max.) OK
O
T = P ( + ) + T
ji
i
i1
1A
A
T
= P (
+
) + T
Therefore, the power dissipation absolute maximum
rating has not been exceeded for the example.
jo
o
o9,12
9,12A A
where P = power into input IC and P = power into output
i
o
IC.
Please refer to the following Thermal Model section for an
explanation on how to calculate the maximum junction
temperature of the ACPL-38JT for a given PC board layout
configuration.
Since and θ
are dependent on PCB layout
9,12A
1A
and airflow, their exact number may not be available.
Therefore, a more accurate method of calculating the
junction temperature is with the following equations:
SWITCHING ENERGY vs. GATE RESISTANCE
(VCC2 / VEE2 = 25 V / 5 V)
T = P + T
ji
9
i i1
P1
8
7
6
T
= P
+ T
jo
o o9,12 P9,12
These equations, however, require that the pin 1 and pins
9, 12 temperatures be measured with a thermal couple on
the pin at the ACPL-38JT package edge.
5
Ess (Qg = 650 nC)
4
P = 90.8 mW, P = 314 mW, T = 125°C, and assuming the
thermal model shown in Figure 77 below.
i
o
A
3
2
T
T
= (90.8 mW)(60°C/W + 50°C/W) + 125°C = 135°C
= (187.01 mW)(30°C/W + 50°C/W) + 125°C = 140°C
1
0
ji
jo
0
50
100
150
200
Rg (Ω)
If we, however, assume a worst case PCB layout and no
air flow where the estimated q1A and q9,12A are 100°C/W.
Then the junction temperatures become
Figure 76. Switching energy plot for calculating average Pswitch
(for ACPL-38JT output driving an IGBT rated at 600 V/100 A).
T
T
= (90.8 mW)(60°C/W + 100°C/W) + 125°C = 140°C
= (187.01 mW)(30°C/W + 100°C/W) + 125°C = 149°C
ji
Thermal Model
jo
The ACPL-38JT is designed to dissipate the majority of the
heat through pins 1 for the input IC and pins 9 and 12 for
the output IC. (There are two V pins on the output side,
both of which are within the absolute maximum specifi-
cation of 150°C.
EE
pins 9 and 12, for this purpose.) Heat flow through other
pins or through the package directly into ambient are
considered negligible and not modeled here.
If the calculated junction temperatures for the thermal
model in Figure 77 is higher than 150°C, the pin tempera-
ture for pins 9 and 12 should be measured (at the package
edge) under worst case operating environment for a more
accurate estimate of the junction temperatures.
In order to achieve the power dissipation specified in the
absolute maximum specification, it is imperative that
pins 1, 9, and 12 have ground planes connected to them.
From the earlier power dissipation calculation example:
Tji = junction temperature of input side IC
Tjo = junction temperature of output side IC
TP1 = pin 1 temperature at package edge
TP9,12 = pin 9 and 12 temperature at package edge
Tji
Tjo
I1 = 60°C/W
l9, 12 = 30°C/W
I1 = input side IC to pin 1 thermal resistance
I9,12 = output side IC to pin 9 and 12 thermal resistance
1A = pin 1 to ambient thermal resistance
TP9, 12
9, 12A = 50°C/W*
TP1
9,12A = pin 9 and 12 to ambient thermal resistance
1A = 50°C/W*
* The and
values shown here are for PCB layouts shown in Figure 77
9,12A
1A
with reasonable air flow. This value may increase or decrease by a factor of
2 depending on PCB layout and/or airflow.
TA
Figure 77. Thermal Model for ACPL-38JT
31
Printed Circuit Board Layout Considerations
Adequate spacing should always be maintained between Bypass Capacitors should be placed in between these
the high voltage isolated circuitry and any input refer- pins: V
enced circuitry. Care must be taken to provide the same
to V , V to V , V
to GND1 and V
to V .
CC2
E
E
EE CC1
CC2 EE
Ground plane connections are necessary for PIN1 (GND1)
minimum spacing between two adjacent high-side
isolated regions of the printed circuit board. Insufficient
spacing will reduce the effective isolation and increase
parasitic coupling that will degrade CMR performance.
and PIN 9 (V ) in order to achieve maximum power as the
EE
ACPL-38JT is designed to dissipate the majority of heat
generated through these pins. Actual power dissipation
will depend on the application environment (PCB layout,
The placement and routing of supply bypass capacitors airflow, part placement, etc. (See Figure 77B and 77C).
requires special attention. During switching transients, V should have direct connection (Kelvin connection) to
E
the majority of the gate charge is supplied by the bypass
IGBT Emitter to avoid switching noise on the ground line
capacitors. Maintaining short bypass capacitor trace affecting accurate DESAT voltage sensing. See Figure77C.
lengths will ensure low supply ripple and clean switching
waveforms. See Figure 77A.
Bypass Cap
C1, C2, C4
Ground Plane for GND1
(Pin 1)
Bypass Cap
C13
ACPL-36JV/38JT
Top Gate
Driver (U1)
Board Isolation
Figure 77a. Bypass Capacitors
Ground Plane for VEE (Pin 9)
Figure 77b. Ground Plane
Kelvin Connection between VEE and IGBT Emitter
IGBT
Emitter
Figure 77c. Kelvin Connection between VEE and IGBT Emitter
32
System Considerations
Propagation Delay Difference (PDD)
ILED1
The ACPL-38JT includes a Propagation Delay Difference
(PDD) specification intended to help designers minimize
“dead time” in their power inverter designs. Dead time
is the time period during which both the high and low
side power transistors (Q1 and Q2 in Figure 62) are off.
Any overlap in Q1 and Q2 conduction will result in large
currents flowing through the power devices between
the high and low voltage motor rails, a potentially cata-
strophic condition that must be prevented.
VOUT1
Q1 ON
Q1 OFF
Q2 ON
Q2 OFF
VOUT2
ILED2
tPHL MAX
To minimize dead time in a given design, the turn-on of
the ACPL-38JT driving Q2 should be delayed (relative to
the turn-off of the ACPL-38JT driving Q1) so that under
worst-case conditions, transistor Q1 has just turned off
when transistor Q2 turns on, as shown in Figure 80. The
amount of delay necessary to achieve this condition is
equal to the maximum value of the propagation delay
tPLH MIN
PDD* MAX = (tPHL - tPLH) MAX = tPHL MAX - tPLH MIN
*PDD = Propagation Delay Difference
Note: for PDD calculations the propagation delays
Are taken at the same temperature and test conditions.
Figure 78. Minimum LED Skew for Zero Dead Time.
difference specification, P
, which is specified to be
DDMAX
400 ns over the operating temperature range of -40°C to
125°C.
ILED1
Delaying the ACPL-38JT turn-on signals by the maximum
propagation delay difference ensures that the minimum
dead time is zero, but it does not tell a designer what the
maximum dead time will be. The maximum dead time is
equivalent to the difference between the maximum and
minimum propagation delay difference specifications
as shown in Figure 79. The maximum dead time for the
ACPL-38JT is 800 ns (= 400 ns - (-400 ns)) over an operating
temperature range of -40°C to 125°C.
VOUT1
Q1 ON
Q1 OFF
Q2 ON
Q2 OFF
VOUT2
ILED2
tPLH MIN
tPHL MAX
tPLH MIN
Note that the propagation delays used to calculate PDD
and dead time are taken at equal temperatures and test
conditions since the components under consideration are
typically mounted in close proximity to each other and are
switching identical IGBTs.
tPLH MAX
(tPHL - tPLH MAX
)
PDD* MAX
MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
= (tPHL MAX - tPHL MIN) + (tPLH MAX - tPLH MIN
= (tPHL MAX - tPLH MIN) + (tPHL MIN - tPLH MAX
= PDD* MAX - PDD* MIN
)
)
*PDD = Propagation Delay Difference
Note: For Dead Time and PDD calculations all propagation
delays are taken at the same temperature and test conditions.
Figure 79. Waveforms for Dead Time Calculation.
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Avago, Avago Technologies, the A logo and R2Coupler™ are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved.
AV02-2546EN - February 17, 2012
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