ATR0625-PYQW [ATMEL]
GPS Baseband Processor SuperSense; GPS基带处理器的SuperSense
| 型号： | ATR0625-PYQW |
| 厂家： | 
ATMEL |
| 描述： | GPS Baseband Processor SuperSense |
| 文件： | 总26页 (文件大小：336K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• 16-channel GPS Correlator
– 8192 Search Bins with GPS Acquisition Accelerator
– Accuracy: 2.5m CEP (Stand-Alone, S/A off)
– Time to First Fix: 34s (Cold Start)
– Acquisition Sensitivity: –142 dBm
– Tracking Sensitivity: –158 dBm
• Utilizes the ARM7TDMI® ARM® Thumb® Processor Core
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
GPS Baseband
Processor
SuperSense
– Embedded ICE (In-circuit Emulator)
• 128 Kbyte Internal RAM
• 384 Kbyte Internal ROM with u-blox GPS Firmware
• 6-channel Peripheral Data Controller (PDC)
• 8-level Priority, Individually Maskable, Vectored Interrupt Controller
– 2 External Interrupts
ATR0625
• 24 User-programmable I/O Lines
• 1 USB Device Port
– Universal Serial Bus (USB) V2.0 Full-speed Device
– Embedded USB V2.0 Full-speed Transceiver
– Suspend/Resume Logic
Preliminary
– Ping-pong Mode for Isochronous and Bulk Endpoints
• 2 USARTs
– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART
• Master/Slave SPI Interface
– 2 Dedicated Peripheral Data Controller (PDC) Channels
– 8-bit to 16-bit Programmable Data Length
– 4 External Slave Chip Selects
• Programmable Watchdog Timer
• Advanced Power Management Controller (APMC)
– Peripherals Can Be Deactivated Individually
– Geared Master Clock to Reduce Power Consumption
– Sleep State with Disabled Master Clock
– Hibernate State with 32.768 kHz Master Clock
• Real Time Clock (RTC)
• 2.3V to 3.6V or 1.8V Core Supply Voltage
• Includes Power Supervisor
• 1.8V to 3.3V User-definable I/O Voltage for Several GPIOs with 5V Tolerance
• 4 Kbytes Battery Backup Memory
• 8 mm × 8 mm 56 Pin QFN56 Package
• Pb-free, RoHS-compliant, Green
Rev. 4925A–GPS–02/06
1. Description
The GPS baseband processor ATR0625 includes a 16-channel GPS correlator and is based
on the ARM7TDMI® processor core.
This processor has a high-performance 32-bit RISC architecture and very low power con-
sumption. In addition, a large number of internally banked registers result in very fast
exception handling, making the device ideal for real-time control applications. The ATR0625
has two USART and an USB device port. This port is compliant with the Universal Serial Bus
(USB) V2.0 full-speed device specification.
The ATR0625 includes full GPS SuperSense™ firmware, licensed from u-blox AG, which per-
forms the basic GPS operation, including tracking, acquisition, navigation and position data
output. For normal PVT (Position/Velocity/Time) applications, there is no need for off-chip
Flash memory or ROM. The firmware supports the possibility to store the configuration set-
tings in an optional external EEPROM. For customer-specific applications, a Software
Development Kit is available.
The ATR0625 is manufactured using Atmel’s high-density CMOS technology. By combining
the ARM7TDMI microcontroller core with on-chip SRAM, 16-channel GPS correlator, and a
wide range of peripheral functions on a monolithic chip, the ATR0625 provides a highly flexible
and cost-effective solution for GPS applications.
2
ATR0625 [Preliminary]
4925A–GPS–02/06
ATR0625 [Preliminary]
Figure 1-1. ATR0625 Block Diagram
NSHDN
NSLEEP
XT_IN
XT_OUT
SIGLO0
SIGHI0
RF_ON
CLK23
P15/ANTON
P0/NANTSHORT
P14/NAADET1
P25/NAADET0
P20/TIMEPULSE
P29/GPSMODE12
P27/GPSMODE11
P26/GPSMODE10
P24/GPSMODE8
P23/GPSMODE7
P19/GPSMODE6
P17/GPSMODE5
P13/GPSMODE3
P12/GPSMODE2
P1/GPSMODE0
P21/TXD2
P22/RXD2
P9/EXTINT0
P2/BOOT_MODE
P30/AGCOUT0
P8/STATUSLED
P18/TXD1
P31/RXD1
USB_DP
USB_DM
P16/NEEPROM
DBG_EN
NTRST
TDI
TDO
TCK
TMS
VBAT18
VBAT
LDOBAT_IN
LDO_OUT
LDO_IN
NRESET
LDO_EN
3
4925A–GPS–02/06
2. Architectural Overview
2.1
Description
The ATR0625 architecture consists of two main buses, the Advanced System Bus (ASB) and
the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It inter-
faces the processor with the on-chip 32-bit memories. The APB is designed for accesses to
on-chip peripherals and is optimized for low power consumption. The AMBA™ Bridge provides
an interface between the ASB and the APB.
An on-chip Peripheral Data Controller (PDC2) transfers data between the on-chip
USARTs/SPI and the on-chip and off-chip memories without processor intervention. Most
importantly, the PDC2 removes the processor interrupt handling overhead and significantly
reduces the number of clock cycles required for a data transfer. It can transfer up to 64K con-
tiguous bytes without reprogramming the starting address. As a result, the performance of the
microcontroller is increased and the power consumption reduced.
The ATR0625 peripherals are designed to be easily programmable with a minimum number of
instructions. Each peripheral has a 16 Kbyte address space allocated in the upper 3 Mbyte of
the 4 Gbyte address space. (Except for the interrupt controller, which has 4 Kbyte address
space.) The peripheral base address is the lowest address of its memory space. The periph-
eral register set is composed of control, mode, data, status, and interrupt registers.
To maximize the efficiency of bit manipulation, frequently written registers are mapped into
three memory locations. The first address is used to set the individual register bits, the second
resets the bits, and the third address reads the value stored in the register. A bit can be set or
reset by writing a “1” to the corresponding position at the appropriate address. Writing a “0”
has no effect. Individual bits can thus be modified without having to use costly read-modify-
write and complex bit-manipulation instructions.
All of the external signals of the on-chip peripherals are under the control of the Parallel I/O
(PIO2) Controller. The PIO2 Controller can be programmed to insert an input filter on each pin
or generate an interrupt on a signal change. After reset, the user must carefully program the
PIO2 Controller in order to define which peripheral signals are connected with off-chip logic.
The ARM7TDMI® processor operates in little-endian mode on the ATR0625 GPS Baseband.
The processor's internal architecture and the ARM® and Thumb® instruction sets are
described in the ARM7TDMI datasheet. The memory map and the on-chip peripherals are
described in detail in the ATR0625 full datasheet. The electrical and mechanical characteris-
tics are also documented in the ATR0625 full datasheet.
The ARM standard In-Circuit Emulator (ICE) debug interface is supported via the JTAG/ICE
port of the ATR0625.
For features of the ROM firmware, refer to the software documentation available from u-blox
AG, Switzerland.
4
ATR0625 [Preliminary]
4925A–GPS–02/06
ATR0625 [Preliminary]
3. Pin Configuration
3.1
Pinout
Figure 3-1. Pinout QFN56 (Top View)
42
29
43
56
28
15
ATR0625
1
14
Table 3-1.
ATR0625 Pinout
PIO Bank A
PIO Bank B
Pin
Pull Resistor
Pin Name QFN56 Type
(Reset Value)(1) Firmware Label
I
O
I
O
CLK23
DBG_EN
GND
37
IN
IN
8
(2)
PD
IN
LDOBAT_IN
LDO_EN
LDO_IN
LDO_OUT
NRESET
NSHDN
NSLEEP
NTRST
P0
21
25
20
19
41
26
24
13
40
47
46
48
29
49
32
IN
IN
IN
OUT
I/O
OUT
OUT
IN
Open Drain PU
PD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PD
NANTSHORT
GPSMODE0
P1
Configurable (PD)
AGCOUT1
P2
Configurable (PD) BOOT_MODE
“0”
“0”
P8
Configurable (PD)
STATUSLED
EXTINT0
P9
PU
Configurable (PU)
PU
EXTINT0
EXTINT1
P12
GPSMODE2
GPSMODE3
NPCS2
P13
Notes: 1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset
2. Ground plane
3. VBAT18 represent the internal power supply of the backup power domain, see section “Power Supply” on page 17.
4. VDDIO is the supply voltage for the following GPIO-pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29, see section “Power Supply” on page 17.
5. VDD_USB is the supply voltage for following the USB-pins: USB_DM and USB_DP, see section “Power Supply” on page
17. For operation of the USB interface, supply of 3.0V to 3.6V is required.
6. This pin is not connected
5
4925A–GPS–02/06
Table 3-1.
ATR0625 Pinout (Continued)
PIO Bank A
PIO Bank B
Pin
Pin Name QFN56 Type
Pull Resistor
(Reset Value)(1) Firmware Label
I
O
I
O
P14
P15
1
17
6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
OUT
IN
Configurable (PD)
PD
NAADET1
ANTON
“0”
P16
Configurable (PU)
Configurable (PD)
Configurable (PU)
Configurable (PU)
Configurable (PD)
Configurable (PU)
PU
NEEPROM
GPSMODE5
TXD1
SIGHI1
SCK1
NWD_OVF
P17
2
SCK1
TXD1
P18
45
53
4
“0”
“0”
P19
GPSMODE6
TIMEPULSE
TXD2
SIGLO1
SCK2
P20
SCK2
TXD2
TIMEPULSE
“0”
P21
52
30
3
P22
RXD2
RXD2
SCK
P23
Configurable (PU)
Configurable (PU)
Configurable (PD)
GPSMODE7
GPSMODE8
NAADET0
SCK
MOSI
MCLK_OUT
P24
5
MOSI
MISO
NSS
“0”
“0”
“0”
P25
55
44
54
50
16
31
15
38
39
9
MISO
P26
Configurable (PU) GPSMODE10
Configurable (PU) GPSMODE11
Configurable (PU) GPSMODE12
NPCS0
NPCS1
NPCS3
AGCOUT0
P27
P29
P30
PD
PU
PD
AGCOUT0
RXD1
“0”
P31
RXD1
RF_ON
SIGHI0
SIGLO0
TCK
IN
IN
PU
PU
TDI
10
11
12
34
35
22
23
7, 14
18, 36
51
43, 56
33
28
27
42
IN
TDO
OUT
IN
TMS
PU
USB_DM
USB_DP
VBAT
VBAT18(3)
VDD18
VDD18
VDD18
VDDIO(4)
VDD_USB(5)
XT_IN
XT_OUT
NC(6)
I/O
I/O
IN
OUT
IN
IN
IN
IN
IN
IN
OUT
Notes: 1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset
2. Ground plane
3. VBAT18 represent the internal power supply of the backup power domain, see section “Power Supply” on page 17.
4. VDDIO is the supply voltage for the following GPIO-pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29, see section “Power Supply” on page 17.
5. VDD_USB is the supply voltage for following the USB-pins: USB_DM and USB_DP, see section “Power Supply” on page
17. For operation of the USB interface, supply of 3.0V to 3.6V is required.
6. This pin is not connected
6
ATR0625 [Preliminary]
4925A–GPS–02/06
ATR0625 [Preliminary]
3.2
Signal Description
Table 3-2.
Module
ATR0625 Signal Description
Name
Function
Type
Active Level Comment
PIO-controlled after reset,
internal pull-down resistor
EBI
BOOT_MODE
Boot Mode Input
Input
–
TXD1 to TXD2
RXD1 to RXD2
SCK1 to SCK2
USB_DP
Transmit Data Output
Receive Data Input
External Synchronous Serial Clock
USB Data (D+)
Output
Input
I/O
–
–
–
–
–
–
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
USART
I/O
USB
USB_DM
USB Data (D-)
I/O
APMC
RF_ON
Output
Interface to ATR0601
High/
Low/
Edge
AIC
EXTINT0-1
External Interrupt Request
Automatic Gain Control
Input
PIO-controlled after reset
Interface to ATR0601
PIO-controlled after reset
AGC
AGCOUT0-1
Output
–
NSLEEP
NSHDN
XT_IN
Sleep Output
Output
Output
Input
Output
I/O
Low
Low
–
Interface to ATR0601
Connect to pin LDO_EN
RTC oscillator
Shutdown Output
Oscillator Input
Oscillator Output
SPI Clock
RTC
SPI
XT_OUT
SCK
–
RTC oscillator
–
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
Input after reset
MOSI
Master Out Slave In
Master In Slave Out
Slave Select
I/O
–
MISO
I/O
–
NSS/NPCS0
I/O
Low
Low
–
NPCS1 to NPCS3 Slave Select
Output
Output
I/O
WD
PIO
NWD_OVF
P0 to P31
SIGHI0
Watchdog Timer Overflow
Programmable I/O Port
Digital IF
–
Input
Input
Input
Input
Output
Input
Output
Input
Output
–
Interface to ATR0601
Interface to ATR0601
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
SIGLO0
Digital IF
–
GPS
SIGHI1
Digital IF
–
SIGLO1
Digital IF
–
TIMEPULSE
GPSMODE0-12
STATUSLED
NEEPROM
ANTON
GPS synchronized time pulse
GPS Mode
–
–
Status LED
–
Enable EEPROM Support
Active antenna power on Output
Low
–
CONFIG
Active antenna short circuit
detection Input
NANTSHORT
Input
Input
Low
Low
PIO-controlled after reset
PIO-controlled after reset
NAADET0-1
Active antenna detection Input
Note:
1. The USB transceiver is disabled if VDD_USB < 2.0V. In this case the pins USB_DM and USB_DP are connected to GND
(internal pull-down resistors). The USB transceiver is enabled if VDD_USB is within 3.0V and 3.6V.
7
4925A–GPS–02/06
Table 3-2.
Module
ATR0625 Signal Description (Continued)
Name
TMS
Function
Type
Input
Input
Output
Input
Input
Input
Active Level Comment
Test Mode Select
Test Data In
–
–
Internal pull-up resistor
TDI
Internal pull-up resistor
TDO
Test Data Out
Test Clock
–
JTAG/ICE
TCK
–
Internal pull-up resistor
Internal pull-down resistor
Internal pull-down resistor
NTRST
DBG_EN
Test Reset Input
Debug Enable
Low
High
Interface to ATR0601,
Schmitt trigger input
CLK23
MCLK_OUT
NRESET
Clock Input
Input
Output
I/O
–
–
CLOCK
RESET
Master Clock Output
Reset Input
PIO-controlled after reset
Open drain with internal pull-up
resistor
Low
VDD18
VDDIO
Power
Power
–
–
Core voltage 1.8V
Variable IO voltage 1.65V to 3.6V
POWER
USB voltage 0 to 2.0V or
3.0V to 3.6V(1)
VDD_USB
Power
–
GND
LDOBAT_IN
VBAT
Power
Power
Power
Out
–
–
–
–
–
–
–
Ground
2.3V to 3.6V
LDOBAT
LDO18
1.5V to 3.6V
VBAT18
LDO_IN
LDO_OUT
LDO_EN
1.8V backup voltage
2.3V to 3.6V
LDO In
Power
Power
Input
LDO Out
LDO Enable
1.8V core voltage, max. 80 mA
Note:
1. The USB transceiver is disabled if VDD_USB < 2.0V. In this case the pins USB_DM and USB_DP are connected to GND
(internal pull-down resistors). The USB transceiver is enabled if VDD_USB is within 3.0V and 3.6V.
8
ATR0625 [Preliminary]
4925A–GPS–02/06
ATR0625 [Preliminary]
3.3
Setting GPSMODE0 to GPSMODE12
The start-up configuration of a ROM-based system without external non-volatile memory is
defined by the status of the GPSMODE pins after system reset. Alternatively, the system can
be configured through message commands passed through the serial interface after start-up.
This configuration of the ATR0625 can be stored in an external non-volatile memory like
EEPROM. Default designates settings used by ROM firmware if GPSMODE configuration is
disabled (GPSMODE0 = 0).
Table 3-3.
Pin
GPSMODE Functions
Function
GPSMODE0 (P1)
Enable configuration with GPSMODE pins
This pin (EXTINT0) is used for FixNow functionality and not used for GPSMODE
configuration.
GPSMODE1 (P9)
GPSMODE2 (P12)
GPSMODE3 (P13)
GPS sensitivity settings
This pin (NAADET1) is used as active antenna supervisor input and not used for
GPSMODE4 (P14) GPSMODE configuration. This is the default selection if GPSMODE configuration
is disabled.
GPSMODE5 (P17)
Serial I/O configuration
GPSMODE6 (P19)
GPSMODE7 (P23) USB Power Mode
GPSMODE8 (P24) General I/O Configuration
This pin (NAADET0) is used as active antenna supervisor input and not used for
GPSMODE configuration.
GPSMODE9 (P25)
GPSMODE10 (P26)
General I/O Configuration
GPSMODE11 (P27)
GPSMODE12 (P29) Serial I/O configuration
3.3.1
Enable GPSMODE Pin Configuration
Table 3-4. Enable Configuration with GPSMODE Pins
GPSMODE0
(Reset = PD) Description
0
1
Ignore all GPSMODE pins. The default settings as indicated below are used.
Use settings as specified with GPSMODE[2, 3, 5 to 8, 10 to 12]
If the GPSMODE configuration is enabled (GPSMODE0 = 1) and the other GPSMODE pins
are not connected externally, the reset default values of the internal pull-down and pull-up
resistors will be used.
9
4925A–GPS–02/06
3.3.2
Sensitivity Settings
Table 3-5.
GPS Sensitivity Settings
GPSMODE3 GPSMODE2
(Fixed PU)
(Reset = PU) Description
0
0
1
1
0
1
0
1
Auto mode
Fast mode
Normal mode (Default ROM value)
High sensitivity
3.3.3
Serial I/O Configuration
The ATR0625 features a two-stage I/O message and protocol selection procedure for the two
available serial ports. At the first stage, a certain protocol can be enabled or disabled for a
given USART port or the USB port. Selectable protocols are RTCM, NMEA and UBX. At the
second stage, messages can be enabled or disabled for each enabled protocol on each port.
In all configurations discussed below, all protocols are enabled on all ports. But output mes-
sages are enabled in a way that ports appear to communicate at only one protocol. However,
each port will accept any input message in any of the three implemented protocols
Table 3-6.
Serial I/O Configuration
USART1/USB
USART2
GPSMODE12 GPSMODE6
GPSMODE5 (Output Protocol/
(Output Protocol/
(Reset = PU) (Reset = PU) (Reset = PD) Baud Rate (kBaud)) Baud Rate (kBaud)) Messages Information Messages
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
UBX/57.6
UBX/38.4
UBX/19.2
–/Auto
NMEA/19.2
NMEA/9.6
NMEA/4.8
–/Auto
High
User, Notice, Warning, Error
User, Notice, Warning, Error
User, Notice, Warning, Error
None
Medium
Low
Off
NMEA/19.2
NMEA/4.8
NMEA/9.6
UBX/115.2
UBX/57.6
UBX/19.2
UBX/38.4
NMEA/19.2
High
User, Notice, Warning, Error
User, Notice, Warning, Error
User, Notice, Warning, Error
All
Low
Medium
Debug
Both USART ports and the USB port accept input messages in all three supported protocols
(NMEA, RTCM and UBX) at the configured baud rate. Input messages of all three protocols
can be arbitrarily mixed. Response to a query input message will always use the same proto-
col as the query input message. The USB port does only accept NMEA and UBX as input
protocol by default. RTCM can be enabled via protocol messages on demand.
In Auto Mode, no output message is sent out by default, but all input messages are accepted
at any supported baud rate. Again, USB is restricted to only NMEA and UBX protocols.
Response to query input commands will be given the same protocol and baud rate as it was
used for the query command. Using the respective configuration commands, periodic output
messages can be enabled.
10
ATR0625 [Preliminary]
4925A–GPS–02/06
ATR0625 [Preliminary]
The following message settings are used in the tables below:
Table 3-7.
NMEA Port
Supported Messages at Setting Low
Standard
NAV
GGA, RMC
SOL, SVINFO
EXCEPT
UBX Port
MON
Table 3-8.
NMEA Port
Supported Messages at Setting Medium
Standard
GGA, RMC, GSA, GSV, GLL, VTG, ZDA
SOL, SVINFO, POSECEF, POSLLH, STATUS, DOP, VELECEF,
VELNED, TIMEGPS, TIMEUTC, CLOCK
NAV
UBX Port
MON
EXCEPT
Table 3-9.
NMEA Port
Supported Messages at Setting High
Standard
GGA, RMC, GSA, GSV, GLL, VTG, ZDA, GRS, GST
Proprietary PUBX00, PUBX03, PUBX04
SOL, SVINFO, POSECEF, POSLLH, STATUS, DOP, VELECEF,
VELNED, TIMEGPS, TIMEUTC, CLOCK
NAV
UBX Port
MON
SCHD, IO, IPC, EXCEPT
Table 3-10. Supported Messages at Setting Debug (Additional Undocumented Message
May be Part of Output Data)
Standard
GGA, RMC, GSA, GSV, GLL, VTG, ZDA, GRS, GST
NMEA Port
UBX Port
Proprietary PUBX00, PUBX03, PUBX04
SOL, SVINFO, POSECEF, POSLLH, STATUS, DOP, VELECEF,
VELNED, TIMEGPS, TIMEUTC, CLOCK
NAV
MON
RXM
SCHD, IO, IPC, EXCEPT
RAW (RAW message support requires an additional license)
The following settings apply if GPSMODE configuration is not enabled, that is, GPSMODE = 0
(ROM-Defaults):
Table 3-11. Serial I/O Default Setting if GPSMODE Configuration is Deselected
(GPSMODE0 = 0)
USB
NMEA
USART1
NMEA
USART2
UBX
Baud Rate (kBaud)
Input Protocol
57.6
57.6
UBX, NMEA
NMEA
UBX, NMEA, RTCM
NMEA
UBX, NMEA, RTCM
UBX
Output Protocol
NAV: SOL, SVINFO
MON: EXCEPT
Messages
GGA, RMC, GSA, GSV GGA, RMC, GSA, GSV
Information Messages
(UBX INF or NMEA
TXT)
User, Notice, Warning,
Error
User, Notice, Warning,
Error
User, Notice, Warning,
Error
11
4925A–GPS–02/06
3.3.4
USB Power Mode
For correct response to the USB host queries, the device has to know its power mode. This is
configured via GPSMODE7. If set to bus powered, an upper current limit of 100 mA is reported
to the USB host; that is, the device classifies itself as a “low-power bus-powered function” with
no more than one USB power unit load.
Table 3-12. USB Power Modes
GPSMODE7 (Reset = PU) Description
0
1
USB device is bus-powered (max. current limit 100 mA)
USB device is self-powered (Default ROM value)
3.3.5
Active Antenna Supervisor
The two pins P0/NANTSHORT and P15/ANTON plus one pin of P25/NAADET0/MISO or
P14/NAADET1 are always initialized as general purpose I/Os and used as follows:
• P15/ANTON is an output which can be used to switch on and off antenna power supply.
• Input P0/NANTSHORT will indicate an antenna short circuit, i.e. zero DC voltage at the
antenna, to the firmware. If the antenna is switched off by output P15/ANTON, it is
assumed that also input P0/NANTSHORT will signal zero DC voltage, i.e. switch to its
active low state.
• Input P25/NAADET0/MISO or P14/NAADET1 will indicate a DC current into the antenna. In
case of short circuit, both P0 and P25/P14 will be active, i.e. at low level. If the antenna is
switched off by output P15/ANTON, it is assumed that also input P25/NAADET0/MISO will
signal zero DC current, i.e. switch to its active low state. Which pin is used as NAADET
(P14 or P25) depends on the settings of GPSMODE11 and GPSMODE10 (see Table 3-14
on page 13).
Table 3-13. Pin Usage of Active Antenna Supervisor
Pin
Usage
Meaning
Active antenna short circuit detection
High = No antenna DC short circuit present
Low = Antenna DC short circuit present
P0/NANTSHORT
NANTSHORT
P25/NAADET0/
MISO or
P14/NAADET1
Active antenna detection input
High = No active antenna present
Low = Active antenna is present
NAADET
ANTON
Active antenna power on output
High = Power supply to active antenna is switched on
Low = Power supply to active antenna is switched off
P15/ANTON
12
ATR0625 [Preliminary]
4925A–GPS–02/06
ATR0625 [Preliminary]
Table 3-14. Antenna Detection I/O Settings
GPSMODE11 GPSMODE10 GPSMODE8
(Reset = PU) (Reset = PU) (Reset = PU) Location of NAADET
Comment
0
0
0
0
0
1
P25/NAADET0/MISO
P25/NAADET0/MISO
Reserved for further use.
Do not use this setting.
0
0
1
1
1
1
0
0
0
1
0
1
P14/NAADET1
P14/NAADET1
(Default ROM value)
Reserved for further use.
Do not use this setting.
P14/NAADET1
P14/NAADET1
Reserved for further use.
Do not use this setting.
1
1
1
1
0
1
P25/NAADET0/MISO
P25/NAADET0/MISO
The Antenna Supervisor Software will be configured as follows:
1. Enable Control Signal
2. Enable Short Circuit Detection (power down antenna via ANTON if short is detected
via NANTSHORT)
3. Enable Open Circuit Detection via NAADET
The antenna supervisor function may not be disabled by GPSMODE pin selection.
13
4925A–GPS–02/06
3.4
External Connections for a Working GPS System
Figure 3-2. Example of an External Connection
ATR0625
ATR0601
SIGH
SIGL
SIGHI
SIGLO
CLK23
RF_ON
NSLEEP
SC
PURF
PUXTO
P8
STATUS LED
TIMEPULSE
P20
NC
NRESET
USB_DM
USB_DP
Optional
USB
see Table 3-15
see Table 3-15
see Table 3-15
see Table 3-15
see Table 3-15
see Table 3-15
P0 - 2
P9
P31
P18
Optional
USART 1
P12 - 17
P19
P22
P21
Optional
USART 2
P23 - 27
P29 - 30
NC
NC
NC
NC
NC
TMS
TCK
XT_IN
32.368 kHz
(see RTC)
TDI
NTRST
TDO
XT_OUT
NC
DBG_EN
GND
GND
NSHDN
LDO_EN
LDO_OUT
VDD18
+3V
+3V
(see Power Supply)
(see Power Supply)
LDO_IN
LDOBAT_IN
VDDIO
+3V
(see Power Supply)
VBAT18
VBAT
VDD_USB
+3V
(see Power Supply)
GND
NC: Not connected
14
ATR0625 [Preliminary]
4925A–GPS–02/06
ATR0625 [Preliminary]
Table 3-15. Recommended Pin Connection
Pin Name
Recommended External Circuit
Internal pull-down resistor, leave open if Antenna Supervision functionality is unused. Can be left open if
configured as output by user application.
P0/NANTSHORT
Internal pull-down resistor, leave open, in order to disable the GPSMODE pin configuration feature. Connect
to VDDIO to enable the GPSMODE pin configuration feature. Refer to GPSMODE definitions in section
“Setting GPSMODE0 to GPSMODE12” on page 9. Can be left open if configured as output by user
application.
P1/GPSMODE0
P2/BOOT_MODE
P8/STATUSLED
Internal pull-down resistor, leave open.
Output in default ROM firmware: leave open, only needs pull-up resistor to VDDIO or pull-down resistor to
GND if used as GPIO input by user application and is not always driven from external sources.
P9/EXTINT0
Internal pull-up resistor, leave open if unused.
Internal pull-up resistor, can be left open if the GPSMODE feature is not used or configured as output by user
application. Refer to GPSMODE definitions in section “Setting GPSMODE0 to GPSMODE12” on page 9.
P12/GPSMODE2/NPCS2
P13/GPSMODE3/
EXTINT1
Internal pull-up resistor, can be left open if the GPSMODE feature is not used or configured as output by user
application. Refer to GPSMODE definitions in section “Setting GPSMODE0 to GPSMODE12” on page 9.
Internal pull-down resistor, leave open if Antenna Supervision functionality is unused. Can be left open if
configured as output by user application.
P14/NAADET1
Internal pull-down resistor, leave open if Antenna Supervision functionality is unused. Can be left open if
configured as output by user application.
P15/ANTON
P16/NEEPROM
Internal pull-up resistor, leave open if no serial EEPROM is connected. Otherwise connect to GND.
Internal pull-down resistor, can be left open if the GPSMODE feature is not used or configured as output by
P17/GPSMODE5/SCK1
user application. Refer to GPSMODE definitions in section “Setting GPSMODE0 to GPSMODE12” on page
9.
P18/TXD1
Output in default ROM firmware: leave open if serial interface is not used.
Internal pull-up resistor, can be left open if the GPSMODE feature is not used or configured as output by user
application. Refer to GPSMODE definitions in section “Setting GPSMODE0 to GPSMODE12” on page 9.
P19/GPSMODE6/SIGLO1
P20/TIMEPULSE/SCK2
P21/TXD2
Output in default ROM firmware: leave open if timepulse feature is not used.
Output in default ROM firmware: leave open if serial interface not used.
Internal pull-up resistor, leave open if serial interface is not used.
P22/RXD2
Internal pull-up resistor, can be left open if the GPSMODE feature is not used or configured as output by user
application. Refer to GPSMODE definitions in section “Setting GPSMODE0 to GPSMODE12” on page 9.
P23/GPSMODE7/SCK
P24/GPSMODE8/MOSI
P25/NAADET0/MISO
Internal pull-up resistor, can be left open if the GPSMODE feature is not used or configured as output by user
application. Refer to GPSMODE definitions in section “Setting GPSMODE0 to GPSMODE12” on page 9.
Internal pull-down resistor, leave open if Antenna Supervision functionality is unused. Can be left open if
configured as output by user application.
P26/GPSMODE10/NSS/ Internal pull-up resistor, can be left open if the GPSMODE feature is not used or configured as output by user
NPCS0
application. Refer to GPSMODE definitions in section “Setting GPSMODE0 to GPSMODE12” on page 9.
Internal pull-up resistor, can be left open if the GPSMODE feature is not used or configured as output by user
application. Refer to GPSMODE definitions in section “Setting GPSMODE0 to GPSMODE12” on page 9.
P27/GPSMODE11/NPCS1
Internal pull-up resistor, can be left open if the GPSMODE feature is not used or configured as output by user
application. Refer to GPSMODE definitions in section “Setting GPSMODE0 to GPSMODE12” on page 9.
P29/GPSMODE12/NPCS3
P30/AGCOUT0
P31/RXD1
Internal pull-down resistor, leave open.
Internal pull-up resistor, leave open if serial interface is not used.
15
4925A–GPS–02/06
3.4.1
Connecting an Optional Serial EEPROM
The ATR0625 offers the possibility to connect an external serial EEPROM. The internal ROM
firmware supports to store the configuration of the ATR0625 in serial EEPROM. The pin
P16/NEEPROM signals the firmware that a serial EEPROM is connected with the ATR0625.
The 32-bit RISC processor of the ATR0625 accesses the external memory with SPI (Serial
Peripheral Interface). Atmel recommend to use 32 Kbit 1.8V serial EEPROM, e.g. the Atmel
AT25320AY1-1.8. Figure 3-3 shows an example of the serial EEPROM connection.
Figure 3-3. Example of a Serial EEPROM Connection
ATR0625
AT25320AY1-1.8
SCK
SI
P23/SCK
P24/MOSI
SO
P25/MISO/NAADET0
P29/NPCS3
CS_N
HOLD_N
WP_N
GND
NC
P16/NEEPROM
P1/GPSMODE0
GND
GND
NSHDN
LDO_EN
LDO_OUT
VDD18
VDDIO
+3V
(see Power Supply)
LDO_IN
LDOBAT_IN
NC: Not connected
Note:
The GPSMODE pin configuration feature can be disabled, because the configuration can be
stored in the serial EEPROM. VDDIO is the supply voltage for the pins: P23, P24, P25 and P29.
16
ATR0625 [Preliminary]
4925A–GPS–02/06
ATR0625 [Preliminary]
4. Power Supply
The baseband IC is supplied with four distinct supply voltages:
• VDD18, the nominal 1.8V supply voltage for the core, the RF-I/O pins, the memory
interface and the test pins and all GPIO-pins not mentioned in next item.
• VDDIO, the variable supply voltage within 1.8V to 3.6V for following GPIO-pins: P1, P2, P8,
P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29 In input mode,
these pins are 5V input tolerant.
• VDD_USB, the power supply of the USB pins: USB_DM and USB_DP.
• VBAT18 to supply the backup domain: RTC, backup SRAM and the pins NSLEEP, NSHDN,
LDO_EN, VBAT18, P9/EXTIN0, P13/EXTINT1, P22/RXD2 and P31/RXD1 and the 32kHz
oscillator. In input mode, the four GPIO-pins are 5V input tolerant.
Figure 4-1, Figure 4-2, and Figure 4-3 show examples of the wiring of ATR0625 power supply.
Figure 4-1. External Wiring Example Using Internal LDOs and Backup Power Supply
ATR0625 internal
2.3V to 3.6V
LDO18
ldoin
LDO_IN
ldoen
NSHDN
LDO_EN
ldoout
LDO_OUT
VDD18
VDDIO
Core
1 µF
(X7R)
1.8V to 3.3V
variable IO Domain
LDOBAT
ldobat_in
LDOBAT_IN
VBAT
vbat
1.5V to 3.6V
vbat18
VBAT18
vdd
1 µF
(X7R)
RTC
Backup Memory
USB SM and
Transceiver
0 to 2V or 3V to 3.6V
VDDUSB
17
4925A–GPS–02/06
The baseband IC contains a built in low dropout voltage regulator LDO18. This regulator can
be used if the host system does not provide the core voltage VDD18 of 1.8V nominal. In such
case, LDO18 will provide a 1.8V supply voltage from any input voltage VDD between 2.3V and
3.6V. The LDO_EN input can be used to shut down VDD18 if the system is in standby mode.
If the host system does however supply a 1.8V core voltage directly, this voltage has to be
connected to the VDD18 supply pins of the baseband IC. LDO_EN must be connected to
GND. LDO_IN can be connected to GND. LDO_OUT must not be connected.
A second built in low dropout voltage regulator LDOBAT provides the supply voltage for the
RTC and backup SRAM from any input voltage LDOBAT_IN between 2.3V and 3.6V or from
VBAT between 1.5V and 3.6V. The backup battery connected to VBAT is only discharged if
the supply connected to LDOBAT_IN is shut-down.
Only after VDD18 has been supplied to ATR0625 the RTC section will be initialized properly. If
only VBAT is applied first, the current consumption of the RTC and backup SRAM is
undetermined.
Figure 4-2. External Wiring Example Using 1.8V from Host System and Backup Power
Supply
ATR0625 internal
LDO18
ldoin
LDO_IN
ldoen
LDO_EN
ldoout
LDO_OUT
1.65V to 1.95V
VDD18
VDDIO
Core
1.8V to 3.3V
variable IO Domain
1 µF
(X7R)
2.3V to 3.6V
LDOBAT
ldobat_in
LDOBAT_IN
VBAT
vbat
1.5V to 3.6V
vbat18
VBAT18
vdd
1 µF
(X7R)
RTC
Backup Memory
USB SM and
Transceiver
0 to 2V or 3V to 3.6V
VDDUSB
18
ATR0625 [Preliminary]
4925A–GPS–02/06
ATR0625 [Preliminary]
The USB Transceiver is disabled if VDD_USB < 2.0V. In this case the pins USB_DM and
USB_DP are connected to GND (internal pull-down resistors). The USB Transceiver is
enabled if VDD_USB within 3.0V and 3.6V.
Figure 4-3. External Wiring Example Using Internal LDOs, USB Supply Voltage and Backup Power Supply
ATR0625 internal
LDO18
ldoin
LDO_IN
ldoen
NSHDN
LDO_EN
ldoout
LDO_OUT
VDD18
VDDIO
Core
1 µF
(X7R)
1.8V to 3.3V
variable IO Domain
LDOBAT
ldobat_in
LDOBAT_IN
VBAT
vbat
1.5V to 3.6V
vbat18
VBAT18
vdd
1 µF
(X7R)
RTC
Backup Memory
External
LDO 3.3V
USB SM and
Transceiver
USB-VSB 5V
VDDUSB
19
4925A–GPS–02/06
5. Oscillator
Figure 5-1. Crystal Connection
ATR0625 internal
XT_IN
32 kHz
Crystal
32.768 kHz
50 ppm
Oscillator
32.768 kHz clock
RTC
XT_OUT
max.
max.
25 pF
25 pF
6. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Pin
Symbol
Min.
–40
Max.
+85
Unit
°C
°C
V
Operating Free Air Temperature Range
Storage Temperature
DC Supply Voltage
DC Supply Voltage
DC Supply Voltage
DC Supply Voltage
DC Supply Voltage
DC Supply Voltage
–60
+150
+1.95
+3.6
+3.6
+3.6
+3.6
+3.6
VDD18
VDDIO
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
V
VDD_USB
LDO_IN
LDOBAT_IN
VBAT
V
V
V
V
P0, P15, P30, SIGHI, SIGLO,
CLK23, XT_IN, TMS, TCK,
TDI, NTRST, DBG_EN,
LDO_EN, NRESET
DC Input Voltage
–0.3
+1.95
V
DC Input Voltage
DC Input Voltage
USB_DM, USB_DP
–0.3
–0.3
+3.6
+5.0
V
V
P1, P2, P8, P9, P12 to P14,
P16 to P27, P29, P31
Note:
Minimum/maximum limits are at +25°C ambient temperature, unless otherwise specified
20
ATR0625 [Preliminary]
4925A–GPS–02/06
ATR0625 [Preliminary]
7. Electrical Characteristics
If no additional information is given in column Test Conditions, the values apply to a temperature range from –40°C to +85°C.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
1.1 DC Supply Voltage Core
VDD18
VDD18
1.65
1.8
1.95
V
DC Supply Voltage VDDIO
1.2
VDDIO
VDD_USB
VBAT18
VDDIO
VDDUSB
VBAT18
1.65
3.0
1.8/3.3
3.3
3.6
3.6
3.6
V
V
V
Domain(1)
1.3 DC Supply Voltage USB(2)
DC Supply Voltage Backup
1.4
1.65
1.8
Domain(3)
1.5 DC Output Voltage VDD18
1.6 DC Output Voltage VDDIO
VO,18
VO,IO
0
0
VDD18
VDDIO
V
V
Low-level Input Voltage
VDD18 Domain
0.3 ×
1.7
VDD18 = 1.65V to 1.95V
VDD18 = 1.65V to 1.95V
VDDIO = 1.65V to 3.6V
VDDIO = 1.65V to 3.6V
VBAT18 = 1.65V to 1.95V
VBAT18 = 1.65V to 1.95V
VIL,18
VIH,18
VIL,IO
–0.3
V
V
V
V
V
V
VDD18
High-level Input Voltage
VDD18 Domain
0.7 ×
VDD18
VDD18 +
0.3
1.8
Low-level Input Voltage
VDDIO Domain
1.9
–0.3
1.46
–0.3
1.46
+0.41
5.0
High-level Input Voltage
1.10
VIH,IO
VIL,BAT
VIH,BAT
VDDIO Domain
Low-level Input Voltage
1.11
P9, P13, P22,
P31
+0.41
5.0
VBAT18 Domain
High-level Input Voltage
1.12
P9, P13, P22,
P31
VBAT18 Domain
1.13 Low-level Input Voltage USB VDD_USB = 3.0V to 3.6V
1.14 High-level Input Voltage USB VDD_USB = 3.0V to 3.6V
Low-level Output Voltage
DP, DM
DP, DM
VIL,USB
VIH,USB
–0.3
2.0
+0.8
4.6
V
V
1.15
1.16
1.17
1.18
1.19
1.20
IOL = 1.5 mA, VDD18 = 1.65V
VOL,18
VOH,18
VOL,IO
0.4
0.4
0.4
V
V
V
V
V
V
VDD18 Domain
High-level Output Voltage
VDD18 Domain
I
OH = –1.5 mA,
VDD18–
0.45
VDD18 = 1.65V
Low-level Output Voltage
VDDIO Domain
IOL = 1.5 mA, VDDIO = 3.0V
High-level Output Voltage
VDDIO Domain
VDDIO–
0.5
IOH = –1.5 mA, VDDIO = 3.0V
IOL = 1 mA
VOH,IO
VOL,BAT
VOH,BAT
Low-level Output Voltage
VBAT18 Domain
P9, P13, P22,
P31
High-level Output Voltage
VBAT18 Domain
P9, P13, P22,
P31
I
OH = –1 mA
1.2
IOL = 1.5 mA,
VDD_USB = 3.0V to 3.6V,
27Ωexternal series resistor
Low-level Output Voltage
USB
1.21
1.22
DP, DM
DP, DM
VOL,USB
0.4
V
V
IOH = –1.5 mA,
VDD_USB = 3.0V to 3.6V,
27Ωexternal series resistor
High-level Output Voltage
USB
VOH,USB
2.7
Notes: 1. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29
2. Values defined for operating the USB interface. Otherwise VDD_USB may be connected to ground
3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT
21
4925A–GPS–02/06
7. Electrical Characteristics (Continued)
If no additional information is given in column Test Conditions, the values apply to a temperature range from –40°C to +85°C.
No. Parameters
Input-leakage Current
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
VDD18 = 1.95V
VIL = 0V
1.23
ILEAK
–1
+1
µA
(standard Inputs and I/Os)
1.24 Input Capacitance
ICAP
RPU
10
pF
1.25 Input Pull-up Resistor
NRESET
0.7
10
1.6
kΩ
TCK, TDI,
TMS
1.26 Input Pull-up Resistor
1.27 Input Pull-up Resistor
1.28 Input Pull-down Resistor
1.29 Input Pull-down Resistor
RPU
RPU
RPD
RPD
30
220
30
kΩ
kΩ
kΩ
kΩ
P9, P13, P22,
P31
100
10
DBG_EN,
NTRST,
RF_ON, P0,
P15, P30
100
220
P1, P2, P8,
P12, P14,
P[16-21],
Configurable Input Pull-up
Resistor
1.30
RCPU
62
45
330
160
kΩ
kΩ
P[23-27], P29
P1, P2, P8,
P12, P14,
P[16-21],
Configurable Input Pull-down
Resistor
1.31
RCPD
P[23-27], P29
Configurable Input Pull-up
1.32
USB_DP
USB_DP
RCPU
RCPU
RPD
0.9
1.425
10
1.575
3.09
500
kΩ
kΩ
kΩ
Resistor (Idle state)
Configurable Input Pull-up
1.33
Resistor (Operation state)
USB_DP
USB_DM
1.34 Input Pull-down Resistor
Notes: 1. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29
2. Values defined for operating the USB interface. Otherwise VDD_USB may be connected to ground
3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT
22
ATR0625 [Preliminary]
4925A–GPS–02/06
ATR0625 [Preliminary]
8. Power Consumption
Mode
Conditions
Typ.
0.065(1)
0.007(1)
25
Unit
Sleep
At 1.8V, no CLK23
Shutdown RTC, backup SRAM and LDOBAT
Satellite acquisition
mA
Normal
Normal tracking on 6 channels with 1 fix/s; each additional active tracking channel adds 0.5 mA
14
All channels disabled
11
Note:
1. Specified value only
9. ESD Sensitivity
The ATR0625 is an ESD sensitive device. The current ESD values are to be defined.
Observe precautions for handling
10. LDO18
The LDO18 is a built in low dropout voltage regulator which can be used if the host system
does not provide the core voltage VDD18.
Table 10-1. Electrical Characteristics of LDO18
Parameter
Conditions
Min.
Typ.
Max.
Unit
Supply voltage LDO_IN
2.3
3.6
V
Output Voltage
(LDO_OUT)
1.65
1.8
1.95
80
80
5
V
Output Current
(LDO_OUT)
mA
µA
µA
After startup, no load, at room
temperature
Current consumption
Current consumption
Standby Mode (LDO_EN = 0), at room
temperature
1
23
4925A–GPS–02/06
11. LDOBAT and Backup Domain
The LDOBAT is a built in low dropout voltage regulator which provides the supply voltage
VBAT18 for the RTC, backup SRAM, P9, P13, P22, P31, NSLEEP and NSHDN. The LDOBAT
voltage regulator switches in battery mode if LDOBAT_IN falls below 1.5V.
Table 11-1. Electrical Characteristics of LDOBAT
Parameter
Conditions
Min.
Typ.
Max.
Unit
Supply voltage
LDOBAT_IN
2.3
3.6
V
Supply voltage VBAT
1.5
3.6
1.95
1.5
V
V
Output Voltage (VBAT18) If switch connects to LDOBAT_IN.
Output Current (VBAT18)
1.65
1.8
mA
Current consumption
LDOBAT_IN(1)
After startup (sleep/backup mode), at
room temperature
15
µA
After startup (backup mode and
LDOBAT_IN = 0V), at room
temperature
Current consumption
VBAT(1)
10
µA
After startup (normal mode), at room
temperature
Current consumption
1.5
mA
Note:
1. If no current is caused by outputs (pad output current as well as current across internal
pull-up resistors)
24
ATR0625 [Preliminary]
4925A–GPS–02/06
ATR0625 [Preliminary]
12. Ordering Information
Extended Type Number
ATR0625-PYQW
ATR0625-EK1
Package
MPQ
2000
1
Remarks
8 mm × 8 mm, 0.50 mm pitch, Pb-free,
RoHS-compliant, green
QFN56
-
-
Evaluation kit/Road test kit
Development kit inclusive example design
information
ATR0625-DK1
1
13. Package QFN56
Package: QFN56 8 x 8
Exposed pad 6.5 x 6.5
8
Dimensions in mm
0.9 max.
Not indicated tolerances 0.05
+0
6.5
0.05-0.05
43
56
56
1
Pin 1 ID
1
42
29
technical drawings
according to DIN
specifications
14
15
14
28
0.5 nom.
Drawing-No.: 6.543-5121.01-4
Issue: 1; 02.09.05
25
4925A–GPS–02/06
Atmel Corporation
Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Regional Headquarters
Microcontrollers
2325 Orchard Parkway
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相关型号：
ATR0630-7KQY
Telecom Circuit, 1-Func, PBGA96, 7 X 10 MM, 0.80 MM PITCH, ROHS COMPLIANT, BGA-96
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