ATR0630-EK1 [ATMEL]
ANTARIS4 Single-chip GPS Receiver; ANTARIS 4单芯片GPS接收器
| 型号： | ATR0630-EK1 |
| 厂家： | 
ATMEL |
| 描述： | ANTARIS4 Single-chip GPS Receiver |
| 文件： | 总14页 (文件大小：321K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• 16-channel GPS Correlator
– 8192 Search Bins with GPS Acquisition Accelerator
– Accuracy: 2.5m CEP (2D, Stand Alone)
– Time to First Fix: 34s (Cold Start)
– Acquisition Sensitivity: –140 dBm (With External LNA)
– Tracking Sensitivity: –150 dBm (With External LNA)
• Utilizes the ARM7TDMI® ARM® Thumb® Processor Core
– High-performance 32-bit RISC Architecture
– EmbeddedICE™ (In-Circuit Emulation)
• 128 Kbytes Internal RAM
• 384 Kbytes Internal ROM with u-blox GPS Firmware
• 1.5-bit ADC On-chip
• Single IF Architecture
ANTARIS4
Single-chipGPS
Receiver
• 2 External Interrupts
• 24 User-programmable I/O Lines
ATR0630P1
Automotive
• 1 USB Device Port
– Universal Serial Bus (USB) 2.0 Full-speed Device
– Embedded USB V2.0 Full-speed Transceiver
• 2 USARTs
• Master/Slave SPI Interface
– 4 External Slave Chip Selects
Summary
• Programmable Watchdog Timer
• Advanced Power Management Controller (APMC)
– Geared Master Clock to Reduce Power Consumption
– Sleep State with Disabled Master Clock
– Hibernate State with 32.768 kHz Master Clock
• Real Time Clock (RTC)
• 1.8V to 3.3V User-definable IO Voltage for Several GPIOs with 5V Tolerance
• 4 KBytes of Battery Backup Memory
• 7 mm × 10 mm 96 Pin BGA Package, 0.8 mm Pitch, Pb-free, RoHS-compliant
Benefits
• Fully Integrated Design With Low BOM
• No External Flash Memory Required
• Requires Only a GPS XTAL, No TCXO
• Supports NMEA®, UBX Binary and RTCM Protocol for DGPS
• Supports SBAS (WAAS, EGNOS, MSAS)
• Up to 4Hz Update Rate
• Supports A-GPS (Aiding)
• Excellent Noise Performance
NOTE: This is a summary document.
The complete document is available.
For more information, please contact
your local Atmel sales office.
4978AS–GPS–12/07
1. Description
The ATR0630P1 is a low-power, single-chip GPS receiver, especially designed to meet the
requirements of mobile applications. It is based on Atmel®’s ANTARIS®4 technology and inte-
grates an RF front-end, filtering, and a baseband processor in a single, tiny 7 mm × 10 mm
96 pin BGA package. Providing excellent RF performance with low noise figure and low power
consumption.
Due to the fully integrated design, just an RF SAW filter, a GPS XTAL (no TCXO) and blocking
capacitors are required to realize a stand-alone GPS functionality.
The ATR0630P1 includes a complete GPS firmware, licensed from u-blox AG, which performs
the GPS operation, including tracking, acquisition, navigation and position data output. For nor-
mal PVT (Position/Velocity/Time) applications, there is no need for external Flash- or
ROM-memory.
The firmware supports e.g. the NMEA protocol (2.1 and 2.3), a binary protocol for PVT data,
configuration and debugging, the RTCM protocol for DGPS, SBAS (WAAS, EGNOS and MSAS)
and A-GPS (aiding). It is also possible to store the configuration settings in an optional external
EEPROM.
Due to the integrated ARM7TDMI processor and an intelligent radio architecture, the
ATR0630P1 operates in a complete autonomous mode, utilizing on chip AGC in closed loop
operation.
For maximum performance, we recommend to use the ATR0630P1 together with a low noise
amplifier (e.g. ATR0610).
The ATR0630P1 supports assisted GPS.
2
ATR0630P1
4978AS–GPS–12/07
ATR0630P1
2. Architectural Overview
2.1
Block Diagram
Figure 2-1. ATR0630P1 Block Diagram
PUXTO
PURF
VDD18
VDDIO
VDD_USB
VDIG
VBAT18
VBAT
LDOBAT_IN
Power Supply Manager/
PMSS/Logic
LDO_OUT
LDO_IN
VCC1
VCC2
LDO_EN
VBP
AGCO
EGC
SDI
TEST
MO
1
A
A
SIGHI
SIGLO
CLK23
D
D
RF
NRF
VCO
PLL
XTO
NXTO
X
XTO
NX
RF_ON
NSHDN
NSLEEP
XT_IN
XT_OUT
P20/TIMEPULSE
P29/GPSMODE12
P27/GPSMODE11
P26/GPSMODE10
P24/GPSMODE8
P23/GPSMODE7
P19/GPSMODE6
P17/GPSMODE5
P13/GPSMODE3
P12/GPSMODE2
P1/GPSMODE0
P21/TXD2
P22/RXD2
P14/NAADET1
P25/NAADET0
P15/ANTON
P0/NANTSHORT
P18/TXD1
P31/RXD1
P9/EXTINT0
USB_DP
USB_DM
P16/NEEPROM
P8/STATUSLED
P30/AGCOUT0
P2/BOOT_MODE
DBG_EN
NTRST
TDI
TDO
TCK
NRESET
TMS
3
4978AS–GPS–12/07
2.2
General Description
The ATR0630P1 has been designed especially for mobile applications. It provides high isolation
between GPS and cellular bands, as well as very low power consumption.
ATR0630P1 is based on the successful ANTARIS4 technology which includes the ANTARIS
ROM software, developed by u-blox AG, Switzerland. ANTARIS provides a proven navigation
engine which is used in high-end car navigation systems, automatic vehicle location (AVL),
security and surveying systems, traffic control, road pricing, and speed camera detectors, and
provides location-based services (LBS) worldwide.
The ANTARIS4 chipset has a very low power consumption and comes with a very low BoM for
the passive components. Especially, due to its fast search engine and GPS accelerator, the
ATR0630P1 only needs a GPS crystal (XTAL) as a resonator for the integrated crystal oscillator
of the ATR0630P1. This saves the considerable higher cost of a TCXO which is required for
competitor’s systems. Also, as the powerful standard software is available in ROM, no external
flash memory is needed.
The L1 input signal (fRF) is a Direct Sequence Spread Spectrum (DSSS) signal with a center fre-
quency of 1575.42 MHz. The digital modulation scheme is Bi-Phase-Shift-Keying (BPSK) with a
chip rate of 1.023 Mbps.
2.3
2.4
PMSS Logic
The power management, startup and shutdown (PMSS) logic ensures reliable operation within
the recommended operating conditions. The external power control signals PUrf and PUxto are
passed through Schmitt trigger inputs to eliminate voltage ripple and prevent undesired behavior
during start-up and shut-down. Digital and analog supply voltages are analyzed by a monitoring
circuit, enabling the startup of the IC only when it is within a safe operating range.
XTO
The XTO is designed for minimum phase noise and frequency perturbations. The balanced
topology gives maximum isolation from external and ground coupled noise. The built-in jump
start circuitry ensures reliable start-up behavior of any specified crystal. For use with an external
TCXO, the XTO circuitry can be used as a single-ended or balanced input buffer.
The recommended reference frequency is: fXTO = 23.104 MHz.
2.5
2.6
VCO/PLL
The frequency synthesizer features a balanced VCO and a fully integrated loop filter, thus no
external components are required. The VCO combines very good phase noise behavior and
excellent spurious suppression. The relation between the reference frequency (fXTO) and the
VCO center frequency (fVCO) is given by: fVCO = fXTO × 64 = 23.104 MHz × 64 = 1478.656 MHz.
RF Mixer/Image Filter
Combined with the antenna, an external LNA provides a first band-path filtering of the signal.
Atmel’s ATR0610 is recommended for the LNA due to its low noise figure, high linearity and low
power consumption. The output of the LNA drives a SAW filter, which provides image rejection
for the mixer and the required isolation to all GSM bands. The output of the SAW filter is fed into
a highly linear mixer with high conversion gain and excellent noise performance.
4
ATR0630P1
4978AS–GPS–12/07
ATR0630P1
2.7
2.8
VGA/AGC
The on-chip automatic gain control (AGC) stage sets the gain of the VGA in order to optimally
load the input of the following analog-to-digital converter. The AGC control loop can be selected
for on-chip closed-loop operation or for baseband controlled gain mode.
Analog-to-digital Converter
The analog-to-digital converter stage has a total resolution of 1.5 bits. It comprises balanced
comparators and a sub-sampling unit, clocked by the reference frequency (fXTO). The frequency
spectrum of the digital output signal (fOUT), present at the data outputs SIGLO and SIGH1, is
4.348 MHz.
2.9
Baseband
The GPS baseband core includes a 16-channel correlator and is based on an ARM7TDMI ARM
processor core with very low power consumption. It has a high-performance 32 bit RISC archi-
tecture, uses a high-density 16-bit instruction set, The ARM standard In-Circuit Emulation debug
interface is supported via the JTAG/ICE port of the ATR0630P1.
The ATR0630P1 architecture consists of two main buses, the Advanced System Bus (ASB) and
the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It inter-
faces the processor with the on-chip 32-bit memories and the external memories and devices by
means of the External Bus Interface (EBI). The APB is designed for accesses to on-chip periph-
erals and is optimized for low power consumption. The AMBA™ Bridge provides an interface
between the ASB and the APB.
An on-chip Peripheral Data Controller (PDC2) transfers data between the on-chip USARTs/SPI
and the on- and off-chip memories without processor intervention. Most importantly, the PDC2
removes the processor interrupt handling overhead and significantly reduces the number of
clock cycles required for a data transfer. It can transfer up to 64K contiguous bytes without
reprogramming the starting address. As a result, the performance of the microcontroller is
increased and the power consumption reduced.
All of the external signals of the on-chip peripherals are under the control of the Parallel I/O Con-
troller (PIO2). The PIO2 Controller can be programmed to insert an input filter on each pin or
generate an interrupt on a signal change. After reset, the user must carefully program the PIO2
Controller in order to define which peripheral signals are connected with off-chip logic.
The ATR0630P1 features a Programmable Watchdog Timer.
An Advanced Power Management Controller (APMC) allows for the peripherals to be deacti-
vated individually. Automatic master clock gearing reduces power consumption. A Sleep Mode
is available with disabled 23.104 MHz master clock, as well as a Back-up Mode operating
32.768 kHz master clock.
A 32.768 kHz Real Time Clock (RTC), together with a buit-in battery back-up SRAM, allows for
storage of Almanac, Ephemeris, software configurations to make quick hot- and warm starts.
The ATR0630P1 includes full GPS firmware, licensed from u-blox AG, Switzerland. Features of
the ROM firmware are described in software documentation available from u-blox AG,
Switzerland.
5
4978AS–GPS–12/07
3. Pin Configuration
3.1
Pinout
Figure 3-1. Pinning BGA96 (Top View)
1
2
3
4
5
6
7
8
9
10 11 12
A
B
C
D
E
F
ATR0630P1
G
H
Table 3-1.
ATR0630P1 Pinout
PIO Bank A
Pull Resistor
Pin Name BGA 96
Pin Type
(Reset Value)(1)
Firmware Label
I
O
AGCO
CLK23
DBG_EN
EGC
A4
A8
E8
D4
C5
A6
A9
B11
F5
Analog I/O
Digital OUT
Digital IN
Digital IN
Supply
PD
GDIG
GND
Supply
GND
Supply
GND
Supply
GND
Supply
GND
H8
H12
A3
B1
Supply
GND
Supply
GNDA
GNDA
Supply
Supply
Notes: 1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset
2. VBAT18 represent the internal power supply of the backup power domain.
3. VDD_USB is the supply voltage for following the USB pins: USB_DM and USB_DP. For operation of the USB interface, sup-
ply of 3.0V to 3.6V is required.
4. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29.
6
ATR0630P1
4978AS–GPS–12/07
ATR0630P1
Table 3-1.
ATR0630P1 Pinout (Continued)
PIO Bank A
Pull Resistor
Pin Name BGA 96
Pin Type
Supply
(Reset Value)(1)
Firmware Label
I
O
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
LDOBAT_IN
LDO_EN
LDO_IN
LDO_OUT
MO
B4
D2
E1
Supply
Supply
E2
Supply
E3
Supply
F1
Supply
F2
Supply
F3
Supply
G1
H1
D11
C11
E11
E12
C3
A7
Supply
Supply
Supply
Digital IN
Supply
Supply
Analog OUT
Digital I/O
Analog IN
Digital OUT
Digital OUT
Digital IN
Analog OUT
Analog IN
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
NRESET
NRF
Open Drain PU
C1
E9
NSHDN
NSLEEP
NTRST
NX
E10
H11
B2
PD
NXTO
P0
B3
C8
D8
C6
D7
A11
D6
B10
G6
F11
G8
H6
C7
F6
PD
NANTSHORT
GPSMODE0
BOOT_MODE
STATUSLED
EXTINT0
P1
Configurable (PD)
Configurable (PD)
Configurable (PD)
PU to VBAT18
Configurable (PU)
PU to VBAT18
Configurable (PD)
PD
P2
‘0’
‘0’
P8
P9
EXTINT0
EXTINT1
P12
GPSMODE2
GPSMODE3
NAADET1
NPCS2
‘0’
P13
P14
P15
ANTON
P16
Configurable (PU)
Configurable (PD)
Configurable (PU)
Configurable (PU)
NEEPROM
GPSMODE5
TXD1
P17
SCK1
SCK1
TXD1
P18
P19
GPSMODE6
Notes: 1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset
2. VBAT18 represent the internal power supply of the backup power domain.
3. VDD_USB is the supply voltage for following the USB pins: USB_DM and USB_DP. For operation of the USB interface, sup-
ply of 3.0V to 3.6V is required.
4. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29.
7
4978AS–GPS–12/07
Table 3-1.
ATR0630P1 Pinout (Continued)
PIO Bank A
Pull Resistor
Pin Name BGA 96
Pin Type
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital IN
Digital IN
Digital IN
Analog IN
Digital OUT
Digital IN
Digital OUT
Digital OUT
Digital IN
Digital IN
Digital OUT
Analog IN
Digital IN
Digital I/O
Digital I/O
Supply
(Reset Value)(1)
Firmware Label
TIMEPULSE
TXD2
I
O
P20
P21
G7
E6
Configurable (PD)
Configurable (PU)
PU to VBAT18
Configurable (PU)
Configurable (PU)
Configurable (PD)
Configurable (PU)
Configurable (PU)
OH
SCK2
SCK2
TXD2
P22
D10
F8
RXD2
RXD2
SCK
P23
GPSMODE7
GPSMODE8
NAADET0
SCK
MOSI
P24
H7
G5
B6
MOSI
MISO
NSS
P25
MISO
P26
GPSMODE10
GPSMODE11
NPCS0
NPCS1
P27
F7
P28
E7
P29
D5
G12
C10
G4
H4
F4
Configurable (PU)
PD
GPSMODE12
AGCOUT0
RXD1
NPCS3
P30
AGCOUT0
P31
PU to VBAT18
RXD1
PURF
PURF
PUXTO
RF
D1
F10
C4
B8
RF_ON
SDI
PD
SIGHI0
SIGLO0
TCK
B7
G9
H10
F9
PU
PU
TDI
TDO
TEST
TMS
D3
G10
D9
C9
D12
C12
G2
G3
H2
H3
C2
E4
PU
USB_DM
USB_DP
VBAT
VBAT18(2)
VBP
Supply
Supply
VBP
Supply
VBP
Supply
VBP
Supply
VCC1
VCC2
Supply
Supply
Notes: 1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset
2. VBAT18 represent the internal power supply of the backup power domain.
3. VDD_USB is the supply voltage for following the USB pins: USB_DM and USB_DP. For operation of the USB interface, sup-
ply of 3.0V to 3.6V is required.
4. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29.
8
ATR0630P1
4978AS–GPS–12/07
ATR0630P1
Table 3-1.
ATR0630P1 Pinout (Continued)
PIO Bank A
Pull Resistor
Pin Name BGA 96
Pin Type
Supply
(Reset Value)(1)
Firmware Label
I
O
VDD_USB(3)
VDD18
VDD18
VDD18
VDD18
VDD18
VDDIO(4)
VDDIO
VDIG
A10
H9
Supply
G11
F12
B9
Supply
Supply
Supply
E5
Supply
B5
Supply
H5
Supply
A5
Supply
X
A2
Analog OUT
Analog IN
Analog OUT
Analog Input
XT_IN
A12
B12
A1
XT_OUT
XTO
Notes: 1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset
2. VBAT18 represent the internal power supply of the backup power domain.
3. VDD_USB is the supply voltage for following the USB pins: USB_DM and USB_DP. For operation of the USB interface, sup-
ply of 3.0V to 3.6V is required.
4. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29.
3.2
Signal Description
Table 3-2.
Signal Description
Pin Number
Pin Name
Type
Active Level Pin Description/Comment
RF Section
D1
RF
ANALOG IN
ANALOG IN
-
-
Input from SAW filter
C1
NRF
Inverted input from SAW filter
GPS XTAL Section
A1
XTO
ANALOG IN
ANALOG IN
-
-
-
-
XTO input (23.104 MHz)/optional TCXO input
Inverted XTO input (23.104 MHz)/optional TCXO input
XTO interface (capacitor)
B3
NXTO
X
A2
B2
ANALOG OUT
ANALOG OUT
NX
Inverted XTO interface (capacitor)
RTC Section
A12
XT_IN
ANALOG IN
-
-
Oscillator input (32.768 kHz)
Oscillator output (32.768 kHz)
B12
XT_OUT
ANALOG OUT
Automatic Gain Control, bandwidth setting
A4
AGCO
ANALOG IO
-
-
Automatic gain control analog voltage, connect shunt capacitor to GND
Enable external gain control
(high = software gain control, low = automatic gain control)
D4
EGC
DIGITAL IN
G12
C4
AGCOUT0
SDI
DIGITAL OUT
DIGITAL IN
-
-
Software gain control
Software gain control
9
4978AS–GPS–12/07
Table 3-2.
Pin Number
Boot Section
C6
Signal Description (Continued)
Pin Name
BOOT_MODE
NRESET
Type
Active Level Pin Description/Comment
DIGITAL IN
DIGITAL IN
-
Leave open, internal pull down
Reset
A7
Low
Reset input; open drain with internal pull-up resistor
APMC/Power Management
E9
C11
E10
NSHDN
LDO_EN
NSLEEP
PUXTO
PURF
DIGITAL OUT
DIGITAL IN
Low
Shutdown output, connect to LDO_EN (C11)
Enable LDO18
-
DIGITAL OUT
DIGITAL IN
Low
Power-up output for GPS XTAL, connect to PUXTO (F4)
Power-up input for GPS XTAL
F4
-
-
-
G4, H4
F10
DIGITAL IN
Power-up input for GPS radio
RF_ON
DIGITAL OUT
Power-up output for GPS radio, connect to PURF (G4, H4)
Advanced Interrupt Controller (AIC)
High/Low/
Edge
A11, B10
EXTINT0-1
DIGITAL IN
External interrupt request
USART
C10, D10
C7, E6
RXD1/RXD2
TXD1/TXD2
SCK1/SCK2
DIGITAL IN
DIGITAL OUT
DIGITAL I/O
-
-
-
USART receive data
USART transmit data
H6, G7
External synchronous serial clock
USB
C9
USB_DP
USB_DM
DIGITAL I/O
DIGITAL I/O
-
-
USB data (D+)
USB data (D-)
D9
SPI Interface
F8
H7
G5
B6
SCK
MOSI
DIGITAL I/O
DIGITAL I/O
DIGITAL I/O
DIGITAL I/O
-
SPI clock
-
-
Master out slave in
Master in slave out
Slave select
MISO
NSS/NPCS0
Low
NPCS1/NPCS2
/NPCS3
F7, D6, D5
DIGITAL OUT
Low
Slave select
PIO
A11, B[6,10],
C[6-8,10],
D[5-8,10],
E[6,7],
P0 to P31
DIGITAL I/O
-
Programmable I/O ports
F[6-8],
G[5-8],
H[6,7]
Configuration
B[6,10],
D[5,6,8],
F[6-8], H[6,7]
GPSMODE0-1
2
DIGITAL IN
DIGITAL IN
-
GPS mode pins
G8
GPS
D7
NEEPROM
Low
Enable EEPROM support
STATUSLED
TIMEPULSE
DIGITAL OUT
DIGITAL OUT
-
-
Status LED
G7
GPS synchronized time pulse
10
ATR0630P1
4978AS–GPS–12/07
ATR0630P1
Table 3-2.
Signal Description (Continued)
Pin Number
Pin Name
Type
Active Level Pin Description/Comment
Active Antenna Supervision
C8
NANTSHORT
DIGITAL IN
DIGITAL IN
Low
Low
-
Active antenna short detection Input
Active antenna detection Input
Active antenna power-on Output
NAADET0/
NAADET1
G5, G6
F11
ANTON
DIGITAL OUT
JTAG Interface
E8
F9
DBG_EN
TDO
DIGITAL IN
DIGITAL OUT
DIGITAL IN
DIGITAL IN
DIGITAL IN
DIGITAL IN
-
Debug enable
Test data out
Test clock
-
G9
TCK
-
G10
H10
H11
Debug/Test
C3
TMS
-
-
Test mode select
Test data in
TDI
NTRST
Low
Test reset input
MO
ANALOG OUT
ANALOG IN
-
-
-
-
-
IF output buffer
D3
TEST
SIGLO
SIGHI
CLK23
Enable IF output buffer
Digital IF (data output “Low”)
Digital IF (data output “High”)
Digital IF (sample clock)
B7
DIGITAL OUT
DIGITAL OUT
DIGITAL OUT
B8
A8
Power Analog Part
C2
E4
VCC1
SUPPLY
SUPPLY
-
-
Analog supply 3V
Analog supply 3V
VCC2
G2, G3, H2,
H3
VBP
SUPPLY
-
Analog supply 3V
A3, B1, B4,
D2, E[1-3],
F[1-3], G1,
H1
GNDA
VDIG
SUPPLY
-
Analog Ground
Power Digital Part
A5
SUPPLY
SUPPLY
-
-
Digital supply (radio) 1.8V
Core voltage 1.8V
B9, E5, F12,
G11,H9
VDD18
USB transceiver supply voltage (3.0V to 3.6V (USB enabled) or 0 to
2.0V (USB disabled))
A10
VDD_USB
SUPPLY
-
B5, H5
C5
VDDIO
GDIG
SUPPLY
SUPPLY
-
-
Variable I/O voltage 1.65V to 3.6V
Digital ground (radio)
A6, A9, B11,
F5, H8, H12
GND
SUPPLY
-
Digital ground
LDO18
E11
LDO_IN
SUPPLY
SUPPLY
-
-
2.3V to 3.6V
E12
LDO_OUT
1.8V LDO18 output, max. 80 mA
LDOBAT
D11
LDOBAT_IN
VBAT
SUPPLY
SUPPLY
SUPPLY
-
-
-
2.3V to 3.6V
D12
1.5V to 3.6V
C12
VBAT18
1.8V LDOBAT Output
11
4978AS–GPS–12/07
3.3
External Connections for a Working GPS System
Figure 3-2. Example of an External Connection (ATR0630P1)
ATR0630P1
XT_IN
NC
NC
NC
SIGHI
SIGLO
CLK23
LNA
(optional)
SAW
32.768 kHz
(see RTC)
RF
XT_OUT
XTO
NXTO
X
ATR0610
NRF
RF_ON
PURF
NSLEEP
PUXTO
23.104 MHz
NX
(see GPS crystal)
NC
NC
NC
NC
NC
NC
NC
NRESET
TMS
TCK
TDI
NTRST
TDO
DBG_EN
P8
STATUS LED
P20
TIMEPULSE
see Table 3-15
see Table 3-15
see Table 3-15
see Table 3-15
see Table 3-15
see Table 3-15
P0 - 2
P9
USB_DM
USB_DP
Optional
USB
P12 - 17
P19
P23 - 27
P29 - 30
P31
P18
Optional
USART 1
P30/AGCOUT0
SDI
P22
P21
Optional
USART 2
NC
NC
MO
TEST
EGC
GND analog
AGCO
GND digital
GND analog
GNDD
GNDA
+3V
GND
(see Power Supply)
NSHDN
LDO_EN
VDDIO
+3V
+3V
(see Power Supply)
LDO_OUT
VDD18
VDIG
(see Power Supply)
VDD_USB
+3V
LDO_IN
(see Power Supply)
LDOBAT_IN
VCC1
VCC2
VBP
VBAT18
VBAT
+3V
(see Power Supply)
GND
NC: Not connected
12
ATR0630P1
4978AS–GPS–12/07
ATR0630P1
4. Ordering Information
Extended Type Number
Package
MPQ
3000
1
Remarks
7 mm × 10 mm, 0.8 mm pitch, Pb-free,
RoHS-compliant
ATR0630P1-7KQY
ATR0630-EK1
BGA96
-
-
Evaluation kit/Road test kit
Design kit including design guide and PCB
Gerber files
ATR0630-DK1
1
5. Package Information
2.
Package: BGA96
Dimensions in mm
0.08
0.15
n
n
m
m
C
0.4±0.05
B A
A1 Corner
Top View
Bottom View
A1 Corner
1 2 3 4 5 6 7 8 9 10 11 12
12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
G
H
Pin A1 Laser Marking
0.8
A
8.8
10±0.05
B
technical drawings
according to DIN
specifications
0.1C
0.08 C
Drawing-No.: 6.580-5005.01-4
Issue: 2; 31.05.06
Seating plane
3.
C
Note:
1. All dimensions and tolerance conform to ASME Y 14.5M-1994
Dimension is measured at the maximum solder ball diameter, parallel to primary datum
C
2.
3.
Primary datum
and seating plane are defined by the spherical crowns of the solder balls
C
4. The surface finish of the package shall be EDM CHARMILLE #24 - #27
5. Unless otherwise specified tolerance: Decimal ±0.05, Angular ±2
5. Raw ball diameter: 0.4 mm ref.
˚
13
4978AS–GPS–12/07
Headquarters
International
Atmel Corporation
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Tel: (33) 1-30-60-70-00
Fax: (33) 1-30-60-71-11
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Product Contact
Web Site
Technical Support
Sales Contact
www.atmel.com
gps@atmel.com
www.atmel.com/contacts
Literature Requests
www.atmel.com/literature
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