ATR0630-7KQY [ATMEL]
Telecom Circuit, 1-Func, PBGA96, 7 X 10 MM, 0.80 MM PITCH, ROHS COMPLIANT, BGA-96;
| 型号： | ATR0630-7KQY |
| 厂家： | 
ATMEL |
| 描述： | Telecom Circuit, 1-Func, PBGA96, 7 X 10 MM, 0.80 MM PITCH, ROHS COMPLIANT, BGA-96 电信 电信集成电路 |
| 文件： | 总36页 (文件大小：286K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• 16-channel GPS Correlator
– 8192 Search Bins with GPS Acquisition Accelerator
– Accuracy: 2.5m CEP (2D, Stand Alone)
– Time to First Fix: 34s (Cold Start)
– Acquisition Sensitivity: –139 dBm (With External LNA)
– Tracking Sensitivity: –149 dBm (With External LNA)
• Utilizes the ARM7TDMI® ARMt® Thumb® Processor Core
– High-performance 32-bit RISC Architecture
– EmbeddedICE™ (In-Circuit Emulation)
• 128 Kbytes Internal RAM
• 384 Kbytes Internal ROM with u-blox GPS Firmware
• 1.5-bit ADC On-chip
• Single IF Architecture
ANTARIS4
Single-chipGPS
Receiver
• 2 External Interrupts
• 24 User-programmable I/O Lines
ATR0630
• 1 USB Device Port
– Universal Serial Bus (USB) 2.0 Full-speed Device
– Embedded USB V2.0 Full-speed Transceiver
• 2 USARTs
Preliminary
• Master/Slave SPI Interface
– 4 External Slave Chip Selects
• Programmable Watchdog Timer
• Advanced Power Management Controller (APMC)
– Geared Master Clock to Reduce Power Consumption
– Sleep State with Disabled Master Clock
– Hibernate State with 32.768 kHz Master Clock
• Real Time Clock (RTC)
• 1.8V to 3.3V User-definable IO Voltage for Several GPIOs with 5V Tolerance
• 4 KBytes of Battery Backup Memory
• 7 mm × 10 mm 96 Pin BGA Package, 0.8 mm Pitch, Pb-free, RoHS-compliant
Benefits
• Fully Integrated Design With Low BOM
• No External Flash Memory Required
• Requires Only a GPS XTAL, No TCXO
• Supports NMEA, UBX Binary and RTCM Protocol for DGPS
• Supports SBAS (WAAS, EGNOS, MSAS)
• Up to 4Hz Update Rate
• Supports A-GPS (Aiding)
• Excellent Noise Performance
4920B–GPS–06/06
1. Description
The ATR0630 is a low-power, single-chip GPS receiver, especially designed to meet the
requirements of mobile applications. It is based on Atmel’s ANTARIS™4 technology and inte-
grates an RF front-end, filtering, and a baseband processor in a single, tiny 7 mm × 10 mm
96 pin BGA package. Providing excellent RF performance with low noise figure and low power
consumption.
Due to the fully integrated design, just an RF SAW filter, a GPS XTAL (no TCXO) and blocking
capacitors are required to realize a stand-alone GPS functionality.
The ATR0630 includes a complete GPS firmware, licensed from u-blox AG, which performs the
GPS operation, including tracking, acquisition, navigation and position data output. For normal
PVT (Position/Velocity/Time) applications, there is no need for external Flash- or ROM-memory.
The firmware supports e.g. the NMEA protocol (2.1 and 2.3), a binary protocol for PVT data,
configuration and debugging, the RTCM protocol for DGPS, SBAS (WAAS, EGNOS and MSAS)
and A-GPS (aiding). It is also possible to store the configuration settings in an optional external
EEPROM.
Due to the integrated ARM7TDMI processor and an intelligent radio architecture, the ATR0630
operates in a complete autonomous mode, utilizing on chip AGC in closed loop operation.
For maximum performance, we recommend to use the ATR0630 together with a low noise
amplifier (e.g. ATR0610).
The ATR0630 supports assisted GPS.
2
ATR0630 [Preliminary]
4920B–GPS–06/06
ATR0630 [Preliminary]
2. Architectural Overview
2.1
Block Diagram
Figure 2-1. ATR0630 Block Diagram
PUXTO
PURF
VDD18
VDDIO
VDD_USB
VDIG
VBAT18
VBAT
LDOBAT_IN
Power Supply Manager/
PMSS/Logic
LDO_OUT
LDO_IN
VCC1
VCC2
LDO_EN
VBP
AGCO
EGC
SDI
TEST
MO
1
A
A
SIGHI
SIGLO
CLK23
D
D
RF
NRF
VCO
PLL
XTO
NXTO
X
XTO
NX
RF_ON
NSHDN
NSLEEP
XT_IN
XT_OUT
P20/TIMEPULSE
P29/GPSMODE12
P27/GPSMODE11
P26/GPSMODE10
P24/GPSMODE8
P23/GPSMODE7
P19/GPSMODE6
P17/GPSMODE5
P13/GPSMODE3
P12/GPSMODE2
P1/GPSMODE0
P21/TXD2
P22/RXD2
P14/NAADET1
P25/NAADET0
P15/ANTON
P0/NANTSHORT
P18/TXD1
P31/RXD1
P9/EXTINT0
USB_DP
USB_DM
P16/NEEPROM
P8/STATUSLED
P30/AGCOUT0
P2/BOOT_MODE
DBG_EN
NTRST
TDI
TDO
TCK
NRESET
TMS
3
4920B–GPS–06/06
2.2
General Description
The ATR0630 has been designed especially for mobile applications. It provides high isolation
between GPS and cellular bands, as well as very low power consumption.
ATR0630 is based on the successful ANTARIS4 technology which includes the ANTARIS ROM
software, developed by u-blox AG, Switzerland. ANTARIS provides a proven navigation engine
which is used in high-end car navigation systems, automatic vehicle location (AVL), security and
surveying systems, traffic control, road pricing, and speed camera detectors, and provides loca-
tion-based services (LBS) worldwide.
The ANTARIS4 chipset has a very low power consumption and comes with a very low BoM for
the passive components. Especially, due to its fast search engine and GPS accelerator, the
ATR0630 only needs a GPS crystal (XTAL) as a resonator for the integrated crystal oscillator of
the ATR0630. This saves the considerable higher cost of a TCXO which is required for competi-
tor’s systems. Also, as the powerful standard software is available in ROM, no external flash
memory is needed.
The L1 input signal (fRF) is a Direct Sequence Spread Spectrum (DSSS) signal with a center fre-
quency of 1575.42 MHz. The digital modulation scheme is Bi-Phase-Shift-Keying (BPSK) with a
chip rate of 1.023 Mbps.
2.3
2.4
PMSS Logic
The power management, startup and shutdown (PMSS) logic ensures reliable operation within
the recommended operating conditions. The external power control signals PUrf and PUxto are
passed through Schmitt trigger inputs to eliminate voltage ripple and prevent undesired behavior
during start-up and shut-down. Digital and analog supply voltages are analyzed by a monitoring
circuit, enabling the startup of the IC only when it is within a safe operating range.
XTO
The XTO is designed for minimum phase noise and frequency perturbations. The balanced
topology gives maximum isolation from external and ground coupled noise. The built-in jump
start circuitry ensures reliable start-up behavior of any specified crystal. For use with an external
TCXO, the XTO circuitry can be used as a single-ended or balanced input buffer.
The recommended reference frequency is: fXTO = 23.104 MHz.
2.5
2.6
VCO/PLL
The frequency synthesizer features a balanced VCO and a fully integrated loop filter, thus no
external components are required. The VCO combines very good phase noise behavior and
excellent spurious suppression. The relation between the reference frequency (fXTO) and the
VCO center frequency (fVCO) is given by: fVCO = fXTO × 64 = 23.104 MHz × 64 = 1478.656 MHz.
RF Mixer/Image Filter
Combined with the antenna, an external LNA provides a first band-path filtering of the signal.
Atmel’s ATR0610 is recommended for the LNA due to its low noise figure, high linearity and low
power consumption. The output of the LNA drives a SAW filter, which provides image rejection
for the mixer and the required isolation to all GSM bands. The output of the SAW filter is fed into
a highly linear mixer with high conversion gain and excellent noise performance.
4
ATR0630 [Preliminary]
4920B–GPS–06/06
ATR0630 [Preliminary]
2.7
2.8
VGA/AGC
The on-chip automatic gain control (AGC) stage sets the gain of the VGA in order to optimally
load the input of the following analog-to-digital converter. The AGC control loop can be selected
for on-chip closed-loop operation or for baseband controlled gain mode.
Analog-to-digital Converter
The analog-to-digital converter stage has a total resolution of 1.5 bits. It comprises balanced
comparators and a sub-sampling unit, clocked by the reference frequency (fXTO). The frequency
spectrum of the digital output signal (fOUT), present at the data outputs SIGLO and SIGH1, is
4.348 MHz.
2.9
Baseband
The GPS baseband core includes a 16-channel correlator and is based on an ARM7TDMI ARM
processor core with very low power consumption. It has a high-performance 32 bit RISC archi-
tecture, uses a high-density 16-bit instruction set, The ARM standard In-Circuit Emulation debug
interface is supported via the JTAG/ICE port of the ATR0630.
The ATR0630 architecture consists of two main buses, the Advanced System Bus (ASB) and
the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It inter-
faces the processor with the on-chip 32-bit memories and the external memories and devices by
means of the External Bus Interface (EBI). The APB is designed for accesses to on-chip periph-
erals and is optimized for low power consumption. The AMBA™ Bridge provides an interface
between the ASB and the APB.
An on-chip Peripheral Data Controller (PDC2) transfers data between the on-chip USARTs/SPI
and the on- and off-chip memories without processor intervention. Most importantly, the PDC2
removes the processor interrupt handling overhead and significantly reduces the number of
clock cycles required for a data transfer. It can transfer up to 64K contiguous bytes without
reprogramming the starting address. As a result, the performance of the microcontroller is
increased and the power consumption reduced.
All of the external signals of the on-chip peripherals are under the control of the Parallel I/O Con-
troller (PIO2). The PIO2 Controller can be programmed to insert an input filter on each pin or
generate an interrupt on a signal change. After reset, the user must carefully program the PIO2
Controller in order to define which peripheral signals are connected with off-chip logic.
The ATR0630 features a Programmable Watchdog Timer.
An Advanced Power Management Controller (APMC) allows for the peripherals to be deacti-
vated individually. Automatic master clock gearing reduces power consumption. A Sleep Mode
is available with disabled 23.104 MHz master clock, as well as a Back-up Mode operating
32.768 kHz master clock.
A 32.768 kHz Real Time Clock (RTC), together with a buit-in battery back-up SRAM, allows for
storage of Almanac, Ephemeris, software configurations to make quick hot- and warm starts.
The ATR0630 includes full GPS firmware, licensed from u-blox AG, Switzerland. Features of the
ROM firmware are described in software documentation available from u-blox AG, Switzerland.
5
4920B–GPS–06/06
3. Pin Configuration
3.1
Pinout
Figure 3-1. Pinning BGA96 (Top View)
1
2
3
4
5
6
7
8
9
10 11 12
A
B
C
D
E
F
ATR0630
G
H
Table 3-1.
ATR0630 Pinout
PIO Bank A
Pull Resistor
Pin Name BGA 96
Pin Type
(Reset Value)(1)
Firmware Label
I
O
AGCO
CLK23
DBG_EN
EGC
A4
A8
E8
D4
C5
A6
A9
B11
F5
Analog I/O
Digital IN
Digital IN
Digital IN
Supply
PD
GDIG
GND
Supply
GND
Supply
GND
Supply
GND
Supply
GND
H8
H12
A3
B1
Supply
GND
Supply
GNDA
GNDA
Supply
Supply
Notes: 1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset
2. VBAT18 represent the internal power supply of the backup power domain, see section “Power Supply” on page 20.
3. VDD_USB is the supply voltage for following the USB pins: USB_DM and USB_DP, see section “Power Supply” on page
20. For operation of the USB interface, supply of 3.0V to 3.6V is required.
4. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29, see section “Power Supply” on page 20.
6
ATR0630 [Preliminary]
4920B–GPS–06/06
ATR0630 [Preliminary]
Table 3-1.
ATR0630 Pinout (Continued)
PIO Bank A
Pull Resistor
Pin Name BGA 96
Pin Type
Supply
(Reset Value)(1)
Firmware Label
I
O
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
LDOBAT_IN
LDO_EN
LDO_IN
LDO_OUT
MO
B4
D2
E1
Supply
Supply
E2
Supply
E3
Supply
F1
Supply
F2
Supply
F3
Supply
G1
H1
D11
C11
E11
E12
C3
A7
Supply
Supply
Supply
Digital IN
Supply
Supply
Analog OUT
Digital I/O
Analog IN
Digital OUT
Digital OUT
Digital IN
Analog OUT
Analog IN
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
NRESET
NRF
Open Drain PU
C1
E9
NSHDN
NSLEEP
NTRST
NX
E10
H11
B2
PD
NXTO
P0
B3
C8
D8
C6
D7
A11
D6
B10
G6
F11
G8
H6
C7
F6
PD
NANTSHORT
GPSMODE0
BOOT_MODE
STATUSLED
EXTINT0
P1
Configurable (PD)
Configurable (PD)
Configurable (PD)
PU to VBAT18
Configurable (PU)
PU to VBAT18
Configurable (PD)
PD
P2
‘0’
‘0’
P8
P9
EXTINT0
EXTINT1
P12
GPSMODE2
GPSMODE3
NAADET1
NPCS2
‘0’
P13
P14
P15
ANTON
P16
Configurable (PU)
Configurable (PD)
Configurable (PU)
Configurable (PU)
NEEPROM
GPSMODE5
TXD1
P17
SCK1
SCK1
TXD1
P18
P19
GPSMODE6
Notes: 1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset
2. VBAT18 represent the internal power supply of the backup power domain, see section “Power Supply” on page 20.
3. VDD_USB is the supply voltage for following the USB pins: USB_DM and USB_DP, see section “Power Supply” on page
20. For operation of the USB interface, supply of 3.0V to 3.6V is required.
4. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29, see section “Power Supply” on page 20.
7
4920B–GPS–06/06
Table 3-1.
ATR0630 Pinout (Continued)
PIO Bank A
Pull Resistor
Pin Name BGA 96
Pin Type
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital IN
Digital IN
Digital IN
Analog IN
Digital OUT
Digital IN
Digital OUT
Digital OUT
Digital IN
Digital IN
Digital OUT
Analog IN
Digital IN
Digital I/O
Digital I/O
Supply
(Reset Value)(1)
Firmware Label
TIMEPULSE
TXD2
I
O
P20
P21
G7
E6
Configurable (PD)
Configurable (PU)
PU to VBAT18
Configurable (PU)
Configurable (PU)
Configurable (PD)
Configurable (PU)
Configurable (PU)
OH
SCK2
SCK2
TXD2
P22
D10
F8
RXD2
RXD2
SCK
P23
GPSMODE7
GPSMODE8
NAADET0
SCK
MOSI
P24
H7
G5
B6
MOSI
MISO
NSS
P25
MISO
P26
GPSMODE10
GPSMODE11
NPCS0
NPCS1
P27
F7
P28
E7
P29
D5
G12
C10
G4
H4
F4
Configurable (PU)
PD
GPSMODE12
AGCOUT0
RXD1
NPCS3
P30
AGCOUT0
P31
PU to VBAT18
RXD1
PURF
PURF
PUXTO
RF
D1
F10
C4
B8
RF_ON
SDI
PD
SIGHI0
SIGLO0
TCK
B7
G9
H10
F9
PU
PU
TDI
TDO
TEST
TMS
D3
G10
D9
C9
D12
C12
G2
G3
H2
H3
C2
E4
PU
USB_DM
USB_DP
VBAT
VBAT18(2)
VBP
Supply
Supply
VBP
Supply
VBP
Supply
VBP
Supply
VCC1
VCC2
Supply
Supply
Notes: 1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset
2. VBAT18 represent the internal power supply of the backup power domain, see section “Power Supply” on page 20.
3. VDD_USB is the supply voltage for following the USB pins: USB_DM and USB_DP, see section “Power Supply” on page
20. For operation of the USB interface, supply of 3.0V to 3.6V is required.
4. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29, see section “Power Supply” on page 20.
8
ATR0630 [Preliminary]
4920B–GPS–06/06
ATR0630 [Preliminary]
Table 3-1.
ATR0630 Pinout (Continued)
PIO Bank A
Pull Resistor
Pin Name BGA 96
Pin Type
Supply
(Reset Value)(1)
Firmware Label
I
O
VDD_USB(3)
VDD18
VDD18
VDD18
VDD18
VDD18
VDDIO(4)
VDDIO
VDIG
A10
H9
Supply
G11
F12
B9
Supply
Supply
Supply
E5
Supply
B5
Supply
H5
Supply
A5
Supply
X
A2
Analog OUT
Analog IN
Analog OUT
Analog Input
XT_IN
A12
B12
A1
XT_OUT
XTO
Notes: 1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset
2. VBAT18 represent the internal power supply of the backup power domain, see section “Power Supply” on page 20.
3. VDD_USB is the supply voltage for following the USB pins: USB_DM and USB_DP, see section “Power Supply” on page
20. For operation of the USB interface, supply of 3.0V to 3.6V is required.
4. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29, see section “Power Supply” on page 20.
3.2
Signal Description
Table 3-2.
Signal Description
Pin Number
Pin Name
Type
Active Level Pin Description/Comment
RF Section
D1
RF
ANALOG IN
ANALOG IN
-
-
Input from SAW filter
C1
NRF
Inverted input from SAW filter
GPS XTAL Section
A1
XTO
ANALOG IN
ANALOG IN
-
-
-
-
XTO input (23.104 MHz)/optional TCXO input
Inverted XTO input (23.104 MHz)/optional TCXO input
XTO interface (capacitor)
B3
NXTO
X
A2
B2
ANALOG OUT
ANALOG OUT
NX
Inverted XTO interface (capacitor)
RTC Section
A12
XT_IN
ANALOG IN
-
-
Oscillator input (32.768 kHz)
Oscillator output (32.768 kHz)
B12
XT_OUT
ANALOG OUT
Automatic Gain Control, bandwidth setting
A4
AGCO
ANALOG IO
-
-
Automatic gain control analog voltage, connect shunt capacitor to GND
Enable external gain control
(high = software gain control, low = automatic gain control)
D4
EGC
DIGITAL IN
G12
C4
AGCOUT0
SDI
DIGITAL OUT
DIGITAL IN
-
-
Software gain control
Software gain control
9
4920B–GPS–06/06
Table 3-2.
Pin Number
Boot Section
C6
Signal Description (Continued)
Pin Name
BOOT_MODE
NRESET
Type
Active Level Pin Description/Comment
DIGITAL IN
DIGITAL IN
-
Leave open, internal pull down
Reset
A7
Low
Reset input; open drain with internal pull-up resistor
APMC/Power Management
E9
C11
E10
NSHDN
LDO_EN
NSLEEP
PUXTO
PURF
DIGITAL OUT
DIGITAL IN
Low
Shutdown output, connect to LDO_EN (C11)
Enable LDO18
-
DIGITAL OUT
DIGITAL IN
Low
Power-up output for GPS XTAL, connect to PUXTO (F4)
Power-up input for GPS XTAL
F4
-
-
-
G4, H4
F10
DIGITAL IN
Power-up input for GPS radio
RF_ON
DIGITAL OUT
Power-up output for GPS radio, connect to PURF (G4, H4)
Advanced Interrupt Controller (AIC)
High/Low/
Edge
A11, B10
EXTINT0-1
DIGITAL IN
External interrupt request
USART
C10, D10
C7, E6
RXD1/RXD2
TXD1/TXD2
SCK1/SCK2
DIGITAL OUT
DIGITAL IN
DIGITAL I/O
-
-
-
USART receive data output
USART transmit data input
External synchronous serial clock
H6, G7
USB
C9
USB_DP
USB_DM
DIGITAL I/O
DIGITAL I/O
-
-
USB data (D+)
USB data (D-)
D9
SPI Interface
F8
H7
G5
B6
SCK
MOSI
DIGITAL I/O
DIGITAL I/O
DIGITAL I/O
DIGITAL I/O
-
SPI clock
-
-
Master out slave in
Master in slave out
Slave select
MISO
NSS/NPCS0
Low
NPCS1/NPCS2
/NPCS3
F7, D6, D5
DIGITAL OUT
Low
Slave select
PIO
A11, B[6,10],
C[6-8,10],
D[5-8,10],
E[6,7],
P0 to P31
DIGITAL I/O
-
Programmable I/O ports
F[6-8],
G[5-8],
H[6,7]
Configuration
B[6,10],
D[5,6,8],
F[6-8], H[6,7]
GPSMODE0-1
2
DIGITAL IN
DIGITAL IN
-
GPS mode pins
G8
GPS
D7
NEEPROM
Low
Enable EEPROM support
STATUSLED
TIMEPULSE
DIGITAL OUT
DIGITAL OUT
-
-
Status LED
G7
GPS synchronized time pulse
10
ATR0630 [Preliminary]
4920B–GPS–06/06
ATR0630 [Preliminary]
Table 3-2.
Signal Description (Continued)
Pin Number
Pin Name
Type
Active Level Pin Description/Comment
Active Antenna Supervision
C8
G5, G6
F11
NANTSHORT
DIGITAL IN
DIGITAL IN
Low
Low
-
Active antenna short detection Input
NAADET0/NAA
DET1
Active antenna detection Input
Active antenna power-on Output
ANTON
DIGITAL OUT
JTAG Interface
E8
F9
DBG_EN
TDO
DIGITAL IN
DIGITAL OUT
DIGITAL IN
DIGITAL IN
DIGITAL IN
DIGITAL IN
-
Debug enable
Test data out
Test clock
-
G9
TCK
-
G10
H10
H11
Debug/Test
C3
TMS
-
-
Test mode select
Test data in
TDI
NTRST
Low
Test reset input
MO
ANALOG OUT
ANALOG IN
-
-
-
-
-
IF output buffer
D3
TEST
SIGLO
SIGHI
CLK23
Enable IF output buffer
Digital IF (data output “Low”)
Digital IF (data output “High”)
Digital IF (sample clock)
B7
DIGITAL OUT
DIGITAL OUT
DIGITAL OUT
B8
A8
Power Analog Part
C2
E4
VCC1
SUPPLY
SUPPLY
-
-
Analog supply 3V
Analog supply 3V
VCC2
G2, G3, H2,
H3
VBP
SUPPLY
-
Analog supply 3V
A3, B1, B4,
D2, E[1-3],
F[1-3], G1,
H1
GNDA
VDIG
SUPPLY
-
Analog Ground
Power Digital Part
A5
SUPPLY
SUPPLY
-
-
Digital supply (radio) 1.8V
Core voltage 1.8V
B9, E5, F12,
G11,H9
VDD18
USB transceiver supply voltage (3.0V to 3.6V (USB enabled) or 0 to
2.0V (USB disabled))
A10
VDD_USB
SUPPLY
-
B5, H5
C5
VDDIO
GDIG
SUPPLY
SUPPLY
-
-
Variable I/O voltage 1.65V to 3.6V
Digital ground (radio)
A6, A9, B11,
F5, H8, H12
GND
SUPPLY
-
Digital ground
LDO18
E11
LDO_IN
SUPPLY
SUPPLY
-
-
2.3V to 3.6V
E12
LDO_OUT
1.8V LDO18 output, max. 80 mA
LDOBAT
D11
LDOBAT_IN
VBAT
SUPPLY
SUPPLY
SUPPLY
-
-
-
2.3V to 3.6V
D12
1.5V to 3.6V
C12
VBAT18
1.8V LDOBAT Output
11
4920B–GPS–06/06
3.3
Setting GPSMODE0 to GPSMODE12
The start-up configuration of this ROM-based system without external non-volatile memory is
defined by the status of the GPSMODE pins after system reset. Alternatively, the system can be
configured through message commands passed through the serial interface after start-up. This
configuration of the ATR0630 can be stored in an external non-volatile memory like EEPROM.
Default designates settings used by ROM firmware if GPSMODE configuration is disabled
(GPSMODE0 = 0).
Table 3-3.
Pin
GPSMODE Functions
Function
GPSMODE0 (P1)
Enable configuration with GPSMODE pins
This pin (EXTINT0) is used for FixNOW™ functionality and not used for GPSMODE
configuration.
GPSMODE1 (P9)
GPSMODE2 (P12)
GPSMODE3 (P13)
GPS sensitivity settings
This pin (NAADET1) is used as active antenna supervisor input and not used for
GPSMODE4 (P14) GPSMODE configuration. This is the default selection if GPSMODE configuration is
disabled.
GPSMODE5 (P17)
Serial I/O configuration
GPSMODE6 (P19)
GPSMODE7 (P23) USB power mode
GPSMODE8 (P24) General I/O configuration
This pin (NAADET0) is used as an active Antenna Supervisor input and not used for
GPSMODE configuration
GPSMODE9 (P25)
GPSMODE10 (P26)
General I/O configuration
GPSMODE11 (P27)
GPSMODE12 (P29) Serial I/O configuration
In the case that GPSMODE pins with internal pull-up or pull-down resistors are connected to
GND/VDD18, additional current is drawn over these resistors. Especially GPSMODE3 can
impact the back-up current.
3.3.1
Enable GPSMODE Pin Configuration
Table 3-4. Enable Configuration With GPSMODE Pins
GPSMODE0
(Reset = PD) Description
0(1)
1
Ignore all GPSMODE pins. The default settings as indicated below are used.
Use settings as specified with GPSMODE[2, 3, 5 to 8, 10 to 12]
1. Leave open
Note:
If the GPSMODE configuration is enabled (GPSMODE0 = 1) and the other GPSMODE pins are
not connected externally, the reset default values of the internal pull-down and pull-up resistors
will be used.
12
ATR0630 [Preliminary]
4920B–GPS–06/06
ATR0630 [Preliminary]
3.3.2
Sensitivity Settings
Table 3-5.
GPS Sensitivity Settings
GPSMODE3
(Fixed PU)
GPSMODE2
(Reset = PU) Description
0(1)
0(1)
1(2)
1(2)
0
1(2)
Auto mode
Fast mode
0
1(2)
Normal mode (Default ROM value)
High sensitivity
Notes: 1. Increased back-up current
2. Leave open
For all GPS receivers the sensitivity depends on the integration time of the GPS signals. There-
fore there is a trade-off between sensitivity and the time to detect the GPS signal (Time to first
fix). The three modes, “Fast Acquisition”, “Normal” and “High Sensitivity”, have a fixed integra-
tion time. The “Normal” mode, recommended for the most applications, is a trade off between
the sensitivity and TTFF. The “Fast Acquisition” mode is optimized for fast acquisition, at the
cost of a lower sensitivity. The “High Sensitivity” mode is optimized for higher sensitivity, at the
cost of longer TTFF. The “Auto” mode adjusts the integration time (sensitivity) automatically
according to the measured signal levels. That means the receiver with this setting has a fast
TTFF at strong signals, a high sensitivity to acquire weak signals but some times at medium sig-
nal level a higher TTFF as the “Normal” mode. These sensitivity settings affect only the startup
performance not the tracking performance.
3.4
Serial I/O Configuration
The ATR0630 features a two-stage I/O-message and protocol-selection procedure for the two
available serial ports. At the first stage, a certain protocol can be enabled or disabled for a given
USART port or the USB port. Selectable protocols are RTCM, NMEA and UBX. At the second
stage, messages can be enabled or disabled for each enabled protocol on each port. In all con-
figurations described below, all protocols are enabled on all ports, but output messages are
enabled in a way that ports appear to communicate at only one protocol. However, each port will
accept any input message in any of the three implemented protocols.
Table 3-6.
Serial I/O Configuration
USART1/USB
GPSMODE12 GPSMODE6 GPSMODE5 (Output Protocol/
USART2
(Output Protocol/
(Reset = PU) (Reset = PU) (Reset = PD) Baud Rate (kBaud)) Baud Rate (kBaud)) Messages(1) Information Messages
0
0
0
0
1(2)
1(2)
0
0(2)
UBX/57.6
UBX/38.4
UBX/19.2
–/Auto
NMEA/19.2
NMEA/9.6
NMEA/4.8
–/Auto
High
User, Notice, Warning, Error
User, Notice, Warning, Error
User, Notice, Warning, Error
None
1
Medium
Low
0
0(2)
1
0(2)
0
Off
1(2)
1(2)
1(2)
1(2)
NMEA/19.2
NMEA/4.8
NMEA/9.6
UBX/115.2
UBX/57.6
UBX/19.2
UBX/38.4
NMEA/19.2
High
User, Notice, Warning, Error
User, Notice, Warning, Error
User, Notice, Warning, Error
All
0
1
Low
1(2)
1(2)
0(2)
1
Medium
Debug
Notes: 1. See Table 3-7 to Table 3-10 on page 14, the messages are described in the ANTARIS4 protocol specification
2. Leave open
13
4920B–GPS–06/06
Both USART ports accept input messages in all three supported protocols (NMEA, RTCM and
UBX) at the configured baud rate. Input messages of all three protocols can be arbitrarily mixed.
Response to a query input message will always use the same protocol as the query input mes-
sage. The USB port does only accept NMEA and UBX as input protocol by default. RTCM can
be enabled via protocol messages on demand.
In Auto mode, no output message is sent out by default, but all input messages are accepted at
any supported baud rate. Again, USB is restricted to only NMEA and UBX protocols. Response
to query input commands will be given by the same protocol and baud rate as it was used for the
query command. Using the respective configuration commands, periodic output messages can
be enabled.
The following message settings are used in the tables below:
Table 3-7.
NMEA Port
Supported Messages at Setting Low
Standard
NAV
GGA, RMC
SOL, SVINFO
EXCEPT
UBX Port
MON
Table 3-8.
NMEA Port
Supported Messages at Setting Medium
Standard
GGA, RMC, GSA, GSV, GLL, VTG, ZDA
SOL, SVINFO, POSECEF, POSLLH, STATUS, DOP, VELECEF,
VELNED, TIMEGPS, TIMEUTC, CLOCK
UBX Port
NAV
Table 3-9.
NMEA Port
Supported Messages at Setting High
Standard
GGA, RMC, GSA, GSV, GLL, VTG, ZDA, GRS, GST
Proprietary
PUBX00, PUBX03, PUBX04
SOL, SVINFO, POSECEF, POSLLH, STATUS, DOP, VELECEF,
VELNED, TIMEGPS, TIMEUTC, CLOCK
NAV
UBX Port
MON
SCHD, IO, IPC, EXCEPT
Table 3-10. Supported Messages at Setting Debug (Additional Undocumented Message May
be Part of Output Data)
Standard
GGA, RMC, GSA, GSV, GLL, VTG, ZDA, GRS, GST
PUBX00, PUBX03, PUBX04
NMEA Port
UBX Port
Proprietary
SOL, SVINFO, POSECEF, POSLLH, STATUS, DOP, VELECEF,
VELNED, TIMEGPS, TIMEUTC, CLOCK
NAV
MON
RXM
SCHD, IO, IPC, EXCEPT
RAW (RAW message support requires an additional license)
14
ATR0630 [Preliminary]
4920B–GPS–06/06
ATR0630 [Preliminary]
The following settings apply if GPSMODE configuration is not enabled, that is, GPSMODE = 0
(ROM defaults):
Table 3-11. Serial I/O Default Setting if GPSMODE Configuration is Deselected
(GPSMODE0 = 0)
USART1/USB
NMEA
USART2
UBX
Setting
Baud rate (kBaud)
Input protocol
Output protocol
57.6, Auto enabled
UBX, NMEA, RTCM
NMEA
57.6, Auto enabled
UBX, NMEA, RTCM
UBX
NAV: SOL, SVINFO
MON: EXCEPT
Messages
GGA, RMC, GSA, GSV
Information messages
(UBX INF or NMEA TXT)
User, Notice, Warning, Error
User, Notice, Warning, Error
3.4.1
USB Power Mode
For correct response to the USB host queries, the device has to know its power mode. This is
configured via GPSMODE7. If set to bus powered, an upper current limit of 100 mA is reported
to the USB host; that is, the device classifies itself as a “low-power bus-powered function” with
no more than one USB power unit load.
Table 3-12. USB Power Modes
GPSMODE7 (Reset = PU) Description
0
1(1)
USB device is bus-powered (maximum current limit 100 mA)
USB device is self-powered (default ROM value)
Note:
1. Leave open
3.4.2
Active Antenna Supervisor
The two pins P0/NANTSHORT and P15/ANTON plus one pin of P25/NAADET0/MISO or
P14/NAADET1 are always initialized as general purpose I/Os and used as follows:
• P15/ANTON is an output which can be used to switch on and off antenna power supply.
• Input P0/NANTSHORT will indicate an antenna short circuit, i.e. zero DC voltage at the
antenna, to the firmware. If the antenna is switched off by output P15/ANTON, it is assumed
that also input P0/NANTSHORT will signal zero DC voltage, i.e. switch to its active low state.
• Input P25/NAADET0/MISO or P14/NAADET1 will indicate a DC current into the antenna. In
case of short circuit, both P0 and P25/P14 will be active, i.e. at low level. If the antenna is
switched off by output P15/ANTON, it is assumed that also input P25/NAADET0/MISO will
signal zero DC current, i.e. switch to its active low state. Which pin is used as NAADET (P14
or P25) depends on the settings of GPSMODE11 and GPSMODE10 (see Table 3-14 on
page 16).
15
4920B–GPS–06/06
Table 3-13. Pin Usage of Active Antenna Supervisor
Pin
Usage
Meaning
Active antenna short circuit detection
High = No antenna DC short circuit present
Low = Antenna DC short circuit present
P0/NANTSHORT
NANTSHORT
P25/NAADET0/
MISO or
P14/NAADET1
Active antenna detection input
High = No active antenna present
Low = Active antenna is present
NAADET
ANTON
Active antenna power on output
High = Power supply to active antenna is switched on
Low = Power supply to active antenna is switched off
P15/ANTON
Table 3-14. Antenna Detection I/O Settings
GPSMODE11 GPSMODE10 GPSMODE8
(Reset = PU) (Reset = PU) (Reset = PU) Location of NAADET
Comment
0
0
0
0
0
1(1)
P25/NAADET0/MISO
P25/NAADET0/MISO
Reserved for further use.
Do not use this setting.
0
1(1)
1(1)
0
0
P14/NAADET1
P14/NAADET1
(Default ROM value)
0
1(1)
0
Reserved for further use.
Do not use this setting.
1(1)
1(1)
P14/NAADET1
P14/NAADET1
Reserved for further use.
Do not use this setting.
0
1(1)
1(1)
1(1)
1(1)
1(1)
0
1(1)
P25/NAADET0/MISO
P25/NAADET0/MISO
Note:
1. Leave open
The Antenna Supervisor Software will be configured as follows:
1. Enable Control Signal
2. Enable Short Circuit Detection (power down antenna via ANTON if short is detected via
NANTSHORT)
3. Enable Open Circuit Detection via NAADET
The antenna supervisor function may not be disabled by GPSMODE pin selection.
If the antenna supervisor function is not used, please leave open ANTON, NANTSHORT and
NAADET.
16
ATR0630 [Preliminary]
4920B–GPS–06/06
ATR0630 [Preliminary]
3.4.3
External Connections for a Working GPS System
Figure 3-2. Example of an External Connection (ATR0630)
ATR0630
XT_IN
NC
NC
NC
SIGHI
SIGLO
CLK23
LNA
(optional)
SAW
32.768 kHz
(see RTC)
RF
XT_OUT
XTO
NXTO
X
ATR0610
NRF
RF_ON
PURF
NSLEEP
PUXTO
23.104 MHz
NX
(see GPS crystal)
NC
NC
NC
NC
NC
NC
NC
NRESET
TMS
TCK
TDI
NTRST
TDO
DBG_EN
P8
STATUS LED
TIMEPULSE
P20
see Table 3-15
see Table 3-15
see Table 3-15
see Table 3-15
see Table 3-15
see Table 3-15
P0 - 2
P9
USB_DM
USB_DP
Optional
USB
P12 - 17
P19
P23 - 27
P29 - 30
P31
P18
Optional
USART 1
P30/AGCOUT0
SDI
P22
P21
Optional
USART 2
NC
NC
MO
TEST
EGC
GND analog
AGCO
GND digital
GND analog
GNDD
GNDA
+3V
GND
(see Power Supply)
NSHDN
LDO_EN
VDDIO
+3V
+3V
(see Power Supply)
LDO_OUT
VDD18
VDIG
(see Power Supply)
VDD_USB
+3V
LDO_IN
(see Power Supply)
LDOBAT_IN
VCC1
VCC2
VBP
VBAT18
VBAT
+3V
(see Power Supply)
GND
NC: Not connected
17
4920B–GPS–06/06
Table 3-15. Recommended Pin Connections
Pin Name
Recommended External Circuit
P0/NANTSHORT
Internal pull-down resistor; leave open if Antenna Supervision functionality is unused.
Internal pull-down resistor; leave open in order to disable the GPSMODE pin configuration feature. Connect
to VDD18 to enable the GPSMODE pin configuration feature. Refer to GPSMODE definitions in “Setting
GPSMODE0 to GPSMODE12” on page 12.
P1/GPSMODE0
P2/BOOT_MODE
P8/STATUSLED
P9/EXTINT0
Internal pull-down resistor; leave open.
Output in default ROM firmware: leave open if not used.
Internal pull-up resistor; leave open if unused.
Internal pull-up resistor; can be left open if the GPSMODE feature is not used. Refer to GPSMODE
definitions in “Setting GPSMODE0 to GPSMODE12” on page 12.
P12/GPSMODE2/NPCS2
P13/GPSMODE3/
EXTINT1
Internal pull-up resistor; can be left open if the GPSMODE feature is not used. Refer to GPSMODE
definitions in “Setting GPSMODE0 to GPSMODE12” on page 12.
P14/NAADET1
P15/ANTON
Internal pull-down resistor; leave open if Antenna Supervision functionality is unused.
Internal pull-down resistor; leave open if Antenna Supervision functionality is unused.
Internal pull-up resistor; leave open if no serial EEPROM is connected. Otherwise connect to GND.
P16/NEEPROM
Internal pull-down resistor; can be left open if the GPSMODE feature is not used. Refer to GPSMODE
definitions in “Setting GPSMODE0 to GPSMODE12” on page 12.
P17/GPSMODE5/SCK1
P18/TXD1
Output in default ROM firmware: leave open if serial interface is not used.
Internal pull-up resistor; can be left open if the GPSMODE feature is not used. Refer to GPSMODE
definitions in “Setting GPSMODE0 to GPSMODE12” on page 12.
P19/GPSMODE6/SIGLO1
P20/TIMEPULSE/SCK2
P21/TXD2
Output in default ROM firmware: leave open if time pulse feature is not used.
Output in default ROM firmware: leave open if serial interface not used.
Internal pull-up resistor; leave open if serial interface is not used.
P22/RXD2
Internal pull-up resistor; can be left open if the GPSMODE feature is not used. Refer to GPSMODE
definitions in “Setting GPSMODE0 to GPSMODE12” on page 12.
P23/GPSMODE7/SCK
Internal pull-up resistor; can be left open if the GPSMODE feature is not used. Refer to GPSMODE
definitions in “Setting GPSMODE0 to GPSMODE12” on page 12.
P24/GPSMODE8/MOSI
P25/NAADET0/MISO
Internal pull-down resistor; leave open if Antenna Supervision functionality is unused.
P26/GPSMODE10/NSS/ Internal pull-up resistor; can be left open if the GPSMODE feature is not used. Refer to GPSMODE
NPCS0
definitions in “Setting GPSMODE0 to GPSMODE12” on page 12.
Internal pull-up resistor; can be left open if the GPSMODE feature is not used. Refer to GPSMODE
definitions in “Setting GPSMODE0 to GPSMODE12” on page 12.
P27/GPSMODE11/NPCS1
Internal pull-up resistor; can be left open if the GPSMODE feature is not used. Refer to GPSMODE
definitions in “Setting GPSMODE0 to GPSMODE12” on page 12.
P29/GPSMODE12/NPCS3
P30/AGCOUT0
P31/RXD1
Internal pull-down resistor; leave open.
Internal pull-up resistor; leave open if serial interface is not used.
18
ATR0630 [Preliminary]
4920B–GPS–06/06
ATR0630 [Preliminary]
3.5
Connecting an Optional Serial EEPROM
The ATR0630 offers the possibility of connecting an external serial EEPROM. The internal ROM
firmware supports storing the configuration of the ATR0630 in serial EEPROM. The pin
P16/NEEPROM signals the firmware that a serial EEPROM is connected to the ATR0630. The
ATR0630’s 32-bit RISC processor accesses the external memory via SPI (serial peripheral inter-
face). For best results, use a 32-Kbit 1.8V serial EEPROM such as Atmel’s AT25320AY1-1.8.
Figure 3-3 shows an example of the serial EEPROM connection.
Figure 3-3. Example of a Serial EEPROM Connection
ATR0630
AT25320AY1-1.8
SCK
SI
P23/SCK
P24/MOSI
SO
P25/MISO/NAADET0
P29/NPCS3
CS_N
HOLD_N
WP_N
GND
NC
P16/NEEPROM
P1/GPSMODE0
GND
GND
NSHDN
LDO_EN
LDO_OUT
VDD18
VDDIO
+3V
(see Power Supply)
LDO_IN
LDOBAT_IN
NC: Not connected
Note:
The GPSMODE pin configuration feature can be disabled, because the configuration can be
stored in the serial EEPROM. VDDIO is the supply voltage for the pins: P23, P24, P25 and P29.
19
4920B–GPS–06/06
4. Power Supply
The ATR0630 is supplied with six distinct supply voltages:
• The power supplies for the RF part (VCC1, VCC2, VBP) within 2.7V to 3.3V.
• VDIG, the 1.8V supply of the digital pins of the RF part (SIGHI, SIGLO and CLK23). VDIG
should be connected to VDD18.
• VDD18, the nominal 1.8V supply voltage for the core, the I/O pins, the memory interface and
the test pins and all GPIO pins not mentioned in next item.
• VDDIO, the variable supply voltage within 1.8V to 3.6V for the following GPIO pins: P1, P2,
P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29. In input
mode, these pins are 5V input tolerant.
• VDD_USB, the power supply of the USB pins: USB_DM and USB_DP.
• VBAT18 to supply the backup domain: RTC, backup SRAM and the pins NSLEEP, NSHDN,
LDO_EN, VBAT18, P9/EXTIN0, P13/EXTINT1, P22/RXD2 and P31/RXD1 and the 32kHz
oscillator. In input mode, the four GPIO-pins are 5V input tolerant.
20
ATR0630 [Preliminary]
4920B–GPS–06/06
ATR0630 [Preliminary]
Figure 4-1. Connecting Example: Separate Power Supplies for RF and Digital Part Using the Internal LDOs
ATR0630 internal
VCC1
VCC2
VBP
2.7V to 3.3V
RF
VDIG
2.3V to 3.6V
LDO18
ldoin
LDO_IN
LDO_EN
LDO_OUT
ldoen
ldoout
NSHDN
VDD18
VDDIO
Core
1 µF
(X7R)
1.8V to 3.3V
variable I/O domain
LDOBAT
ldobat_in
LDOBAT_IN
VBAT
vbat
1.5V to 3.6V
vbat18
VBAT18
VDD
1 µF
(X7R)
RTC
backup memory
USB SM and
transceiver
0V or 3V to 3.6V
VDDUSB
The ATR0630 contains a built in low dropout voltage regulator LDO18. This regulator can be
used if the host system does not provide the core voltage VDD18 of 1.8V nominal. In such case,
LDO18 will provide a 1.8V supply voltage from any input voltage VDD between 2.3V and 3.6V.
The LDO_EN input can be used to shut down VDD18 if the system is in standby mode.
If the host system does supply a 1.8V core voltage directly, this voltage has to be connected to
the VDD18 supply pins of the Core. LDO_EN must be connected to GND. LDO_IN can be con-
nected to GND. LDO_OUT must not be connected.
A second built in low dropout voltage regulator LDOBAT provides the supply voltage for the RTC
and backup SRAM from any input voltage VBAT between 1.5V and 3.6V. The backup battery
delivers the supply current if LDOBAT_IN is not powered.
21
4920B–GPS–06/06
The RTC section will be initialized properly if VDD18 is supplied first to the ATR0630. If VBAT is
applied first, the current consumption of the RTC and backup SRAM is undetermined.
Figure 4-2. Connecting Example: Common Power Supplies for RF and Digital Part Using the Internal LDOs
ATR0630 internal
VCC1
VCC2
RF
VBP
VDIG
LDO18
ldoin
2.7V to 3.3V
NSHDN
LDO_IN
LDO_EN
LDO_OUT
ldoen
ldoout
VDD18
VDDIO
Core
1 µF
(X7R)
1.8V to 3.3V
variable IO domain
LDOBAT
ldobat_in
LDOBAT_IN
VBAT
vbat
1.5V to 3.6V
vbat18
VBAT18
VDD
1 µF
(X7R)
RTC
backup memory
USB SM and
transceiver
0V or 3V to 3.6V
VDDUSB
The USB Transceiver is disabled if VDD_USB < 2.0V. In this case the pins USB_DM and
USB_DP are connected to GND (internal pull-down resistors). The USB Transceiver is enabled
if VDD_USB within 3.0V and 3.6V.
22
ATR0630 [Preliminary]
4920B–GPS–06/06
ATR0630 [Preliminary]
Figure 4-3. Connecting Example: Separate Power Supplies for RF and Digital Part Using 1.8V from Host System
ATR0630 internal
VCC1
2.7V to 3.3V
VCC2
RF
VBP
VDIG
LDO18
ldoin
LDO_IN
ldoen
LDO_EN
ldoout
LDO_OUT
1.65V to 1.95V
VDD18
VDDIO
Core
1.8V to 3.3V
variable I/O domain
1 µF
(X7R)
LDOBAT
ldobat_in
2.3V to 3.6V
1.5V to 3.6V
LDOBAT_IN
VBAT
vbat
vbat18
VBAT18
VDD
1 µF
(X7R)
RTC
backup memory
USB SM and
transceiver
0V or 3V to 3.6V
VDDUSB
23
4920B–GPS–06/06
Figure 4-4. Connecting Example: Power Supply from USB Using the Internal LDOs
ATR0630 internal
VCC1
VCC2
VBP
RF
VDIG
LDO18
ldoin
LDO_IN
ldoen
ldoout
NSHDN
LDO_EN
LDO_OUT
VDD18
VDDIO
Core
1 µF
(X7R)
1.8V to 3.3V
variable I/O domain
LDOBAT
ldobat_in
LDOBAT_IN
VBAT
vbat
1.5V to 3.6V
vbat18
VBAT18
VDD
1 µF
(X7R)
RTC
backup memory
External LDO
3.0V to 3.3V
USB SM and
transceiver
USB-VSB 5V
VDDUSB
24
ATR0630 [Preliminary]
4920B–GPS–06/06
ATR0630 [Preliminary]
5. Crystals
The ATR0630 only needs a GPS crystal (XTAL), but supports also TCXOs. The reference fre-
quency is 23.104 MHz. By connecting an optional RTC crystal, different power modes are
available. The reference frequency is 32.768 kHz.
5.1
GPS XTAL
Figure 5-1. Application Example Using a GPS Crystal with ESR Typically = 12Ω
(See Table 5-1 on page 27)
A1
XTO
B3
NXTO
47 pF
A2
B2
27
X
68 pF
47 pF
NX
X1
Figure 5-2. Application Example Using a GPS Crystal With ESR Typically ≠ 12Ω
(See Table 5-2 on page 27)
A1
XTO
B3
NXTO
47 pF
A2
B2
R1
X
68 pF
47 pF
NX
X1
Note:
The external series resistor R1 has to be selected depending on the typical value of the crystal
ESR. Refer to the application note “ATR0601: Crystal and TXCO Selection”.
25
4920B–GPS–06/06
Figure 5-3. Equivalent Application Examples Using a GPS TCXO (See Table 5-3 on page 27)
22 pF
A1
XTO
12 pF
B3
TCXO
NXTO
4.7 pF
A2
X
Do not
connect
B2
NX
A1
B3
12 pF
XTO
22 pF
TCXO
NXTO
4.7 pF
A2
B2
X
Do not
connect
NX
Figure 5-4. Application Example Using an External Reference Frequency and Balanced
Inputs (See Table 5-4 on page 27)
1:1
A1
XTO
Vin
B3
NXTO
A2
X
Do not
connect
B2
NX
26
ATR0630 [Preliminary]
4920B–GPS–06/06
ATR0630 [Preliminary]
Table 5-1.
Specification of GPS Crystals Appropriate for the Application Example Shown in
Figure 5-1 on page 25
Parameter
Comment
Min
Typ
Max
Units
Frequency Characteristics
Nominal frequency referenced to
25°C
Fundamental frequency
23.104
MHz
Calibration tolerance
Frequency deviation
Temperature range
Electrical
Frequency at 23°C ±2°C
7.0
15.0
±ppm
±ppm
°C
Over operating temperature range
Operating temperature range
–40.0
18.5
7
+85.0
Load capacitance (CL)
19.5
23
pF
Equivalent Series Resistance (ESR)
Fundamental
Specification
12
Ω
Table 5-2.
Parameter
Specification of GPS Crystals Appropriate for the Application Example Shown in
Figure 5-2 on page 25
Comment
Min
Typ
Max
Units
Equivalent Series Resistance (ESR)
Fundamental Specification
7
40
Ω
Note:
All other parameters as specified in Table 5-1.
Table 5-3.
Specification of GPS TCXOs Appropriate for the Application Example Shown in
Figure 5-3 on page 26
Parameter
Comment
Min
Typ
Max
Units
Frequency Characteristics
Nominal frequency referenced to
25°C
Nominal Frequency
23.104
MHz
Frequency deviation
Temperature range
Electrical
Over operating temperature range
Operating temperature range
2.0
±ppm
°C
–40.0
+85.0
Output waveform
DC coupled clipped sine wave
Operating range
Output voltage
(peak-to-peak)
0.8
10
1.5
V
Output load capacitance
Tolerable load capacitance
pF
Table 5-4.
Specification of an External Reference Signal for the Application Example Shown
in Figure 5-4 on page 26
Parameter
Comment
Min
Typ
23.104
0.9
Max
Units
MHz
V
Signal Characteristics
Nominal Frequency
Waveform
Sine wave or clipped sine wave
Voltage peak-to-peak
Amplitude
0.6
1.2
27
4920B–GPS–06/06
5.2
RTC Oscillator
Figure 5-5. Crystal Connection
ATR0630 internal
XT_IN
32 kHz
Crystal
32.768 kHz
50 ppm
Oscillator
32.768 kHz clock
RTC
XT_OUT
C
C
C = 2 × Cload, Cload can be derived from the crystal datasheet. Maximum value for C is 25 pF
28
ATR0630 [Preliminary]
4920B–GPS–06/06
ATR0630 [Preliminary]
6. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Pins
Symbol
Top
Min
–40
Max
+85
Unit
°C
°C
V
Operating temperature
Storage temperature
Analog supply voltage
Digital supply voltage RF
DC supply voltage core
Tstg
–55
–0.3
–0.3
–0.3
+125
+3.7
+3.7
+1.95
VCC1, VCC2, VBP
VDIG
VCC
VDIG
V
VDD18
VDD18
V
DC supply voltage VDDIO
domain
VDDIO
VDDIO
–0.3
+3.6
V
DC supply voltage USB
DC supply voltage LDO18
DC supply voltage LDOBAT
DC supply voltage VBAT
VDD_USB
LDO_IN
VDD_USB
LDO_IN
–0.3
–0.3
–0.3
–0.3
+3.6
+3.6
+3.6
+3.6
V
V
V
V
LDOBAT_IN
VBAT
LDOBAT_IN
VBAT
P0, P15, P30, XT_IN,
TMS, TCK, TDI, NTRST,
DBG_EN, LDO_EN,
NRESET
Digital input voltage
–0.3
+1.95
V
Digital input voltage
Digital input voltage
USB_DM, USB_DP
–0.3
–0.3
+3.6
+5.0
V
V
P1, P2, P8, P9, P12 to
P14, P16 to P27, P29, P31
Note:
Minimum/maximum limits are at +25°C ambient temperature, unless otherwise specified.
7. Handling
The ATR0630 is an ESD-sensitive device. The current ESD values are to be defined. Observe
proper precautions for handling.
29
4920B–GPS–06/06
8. Operating Range
Parameters
Pins
VCC1, VCC2, VBP
VDIG
Symbol
VCC
Min
2.70
1.65
1.65
Typ
Max
3.30
1.95
1.95
Unit
V
Analog supply voltage RF
Digital supply voltage RF
Digital supply voltage core
VDIG
1.8
1.8
V
VDD18
VDD18
V
Digital supply voltage VDDIO
domain(1)
VDDIO
VDDIO
1.65
1.8/3.3
3.3
3.6
V
Digital supply voltage USB(2)
DC supply voltage LDO18
DC supply voltage LDOBAT
DC Supply voltage VBAT
Supply voltage difference
VDD_USB
LDO_IN
VDD_USB
LDO_IN
3.0
2.3
2.3
1.5
3.6
3.6
3.6
3.6
V
V
V
V
LDOBAT_IN
VBAT
LDOBAT_IN
VBAT
V∆
≥ 0.80
V
(V∆ = VCC – VDIG
)
Temperature range
Temp
fRF
–40
+85
°C
Input frequency
1575.42
23.104
32.768
MHz
MHz
KHz
Reference frequency GPS XTAL
Reference frequency RTC
fXTO
fXTC
Notes: 1. VDDIO is the supply voltage for the following GPIO-pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29
2. Values defined for operating USB Interface. Otherwise VDD_USB may be connected to ground.
9. Electrical Characteristics
If no additional information is given in column Test Conditions, the values apply to temperature range from –40°C to +85°C.
No.
1
Parameters
Test Conditions
Pin
Symbol
Min
Typ
Max
Unit
RF Front-end
Output frequency
1.1
fXTO = 23.104 MHz
fRF = 1575.42 MHz
C3
fIF
96.764
MHz
Input impedance
(balanced)
1.2
D1, C1
Z11
10 – j80
Ω
1.3
1.4
1.5
1.6
2
Mixer conversion gain
Mixer noise figure (SSB)
Maximum total gain
Total noise figure (SSB)
VGA/AGC
C3
C3
GMIX
NFMIX
Gmax_tot
NFtot
10
6
dB
dB
dB
dB
VAGCO = 2.2V
90
6.8
2.1
2.2
Minimum gain
VAGCO = 1.0V
VAGCO = 2.2V
GVGA,min
GVGA,max
0
dB
dB
Maximum gain
70
Notes: 1. The LDO18 is a built in low dropout voltage regulator, which can be used if the host system does not provide the core volt-
age VDD18.
2. The LDOBAT is a built in low dropout voltage regulator, which provides the supply voltage VBAT18 for the RTC, backup
SRAM, P9, P13, P22, P31, NSLEEP and NSHDN. The LDOBAT voltage regulator switches in battery mode if LDOBAT_IN
falls below 1.5V.
3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT.
4. No external load allowed.
5. If no current is caused by outputs (pad output current as well as current across internal pull-up resistors)
30
ATR0630 [Preliminary]
4920B–GPS–06/06
ATR0630 [Preliminary]
9. Electrical Characteristics (Continued)
If no additional information is given in column Test Conditions, the values apply to temperature range from –40°C to +85°C.
No.
Parameters
Test Conditions
VAGCO = 2.2V
VAGCO = 1.0V
Cext = open
Pin
Symbol
NVGA,min
NVGA,max
f3dB_AGC
f3dB_AGC
Min
Typ
6.6
150
250
33
Max
Unit
dB/V
dB/V
kHz
2.3
Control-voltage sensitivity
2.4
2.5
AGC cut-off frequency
AGC cut-off frequency
A4
A4
Cext = 100 pF
kHz
Gain-control output
voltage
2.6
3
A4
VAGCO
0.9
2.3
V
Reference Oscillator
XTO phase noise at
100Hz
3.1
With specified crystal
A8
A8
Pn100
Pn1k
–80
dBc/Hz
dBc/Hz
3.2
4
XTO phase noise at 1 kHz With specified crystal
–100
PMSS
4.1
4.2
5
Voltage level power-on
Voltage level power-off
LDO18(1)
F4, G4, H4
F4, G4, H4
VPU,on
VPU,off
1.3
V
V
0.5
5.1
5.2
5.3
Output voltage
Output current
LDO_OUT
LDO_OUT
1.65
1.8
1.95
80
V
mA
µA
Current consumption
After startup, no load
80
Standby mode
(LDO_EN = 0)
5.4
Current consumption
1
5
µA
6
LDOBAT(2)
6.1
6.2
Output voltage(3)
Output current(4)
VBAT18
VBAT18
1.65
1.8
1.95
1.5
V
mA
After startup (sleep/backup
mode), at room
temperature
Current consumption
LDOBAT_IN(5)
6.3
6.4
6.5
15
10
µA
µA
After startup (backup mode
and LDOBAT_IN = 0V), at
room temperature
Current consumption
VBAT
After startup (normal
mode), at room
temperature
Current consumption
1.5
mA
7
Core
7.1
7.2
DC supply voltage VDD18
DC supply voltage VDDIO
VO,18
VO,IO
0
0
VDD18
VDDIO
V
V
Low-level input voltage
VDD18 domain
0.3 ×
VDD18
7.3
VDD18 = 1.65V to 1.95V
VIL,18
–0.3
V
Notes: 1. The LDO18 is a built in low dropout voltage regulator, which can be used if the host system does not provide the core volt-
age VDD18.
2. The LDOBAT is a built in low dropout voltage regulator, which provides the supply voltage VBAT18 for the RTC, backup
SRAM, P9, P13, P22, P31, NSLEEP and NSHDN. The LDOBAT voltage regulator switches in battery mode if LDOBAT_IN
falls below 1.5V.
3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT.
4. No external load allowed.
5. If no current is caused by outputs (pad output current as well as current across internal pull-up resistors)
31
4920B–GPS–06/06
9. Electrical Characteristics (Continued)
If no additional information is given in column Test Conditions, the values apply to temperature range from –40°C to +85°C.
No.
Parameters
Test Conditions
Pin
Symbol
Min
Typ
Max
Unit
High-level input voltage
VDD18 domain
0.7 ×
VDD18
VDD18 +
0.3
7.4
VDD18 = 1.65V to 1.95V
VIH,18
V
Schmitt trigger threshold
rising
0.7 ×
VDD18
7.5
VDD18 = 1.65V to 1.95V
VDD18 = 1.65V to 1.95V
CLK23
Vth+,CLK23
V
Schmitt trigger threshold
falling
0.3 ×
VDD18
7.6
7.7
7.8
CLK23
CLK23
Vth-,CLK23
V
V
V
Schmitt trigger hysteresis VDD18 = 1.65V to 1.95V
Vhyst,CLK23
0.3
0.55
1.3
Schmitt trigger threshold
VDD18 = 1.65V to 1.95V
rising
NRESET Vth+,NRESET
NRESET Vth-,NRESET
VIL,IO
0.8
Schmitt trigger threshold
VDD18 = 1.65V to 1.95V
falling
7.9
0.46
–0.3
1.46
–0.3
1.46
–0.3
0.77
+0.41
5.0
V
V
V
V
V
V
Low-level input voltage
VDDIO = 1.65V to 3.6V
VDDIO domain
7.10
7.11
7.12
7.13
7.14
High-level input voltage
VDDIO = 1.65V to 3.6V
VDDIO domain
VIH,IO
Low-level input voltage
VBAT18 = 1.65V to 1.95V
VBAT18 domain
A11, B10,
VIL,BAT
+0.41
5.0
C10, D10
High-level input voltage
VBAT18 = 1.65V to 1.95V
VBAT18 domain
A11, B10,
VIH,BAT
C10, D10
Low-level input voltage
VDD_USB = 3.0V to 3.6V
USB
C9, D9
C9, D9
VIL,USB
+0.8
VDD_USB = 3.0V to 3.6V
High-level input voltage
7.15
39Ωsource resistance +
USB
VIH,USB
2.0
3.6
0.4
V
27Ωexternal series resistor
Low-level output voltage
VDD18 domain
IOL = 1.5 mA,
VDD18 = 1.65V
7.16
7.17
7.18
7.19
7.20
7.21
VOL,18
VOH,18
VOL,IO
V
V
V
V
V
V
High-level output voltage IOH = –1.5 mA,
VDD18 domain
VDD18 –
0.45
VDD18 = 1.65V
Low-level output voltage
VDDIO domain
IOL = 1.5 mA,
VDDIO = 3.0V
0.4
0.4
High-level output voltage
VDDIO domain
I
OH = –1.5 mA,
VDDIO –
0.5
VOH,IO
VOL,BAT
VOH,BAT
VDDIO = 3.0V
Low-level output voltage
VBAT18 domain
P9, P13,
P22, P31
IOL = 1 mA
High-level output voltage
VBAT18 domain
P9, P13,
P22, P31
IOH = –1 mA
1.2
Notes: 1. The LDO18 is a built in low dropout voltage regulator, which can be used if the host system does not provide the core volt-
age VDD18.
2. The LDOBAT is a built in low dropout voltage regulator, which provides the supply voltage VBAT18 for the RTC, backup
SRAM, P9, P13, P22, P31, NSLEEP and NSHDN. The LDOBAT voltage regulator switches in battery mode if LDOBAT_IN
falls below 1.5V.
3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT.
4. No external load allowed.
5. If no current is caused by outputs (pad output current as well as current across internal pull-up resistors)
32
ATR0630 [Preliminary]
4920B–GPS–06/06
ATR0630 [Preliminary]
9. Electrical Characteristics (Continued)
If no additional information is given in column Test Conditions, the values apply to temperature range from –40°C to +85°C.
No.
Parameters
Test Conditions
Pin
Symbol
Min
Typ
Max
Unit
IOL = 2.2 mA,
VDD_USB = 3.0V to 3.6V,
27Ωexternal series resistor
Low-level output voltage
USB
7.22
DP, DM
VOL,USB
0.3
V
IOH = 0.2 mA,
VDD_USB = 3.0V to 3.6V,
27Ωexternal series resistor
High-level output voltage
USB
7.23
7.24
DP, DM
VOH,USB
2.8
–1
V
Input-leakage current
(standard inputs and I/Os) VIL = 0V
VDD18 = 1.95V
ILEAK
ICAP
RPU
+1
10
µA
pF
kΩ
7.25 Input capacitance
Input pull-up resistor
NRESET
7.26
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
A7
0.7
7
1.8
Input pull-up resistors
7.27
G9, H10,
G10
RPU
RPU
RPD
RPD
18
235
18
kΩ
kΩ
kΩ
kΩ
TCK, TDI, TMS
Input pull-up resistors P9,
P13, P22, P31
A11, B10,
C10, D10
7.28
100
7
Input pull-down resistors
7.29
E8, H11
DBG_EN, NTRST, RF_ON
Input pull-down resistors
P0, P15, P30
F10, C8,
F11, G12
7.30
100
235
Configurable input pull-up
resistors P1, P2, P8, P12,
P14, P16 to P21, P23 to
7.31
–40°C to +85°C
RCPU
50
160
kΩ
P27, P29
Configurable input
pull-down resistors P1, P2,
P8, P12, P14, P16 to P21,
P23 to P27, P29
7.32
–40°C to +85°C
–40°C to +85°C
RCPD
40
160
kΩ
kΩ
Configurable input pull-up
7.33 resistor USB_DP (idle
state)
C9
RCPU
0.9
1.575
Configurable input pull-up
7.34 resistor USP_DP
(operation state)
–40°C to +85°C
–40°C to +85°C
C9
RCPU
1.425
10
3.09
500
kΩ
kΩ
Input pull-down resistors
7.35
C9, D9
RPD
USB_DP, USB_DM
Notes: 1. The LDO18 is a built in low dropout voltage regulator, which can be used if the host system does not provide the core volt-
age VDD18.
2. The LDOBAT is a built in low dropout voltage regulator, which provides the supply voltage VBAT18 for the RTC, backup
SRAM, P9, P13, P22, P31, NSLEEP and NSHDN. The LDOBAT voltage regulator switches in battery mode if LDOBAT_IN
falls below 1.5V.
3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT.
4. No external load allowed.
5. If no current is caused by outputs (pad output current as well as current across internal pull-up resistors)
33
4920B–GPS–06/06
10. Power Consumption
Mode
Conditions
Typ
0.065(1)
0.007(1)
40
Unit
Sleep
At 1.8V, no CLK23
Shutdown RTC, backup SRAM and LDOBAT
Satellite acquisition
mA
Normal
Normal tracking on 6 channels with 1 fix/s; each additional active tracking channel adds 0.5 mA
29
All channels disabled
26
Note:
1. Specified value only
11. Ordering Information
Extended Type Number
Package
MPQ
3000
1
Remarks
7 mm × 10 mm, 0.8 mm pitch, Pb-free,
RoHS-compliant
ATR0630-7KQY
ATR0630-EK1
ATR0630-DK1
BGA96
-
-
Evaluation kit/Road test kit
Design kit including design guide and PCB
Gerber files
1
34
ATR0630 [Preliminary]
4920B–GPS–06/06
ATR0630 [Preliminary]
12. Package Information
2.
Package: BGA96
Dimensions in mm
0.08
0.15
n
n
m
m
C
0.4±0.05
B A
A1 Corner
Top View
Bottom View
A1 Corner
1 2 3 4 5 6 7 8 9 10 11 12
12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
G
H
Pin A1 Laser Marking
0.8
A
8.8
10±0.05
B
technical drawings
according to DIN
specifications
0.1C
0.08 C
Drawing-No.: 6.580-5005.01-4
Issue: 2; 31.05.06
Seating plane
3.
C
Note:
1. All dimensions and tolerance conform to ASME Y 14.5M-1994
Dimension is measured at the maximum solder ball diameter, parallel to primary datum
C
2.
3.
Primary datum
and seating plane are defined by the spherical crowns of the solder balls
C
4. The surface finish of the package shall be EDM CHARMILLE #24 - #27
5. Unless otherwise specified tolerance: Decimal ±0.05, Angular ±2
5. Raw ball diameter: 0.4 mm ref.
˚
35
4920B–GPS–06/06
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4920B–GPS–06/06
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