ATR0625P1 [ATMEL]
GPS Baseband Processor SuperSense; GPS基带处理器的SuperSense
| 型号： | ATR0625P1 |
| 厂家： | 
ATMEL |
| 描述： | GPS Baseband Processor SuperSense |
| 文件： | 总12页 (文件大小：251K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• 16-channel GPS Correlator
– 8192 Search Bins with GPS Acquisition Accelerator
– Accuracy: 2.5m CEP (Stand-Alone, S/A off)
– Time to First Fix: 34s (Cold Start)
– Acquisition Sensitivity: –142 dBm (Cold Start)
– Tracking Sensitivity: –158 dBm
• Utilizes the ARM7TDMI® ARM® Thumb® Processor Core
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
GPS Baseband
Processor
SuperSense
– EmbeddedICE™ (In-circuit Emulator)
• 128 Kbyte Internal RAM
• 384 Kbyte Internal ROM, Firmware Version V5.0
• Position Technology Provided by µ-blox
• 6-channel Peripheral Data Controller (PDC)
• 8-level Priority, Individually Maskable, Vectored Interrupt Controller
– 2 External Interrupts
ATR0625P1
Automotive
• 24 User-programmable I/O Lines
• 1 USB Device Port
– Universal Serial Bus (USB) V2.0 Full-speed Device
– Embedded USB V2.0 Full-speed Transceiver
– Suspend/Resume Logic
Summary
– Ping-pong Mode for Isochronous and Bulk Endpoints
• 2 USARTs
– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART
• Master/Slave SPI Interface
– 2 Dedicated Peripheral Data Controller (PDC) Channels
– 8-bit to 16-bit Programmable Data Length
– 4 External Slave Chip Selects
• Programmable Watchdog Timer
• Advanced Power Management Controller (APMC)
– Peripherals Can Be Deactivated Individually
– Geared Master Clock to Reduce Power Consumption
– Sleep State with Disabled Master Clock
– Hibernate State with 32.768 kHz Master Clock
• Real Time Clock (RTC)
• 2.3V to 3.6V or 1.8V Core Supply Voltage
• Includes Power Supervisor
• 1.8V to 3.3V User-definable I/O Voltage for Several GPIOs with 5V Tolerance
• 4 Kbytes Battery Backup Memory
• 8 mm × 8 mm 56 Pin QFN56 Package
• RoHS-compliant, Green
NOTE: This is a summary document.
The complete document is available.
For more information, please contact
your local Atmel sales office.
4976BS–GPS–05/08
1. Description
The GPS baseband processor ATR0625P1 includes a 16-channel GPS correlator and is based
on the ARM7TDMI processor core.
This processor has a high-performance 32-bit RISC architecture and very low power consump-
tion. In addition, a large number of internally banked registers result in very fast exception
handling, making the device ideal for real-time control applications. The ATR0625P1 has two
USART and an USB device port. This port is compliant with the Universal Serial Bus (USB) V2.0
full-speed device specification.
The ATR0625P1 includes full GPS SuperSense® firmware, licensed from u-blox AG, which per-
forms the basic GPS operation, including tracking, acquisition, navigation and position data
output. For normal PVT (Position/Velocity/Time) applications, there is no need for off-chip Flash
memory or ROM.
The firmware supports e.g. the NMEA® protocol (2.1 and 2.3), a binary protocol for PVT data,
configuration and debugging, the RTCM protocol for DGPS, SBAS (WAAS, EGNOS and MSAS)
and A-GPS (aiding). It is also possible to store the configuration settings in an optional external
EEPROM.
The ATR0625P1 is manufactured using Atmel®’s high-density CMOS technology. By combining
the ARM7TDMI microcontroller core with on-chip SRAM, 16-channel GPS correlator, and a wide
range of peripheral functions on a monolithic chip, the ATR0625P1 provides a highly flexible and
cost-effective solution for GPS applications.
2
ATR0625P1
4976BS–GPS–05/08
ATR0625P1
Figure 1-1. ATR0625P1 Block Diagram
NSHDN
NSLEEP
XT_IN
XT_OUT
SIGLO0
SIGHI0
RF_ON
CLK23
P15/ANTON
P0/NANTSHORT
P14/NAADET1
P25/NAADET0
P20/TIMEPULSE
P29/GPSMODE12
P27/GPSMODE11
P26/GPSMODE10
P24/GPSMODE8
P23/GPSMODE7
P19/GPSMODE6
P17/GPSMODE5
P13/GPSMODE3
P12/GPSMODE2
P1/GPSMODE0
P21/TXD2
P22/RXD2
P9/EXTINT0
P2/BOOT_MODE
P30/AGCOUT0
P8/STATUSLED
P18/TXD1
P31/RXD1
USB_DP
USB_DM
P16/NEEPROM
DBG_EN
NTRST
TDI
TDO
TCK
TMS
VBAT18
VBAT
LDOBAT_IN
LDO_OUT
LDO_IN
NRESET
LDO_EN
3
4976BS–GPS–05/08
2. Architectural Overview
2.1
Description
The ATR0625P1 architecture consists of two main buses, the Advanced System Bus (ASB) and
the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It inter-
faces the processor with the on-chip 32-bit memories. The APB is designed for accesses to
on-chip peripherals and is optimized for low power consumption. The AMBA™ Bridge provides
an interface between the ASB and the APB.
An on-chip Peripheral Data Controller (PDC2) transfers data between the on-chip USARTs/SPI
and the on-chip and off-chip memories without processor intervention. Most importantly, the
PDC2 removes the processor interrupt handling overhead and significantly reduces the number
of clock cycles required for a data transfer. It can transfer up to 64K contiguous bytes without
reprogramming the starting address. As a result, the performance of the microcontroller is
increased and the power consumption reduced.
The ATR0625P1 peripherals are designed to be easily programmable with a minimum number
of instructions. Each peripheral has a 16 Kbyte address space allocated in the upper 3 Mbyte of
the 4 Gbyte address space. (Except for the interrupt controller, which has 4 Kbyte address
space.) The peripheral base address is the lowest address of its memory space. The peripheral
register set is composed of control, mode, data, status, and interrupt registers.
To maximize the efficiency of bit manipulation, frequently written registers are mapped into three
memory locations. The first address is used to set the individual register bits, the second resets
the bits, and the third address reads the value stored in the register. A bit can be set or reset by
writing a “1” to the corresponding position at the appropriate address. Writing a “0” has no effect.
Individual bits can thus be modified without having to use costly read-modify-write and complex
bit-manipulation instructions.
All of the external signals of the on-chip peripherals are under the control of the Parallel I/O
(PIO2) Controller. The PIO2 Controller can be programmed to insert an input filter on each pin or
generate an interrupt on a signal change. After reset, the user must carefully program the PIO2
Controller in order to define which peripheral signals are connected with off-chip logic.
The ARM7TDMI processor operates in little-endian mode on the ATR0625P1 GPS Baseband.
The processor's internal architecture and the ARM and Thumb instruction sets are described in
the ARM7TDMI datasheet.
The ARM standard In-Circuit Emulator (ICE) debug interface is supported via the JTAG/ICE port
of the ATR0625P1.
For features of the ROM firmware (SuperSense), refer to the software documentation available
from u-blox AG, Switzerland.
4
ATR0625P1
4976BS–GPS–05/08
ATR0625P1
3. Pin Configuration
3.1
Pinout
Figure 3-1. Pinout QFN56 (Top View)
42
29
43
56
28
15
ATR0625P1
1
14
Table 3-1.
Pin Name
ATR0625P1 Pinout
PIO Bank A
O
Pull Resistor
QFN56
Pin Type
(Reset Value)(1)
Firmware Label
I
CLK23
DBG_EN
GND
37
IN
IN
8
(2)
PD
IN
LDOBAT_IN
LDO_EN
LDO_IN
LDO_OUT
NRESET
NSHDN
NSLEEP
NTRST
P0
21
25
20
19
41
26
24
13
40
47
46
48
29
49
32
IN
IN
IN
OUT
I/O
OUT
OUT
IN
Open Drain PU
PD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PD
NANTSHORT
GPSMODE0
BOOT_MODE
STATUSLED
EXTINT0
P1
Configurable (PD)
Configurable (PD)
Configurable (PD)
PU to VBAT18
Configurable (PU)
PU to VBAT18
AGCOUT1
P2
“0”
“0”
P8
P9
EXTINT0
EXTINT1
P12
GPSMODE2
GPSMODE3
NPCS2
P13
Notes: 1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset
2. Ground plane
3. VBAT18 represent the internal power supply of the backup power domain.
4. VDDIO is the supply voltage for the following GPIO-pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29.
5. VDD_USB is the supply voltage for following the USB-pins: USB_DM and USB_DP. For operation of the USB interface, sup-
ply of 3.0V to 3.6V is required.
6. This pin is not connected
5
4976BS–GPS–05/08
Table 3-1.
Pin Name
ATR0625P1 Pinout (Continued)
PIO Bank A
Pull Resistor
QFN56
1
Pin Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
OUT
IN
(Reset Value)(1)
Configurable (PD)
PD
Firmware Label
NAADET1
ANTON
I
O
P14
P15
“0”
17
6
P16
Configurable (PU)
Configurable (PD)
Configurable (PU)
Configurable (PU)
Configurable (PD)
Configurable (PU)
PU to VBAT18
Configurable (PU)
Configurable (PU)
Configurable (PD)
Configurable (PU)
Configurable (PU)
Configurable (PU)
PD
NEEPROM
GPSMODE5
TXD1
SIGHI1
SCK1
P17
2
SCK1
TXD1
P18
45
53
4
P19
GPSMODE6
TIMEPULSE
TXD2
SIGLO1
SCK2
P20
SCK2
TXD2
P21
52
30
3
P22
RXD2
RXD2
SCK
P23
GPSMODE7
GPSMODE8
NAADET0
GPSMODE10
GPSMODE11
GPSMODE12
AGCOUT0
RXD1
SCK
P24
5
MOSI
MISO
NSS
MOSI
P25
55
44
54
50
16
31
15
38
39
9
MISO
P26
NPCS0
NPCS1
NPCS3
P27
P29
P30
AGCOUT0
P31
PU to VBAT18
PD
RXD1
RF_ON
SIGHI0
SIGLO0
TCK
IN
IN
PU
PU
TDI
10
11
12
34
35
22
23
7, 14
18, 36
51
43, 56
33
28
27
42
IN
TDO
OUT
IN
TMS
PU
USB_DM
USB_DP
VBAT
VBAT18(3)
VDD18
VDD18
VDD18
VDDIO(4)
VDD_USB(5)
XT_IN
XT_OUT
NC(6)
I/O
I/O
IN
OUT
IN
IN
IN
IN
IN
IN
OUT
Notes: 1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset
2. Ground plane
3. VBAT18 represent the internal power supply of the backup power domain.
4. VDDIO is the supply voltage for the following GPIO-pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29.
5. VDD_USB is the supply voltage for following the USB-pins: USB_DM and USB_DP. For operation of the USB interface, sup-
ply of 3.0V to 3.6V is required.
6. This pin is not connected
6
ATR0625P1
4976BS–GPS–05/08
ATR0625P1
3.2
Signal Description
Table 3-2.
Module
ATR0625P1 Signal Description
Name
Function
Type
Active Level Comment
PIO-controlled after reset,
internal pull-down resistor
EBI
BOOT_MODE
Boot Mode Input
Input
–
TXD1 to TXD2
RXD1 to RXD2
SCK1 to SCK2
USB_DP
Transmit Data Output
Receive Data Input
External Synchronous Serial Clock
USB Data (D+)
Output
Input
I/O
–
–
–
–
–
–
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
USART
I/O
USB
USB_DM
USB Data (D-)
I/O
APMC
RF_ON
Output
Interface to ATR0601
High/
Low/
Edge
AIC
EXTINT0-1
External Interrupt Request
Automatic Gain Control
Input
PIO-controlled after reset
Interface to ATR0601
PIO-controlled after reset
AGC
AGCOUT0-1
Output
–
NSLEEP
NSHDN
XT_IN
Sleep Output
Output
Output
Input
Output
I/O
Low
Low
–
Interface to ATR0601
Connect to pin LDO_EN
RTC oscillator
Shutdown Output
Oscillator Input
Oscillator Output
SPI Clock
RTC
XT_OUT
SCK
–
RTC oscillator
–
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
Input after reset
MOSI
Master Out Slave In
Master In Slave Out
Slave Select
I/O
–
SPI
PIO
MISO
I/O
–
NSS/NPCS0
I/O
Low
Low
–
NPCS1 to NPCS3 Slave Select
Output
I/O
P0 to P31
SIGHI0
Programmable I/O Port
Digital IF
Input
Input
Input
Input
Output
Input
Output
Input
Output
–
Interface to ATR0601
Interface to ATR0601
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
SIGLO0
Digital IF
–
GPS
SIGHI1
Digital IF
–
SIGLO1
Digital IF
–
TIMEPULSE
GPSMODE0-12
STATUSLED
NEEPROM
ANTON
GPS synchronized time pulse
GPS Mode
–
–
Status LED
–
Enable EEPROM Support
Active antenna power on Output
Low
–
CONFIG
Active antenna short circuit
detection Input
NANTSHORT
Input
Input
Low
Low
PIO-controlled after reset
PIO-controlled after reset
NAADET0-1
Active antenna detection Input
Note:
1. The USB transceiver is disabled if VDD_USB < 2.0V. In this case the pins USB_DM and USB_DP are connected to GND
(internal pull-down resistors). The USB transceiver is enabled if VDD_USB is within 3.0V and 3.6V.
7
4976BS–GPS–05/08
Table 3-2.
Module
ATR0625P1 Signal Description (Continued)
Name
TMS
Function
Type
Input
Input
Output
Input
Input
Input
Active Level Comment
Test Mode Select
Test Data In
–
–
Internal pull-up resistor
TDI
Internal pull-up resistor
TDO
Test Data Out
Test Clock
–
JTAG/ICE
TCK
–
Internal pull-up resistor
Internal pull-down resistor
Internal pull-down resistor
NTRST
DBG_EN
Test Reset Input
Debug Enable
Low
High
Interface to ATR0601,
Schmitt trigger input
CLOCK
RESET
CLK23
Clock Input
Reset Input
Input
I/O
–
Open drain with internal pull-up
resistor
NRESET
Low
VDD18
VDDIO
Power
Power
–
–
Core voltage 1.8V
Variable IO voltage 1.65V to 3.6V
POWER
USB voltage 0 to 2.0V or
3.0V to 3.6V(1)
VDD_USB
Power
–
GND
LDOBAT_IN
VBAT
Power
Power
Power
Out
–
–
–
–
–
–
–
Ground
2.3V to 3.6V
LDOBAT
LDO18
1.5V to 3.6V
VBAT18
LDO_IN
LDO_OUT
LDO_EN
1.8V backup voltage
2.3V to 3.6V
LDO In
Power
Power
Input
LDO Out
LDO Enable
1.8V core voltage, max. 80 mA
Note:
1. The USB transceiver is disabled if VDD_USB < 2.0V. In this case the pins USB_DM and USB_DP are connected to GND
(internal pull-down resistors). The USB transceiver is enabled if VDD_USB is within 3.0V and 3.6V.
8
ATR0625P1
4976BS–GPS–05/08
ATR0625P1
3.3
External Connections for a Working GPS System
Figure 3-2. Example of an External Connection
ATR0625P1
ATR0601
SIGH
SIGL
SIGHI
SIGLO
CLK23
RF_ON
NSLEEP
SC
PURF
PUXTO
P8
STATUS LED
P20
TIMEPULSE
NC
NRESET
USB_DM
USB_DP
Optional
USB
see Table 3-15
see Table 3-15
see Table 3-15
see Table 3-15
see Table 3-15
see Table 3-15
P0 - 2
P9
P31
P18
Optional
USART 1
P12 - 17
P19
P22
P21
Optional
USART 2
P23 - 27
P29 - 30
NC
NC
NC
NC
NC
TMS
TCK
XT_IN
32.368 kHz
(see RTC)
TDI
NTRST
TDO
XT_OUT
NC
DBG_EN
GND
GND
NSHDN
LDO_EN
LDO_OUT
VDD18
+3V
+3V
(see Power Supply)
(see Power Supply)
LDO_IN
LDOBAT_IN
VDDIO
+3V
(see Power Supply)
VBAT18
VBAT
VDD_USB
+3V
(see Power Supply)
GND
NC: Not connected
9
4976BS–GPS–05/08
4. Ordering Information
Extended Type Number
ATR0625P1-PYQW
ATR0625-EK1
Package
MPQ
2000
1
Remarks
8 mm × 8 mm, 0.50 mm pitch,
RoHS-compliant, green, automotive type
QFN56
-
-
Evaluation kit/Road test kit
Development kit including example design
information
ATR0625-DK1
1
5. Package QFN56
Package: QFN56 8 x 8
Exposed pad 6.5 x 6.5
8
Dimensions in mm
0.9 max.
Not indicated tolerances ±0.05
+0
6.5
0.05-0.05
43
56
56
1
Pin 1 ID
1
42
29
technical drawings
according to DIN
specifications
14
15
14
28
0.5 nom.
Drawing-No.: 6.543-5121.01-4
Issue: 1; 02.09.05
Moisture sensitivity level (MSL) = 3
10
ATR0625P1
4976BS–GPS–05/08
ATR0625P1
6. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, and not to this document.
Revision No.
History
4976BS-GPS-05/08
• Table 3-1 “ATR0625P1 Pinout” on page 5: Pin type of pin CLK23 changed.
11
4976BS–GPS–05/08
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4976BS–GPS–05/08
相关型号：
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