AT90S4433-8AC [ATMEL]
8-bit Microcontroller with 2K/4K bytes In-System Programmable Flash; 8 -bit微控制器2K / 4K字节的系统内可编程闪存型号: | AT90S4433-8AC |
厂家: | ATMEL |
描述: | 8-bit Microcontroller with 2K/4K bytes In-System Programmable Flash |
文件: | 总13页 (文件大小:309K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Features
• High-performance and Low-power AVR® 8-bit RISC Architecture
– 118 Powerful Instructions - Most Single Cycle Execution
– 32 x 8 General Purpose Working Registers
– Up to 8 MIPS Throughput at 8 MHz
• Data and Nonvolatile Program Memory
– 2K/4K Bytes of In-System Programmable Flash
Endurance 1,000 Write/Erase Cycles
– 128 Bytes of SRAM
– 128/256 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
• Peripheral Features
8-bit
Microcontroller
with 2K/4K bytes
In-System
– One 8-bit Timer/Counter with Separate Prescaler
– Expanded 16-bit Timer/Counter with Separate Prescaler,
Compare, Capture Modes and 8-, 9- or 10-bit PWM
– On-chip Analog Comparator
– Programmable Watchdog Timer with Separate On-chip Oscillator
– Programmable UART
– 6-channel, 10-bit ADC
Programmable
Flash
– Master/Slave SPI Serial Interface
• Special Microcontroller Features
– Brown-Out Reset Circuit
– Enhanced Power-on Reset Circuit
– Low-Power Idle and Power Down Modes
– External and Internal Interrupt Sources
• Specifications
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
• Power Consumption at 4 MHz, 3V, 25°C
– Active: 3.4 mA
AT90S2333
AT90LS2333
AT90S4433
AT90LS4433
– Idle Mode: 1.4 mA
– Power Down Mode: <1 µA
• I/O and Packages
– 20 Programmable I/O Lines
– 28-pin PDIP and 32-pin TQFP
• Operating Voltage
Preliminary
– 2.7V - 6.0V (AT90LS2333 and AT90LS4433)
– 4.0V - 6.0V (AT90S2333 and AT90S4433)
• Speed Grades
– 0 - 4 MHz (AT90LS2333 and AT90LS4433)
– 0 - 8 MHz (AT90S2333 and AT90S4433)
Pin Configurations
TQFP Top View
PDIP
RESET
(RXD) PD0
(TXD) PD1
(INT0) PD2
(INT1) PD3
(T0) PD4
VCC
1
2
3
4
5
6
7
8
9
28 PC5 (ADC5)
27 PC4 (ADC4)
26 PC3 (ADC3)
25 PC2 (ADC2)
24 PC1 (ADC1)
23 PC0 (ADC0)
22 AGND
(INT1) PD3
(T0) PD4
NC
1
2
3
4
5
6
7
8
24 PC1 (ADC1)
23 PC0 (ADC0)
22 NC
VCC
21 AGND
20 AREF
GND
21 AREF
GND
XTAL1
20 AVCC
NC
19 NC
XTAL2 10
(T1) PD5 11
19 PB5 (SCK)
18 PB4 (MISO)
17 PB3 (MOSI)
16 PB2 (SS)
15 PB1 (OC1)
XTAL1
XTAL2
18 AVCC
17 PB5 (SCK)
(AIN0) PD6 12
(AIN1) PD7 13
(ICP) PB0 14
Rev. 1042DS–04/99
Note: This is a summary document. For the complete 103 page
document, please visit our Web site at www.atmel.com or e-mail
at literature@atmel.com and request literature #1042D.
Description
The AT90S2333/4433 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing pow-
erful instructions in a single clock cycle, the AT90S2333/4433 achieves throughputs approaching 1 MIPS per MHz allowing
the system designer to optimize power consumption versus processing speed.
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly
connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times
faster than conventional CISC microcontrollers.
The AT90S2333/4433 provides the following features: 2K/4K bytes of In-System Programmable Flash, 128/256 bytes
EEPROM, 128 bytes SRAM, 20 general purpose I/O lines, 32 general purpose working registers, two flexible
timer/counters with compare modes, internal and external interrupts, a programmable serial UART, 6-channel, 10-bit ADC,
programmable Watchdog Timer with internal oscillator, an SPI serial port and two software selectable power saving modes.
The Idle mode stops the CPU while allowing the SRAM, timer/counters, SPI port and interrupt system to continue function-
ing. The Power Down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the
next interrupt or hardware reset.
The device is manufactured using Atmel’s high density nonvolatile memory technology. The on-chip Flash program mem-
ory can be reprogrammed in-system through an SPI serial interface or by a conventional nonvolatile memory programmer.
By combining a RISC 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT90S2333/4433 is a
powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.
The AT90S2333/4433 AVR is supported with a full suite of program and system development tools including: C compilers,
macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
Table 1. Comparison Table
Device
Flash
2K
EEPROM
128B
SRAM
128B
128B
128B
128B
Voltage Range
4.0V - 6.0V
2.7V - 6.0V
4.0V - 6.0V
2.7V - 6.0V
Frequency
0 - 8 MHz
0 - 4 MHz
0 - 8 MHz
0 - 4 MHz
AT90S2333
AT90LS2333
AT90S4433
AT90LS4433
2K
128B
4K
256B
4K
256B
AT90S/LS2333 and AT90S/LS4433
2
AT90S/LS2333 and AT90S/LS4433
Block Diagram
Figure 1. The AT90S2333/4433 Block Diagram
PC0 - PC5
VCC
GND
PORTC DRIVERS
DATA REGISTER
PORTC
DATA DIR.
REG. PORTC
8-BIT DATA BUS
AVCC
ANALOG MUX
ADC
AGND
AREF
XTAL1
XTAL2
INTERNAL
OSCILLATOR
OSCILLATOR
PROGRAM
COUNTER
STACK
POINTER
WATCHDOG
TIMER
TIMING AND
CONTROL
RESET
PROGRAM
FLASH
MCU CONTROL
REGISTER
SRAM
INSTRUCTION
REGISTER
GENERAL
PURPOSE
REGISTERS
TIMER/
COUNTERS
X
Y
Z
INSTRUCTION
DECODER
INTERRUPT
UNIT
CONTROL
LINES
ALU
EEPROM
STATUS
REGISTER
PROGRAMMING
LOGIC
SPI
UART
DATA REGISTER
PORTB
DATA DIR.
REG. PORTB
DATA REGISTER
PORTD
DATA DIR.
REG. PORTD
ANALOG
COMPARATOR
PORTB DRIVERS
PORTD DRIVERS
PB0 - PB5
PD0 - PD7
3
Pin Descriptions
VCC
Supply voltage
GND
Ground
Port B (PB5..PB0)
Port B is a 6-bit bi-directional I/O port with internal pullup resistors. The Port B output buffers can sink 20 mA. As inputs,
Port B pins that are externally pulled low will source current if the pull-up resistors are activated.
Port B also serves the functions of various special features of the AT90S2333/4433.
The port B pins are tristated when a reset condition becomes active, even if the clock is not running.
Port C (PC5..PC0)
Port C is a 6-bit bi-directional I/O port with internal pullup resistors. The Port C output buffers can sink 20 mA. As inputs,
Port C pins that are externally pulled low will source current if the pull-up resistors are activated. Port C also serves as the
analog inputs to the A/D Converter.
The port C pins are tristated when a reset condition becomes active, even if the clock is not running.
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output buffers can sink 20 mA. As inputs,
Port D pins that are externally pulled low will source current if the pull-up resistors are activated.
Port D also serves the functions of various special features of the AT90S2333/4433.
The port D pins are tristated when a reset condition becomes active, even if the clock is not running.
RESET
Reset input. An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate
a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier
AVCC
This is the supply voltage pin for the A/D Converter. It should be externally connected to VCC via a low-pass filter. See
Datasheet for details on operation of the ADC.
AREF
This is the analog reference input for the A/D Converter. For ADC operations, a voltage in the range 2.7V to AVCC must be
applied to this pin.
AGND
If the board has a separate analog ground plane, this pin should be connected to this ground plane. Otherwise, connect to
GND.
AT90S/LS2333 and AT90S/LS4433
4
AT90S/LS2333 and AT90S/LS4433
Architectural Overview
The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access
time. This means that during one single clock cycle, one Arithmetic Logic Unit (ALU) operation is executed. Two operands
are output from the register file, the operation is executed, and the result is stored back in the register file - in one clock
cycle.
Six of the 32 registers can be used as three 16-bits indirect address register pointers for Data Space addressing - enabling
efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table
look up function. These added function registers are the 16-bits X-register, Y-register and Z-register.
The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register
operations are also executed in the ALU. Figure 2 shows the AT90S2333/4433 AVR RISC microcontroller architecture.
In addition to the register operation, the conventional memory addressing modes can be used on the register file as well.
This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing
them to be accessed as though they were ordinary memory locations.
Figure 2. The AT90S2333/4433 AVR RISC Architecture
AVR AT90S2333/4433 Architecture
Data Bus 8-bit
Program
Counter
Status
and Control
Interrupt
Unit
1K/2K X 16
Program
Memory
SPI
Unit
32 x 8
General
Purpose
Registrers
Instruction
Register
Serial
UART
Instruction
Decoder
8-bit
Timer/Counter
ALU
Control Lines
16-bit
Timer/Counter
with PWM
128 x 8
Data
SRAM
Watchdog
Timer
Analog to Digital
Converter
128/256 x 8
EEPROM
20
I/O Lines
Analog
Comparator
5
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, A/D-
converters, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following
those of the register file, $20 - $5F.
The AVR uses a Harvard architecture concept - with separate memories and buses for program and data. The program
memory is executed with a two stage pipeline. While one instruction is being executed, the next instruction is pre-fetched
from the program memory. This concept enables instructions to be executed in every clock cycle.
The program memory is In-System Programmable Flash memory.
With the relative jump and call instructions, the whole 1K/2K word address space is directly accessed. Most AVR instruc-
tions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is effec-
tively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the
usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are exe-
cuted). The 8-bit stack pointer SP is read/write accessible in the I/O space.
The 128 bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR
architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
Figure 3. AT90S2333/4433 Memory Maps
Program Memory
Data Memory
$0000
$000
32 Gen. Purpose
Working Registers
$001F
$0020
64 I/O Registers
Program Flash
(1K/2K x 16)
$005F
$0060
Internal SRAM
(128 x 8)
$00DF
$3FF/ $7FF
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status
register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the pro-
gram memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the
interrupt vector address, the higher the priority.
AT90S/LS2333 and AT90S/LS4433
6
AT90S/LS2333 and AT90S/LS4433
Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
$3F ($5F)
$3E ($5E)
$3D ($5D)
$3C ($5C)
$3B ($5B)
$3A ($5A)
$39 ($59)
$38 ($58)
$37 ($57)
$36 ($56)
$35 ($55)
$34 ($54)
$33 ($53)
$32 ($52)
$31 ($51)
$30 ($50)
$2F ($4F)
$2E ($4E)
$2D ($4D)
$2C ($4C)
$2B ($4B)
$2A ($4A)
$29 ($49)
$28 ($48)
$27 ($47)
$26 ($46)
$25 ($45)
$24 ($44)
$23 ($43)
$22 ($42)
$21 ($41)
$20 ($40)
$1F ($3F)
$1E ($3E)
$1D ($3D)
$1C ($3C)
$1B ($3B)
$1A ($3A)
$19 ($39)
$18 ($38)
$17 ($37)
$16 ($36)
$15 ($35)
$14 ($34)
$13 ($33)
$12 ($32)
$11 ($31)
$10 ($30)
$0F ($2F)
$0E ($2E)
$0D ($2D)
$0C ($2C)
$0B ($2B)
$0A ($2A)
$09 ($29)
$08 ($28)
$07 ($27)
$06 ($26)
$05 ($25)
$04 ($24)
$03 ($23)
SREG
I
-
T
-
SP6
H
-
SP5
S
-
SP4
V
-
SP3
N
-
SP2
Z
-
SP1
C
-
SP0
Reserved
SP
Reserved
GIMSK
GIFR
SP7
INT1
INTF1
TOIE1
TOV1
INT0
INTF0
OCIE1
OCF1
-
-
-
-
-
-
TIMSK
-
-
-
-
TICIE1
ICF1
-
-
TOIE0
TOV0
-
-
TIFR
Reserved
Reserved
MCUCR
MCUSR
TCCR0
TCNT0
Reserved
Reserved
TCCR1A
TCCR1B
TCNT1H
TCNT1L
OCR1H
OCR1L
Reserved
Reserved
ICR1H
-
-
-
SE
-
-
SM
-
-
ISC11
WDRF
-
ISC10
BORF
CS02
ISC01
EXTRF
CS01
ISC00
PORF
CS00
-
-
Timer/Counter0 (8 Bits)
COM11
ICNC1
COM10
ICES1
-
-
-
-
-
-
PWM11
CS11
PWM10
CS10
CTC1
CS12
Timer/Counter1 - Counter Register High Byte
Timer/Counter1 - Counter Register Low Byte
Timer/Counter1 - Output Compare Register High Byte
Timer/Counter1 - Output Compare Register Low Byte
Timer/Counter1 - Input Capture Register High Byte
Timer/Counter1 - Input Capture Register Low Byte
ICR1L
Reserved
Reserved
Reserved
Reserved
WDTCR
Reserved
Reserved
EEAR
-
-
-
-
WDTOE
WDE
WDP2
WDP1
EEWE
WDP0
EERE
EEPROM Address Register
EEPROM Data Register
EEDR
EECR
-
-
-
EERIE
EEMWE
Reserved
Reserved
Reserved
PORTB
DDRB
PINB
PORTC
DDRC
PINC
PORTD
DDRD
PIND
SPDR
-
-
-
-
-
-
-
-
PORTB5
DDB5
PINB5
PORTC5
DDC5
PINC5
PORTD5
DDD5
PORTB4
DDB4
PINB4
PORTC4
DDC4
PINC4
PORTD4
DDD4
PORTB3
DDB3
PINB3
PORTC3
DDC3
PINC3
PORTD3
DDD3
PORTB2
DDB2
PINB2
PORTC2
DDC2
PINC2
PORTD2
DDD2
PORTB1
DDB1
PINB1
PORTC1
DDC1
PINC1
PORTD1
DDD1
PORTB0
DDB0
PINB0
PORTC0
DDC0
PINC0
PORTD0
DDD0
-
-
-
-
PORTD7
DDD7
PIND7
PORTD6
DDD6
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
SPI Data Register
SPSR
SPCR
UDR
UCSRA
UCSRB
UBRR
SPIF
SPIE
WCOL
SPE
-
-
-
-
-
-
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
UART I/O Data Register
RXC
RXCIE
UART Baud Rate Register
TXC
TXCIE
UDRE
UDRIE
FE
RXEN
OR
TXEN
-
-
-
CHR9
RXB8
TXB8
ACSR
ACD
-
ADEN
-
ADC7
AINBG
ADCBG
ADSC
-
ACO
-
ADFR
-
ADC5
ACI
-
ADIF
-
ADC4
ACIE
-
ADIE
-
ADC3
ACIC
MUX2
ADPS2
-
ACIS1
MUX1
ADPS1
ADC9
ADC1
ACIS0
MUX0
ADPS0
ADC8
ADC0
ADMUX
ADCSR
ADCH
ADCL
UBRRHI
ADC6
ADC2
UART Baud Rate Register High
7
Register Summary (Continued)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
$02 ($22)
$01 ($21)
$00 ($20)
Reserved
Reserved
Reserved
Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers $00 to $1F only.
AT90S/LS2333 and AT90S/LS4433
8
AT90S/LS2333 and AT90S/LS4433
Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
ADC
ADIW
SUB
SUBI
SBC
SBCI
SBIW
AND
ANDI
OR
Rd, Rr
Rd, Rr
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Add two Registers
Rd ← Rd + Rr
Rd ← Rd + Rr + C
Rdh:Rdl ← Rdh:Rdl + K
Rd ← Rd - Rr
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Add with Carry two Registers
Add Immediate to Word
Subtract two Registers
Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Rd ← Rd - K
Rd ← Rd - Rr - C
Rd ← Rd - K - C
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • Rr
Rd ← Rd • K
Rd ← Rd v Rr
ORI
Logical OR Register and Constant
Exclusive OR Registers
One’s Complement
Rd ← Rd v K
EOR
COM
NEG
SBR
CBR
INC
Rd ← Rd Rr
Rd ← $FF − Rd
Rd ← $00 − Rd
Rd ← Rd v K
Rd ← Rd • ($FF - K)
Rd ← Rd + 1
Z,C,N,V
Z,C,N,V,H
Z,N,V
Z,N,V
Z,N,V
Rd
Two’s Complement
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Decrement
Test for Zero or Minus
Clear Register
Set Register
Rd,K
Rd,K
Rd
Rd
Rd
DEC
TST
Rd ← Rd − 1
Z,N,V
Z,N,V
Rd ← Rd • Rd
Rd ← Rd Rd
Rd ← $FF
CLR
SER
Rd
Rd
Z,N,V
None
BRANCH INSTRUCTIONS
RJMP
IJMP
RCALL
ICALL
RET
k
k
Relative Jump
Indirect Jump to (Z)
Relative Subroutine Call
Indirect Call to (Z)
Subroutine Return
PC ← PC + k + 1
PC ← Z
PC ← PC + k + 1
None
None
None
None
None
I
2
2
3
PC ← Z
PC ← STACK
PC ← STACK
3
4
4
RETI
Interrupt Return
CPSE
CP
CPC
Rd,Rr
Rd,Rr
Rd,Rr
Compare, Skip if Equal
Compare
Compare with Carry
if (Rd = Rr) PC ← PC + 2 or 3
Rd − Rr
Rd − Rr − C
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1 / 2 / 3
1
1
CPI
Rd,K
Rr, b
Rr, b
P, b
P, b
s, k
s, k
k
k
k
k
k
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Branch if Not Equal
Branch if Carry Set
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
Rd − K
1
SBRC
SBRS
SBIC
SBIS
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (N V= 0) then PC ← PC + k + 1
if (N V= 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (V = 0) then PC ← PC + k + 1
if ( I = 1) then PC ← PC + k + 1
if ( I = 0) then PC ← PC + k + 1
1 / 2 / 3
1 / 2 / 3
1 / 2 / 3
1 / 2 / 3
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
BRID
k
k
k
k
k
k
Branch if Minus
Branch if Plus
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
k
k
k
k
k
k
k
9
Instruction Set Summary (Continued)
Mnemonics
Operands
Description
Operation
Flags
#Clocks
DATA TRANSFER INSTRUCTIONS
MOV
LDI
LD
LD
LD
Rd, Rr
Rd, K
Rd, X
Rd, X+
Rd, - X
Rd, Y
Move Between Registers
Load Immediate
Load Indirect
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect
Rd ← Rr
Rd ← K
Rd ← (X)
Rd ← (X), X ← X + 1
X ← X - 1, Rd ← (X)
Rd ← (Y)
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
1
1
2
2
LD
LD
LD
LDD
LD
LD
Rd, Y+
Rd, - Y
Rd,Y+q
Rd, Z
Rd, Z+
Rd, -Z
Rd, Z+q
Rd, k
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Direct from SRAM
Store Indirect
Rd ← (Y), Y ← Y + 1
Y ← Y - 1, Rd ← (Y)
Rd ← (Y + q)
Rd ← (Z)
Rd ← (Z), Z ← Z+1
Z ← Z - 1, Rd ← (Z)
Rd ← (Z + q)
Rd ← (k)
LD
LDD
LDS
ST
ST
ST
X, Rr
(X) ← Rr
X+, Rr
- X, Rr
Y, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect
(X) ← Rr, X ← X + 1
X ← X - 1, (X) ← Rr
(Y) ← Rr
ST
ST
ST
STD
ST
ST
Y+, Rr
- Y, Rr
Y+q,Rr
Z, Rr
Z+, Rr
-Z, Rr
Z+q,Rr
k, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Indirect
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Direct to SRAM
Load Program Memory
In Port
(Y) ← Rr, Y ← Y + 1
Y ← Y - 1, (Y) ← Rr
(Y + q) ← Rr
(Z) ← Rr
(Z) ← Rr, Z ← Z + 1
Z ← Z - 1, (Z) ← Rr
(Z + q) ← Rr
(k) ← Rr
R0 ← (Z)
Rd ← P
P ← Rr
STACK ← Rr
Rd ← STACK
ST
STD
STS
LPM
IN
OUT
PUSH
POP
Rd, P
P, Rr
Rr
Out Port
Push Register on Stack
Pop Register from Stack
Rd
BIT AND BIT-TEST INSTRUCTIONS
SBI
CBI
LSL
P,b
P,b
Rd
Rd
Rd
Rd
Rd
Rd
s
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
Logical Shift Right
Rotate Left Through Carry
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
I/O(P,b) ← 1
I/O(P,b) ← 0
Rd(n+1) ← Rd(n), Rd(0) ← 0
Rd(n) ← Rd(n+1), Rd(7) ← 0
None
None
Z,C,N,V
Z,C,N,V
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
1
LSR
ROL
ROR
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Rd(n) ← Rd(n+1), n=0..6
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
SREG(s) ← 1
SREG(s) ← 0
T ← Rr(b)
Rd(b) ← T
C ← 1
Z,C,N,V
Z,C,N,V
Z,C,N,V
None
SREG(s)
SREG(s)
Flag Set
Flag Clear
s
Rr, b
Rd, b
Bit Store from Register to T
Bit load from T to Register
Set Carry
Clear Carry
Set Negative Flag
Clear Negative Flag
Set Zero Flag
Clear Zero Flag
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
T
None
C
C
N
N
C ← 0
N ← 1
N ← 0
Z ← 1
Z ← 0
I ← 1
I ← 0
S ← 1
S ← 0
Z
Z
I
I
S
S
CLI
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
NOP
SLEEP
WDR
V ← 1
V ← 0
T ← 1
T ← 0
H ← 1
H ← 0
V
V
T
T
H
H
Clear T in SREG
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
No Operation
Sleep
Watchdog Reset
None
None
None
(see specific descr. for Sleep function)
(see specific descr. for WDR/timer)
AT90S/LS2333 and AT90S/LS4433
10
AT90S/LS2333 and AT90S/LS4433
Ordering Information
Power Supply
Speed (MHz)
Ordering Code
Package
Operation Range
2.7 - 6.0V
4
8
4
8
AT90LS2333-4AC
AT90LS2333-4PC
32A
Commercial
28P3
(0°C to 70°C)
AT90LS2333-4AI
AT90LS2333-4PI
32A
Industrial
28P3
(-40°C to 85°C)
4.0 - 6.0V
2.7 - 6.0V
4.0 - 6.0V
AT90S2333-8AC
AT90S2333-8PC
32A
Commercial
28P3
(0°C to 70°C)
AT90S2333-8AI
AT90S2333-8PI
32A
Industrial
28P3
(-40°C to 85°C)
AT90LS4433-4AC
AT90LS4433-4PC
32A
Commercial
28P3
(0°C to 70°C)
AT90LS4433-4AI
AT90LS4433-4PI
32A
Industrial
28P3
(-40°C to 85°C)
AT90S4433-8AC
AT90S4433-8PC
32A
Commercial
28P3
(0°C to 70°C)
AT90S4433-8AI
AT90S4433-8PI
32A
Industrial
28P3
(-40°C to 85°C)
Package Type
28P3
32A
28-lead, 0.300” Wide, Plastic Dual in Line Package (PDIP)
32-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
11
Packaging Information
28P3, 28-lead, 0.300” Wide,
Plastic Dual Inline Package (PDIP)
Dimensions in Inches and (Millimeters)
32A, 32-lead, Thin (1.0 mm) Plastic Gull Wing Quad
Flat Package (TQFP)
Dimensions in Millimeters and (Inches)
PIN 1 ID
9.00 (0.354) BSC
0.45 (0.018)
0.30 (0.012)
0.80 (0.031) BSC
9.00 (0.354) BSC
7.00 (0.276) BSC
1.20 (0.047) MAX
0˚
7˚
0.20 (0.008)
0.10 (0.004)
0.15 (0.006)
0.05 (0.002)
0.75 (0.030)
0.45 (0.018)
AT90S/LS2333 and AT90S/LS4433
12
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