AT90S8515 [ATMEL]
8-Bit Microcontroller with 8K bytes In-System Programmable Flash; 8位微控制器具有8K字节的系统内可编程闪存型号: | AT90S8515 |
厂家: | ATMEL |
描述: | 8-Bit Microcontroller with 8K bytes In-System Programmable Flash |
文件: | 总8页 (文件大小:705K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Features
• AVR - High Performance and Low Power RISC Architecture
• 118 Powerful Instructions - Most Single Clock Cycle Execution
• 8K bytes of In-System Reprogrammable Flash
– SPI Serial Interface for Program Downloading
– Endurance: 1,000 Write/Erase Cycles
• 512 bytes EEPROM
– Endurance: 100,000 Write/Erase Cycles
• 512 bytes Internal SRAM
• 32 x 8 General Purpose Working Registers
• 32 Programmable I/O Lines
• Programmable Serial UART
8-Bit
• SPI Serial Interface
Microcontroller
with 8K bytes
In-System
Programmable
Flash
• VCC: 2.7 - 6.0V
• Fully Static Operation
– 0 - 8 MHz 4.0 - 6.0V,
– 0 - 4 MHz 2.7 - 4.0V
• Up to 8 MIPS Throughput at 8 MHz
• One 8-Bit Timer/Counter with Separate Prescaler
• One 16-Bit Timer/Counter with Separate Prescaler
and Compare and Capture Modes
• Dual PWM
• External and Internal Interrupt Sources
• Programmable Watchdog Timer with On-Chip Oscillator
• On-Chip Analog Comparator
• Low Power Idle and Power Down Modes
• Programming Lock for Software Security
AT90S8515
Preliminary
Description
®
The AT90S8515 is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock
cycle, the AT90S8515 achieves throughputs approaching 1 MIPS per MHz allowing
the system designer to optimize power consumption versus processing speed.
The AVR core combines a rich instruction set with 32 general purpose working regis-
ters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),
allowing two independent registers to be accessed in one single instruction executed
in one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
(continued)
Pin Configurations
Rev. 0841DS–06/98
Note: This is a sumary document. For the complete
76 page document, please visit our Web site at
www.atmel.com or e-mail at literature@atmel.com
and request literature number 0841D.
Block Diagram
Figure 1. The AT90S8515 Block Diagram
The AT90S8515 provides the following features: 8K bytes
of In-System Programmable Flash, 512 bytes EEPROM,
512 bytes SRAM, 32 general purpose I/O lines, 32 general
purpose working registers, flexible timer/counters with
compare modes, internal and external interrupts, a pro-
grammable serial UART, programmable Watchdog Timer
with internal oscillator, an SPI serial port and two software
selectable power saving modes. The Idle Mode stops the
CPU while allowing the SRAM, timer/counters, SPI port
and interrupt system to continue functioning. The power
down mode saves the register contents but freezes the
oscillator, disabling all other chip functions until the next
interrupt or hardware reset.
The device is manufactured using Atmel’s high density
non-volatile memory technology. The on-chip in-system
programmable Flash allows the program memory to be
reprogrammed in-system through an SPI serial interface or
by a conventional nonvolatile memory programmer. By
combining an enhanced RISC 8-bit CPU with In-System
Programmable Flash on a monolithic chip, the Atmel
AT90S8515 is a powerful microcontroller that provides a
highly flexible and cost effective solution to many embed-
ded control applications.
The AT90S8515 AVR is supported with a full suite of pro-
gram and system development tools including: C compil-
ers, macro assemblers, program debugger/simulators, in-
circuit emulators, and evaluation kits.
AT90S8515
2
AT90S8515
ALE
Pin Descriptions
ALE is the Address Latch Enable used when the External
Memory is enabled. The ALE strobe is used to latch the
low-order address (8 bits) into an address latch during the
first access cycle, and the AD0-7 pins are used for data
during the second access cycle.
VCC
Supply voltage
GND
Ground
Port A (PA7..PA0)
Crystal Oscillator
Port A is an 8-bit bidirectional I/O port. Port pins can pro-
vide internal pull-up resistors (selected for each bit). The
Port A output buffers can sink 20mA and can drive LED dis-
plays directly. When pins PA0 to PA7 are used as inputs
and are externally pulled low, they will source current if the
internal pull-up resistors are activated.
XTAL1 and XTAL2 are input and output, respectively, of an
inverting amplifier which can be configured for use as an
on-chip oscillator, as shown in Figure 2. Either a quartz
crystal or a ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven as shown in Figure 3.
Port A serves as Multiplexed Address/Data input/output
when using external SRAM.
Figure 2. Oscillator Connections
Port B (PB7..PB0)
Port B is an 8-bit bidirectional I/O pins with internal pull-up
resistors. The Port B output buffers can sink 20 mA. As
inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated.
Port B also serves the functions of various special features
of the AT90S8515 as listed on page 46.
Port C (PC7..PC0)
Port C is an 8-bit bidirectional I/O port with internal pull-up
resistors. The Port C output buffers can sink 20 mA. As
inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated.
Port C also serves as Address output when using external
SRAM.
Figure 3. External Clock Drive Configuration
Port D (PD7..PD0)
Port D is an 8-bit bidirectional I/O port with internal pull-up
resistors. The Port D output buffers can sink 20 mA. As
inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated.
Port D also serves the functions of various special features
of the AT90S8515 as listed on page 52.
RESET
Reset input. A low on this pin for two machine cycles while
the oscillator is running resets the device.
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier
ICP
ICP is the input pin for the Timer/Counter1 Input Capture
function.
OC1B
OC1B is the output pin for the Timer/Counter1 Output
CompareB function
3
AT90S8515 Architectural Overview
The fast-access register file concept contains 32 x 8-bit
general purpose working registers with a single clock cycle
access time. This means that during one single clock cycle,
one ALU (Arithmetic Logic Unit) operation is executed. Two
operands are output from the register file, the operation is
executed, and the result is stored back in the register file -
in one clock cycle.
Six of the 32 registers can be used as three 16-bits indirect
address register pointers for Data Space addressing -
enabling efficient address calculations. One of the three
address pointers is also used as the address pointer for the
constant table look up function. These added function reg-
isters are the 16-bits X-register, Y-register and Z-register.
Figure 4. The AT90S8515 AVR Enhanced RISC Architecture
The ALU supports arithmetic and logic functions between
registers or between a constant and a register. Single reg-
ister operations are also executed in the ALU. Figure 4
shows the AT90S8515 AVR Enhanced RISC microcontrol-
ler architecture.
The AVR uses a Harvard architecture concept - with sepa-
rate memories and buses for program and data. The pro-
gram memory is executed with a two stage pipeline. While
one instruction is being executed, the next instruction is
pre-fetched from the program memory. This concept
enables instructions to be executed in every clock cycle.
The program memory is in-system programmable Flash
memory.
In addition to the register operation, the conventional mem-
ory addressing modes can be used on the register file as
well. This is enabled by the fact that the register file is
assigned the 32 lowermost Data Space addresses ($00 -
$1F), allowing them to be accessed as though they were
ordinary memory locations.
With the relative jump and call instructions, the whole 4K
address space is directly accessed. Most AVR instructions
have a single 16-bit word format. Every program memory
address contains a 16- or 32-bit instruction.
The I/O memory space contains 64 addresses for CPU
peripheral functions as Control Registers, Timer/Counters,
A/D-converters, and other I/O functions. The I/O Memory
can be accessed directly, or as the Data Space locations
following those of the register file, $20 - $5F.
During interrupts and subroutine calls, the return address
program counter (PC) is stored on the stack. The stack is
effectively allocated in the general data SRAM, and conse-
quently the stack size is only limited by the total SRAM size
and the usage of the SRAM. All user programs must initial-
AT90S8515
4
AT90S8515
ize the SP in the reset routine (before subroutines or inter-
rupts are executed). The 16-bit stack pointer SP is
read/write accessible in the I/O space.
Figure 5. Memory Maps
The 512 bytes data SRAM can be easily accessed through
the five different addressing modes supported in the AVR
architecture.
The memory spaces in the AVR architecture are all linear
and regular memory maps.
A flexible interrupt module has its control registers in the
I/O space with an additional global interrupt enable bit in
the status register. All the different interrupts have a sepa-
rate interrupt vector in the interrupt vector table at the
beginning of the program memory. The different interrupts
have priority in accordance with their interrupt vector posi-
tion. The lower the interrupt vector address the higher the
priority.
5
AT90S8515 Register Summary
Address
Name
SREG
SPH
SPL
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
$3F ($5F)
$3E ($5E)
$3D ($5D)
$3C ($5C)
$3B ($5B)
$3A ($5A)
$39 ($59)
$38 ($58)
$37 ($57)
$36 ($56)
$35 ($55)
$34 ($54)
$33 ($53)
$32 ($52)
$31 ($51)
$30 ($50)
$2F ($4F)
$2E ($4E)
$2D ($4D)
$2C ($4C)
$2B ($4B)
$2A ($4A)
$29 ($49)
$28 ($48)
$27 ($47)
$26 ($46)
$25 ($45)
$24 ($44)
$23 ($43)
$22 ($42)
$21 ($41)
$20 ($40)
$1F ($3F)
$1E ($3E)
$1D ($3D)
$1C ($3C)
$1B ($3B)
$1A ($3A)
$19 ($39)
$18 ($38)
$17 ($37)
$16 ($36)
$15 ($35)
$14 ($34)
$13 ($33)
$12 ($32)
$11 ($31)
$10 ($30)
$0F ($2F)
$0E ($2E)
$0D ($2D)
$0C ($2C)
$0B ($2B)
$0A ($2A)
$09 ($29)
$08 ($28)
…
I
T
H
SP13
SP5
S
SP12
SP4
V
SP11
SP3
N
SP10
SP2
Z
SP9
SP1
C
SP8
SP0
18
19
19
SP15
SP7
SP14
SP6
Reserved
GIMSK
GIFR
TIMSK
TIFR
INT1
INTF1
TOIE1
TOV1
INT0
INTF0
OCIE1A
OCF1A
-
-
-
-
-
-
24
24
24
25
OCIE1B
OCF1B
-
-
TICIE1
ICF1
-
-
TOIE0
TOV0
-
-
Reserved
Reserved
MCUCR
Reserved
TCCR0
TCNT0
Reserved
Reserved
TCCR1A
TCCR1B
TCNT1H
TCNT1L
OCR1AH
OCR1AL
OCR1BH
OCR1BL
Reserved
Reserved
ICR1H
SRE
-
SRW
-
SE
-
SM
-
ISC11
-
ISC10
CS02
ISC01
CS01
ISC00
CS00
26
29
30
Timer/Counter0 (8 Bit)
COM1A1
ICNC1
COM1A0
ICES1
COM1B1
-
COM1B0
-
-
-
PWM11
CS11
PWM10
CS10
32
33
34
34
35
35
35
35
CTC1
CS12
Timer/Counter1 - Counter Register High Byte
Timer/Counter1 - Counter Register Low Byte
Timer/Counter1 - Output Compare Register A High Byte
Timer/Counter1 - Output Compare Register A Low Byte
Timer/Counter1 - Output Compare Register B High Byte
Timer/Counter1 - Output Compare Register B Low Byte
Timer/Counter1 - Input Capture Register High Byte
Timer/Counter1 - Input Capture Register Low Byte
36
36
ICR1L
Reserved
Reserved
WDTCR
Reserved
Reserved
EEARL
EEDR
-
-
-
-
-
-
WDTOE
-
WDE
-
WDP2
-
WDP1
-
WDP0
38
EEAR8
39
39
39
40
54
54
54
56
56
56
61
61
61
63
63
63
45
44
44
48
48
49
51
52
EEPROM Address Register Low Byte
EEPROM Data Register
EECR
PORTA
DDRA
PINA
PORTB
DDRB
-
-
-
-
-
EEMWE
PORTA2
DDA2
PINA2
PORTB2
DDB2
EEWE
PORTA1
DDA1
PINA1
PORTB1
DDB1
EERE
PORTA0
DDA0
PINA0
PORTB0
DDB0
PORTA7
DDA7
PINA7
PORTB7
DDB7
PORTA6
DDA6
PINA6
PORTB6
DDB6
PORTA5
DDA5
PINA5
PORTB5
DDB5
PORTA4
DDA4
PINA4
PORTB4
DDB4
PORTA3
DDA3
PINA3
PORTB3
DDB3
PINB
PORTC
DDRC
PINC
PORTD
DDRD
PINB7
PORTC7
DDC7
PINC7
PORTD7
DDD7
PINB6
PORTC6
DDC6
PINC6
PORTD6
DDD6
PINB5
PORTC5
DDC5
PINC5
PORTD5
DDD5
PINB4
PORTC4
DDC4
PINC4
PORTD4
DDD4
PINB3
PORTC3
DDC3
PINC3
PORTD3
DDD3
PINB2
PORTC2
DDC2
PINC2
PORTD2
DDD2
PINB1
PORTC1
DDC1
PINC1
PORTD1
DDD1
PINB0
PORTC0
DDC0
PINC0
PORTD0
DDD0
PIND
SPDR
SPSR
SPCR
UDR
USR
PIND7
SPI Data Register
SPIF
SPIE
UART I/O Data Register
RXC
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
WCOL
SPE
-
-
-
-
-
-
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
TXC
UDRE
FE
OR
-
-
-
UCR
UBRR
ACSR
Reserved
Reserved
RXCIE
UART Baud Rate Register
ACD
TXCIE
UDRIE
RXEN
TXEN
CHR9
RXB8
TXB8
-
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
$00 ($20)
AT90S8515
6
AT90S8515
AT90S8515 Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
ADC
ADIW
SUB
SUBI
SBC
SBCI
SBIW
AND
ANDI
OR
Rd, Rr
Rd, Rr
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Add two Registers
Rd ← Rd + Rr
Rd ← Rd + Rr + C
Rdh:Rdl ← Rdh:Rdl + K
Rd ← Rd - Rr
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Add with Carry two Registers
Add Immediate to Word
Subtract two Registers
Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Rd ← Rd - K
Rd ← Rd - Rr - C
Rd ← Rd - K - C
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • Rr
Rd ← Rd • K
Rd ← Rd v Rr
ORI
Logical OR Register and Constant
Exclusive OR Registers
One’s Complement
Rd ← Rd v K
EOR
COM
NEG
SBR
CBR
INC
Rd ← Rd Rr
Rd ← $FF − Rd
Rd ← $00 − Rd
Rd ← Rd v K
Rd ← Rd • ($FF - K)
Rd ← Rd + 1
Z,C,N,V
Z,C,N,V,H
Z,N,V
Z,N,V
Z,N,V
Rd
Two’s Complement
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Decrement
Test for Zero or Minus
Clear Register
Set Register
Rd,K
Rd,K
Rd
Rd
Rd
DEC
TST
Rd ← Rd − 1
Z,N,V
Z,N,V
Rd ← Rd • Rd
Rd ← Rd Rd
Rd ← $FF
CLR
SER
Rd
Rd
Z,N,V
None
BRANCH INSTRUCTIONS
RJMP
IJMP
RCALL
ICALL
RET
k
Relative Jump
Indirect Jump to (Z)
Relative Subroutine Call
Indirect Call to (Z)
Subroutine Return
PC ← PC + k + 1
PC ← Z
PC ← PC + k + 1
PC ← Z
PC ← STACK
PC ← STACK
None
None
None
None
None
I
2
2
3
k
3
4
4
RETI
Interrupt Return
CPSE
CP
CPC
Rd,Rr
Rd,Rr
Rd,Rr
Compare, Skip if Equal
Compare
Compare with Carry
if (Rd = Rr) PC ← PC + 2 or 3
Rd − Rr
Rd − Rr − C
None
1 / 2
1
1
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
CPI
Rd,K
Rr, b
Rr, b
P, b
P, b
s, k
s, k
k
k
k
k
k
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Branch if Not Equal
Branch if Carry Set
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
Rd − K
1
SBRC
SBRS
SBIC
SBIS
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (N V= 0) then PC ← PC + k + 1
if (N V= 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (V = 0) then PC ← PC + k + 1
if ( I = 1) then PC ← PC + k + 1
if ( I = 0) then PC ← PC + k + 1
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
None
None
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
BRID
None
None
None
None
None
None
k
k
k
k
k
k
None
None
None
None
None
None
Branch if Minus
Branch if Plus
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
k
k
k
k
k
k
None
None
None
None
None
None
k
None
7
AT90S8515 Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
DATA TRANSFER INSTRUCTIONS
MOV
LDI
LD
LD
LD
LD
LD
LD
Rd, Rr
Rd, K
Move Between Registers
Load Immediate
Rd ← Rr
Rd ← K
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
1
1
2
2
Rd, X
Load Indirect
Rd ← (X)
Rd, X+
Rd, - X
Rd, Y
Rd, Y+
Rd, - Y
Rd,Y+q
Rd, Z
Rd, Z+
Rd, -Z
Rd, Z+q
Rd, k
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Direct from SRAM
Store Indirect
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Indirect
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Direct to SRAM
Load Program Memory
In Port
Rd ← (X), X ← X + 1
X ← X - 1, Rd ← (X)
Rd ← (Y)
Rd ← (Y), Y ← Y + 1
Y ← Y - 1, Rd ← (Y)
Rd ← (Y + q)
Rd ← (Z)
Rd ← (Z), Z ← Z+1
Z ← Z - 1, Rd ← (Z)
Rd ← (Z + q)
Rd ← (k)
LDD
LD
LD
LD
LDD
LDS
ST
ST
ST
ST
ST
ST
X, Rr
(X) ← Rr
X+, Rr
- X, Rr
Y, Rr
Y+, Rr
- Y, Rr
Y+q,Rr
Z, Rr
Z+, Rr
-Z, Rr
Z+q,Rr
k, Rr
(X) ← Rr, X ← X + 1
X ← X - 1, (X) ← Rr
(Y) ← Rr
(Y) ← Rr, Y ← Y + 1
Y ← Y - 1, (Y) ← Rr
(Y + q) ← Rr
STD
ST
ST
(Z) ← Rr
(Z) ← Rr, Z ← Z + 1
Z ← Z - 1, (Z) ← Rr
(Z + q) ← Rr
ST
STD
STS
LPM
IN
OUT
PUSH
POP
(k) ← Rr
R0 ← (Z)
Rd ← P
P ← Rr
STACK ← Rr
Rd ← STACK
Rd, P
P, Rr
Rr
Out Port
Push Register on Stack
Pop Register from Stack
Rd
BIT AND BIT-TEST INSTRUCTIONS
SBI
CBI
LSL
P,b
P,b
Rd
Rd
Rd
Rd
Rd
Rd
s
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
Logical Shift Right
Rotate Left Through Carry
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
Flag Set
Flag Clear
Bit Store from Register to T
Bit load from T to Register
Set Carry
I/O(P,b) ← 1
I/O(P,b) ← 0
Rd(n+1) ← Rd(n), Rd(0) ← 0
Rd(n) ← Rd(n+1), Rd(7) ← 0
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
None
None
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
1
LSR
ROL
ROR
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
Rd(n) ← Rd(n+1), n=0..6
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
Z,C,N,V
None
SREG(s)
SREG(s)
T
None
SREG(s) ← 1
SREG(s) ← 0
T ← Rr(b)
Rd(b) ← T
C ← 1
C ← 0
N ← 1
N ← 0
Z ← 1
s
Rr, b
Rd, b
C
C
N
N
Z
Z
Clear Carry
Set Negative Flag
Clear Negative Flag
Set Zero Flag
Clear Zero Flag
Z ← 0
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
I ← 1
I ← 0
S ← 1
S ← 0
V ← 1
V ← 0
I
I
S
S
V
V
CLI
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
NOP
SLEEP
WDR
T ← 1
T ← 0
H ← 1
H ← 0
T
T
H
H
None
None
None
Clear T in SREG
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
No Operation
Sleep
(see specific descr. for Sleep function)
(see specific descr. for WDR/timer)
Watchdog Reset
AT90S8515
8
相关型号:
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