AT90S8515-4AC_技术文档

Features

• AVR - High Performance and Low Power RISC Architecture

• 118 Powerful Instructions - Most Single Clock Cycle Execution

• 8K bytes of In-System Reprogrammable Flash

– SPI Serial Interface for Program Downloading

– Endurance: 1,000 Write/Erase Cycles

• 512 bytes EEPROM

– Endurance: 100,000 Write/Erase Cycles

• 512 bytes Internal SRAM

• 32 x 8 General Purpose Working Registers

• 32 Programmable I/O Lines

• Programmable Serial UART

8-Bit

• SPI Serial Interface

Microcontroller

with 8K bytes

In-System

Programmable

Flash

• V_CC: 2.7 - 6.0V

• Fully Static Operation

– 0 - 8 MHz 4.0 - 6.0V,

– 0 - 4 MHz 2.7 - 4.0V

• Up to 8 MIPS Throughput at 8 MHz

• One 8-Bit Timer/Counter with Separate Prescaler

• One 16-Bit Timer/Counter with Separate Prescaler

and Compare and Capture Modes

• Dual PWM

• External and Internal Interrupt Sources

• Programmable Watchdog Timer with On-Chip Oscillator

• On-Chip Analog Comparator

• Low Power Idle and Power Down Modes

• Programming Lock for Software Security

AT90S8515

Preliminary

Description

®

The AT90S8515 is a low-power CMOS 8-bit microcontroller based on the AVR

enhanced RISC architecture. By executing powerful instructions in a single clock

cycle, the AT90S8515 achieves throughputs approaching 1 MIPS per MHz allowing

the system designer to optimize power consumption versus processing speed.

The AVR core combines a rich instruction set with 32 general purpose working regis-

ters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),

allowing two independent registers to be accessed in one single instruction executed

in one clock cycle. The resulting architecture is more code efficient while achieving

throughputs up to ten times faster than conventional CISC microcontrollers.

(continued)

Pin Configurations

Rev. 0841D–06/98

1

Block Diagram

Figure 1. The AT90S8515 Block Diagram

The AT90S8515 provides the following features: 8K bytes

of In-System Programmable Flash, 512 bytes EEPROM,

512 bytes SRAM, 32 general purpose I/O lines, 32 general

purpose working registers, flexible timer/counters with

compare modes, internal and external interrupts, a pro-

grammable serial UART, programmable Watchdog Timer

with internal oscillator, an SPI serial port and two software

selectable power saving modes. The Idle Mode stops the

CPU while allowing the SRAM, timer/counters, SPI port

and interrupt system to continue functioning. The power

down mode saves the register contents but freezes the

oscillator, disabling all other chip functions until the next

interrupt or hardware reset.

The device is manufactured using Atmel’s high density

non-volatile memory technology. The on-chip in-system

programmable Flash allows the program memory to be

reprogrammed in-system through an SPI serial interface or

by a conventional nonvolatile memory programmer. By

combining an enhanced RISC 8-bit CPU with In-System

Programmable Flash on a monolithic chip, the Atmel

AT90S8515 is a powerful microcontroller that provides a

highly flexible and cost effective solution to many embed-

ded control applications.

The AT90S8515 AVR is supported with a full suite of pro-

gram and system development tools including: C compil-

ers, macro assemblers, program debugger/simulators, in-

circuit emulators, and evaluation kits.

AT90S8515

2

AT90S8515

ALE

Pin Descriptions

ALE is the Address Latch Enable used when the External

Memory is enabled. The ALE strobe is used to latch the

low-order address (8 bits) into an address latch during the

first access cycle, and the AD0-7 pins are used for data

during the second access cycle.

V_CC

Supply voltage

GND

Ground

Port A (PA7..PA0)

Crystal Oscillator

Port A is an 8-bit bidirectional I/O port. Port pins can pro-

vide internal pull-up resistors (selected for each bit). The

Port A output buffers can sink 20mA and can drive LED dis-

plays directly. When pins PA0 to PA7 are used as inputs

and are externally pulled low, they will source current if the

internal pull-up resistors are activated.

XTAL1 and XTAL2 are input and output, respectively, of an

inverting amplifier which can be configured for use as an

on-chip oscillator, as shown in Figure 2. Either a quartz

crystal or a ceramic resonator may be used. To drive the

device from an external clock source, XTAL2 should be left

unconnected while XTAL1 is driven as shown in Figure 3.

Port A serves as Multiplexed Address/Data input/output

when using external SRAM.

Figure 2. Oscillator Connections

Port B (PB7..PB0)

Port B is an 8-bit bidirectional I/O pins with internal pull-up

resistors. The Port B output buffers can sink 20 mA. As

inputs, Port B pins that are externally pulled low will source

current if the pull-up resistors are activated.

Port B also serves the functions of various special features

of the AT90S8515 as listed on page 46.

Port C (PC7..PC0)

Port C is an 8-bit bidirectional I/O port with internal pull-up

resistors. The Port C output buffers can sink 20 mA. As

inputs, Port C pins that are externally pulled low will source

current if the pull-up resistors are activated.

Port C also serves as Address output when using external

SRAM.

Figure 3. External Clock Drive Configuration

Port D (PD7..PD0)

Port D is an 8-bit bidirectional I/O port with internal pull-up

resistors. The Port D output buffers can sink 20 mA. As

inputs, Port D pins that are externally pulled low will source

current if the pull-up resistors are activated.

Port D also serves the functions of various special features

of the AT90S8515 as listed on page 52.

RESET

Reset input. A low on this pin for two machine cycles while

the oscillator is running resets the device.

XTAL1

Input to the inverting oscillator amplifier and input to the

internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier

ICP

ICP is the input pin for the Timer/Counter1 Input Capture

function.

OC1B

OC1B is the output pin for the Timer/Counter1 Output

CompareB function

3

AT90S8515 Architectural Overview

The fast-access register file concept contains 32 x 8-bit

general purpose working registers with a single clock cycle

access time. This means that during one single clock cycle,

one ALU (Arithmetic Logic Unit) operation is executed. Two

operands are output from the register file, the operation is

executed, and the result is stored back in the register file -

in one clock cycle.

Six of the 32 registers can be used as three 16-bits indirect

address register pointers for Data Space addressing -

enabling efficient address calculations. One of the three

address pointers is also used as the address pointer for the

constant table look up function. These added function reg-

isters are the 16-bits X-register, Y-register and Z-register.

Figure 4. The AT90S8515 AVR Enhanced RISC Architecture

The ALU supports arithmetic and logic functions between

registers or between a constant and a register. Single reg-

ister operations are also executed in the ALU. Figure 4

shows the AT90S8515 AVR Enhanced RISC microcontrol-

ler architecture.

The AVR uses a Harvard architecture concept - with sepa-

rate memories and buses for program and data. The pro-

gram memory is executed with a two stage pipeline. While

one instruction is being executed, the next instruction is

pre-fetched from the program memory. This concept

enables instructions to be executed in every clock cycle.

The program memory is in-system programmable Flash

memory.

In addition to the register operation, the conventional mem-

ory addressing modes can be used on the register file as

well. This is enabled by the fact that the register file is

assigned the 32 lowermost Data Space addresses ($00 -

$1F), allowing them to be accessed as though they were

ordinary memory locations.

With the relative jump and call instructions, the whole 4K

address space is directly accessed. Most AVR instructions

have a single 16-bit word format. Every program memory

address contains a 16- or 32-bit instruction.

The I/O memory space contains 64 addresses for CPU

peripheral functions as Control Registers, Timer/Counters,

A/D-converters, and other I/O functions. The I/O Memory

can be accessed directly, or as the Data Space locations

following those of the register file, $20 - $5F.

During interrupts and subroutine calls, the return address

program counter (PC) is stored on the stack. The stack is

effectively allocated in the general data SRAM, and conse-

quently the stack size is only limited by the total SRAM size

and the usage of the SRAM. All user programs must initial-

AT90S8515

4

AT90S8515

ize the SP in the reset routine (before subroutines or inter-

rupts are executed). The 16-bit stack pointer SP is

read/write accessible in the I/O space.

Figure 5. Memory Maps

The 512 bytes data SRAM can be easily accessed through

the five different addressing modes supported in the AVR

architecture.

The memory spaces in the AVR architecture are all linear

and regular memory maps.

A flexible interrupt module has its control registers in the

I/O space with an additional global interrupt enable bit in

the status register. All the different interrupts have a sepa-

rate interrupt vector in the interrupt vector table at the

beginning of the program memory. The different interrupts

have priority in accordance with their interrupt vector posi-

tion. The lower the interrupt vector address the higher the

priority.

The General Purpose Register File

Figure 6 shows the structure of the 32 general purpose working registers in the CPU.

Figure 6. AVR CPU General Purpose Working Registers

7

0

Addr.

R0

R1

$00

$01

$02

R2

…

R13

R14

R15

R16

R17

…

$0D

$0E

$0F

$10

$11

General

Purpose

Working

Registers

R26

R27

R28

R29

R30

R31

$1A

$1B

$1C

$1D

$1E

$1F

X-register low byte

X-register high byte

Y-register low byte

Y-register high byte

Z-register low byte

Z-register high byte

All the register operating instructions in the instruction set

have direct and single cycle access to all registers. The

only exception is the five constant arithmetic and logic

instructions SBCI, SUBI, CPI, ANDI and ORI between a

constant and a register and the LDI instruction for load

immediate constant data. These instructions apply to the

second half of the registers in the register file - R16..R31.

The general SBC, SUB, CP, AND and OR and all other

operations between two registers or on a single register

apply to the entire register file.

As shown in Figure 6, each register is also assigned a data

memory address, mapping them directly into the first 32

locations of the user Data Space. Although not being phys-

ically implemented as SRAM locations, this memory orga-

nization provides great flexibility in access of the registers,

as the X,Y and Z registers can be set to index any register

in the file.

5

The X-Register, Y-Register And Z-Register

The registers R26..R31 have some added functions to their

general purpose usage. These registers are address point-

ers for indirect addressing of the Data Space. The three

indirect address registers X, Y and Z are defined as:

Figure 7. The X, Y and Z Registers

15

0

X - register

Y - register

Z - register

7

0

7

0

R27 ($1B)

R29 ($1D)

R31 ($1F)

R26 ($1A)

R28 ($1C)

R30 ($1E)

15

7

0

15

7

0

In the different addressing modes these address registers

have functions as fixed displacement, automatic increment

and decrement (see the descriptions for the different

instructions).

instructions are 16-or 32-bit words, the Flash is organized

as 4K x 16. The Flash memory has an endurance of at

least 1000 write/erase cycles. The AT90S8515 Program

Counter (PC) is 12 bits wide, thus addressing the 4096 pro-

gram memory addresses.

The ALU - Arithmetic Logic Unit

See page 62 for a detailed description on Flash data down-

loading.

The high-performance AVR ALU operates in direct connec-

tion with all the 32 general purpose working registers.

Within a single clock cycle, ALU operations between regis-

ters in the register file are executed. The ALU operations

are divided into three main categories - arithmetic, logical

and bit-functions.

Constant tables must be allocated within the address 0-4K

(see the LPM - Load Program Memory instruction descrip-

tion).

See page 8 for the different program memory addressing

modes.

The In-System Programmable Flash Program

Memory

The AT90S8515 contains 8K bytes on-chip In-System Pro-

grammable Flash memory for program storage. Since all

AT90S8515

6

AT90S8515

The SRAM Data Memory - Internal and External

The following figure shows how the AT90S8515 SRAM

Memory is organized:

Figure 8. SRAM Organization

Register File

Data Address Space

R0

R1

R2

…

$0000

$0001

$0002

…

R29

R30

$001D

$001E

$001F

R31

I/O Registers

$00

$0020

$0021

$0022

…

$01

$02

…

$3D

$3E

$3F

$005D

$005E

$005F

Internal SRAM

$0060

$0061

…

$025E

$025F

External SRAM

$0260

$0261

…

$FFFE

$FFFF

The lower 608 Data Memory locations address the Regis-

ter file, the I/O Memory and the internal data SRAM. The

first 96 locations address the Register File + I/O Memory,

and the next 512 locations address the internal data

SRAM. An optional external data SRAM can be placed in

the same SRAM memory space. This SRAM will occupy

the location following the internal SRAM and up to as much

as 64K - 1, depending on SRAM size.

Accessing external SRAM takes one additional clock cycle

per byte compared to access of the internal SRAM. This

means that the commands LD, ST, LDS, STS, PUSH and

POP take one additional clock cycle. If the stack is placed

in external SRAM, interrupts, subroutine calls and returns

take two clock cycles extra because the two-byte program

counter is pushed and popped. When external SRAM inter-

face is used with wait state, two additional clock cycles is

used per byte. This has the following effect: Data transfer

instructions take two extra clock cycles, whereas interrupt,

subroutine calls and returns will need four clock cycles

more than specified in the instruction set manual.

When the addresses accessing the data memory space

exceeds the internal data SRAM locations, the external

data SRAM is accessed using the same instructions as for

the internal data SRAM access. When the internal data

space is accessed, the read and write strobe pins (RD and

WR) are inactive during the whole access cycle. External

SRAM operation is enabled by setting the SRE bit in the

MCUCR register. See page 21 for details.

The five different addressing modes for the data memory

cover: Direct, Indirect with Displacement, Indirect, Indirect

with Pre-Decrement and Indirect with Post-Increment. In

the register file, registers R26 to R31 feature the indirect

addressing pointer registers.

7

The direct addressing reaches the entire data space.

Operands are contained in register r (Rr) and d (Rd). The

result is stored in register d (Rd).

The Indirect with Displacement mode features a 63

address locations reach from the base address given by

the Y or Z-register.

I/O Direct

Figure 11. I/O Direct Addressing

When using register indirect addressing modes with auto-

matic pre-decrement and post-increment, the address reg-

isters X, Y and Z are decremented and incremented.

The 32 general purpose working registers, 64 I/O registers,

the 512 bytes of internal data SRAM, and the 64K bytes of

optional external data SRAM in the AT90S8515 are all

accessible through all these addressing modes.

See the next section for a detailed description of the differ-

ent addressing modes.

The Program and Data Addressing Modes

The AT90S8515 AVR Enhanced RISC microcontroller sup-

ports powerful and efficient addressing modes for access

to the program memory (Flash) and data memory (SRAM,

Register File and I/O Memory). This section describes the

different addressing modes supported by the AVR architec-

ture. In the figures, OP means the operation code part of

the instruction word. To simplify, not all figures show the

exact location of the addressing bits.

Operand address is contained in 6 bits of the instruction

word. n is the destination or source register address.

Data Direct

Figure 12. Direct Data Addressing

Register Direct, Single Register RD

Figure 9. Direct Single Register Addressing

A 16-bit Data Address is contained in the 16 LSBs of a two-

word instruction. Rd/Rr specify the destination or source

register.

Data Indirect With Displacement

The operand is contained in register d (Rd).

Register Direct, Two Registers RD AND RR

Figure 10. Direct Register Addressing, Two Registers

Figure 13. Data Indirect with Displacement

Operand address is the result of the Y or Z-register con-

tents added to the address contained in 6 bits of the

instruction word.

AT90S8515

8

AT90S8515

Data Indirect

Constant Addressing Using The LPM Instruction

Figure 14. Data Indirect Addressing

Figure 17. Code Memory Constant Addressing

Constant byte address is specified by the Z-register con-

tents. The 15 MSBs select word address (0 - 4K) and LSB,

select low byte if cleared (LSB = 0) or high byte if set (LSB

= 1).

Operand address is the contents of the X, Y or the Z-regis-

ter.

Data Indirect With Pre-Decrement

Indirect Program Addressing, IJMP and ICALL

Figure 15. Data Indirect Addressing With Pre-Decrement

Figure 18. Indirect Program Memory Addressing

Program execution continues at address contained by the

Z-register (i.e. the PC is loaded with the contents of the Z-

register).

The X, Y or the Z-register is decremented before the opera-

tion. Operand address is the decremented contents of the

X, Y or the Z-register.

Relative Program Addressing, RJMP and RCALL

Data Indirect With Post-Increment

Figure 19. Relative Program Memory Addressing

Figure 16. Data Indirect Addressing With Post-Increment

Program execution continues at address PC + k + 1. The

relative address k is -2048 to 2047.

The X, Y or the Z-register is incremented after the opera-

tion. Operand address is the content of the X, Y or the Z-

register prior to incrementing.

9

The EEPROM Data Memory

Memory Access Times and Instruction

The AT90S8515 contains 512 bytes of data EEPROM

memory. It is organized as a separate data space, in which

single bytes can be read and written. The EEPROM has an

endurance of at least 100,000 write/erase cycles. The

access between the EEPROM and the CPU is described

on page 32 specifying the EEPROM address registers, the

EEPROM data register, and the EEPROM control register.

Execution Timing

This section describes the general access timing concepts

for instruction execution and internal memory access.

The AVR CPU is driven by the System Clock Ø, directly

generated from the external clock crystal for the chip. No

internal clock division is used.

Figure 20 shows the parallel instruction fetches and

instruction executions enabled by the Harvard architecture

and the fast-access register file concept. This is the basic

pipelining concept to obtain up to 1 MIPS per MHz with the

corresponding unique results for functions per cost, func-

tions per clocks, and functions per power-unit.

For the SPI data downloading, see page 62 for a detailed

description.

Figure 20. The Parallel Instruction Fetches and Instruction Executions

T1

T2

T3

T4

System Clock Ø

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

Figure 21 shows the internal timing concept for the register

file. In a single clock cycle an ALU operation using two reg-

ister operands is executed, and the result is stored back to

the destination register.

Figure 21. Single Cycle ALU Operation

T1

T2

T3

T4

System Clock Ø

Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

The internal data SRAM access is performed in two System Clock cycles as described in Figure 22.

AT90S8515

10

AT90S8515

Figure 22. On-Chip Data SRAM Access Cycles

T1

T2

T3

T4

System Clock Ø

Prev. Address

Address

Data

WR

Data

RD

The external data SRAM access is performed in two System Clock cycles as described in Figure 22.

Figure 23. External Data SRAM Memory Cycles without Wait State

T1

T2

T3

System Clock Ø

ALE

Prev. Address

Address

Data

Address [15..8]

Data / Address [7..0]

WR

Prev. Address

Address

Prev. Address

Address

Data

Data / Address [7..0]

RD

The external data SRAM memory access cycle with the Wait State bit enabled (Wait State active) is shown in Figure 24.

Figure 24. External Data SRAM Memory Cycles with Wait State

T1

T2

T3

T4

System Clock Ø

ALE

Prev. Address

Address

Address [15..8]

Data / Address [7..0]

WR

Prev. Address

Address

Data

Addr.

Prev. Address

Address

Data

Data / Address [7..0]

RD

11

I/O Memory

The I/O space definition of the AT90S8515 is shown in the following table:

Table 1. AT90S8515 I/O Space

Address Hex

$3F ($5F)

$3E ($5E)

$3D ($5D)

$3B ($5B)

$3A ($5A)

$39 ($59)

$38 ($58)

$35 ($55)

$33 ($53)

$32 ($52)

$2F ($4F)

$2E ($4E)

$2D ($4D)

$2C ($4C)

$2B ($4B)

$2A ($4A)

$29 ($49)

$28 ($48)

$25 ($45)

$24 ($44)

$21 ($41)

$1F ($3E)

$1E ($3E)

$1D ($3D)

$1C ($3C)

$1B ($3B)

$1A ($3A)

$19 ($39)

$18 ($38)

$17 ($37)

$16 ($36)

$15 ($35)

$14 ($34)

$13 ($33)

Name

SREG

Function

Status Register

SPH

Stack Pointer High

SPL

Stack Pointer Low

GIMSK

GIFR

General Interrupt Mask register

General Interrupt Flag Register

Timer/Counter Interrupt Mask register

Timer/Counter Interrupt Flag register

MCU general Control Register

Timer/Counter0 Control Register

Timer/Counter0 (8-bit)

TIMSK

TIFR

MCUCR

TCCR0

TCNT0

TCCR1A

TCCR1B

TCNT1H

TCNT1L

OCR1AH

OCR1AL

OCR1BH

OCR1BL

ICR1H

ICR1L

Timer/Counter1 Control Register A

Timer/Counter1 Control Register B

Timer/Counter1 High Byte

Timer/Counter1 Low Byte

Timer/Counter1 Output Compare Register A High Byte

Timer/Counter1 Output Compare Register A Low Byte

Timer/Counter1 Output Compare Register B High Byte

Timer/Counter1 Output Compare Register B Low Byte

T/C 1 Input Capture Register High Byte

T/C 1 Input Capture Register Low Byte

Watchdog Timer Control Register

EEPROM Address Register High Byte

EEPROM Address Register Low Byte

EEPROM Data Register

WDTCR

EEARH

EEARL

EEDR

EECR

EEPROM Control Register

PORTA

DDRA

Data Register, Port A

Data Direction Register, Port A

Input Pins, Port A

PINA

PORTB

DDRB

Data Register, Port B

Data Direction Register, Port B

Input Pins, Port B

PINB

PORTC

DDRC

PINC

Data Register, Port C

Data Direction Register, Port C

Input Pins, Port C

AT90S8515

12

AT90S8515

Table 1. AT90S8515 I/O Space (Continued)

Address Hex

$12 ($32)

$11 ($31)

$10 ($30)

$0F ($2F)

$0E ($2E)

$0D ($2D)

$0C ($2C)

$0B ($2B)

$0A ($2A)

$09 ($29)

$08 ($28)

Name

PORTD

DDRD

PIND

Function

Data Register, Port D

Data Direction Register, Port D

Input Pins, Port D

SPDR

SPSR

SPCR

UDR

SPI I/O Data Register

SPI Status Register

SPI Control Register

UART I/O Data Register

UART Status Register

UART Control Register

UART Baud Rate Register

USR

UCR

UBRR

ACSR

Analog Comparator Control and Status Register

Note:

reserved and unused locations are not shown in the table

All the different AT90S8515 I/Os and peripherals are

placed in the I/O space. The different I/O locations are

accessed by the IN and OUT instructions transferring data

between the 32 general purpose working registers and the

I/O space. I/O registers within the address range $00 - $1F

are directly bit-accessible using the SBI and CBI instruc-

tions. In these registers, the value of single bits can be

checked by using the SBIS and SBIC instructions. Refer to

the instruction set chapter for more details.

When using the I/O specific commands, IN, OUT,SBIS and

SBIC, the I/O addresses $00 - $3F must be used. When

addressing I/O registers as SRAM, $20 must be added to

this address. All I/O register addresses throughout this doc-

ument are shown with the SRAM address in parentheses.

The different I/O and peripherals control registers are

explained in the following chapters.

The Status Register - SREG

The AVR status register - SREG - at I/O space location $3F ($5F) is defined as:

Bit

7

I

6

T

5

H

4

S

3

V

2

N

1

Z

0

C

$3F ($5F)

Read/Write

Initial value

SREG

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 7 - I: Global Interrupt Enable

• Bit 5 - H: Half Carry Flag

The global interrupt enable bit must be set (one) for the

interrupts to be enabled. The individual interrupt enable

control is then performed in the interrupt mask registers -

GIMSK and TIMSK. If the global interrupt enable register is

cleared (zero), none of the interrupts are enabled indepen-

dent of the GIMSK and TIMSK values. The I-bit is cleared

by hardware after an interrupt has occurred, and is set by

the RETI instruction to enable subsequent interrupts.

The half carry flag H indicates a half carry in some arith-

metic operations. See the Instruction Set Description for

detailed information.

• Bit 4 - S: Sign Bit, S = N

V

The S-bit is always an exclusive or between the negative

flag N and the two’s complement overflow flag V. See the

Instruction Set Description for detailed information.

• Bit 3 - V: Two’s Complement Overflow Flag

The two’s complement overflow flag V supports two’s com-

plement arithmetics. See the Instruction Set Description for

detailed information.

• Bit 6 - T: Bit Copy Storage

The bit copy instructions BLD (Bit LoaD) and BST (Bit

STore) use the T bit as source and destination for the oper-

ated bit. A bit from a register in the register file can be cop-

ied into T by the BST instruction, and a bit in T can be

copied into a bit in a register in the register file by the BLD

instruction.

• Bit 2 - N: Negative Flag

The negative flag N indicates a negative result after the dif-

ferent arithmetic and logic operations. See the Instruction

Set Description for detailed information.

• Bit 1 - Z: Zero Flag

The zero flag Z indicates a zero result after the different

arithmetic and logic operations. See the Instruction Set

Description for detailed information.

13

• Bit 0 - C: Carry Flag

The Stack Pointer - SP

The carry flag C indicates a carry in an arithmetic or logic

operation. See the Instruction Set Description for detailed

information.

The general AVR 16-bit Stack Pointer is effectively built up

of two 8-bit registers in the I/O space locations $3E ($5E)

and $3D ($5D). As the AT90S8515 supports up to 64 kB

external SRAM, all 16-bits are used.

Bit

15

SP15

SP7

7

14

SP14

SP6

6

13

SP13

SP5

5

12

SP12

SP4

4

11

SP11

SP3

3

10

SP10

SP2

2

9

SP9

SP1

1

8

SP8

SP0

0

$3E ($5E)

$3D ($5D)

SPH

SPL

Read/Write

Initial value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Stack Pointer points to the data SRAM stack area

where the Subroutine and Interrupt Stacks are located.

This Stack space in the data SRAM must be defined by the

program before any subroutine calls are executed or inter-

rupts are enabled. The Stack Pointer is decremented by

one when data is pushed onto the Stack with the PUSH

instruction, and it is decremented by two when data is

pushed onto the Stack with subroutine CALL and interrupt.

The Stack Pointer is incremented by one when data is

popped from the Stack with the POP instruction, and it is

incremented by two when data is popped from the Stack

with return from subroutine RET or return from interrupt

IRET.

Reset and Interrupt Handling

The AT90S8515 provides 12 different interrupt sources.

These interrupts and the separate reset vector, each have

a separate program vector in the program memory space.

All interrupts are assigned individual enable bits which

must be set (one) together with the I-bit in the status regis-

ter in order to enable the interrupt.

The lowest addresses in the program memory space are

automatically defined as the Reset and Interrupt vectors.

The complete list of vectors is shown in Table 2. The list

also determines the priority levels of the different interrupts.

The lower the address the higher is the priority level.

RESET has the highest priority, and next is INT0 - the

External Interrupt Request 0 etc.

AT90S8515

14

AT90S8515

Table 2. Reset and Interrupt Vectors

Vector No.

Program Address

Source

Interrupt Definition

1

2

$000

$001

$002

$003

$004

$005

$006

$007

$008

$009

$00A

$00B

$00C

RESET

Hardware Pin and Watchdog Reset

External Interrupt Request 0

External Interrupt Request 1

Timer/Counter1 Capture Event

Timer/Counter1 Compare Match A

Timer/Counter1 Compare Match B

Timer/Counter1 Overflow

Timer/Counter0 Overflow

Serial Transfer Complete

INT0

3

INT1

4

TIMER1 CAPT

TIMER1 COMPA

TIMER1 COMPB

TIMER1 OVF

TIMER0, OVF

SPI, STC

5

6

7

8

9

10

11

12

13

UART, RX

UART, Rx Complete

UART, UDRE

UART, TX

UART Data Register Empty

UART, Tx Complete

ANA_COMP

Analog Comparator

The most typical and general program setup for the Reset and Interrupt Vector Addresses are:

Address

$000

$001

$002

$003

$004

$005

$006

$007

$008

$009

$00a

$00b

$00c

;

Labels

Code

rjmp

Comments

RESET

; Reset Handler

; IRQ0 Handler

; IRQ1 Handler

EXT_INT0

EXT_INT1

TIM1_CAPT ; Timer1 Capture Handler

TIM1_COMPA ; Timer1 CompareA Handler

TIM1_COMPB ; Timer1 CompareB Handler

TIM1_OVF

TIM0_OVF

SPI_STC

; Timer1 Overflow Handler

; Timer0 Overflow Handler

; SPI Transfer Complete Handler

; UART RX Complete Handler

; UDR Empty Handler

UART_RXC

UART_DRE

UART_TXC

ANA_COMP

; UART TX Complete Handler

; Analog Comparator Handler

$00d

…

MAIN:

…

<instr> xxx

; Main program start

…

Reset Sources

The AT90S8515 has three sources of reset:

The instruction placed in address $000 must be an RJMP -

relative jump - instruction to the reset handling routine. If

the program never enables an interrupt source, the inter-

rupt vectors are not used, and regular program code can

be placed at these locations. The circuit diagram in Figure

25 shows the reset logic. Table 3 defines the timing and

electrical parameters of the reset circuitry.

• Power-On Reset. The MCU is reset when a supply

voltage is applied to the V_CCand GND pins.

• External Reset. The MCU is reset when a low level is

present on the RESET pin for more than two XTAL

cycles.

• Watchdog Reset. The MCU is reset when the Watchdog

timer period expires and the Watchdog is enabled.

During reset, all I/O registers are then set to their initial val-

ues, and the program starts execution from address $000.

15

Figure 25. Reset Logic

Table 3. Reset Characteristics (V_CC= 5.0V)

Symbol Parameter

Min

Typ

2

Max

Units

V

V_POT

V_RST

t_POR

Power-On Reset Threshold Voltage

RESET Pin Threshold Voltage

1.8

2.2

V_CC/2

3

V

Power-On Reset Period

2

4

ms

t_TOUT

Reset Delay Time-Out Period FSTRT Unprogrammed

Reset Delay Time-Out Period FSTRT Programmed

11

1.0

16

21

1.2

1.1

Power-on Reset

A Power-On Reset (POR) circuit ensures that the device is

not started until V_CChas reached a safe level. As shown in

Figure 25, an internal timer clocked from the Watchdog

timer oscillator prevents the MCU from starting until after a

certain period after V_CChas reached the Power-On Thresh-

old voltage - V_POT, regardless of the V_CCrise time (see Fig-

ure 26 and Figure 27). The total reset period is the Power-

give a shorter start-up time if a ceramic resonator or any

other fast-start oscillator is used to clock the MCU.

If the build-in start-up delay is sufficient, RESET can be

connected to V_CCdirectly or via an external pull-up resistor.

By holding the pin low for a period after V_CChas been

applied, the Power-On Reset period can be extended.

Refer to Figure 28 for a timing example on this.

On Reset period - t_POR+ the Delay Time-out period - t_TOUT

.

The FSTRT fuse bit in the Flash can be programmed to

Figure 26. MCU Start-Up, RESET Tied to V_CC. Rapidly Rising V_CC

AT90S8515

16

AT90S8515

Figure 27. MCU Start-Up, RESET Tied to V_CCor Unconnected. Slowly Rising V_CC

Figure 28. MCU Start-Up, RESET Controlled Externally

External Reset

An external reset is generated by a low level on the RESET

pin. The RESET pin must be held low for at least two crys-

tal clock cycles. When the applied signal reaches the Reset

Threshold Voltage - V_RSTon its positive edge, the delay

timer starts the MCU after the Time-out period t_TOUThas

expired.

17

Figure 29. External Reset During Operation

Watchdog Reset

When the Watchdog times out, it will generate a short reset

pulse of 1 XTAL cycle duration. On the falling edge of this

pulse, the delay timer starts counting the Time-out period

t_TOUT. Refer to page 30 for details on operation of the

Watchdog.

Figure 30. Watchdog Reset During Operation

Interrupt Handling

When the Program Counter is vectored to the actual inter-

rupt vector in order to execute the interrupt handling rou-

tine, hardware clears the corresponding flag that generated

the interrupt. Some of the interrupt flags can also be

cleared by writing a logic one to the flag bit position(s) to be

cleared.

The AT90S8515 has two 8-bit Interrupt Mask control regis-

ters; GIMSK - General Interrupt Mask register and TIMSK -

Timer/Counter Interrupt Mask register.

When an interrupt occurs, the Global Interrupt Enable I-bit

is cleared (zero) and all interrupts are disabled. The user

software must set (one) the I-bit to enable interrupts.

The General Interrupt Mask Register - GIMSK

Bit

7

6

5

-

4

-

3

-

2

-

1

-

0

-

$3B ($5B)

Read/Write

Initial value

INT1

R/W

0

INT0

R/W

0

GIMSK

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 7 - INT1: External Interrupt Request 1 Enable

or falling edge of the INT1 pin or level sensed. Activity on

the pin will cause an interrupt request even if INT1 is con-

figured as an output. The corresponding interrupt of Exter-

nal Interrupt Request 1 is executed from program memory

address $002. See also “External Interrupts”.

When the INT1 bit is set (one) and the I-bit in the Status

Register (SREG) is set (one), the external pin interrupt is

activated. The Interrupt Sense Control1 bits 1/0 (ISC11 and

ISC10) in the MCU general Control Register (MCUCR)

defines whether the external interrupt is activated on rising

AT90S8515

18

AT90S8515

• Bit 6 - INT0: External Interrupt Request 0 Enable

figured as an output. The corresponding interrupt of Exter-

nal Interrupt Request 0 is executed from program memory

address $001. See also “External Interrupts.”

When the INT0 bit is set (one) and the I-bit in the Status

Register (SREG) is set (one), the external pin interrupt is

activated. The Interrupt Sense Control0 bits 1/0 (ISC01 and

ISC00) in the MCU general Control Register (MCUCR)

defines whether the external interrupt is activated on rising

or falling edge of the INT0 pin or level sensed. Activity on

the pin will cause an interrupt request even if INT0 is con-

• Bits 5..0 - Res: Reserved bits

These bits are reserved bits in the AT90S8515 and always

read as zero.

The General Interrupt Flag Register - GIFR

Bit

7

INTF1

R/W

0

6

INTF0

R/W

0

5

-

4

-

3

-

2

-

1

-

0

-

$3A ($5A)

Read/Write

Initial value

GIFR

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 7 - INTF1: External Interrupt Flag1

the INT0 bit in GIMSK are set (one), the MCU will jump to

the interrupt vector at address $001. The flag is cleared

when the interrupt routine is executed. Alternatively, the

flag can be cleared by writing a logical one to it.

When an event on the INT1 pin triggers an interrupt

request, INTF1 becomes set (one). If the I-bit in SREG and

the INT1 bit in GIMSK are set (one), the MCU will jump to

the interrupt vector at address $002. The flag is cleared

when the interrupt routine is executed. Alternatively, the

flag can be cleared by writing a logical one to it.

• Bits 5..0 - Res: Reserved bits

These bits are reserved bits in the AT90S8515 and always

read as zero.

• Bit 6 - INTF0: External Interrupt Flag0

When an event on the INT0 pin triggers an interrupt

request, INTF0 becomes set (one). If the I-bit in SREG and

The Timer/counter Interrupt Mask Register - TIMSK

Bit

7

TOIE1

R/W

0

6

OCIE1A

R/W

0

5

OCIE1B

R/W

0

4

-

3

TICIE1

R/W

0

2

-

1

TOIE0

R/W

0

-

$39 ($59)

Read/Write

Initial value

TIMSK

R

0

R

0

R

0

• Bit 7 - TOIE1: Timer/Counter1 Overflow Interrupt Enable

When the TOIE1 bit is set (one) and the I-bit in the Status

Register is set (one), the Timer/Counter1 Overflow interrupt

is enabled. The corresponding interrupt (at vector $006) is

executed if an overflow in Timer/Counter1 occurs. The

Overflow Flag (Timer/Counter1) is set (one) in the

Timer/Counter Interrupt Flag Register - TIFR. When

Timer/Counter1 is in PWM mode, the Timer Overflow flag

is set when the counter changes counting direction at

$0000.

occurs. The CompareB Flag in Timer/Counter1 is set (one)

in the Timer/Counter Interrupt Flag Register - TIFR.

• Bit 4 - Res: Reserved bit

This bit is a reserved bit in the AT90S8515 and always

reads zero.

• Bit 3 - TICIE1: Timer/Counter1 Input Capture Interrupt

Enable

When the TICIE1 bit is set (one) and the I-bit in the Status

Register is set (one), the Timer/Counter1 Input Capture

Event Interrupt is enabled. The corresponding interrupt (at

vector $003) is executed if a capture-triggering event

occurs on pin 31, ICP. The Input Capture Flag in

Timer/Counter1 is set (one) in the Timer/Counter Interrupt

Flag Register - TIFR.

• Bit 6 - OCE1A:Timer/Counter1 Output CompareA Match

Interrupt Enable

When the OCIE1A bit is set (one) and the I-bit in the Status

Register is set (one), the Timer/Counter1 CompareA Match

interrupt is enabled. The corresponding interrupt (at vector

$004) is executed if a CompareA match in Timer/Counter1

occurs. The CompareA Flag in Timer/Counter1 is set (one)

in the Timer/Counter Interrupt Flag Register - TIFR.

• Bit 2 - Res: Reserved bit

This bit is a reserved bit in the AT90S8515 and always

reads zero.

• Bit 1 - TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is set (one) and the I-bit in the Status

Register is set (one), the Timer/Counter0 Overflow interrupt

is enabled. The corresponding interrupt (at vector $008) is

executed if an overflow in Timer/Counter0 occurs. The

• Bit 5 - OCIE1B:Timer/Counter1 Output CompareB Match

Interrupt Enable

When the OCIE1B bit is set (one) and the I-bit in the Status

Register is set (one), the Timer/Counter1 CompareB Match

interrupt is enabled. The corresponding interrupt (at vector

$005) is executed if a CompareB match in Timer/Counter1

19

• Bit 0 - Res: Reserved bit

This bit is a reserved bit in the AT90S8515 and always

Overflow Flag (Timer0) is set (one) in the Timer/Counter

Interrupt Flag Register - TIFR.

reads zero.

The Timer/Counter Interrupt Flag Register - TIFR

Bit

7

TOV1

R/W

0

6

OCF1A

R/W

0

5

OCIFB

R/W

0

4

-

3

2

-

1

TOV0

R/W

0

-

$38 ($58)

Read/Write

Initial value

ICF1

R/W

0

TIFR

R

0

R

0

R

0

• Bit 7 - TOV1: Timer/Counter1 Overflow Flag

• Bit 1 - TOV: Timer/Counter0 Overflow Flag

The TOV1 is set (one) when an overflow occurs in

Timer/Counter1. TOV1 is cleared by hardware when exe-

cuting the corresponding interrupt handling vector. Alterna-

tively, TOV1 is cleared by writing a logic one to the flag.

When the I-bit in SREG, and TOIE1 (Timer/Counter1 Over-

flow Interrupt Enable), and TOV1 are set (one), the

Timer/Counter1 Overflow Interrupt is executed. In PWM

mode, this bit is set when Timer/Counter1 changes count-

ing direction at $0000.

The bit TOV0 is set (one) when an overflow occurs in

Timer/Counter0. TOV0 is cleared by hardware when exe-

cuting the corresponding interrupt handling vector. Alterna-

tively, TOV0 is cleared by writing a logic one to the flag.

When the SREG I-bit, and TOIE0 (Timer/Counter0 Over-

flow Interrupt Enable), and TOV0 are set (one), the

Timer/Counter0 Overflow interrupt is executed.

• Bit 0 - Res: Reserved bit

This bit is a reserved bit in the AT90S8515 and always

reads zero.

• Bit 6 - OCF1A: Output Compare Flag 1A

The OCF1A bit is set (one) when compare match occurs

between the Timer/Counter1 and the data in OCR1A - Out-

put Compare Register 1A. OCF1A is cleared by hardware

when executing the corresponding interrupt handling vec-

tor. Alternatively, OCF1A is cleared by writing a logic one to

the flag. When the I-bit in SREG, and OCIE1A

(Timer/Counter1 Compare match InterruptA Enable), and

the OCF1A are set (one), the Timer/Counter1 Compare

match Interrupt is executed.

External Interrupts

The external interrupts are triggered by the INT1 and INT0

pins. Observe that, if enabled, the interrupts will trigger

even if the INT0/INT1 pins are configured as outputs. This

feature provides a way of generating a software interrupt.

The external interrupts can be triggered by a falling or ris-

ing edge or a low level. This is set up as indicated in the

specification for the MCU Control Register - MCUCR.

When the external interrupt is enabled and is configured as

level triggered, the interrupt will trigger as long as the pin is

held low.

• Bit 5 - OCF1B: Output Compare Flag 1B

The OCF1B bit is set (one) when compare match occurs

between the Timer/Counter1 and the data in OCR1B - Out-

put Compare Register 1B. OCF1B is cleared by hardware

when executing the corresponding interrupt handling vec-

tor. Alternatively, OCF1B is cleared by writing a logic one to

the flag.. When the I-bit in SREG, and OCIE1B

(Timer/Counter1 Compare match InterruptB Enable), and

the OCF1B are set (one), the Timer/Counter1 Compare

match Interrupt is executed.

The external interrupts are set up as described in the spec-

ification for the MCU Control Register - MCUCR.

Interrupt Response Time

The interrupt execution response for all the enabled AVR

interrupts is 4 clock cycles minimum. 4 clock cycles after

the interrupt flag has been set, the program vector address

for the actual interrupt handling routine is executed. During

this 4 clock cycle period, the Program Counter (2 bytes) is

pushed onto the Stack, and the Stack Pointer is decre-

mented by 2. The vector is a relative jump to the interrupt

routine, and this jump takes 2 clock cycles. If an interrupt

occurs during execution of a multi-cycle instruction, this

instruction is completed before the interrupt is served.

• Bit 4 - Res: Reserved bit

This bit is a reserved bit in the AT90S8515 and always

reads zero.

• Bit 3 - ICF1: - Input Capture Flag 1

The ICF1 bit is set (one) to flag an input capture event, indi-

cating that the Timer/Counter1 value has been transferred

to the input capture register - ICR1. ICF1 is cleared by

hardware when executing the corresponding interrupt han-

dling vector. Alternatively, ICF1 is cleared by writing a logic

one to the flag.

A return from an interrupt handling routine (same as for a

subroutine call routine) takes 4 clock cycles. During these 4

clock cycles, the Program Counter (2 bytes) is popped

back from the Stack, and the Stack Pointer is incremented

by 2. When the AVR exits from an interrupt, it will always

return to the main program and execute one more instruc-

tion before any pending interrupt is served.

• Bit 2 - Res: Reserved bit

This bit is a reserved bit in the AT90S8515 and always

reads zero.

Note that the Status Register - SREG - is not handled by

the AVR hardware, neither for interrupts nor for subrou-

AT90S8515

20

AT90S8515

tines. For the interrupt handling routines requiring a storage

of the SREG, this must be performed by user software.

of Timer/Counter1) the interrupt flag is set when the event

occurs. If the interrupt flag is cleared and the interrupt con-

dition persists, the flag will not be set until the event occurs

the next time.

For Interrupts triggered by events that can remain static

(E.g. the Output Compare Register1 A matching the value

MCU Control Register - MCUCR

The MCU Control Register contains control bits for general MCU functions.

Bit

7

6

SRW

R/W

0

5

SE

R/W

0

4

SM

R/W

0

3

ISC11

R/W

0

2

ISC10

R/W

0

1

ISC01

R/W

0

ISC00

R/W

0

$35 ($55)

Read/Write

Initial value

SRE

R/W

0

MCUCR

• Bit 7 - SRE: External SRAM Enable

external INT1 pin that activate the interrupt are defined in

the following table:

When the SRE bit is set (one), the external data SRAM is

enabled, and the pin functions AD0-7 (Port A), A8-15 (Port

C), WR and RD (Port D) are activated as the alternate pin

functions. Then the SRE bit overrides any pin direction set-

tings in the respective data direction registers. See “The

SRAM Data Memory - Internal and External” for description

of the External SRAM pin functions. When the SRE bit is

cleared (zero), the external data SRAM is disabled, and the

normal pin and data direction settings are used.

Table 4. Interrupt 1 Sense Control

ISC11

ISC10

Description

The low level of INT1 generates an

interrupt request.

0

1

0

1

0

Reserved

The falling edge of INT1 generates an

interrupt request.

• Bit 6 - SRW: External SRAM Wait State

When the SRW bit is set (one), a one cycle wait state is

inserted in the external data SRAM access cycle. When the

SRW bit is cleared (zero), the external data SRAM access

is executed with the normal three-cycle scheme. See Fig-

ure 23: External Data SRAM Memory Cycles without Wait

State and Figure 24: External Data SRAM Memory Cycles

with Wait State.

The rising edge of INT1 generates an

interrupt request.

1

Note:

When changing the ISC11/ISC10 bits, INT1 must be dis-

abled by clearing its Interrupt Enable bit in the GIMSK

Register. Otherwise an interrupt can occur when the bits

are changed.

• Bit 1, 0 - ISC01, ISC00: Interrupt Sense Control 0 bit 1 and

bit 0

• Bit 5 - SE: Sleep Enable

The SE bit must be set (one) to make the MCU enter the

sleep mode when the SLEEP instruction is executed. To

avoid the MCU entering the sleep mode unless it is the pro-

grammers purpose, it is recommended to set the Sleep

Enable SE bit just before the execution of the SLEEP

instruction.

The External Interrupt 0 is activated by the external pin

INT0 if the SREG I-flag and the corresponding interrupt

mask is set. The level and edges on the external INT0 pin

that activate the interrupt are defined in the following table:

Table 5. Interrupt 0 Sense Control

• Bit 4 - SM: Sleep Mode

ISC01

ISC00

Description

This bit selects between the two available sleep modes.

When SM is cleared (zero), Idle Mode is selected as Sleep

Mode. When SM is set (one), Power Down mode is

selected as sleep mode. For details, refer to the paragraph

“Sleep Modes” below.

The low level of INT0 generates an

interrupt request.

0

1

0

1

0

Reserved

The falling edge of INT0 generates an

interrupt request.

• Bit 3, 2 - ISC11, ISC10: Interrupt Sense Control 1 bit 1 and

bit 0

The External Interrupt 1 is activated by the external pin

INT1 if the SREG I-flag and the corresponding interrupt

mask in the GIMSK is set. The level and edges on the

The rising edge of INT0 generates an

interrupt request.

1

Note:

When changing the ISC10/ISC00 bits, INT0 must be dis-

abled by clearing its Interrupt Enable bit in the GIMSK

Register. Otherwise an interrupt can occur when the bits

are changed.

21

Status register - ACSR. This will reduce power consump-

tion in Idle Mode.

Sleep Modes

To enter the sleep modes, the SE bit in MCUCR must be

set (one) and a SLEEP instruction must be executed. If an

enabled interrupt occurs while the MCU is in a sleep mode,

the MCU awakes, executes the interrupt routine, and

resumes execution from the instruction following SLEEP.

The contents of the register file, SRAM and I/O memory are

unaltered. If a reset occurs during sleep mode, the MCU

wakes up and executes from the Reset vector.

Power Down Mode

When the SM bit is set (one), the SLEEP instruction forces

the MCU into the Power Down Mode. In this mode, the

external oscillator is stopped. The user can select whether

the watchdog shall be enabled during power-down mode. If

the watchdog is enabled, it will wake up the MCU when the

Watchdog Time-out period expires. If the watchdog is dis-

abled, only an external reset or an external level triggered

interrupt can wake up the MCU.

Idle Mode

When the SM bit is cleared (zero), the SLEEP instruction

forces the MCU into the Idle Mode stopping the CPU but

allowing Timer/Counters, Watchdog and the interrupt sys-

tem to continue operating. This enables the MCU to wake

up from external triggered interrupts as well as internal

ones like Timer Overflow interrupt and watchdog reset. If

wakeup from the Analog Comparator interrupt is not

required, the analog comparator can be powered down by

setting the ACD-bit in the Analog Comparator Control and

Timer / Counters

The AT90S8515 provides two general purpose

Timer/Counters - one 8-bit T/C and one 16-bit T/C. The

Timer/Counters have individual prescaling selection from

the same 10-bit prescaling timer. Both Timer/Counters can

either be used as a timer with an internal clock timebase or

as a counter with an external pin connection which triggers

the counting.

The Timer/Counter Prescaler

Figure 31 shows the general Timer/Counter prescaler.

Figure 31. Timer/Counter Prescaler

The four different prescaled selections are: CK/8, CK/64,

CK/256 and CK/1024 where CK is the oscillator clock. For

the two Timer/Counters, added selections as CK, external

source and stop, can be selected as clock sources.

AT90S8515

22

AT90S8515

The 8-Bit Timer/Counter0

Figure 32 shows the block diagram for Timer/Counter0.

When Timer/Counter0 is externally clocked, the external

signal is synchronized with the oscillator frequency of the

CPU. To assure proper sampling of the external clock, the

minimum time between two external clock transitions must

be at least one internal CPU clock period. The external

clock signal is sampled on the rising edge of the internal

CPU clock.

The 8-bit Timer/Counter0 can select clock source from CK,

prescaled CK, or an external pin. In addition it can be

stopped as described in the specification for the

Timer/Counter0 Control Register - TCCR0. The overflow

status flag is found in the Timer/Counter Insterrupt Flag

Register - TIFR. Control signals are found in the

Timer/Counter0 Control Register - TCCR0. The interrupt

enable/disable settings for Timer/Counter0 are found in the

Timer/Counter Interrupt Mask Register - TIMSK.

The 8-bit Timer/Counter0 features both a high resolution

and a high accuracy usage with the lower prescaling oppor-

tunities. Similarly, the high prescaling opportunities make

the Timer/Counter0 useful for lower speed functions or

exact timing functions with infrequent actions.

Figure 32. Timer/Counter0 Block Diagram

The Timer/Counter0 Control Register - TCCR0

Bit

7

-

6

-

5

-

4

-

3

-

2

CS02

R/W

0

1

CS01

R/W

0

CS00

R/W

0

$33 ($53)

Read/Write

Initial value

TCCR0

R

0

R

0

R

0

R

0

R

0

• Bits 7,6 - Res: Reserved bits

These bits are reserved bits in the AT90S8515 and always

read zero.

• Bits 2,1,0 - CS02, CS01, CS00: Clock Select0, bit 2,1 and 0

The Clock Select0 bits 2,1 and 0 define the prescaling

source of Timer0.

23

Table 6. Clock 0 Prescale Select

CS02

CS01

CS00

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Stop, the Timer/Counter0 is stopped.

CK

CK / 8

CK / 64

CK / 256

CK / 1024

External Pin T0, falling edge

External Pin T0, rising edge

The Stop condition provides a Timer Enable/Disable func-

tion. The CK down divided modes are scaled directly from

the CK oscillator clock. If the external pin modes are used,

the corresponding setup must be performed in the actual

data direction control register (cleared to zero gives an

input pin).

The Timer Counter 0 - TCNT0

Bit

7

MSB

R/W

0

6

5

4

3

2

1

0

$32 ($52)

Read/Write

Initial value

LSB

R/W

0

TCNT0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Timer/Counter0 is realized as an up-counter with read

and write access. If the Timer/Counter0 is written and a

clock source is present, the Timer/Counter0 continues

counting in the clock cycle following the write operation.

AT90S8515

24

AT90S8515

The 16-Bit Timer/Counter1

Figure 33 shows the block diagram for Timer/Counter1.

Figure 33. Timer/Counter1 Block Diagram

The 16-bit Timer/Counter1 can select clock source from

CK, prescaled CK, or an external pin. In addition it can be

stopped as described in the specification for the

Timer/Counter1 Control Registers - TCCR1A and

TCCR1B. The different status flags (overflow, compare

match and capture event) and control signals are found in

the Timer/Counter1 Control Registers - TCCR1A and

TCCR1B. The interrupt enable/disable settings for

Timer/Counter1 are found in the Timer/Counter Interrupt

Mask Register - TIMSK.

tunities. Similarly, the high prescaling opportunities makes

the Timer/Counter1 useful for lower speed functions or

exact timing functions with infrequent actions.

The Timer/Counter1 supports two Output Compare func-

tions using the Output Compare Register 1 A and B -

OCR1A and OCR1B as the data sources to be compared

to the Timer/Counter1 contents. The Output Compare func-

tions include optional clearing of the counter on compareA

match, and actions on the Output Compare pins on both

compare matches.

When Timer/Counter1 is externally clocked, the external

signal is synchronized with the oscillator frequency of the

CPU. To assure proper sampling of the external clock, the

minimum time between two external clock transitions must

be at least one internal CPU clock period. The external

clock signal is sampled on the rising edge of the internal

CPU clock.

Timer/Counter1 can also be used as a 8, 9 or 10-bit Pulse

With Modulator. In this mode the counter and the

OCR1A/OCR1B registers serve as a dual glitch-free stand-

alone PWM with centered pulses. Refer to page 33 for a

detailed description on this function.

The Input Capture function of Timer/Counter1 provides a

capture of the Timer/Counter1 contents to the Input Cap-

ture Register - ICR1, triggered by an external event on the

Input Capture Pin - ICP. The actual capture event settings

The 16-bit Timer/Counter1 features both a high resolution

and a high accuracy usage with the lower prescaling oppor-

25

are defined by the Timer/Counter1 Control Register -

TCCR1B. In addition, the Analog Comparator can be set to

trigger the Input Capture. Refer to the section, “The Analog

Comparator”, for details on this. The ICP pin logic is shown

in Figure 34.

Figure 34. ICP Pin Schematic Diagram

If the noise canceler function is enabled, the actual trigger

condition for the capture event is monitored over 4 samples

before the capture is activated. The input pin signal is sam-

pled at XTAL clock frequency.

The Timer/Counter1 Control Register A - TCCR1A

Bit

7

COM1A1

R/W

6

COM1A0

R/W

5

COM1B1

R/W

4

COM1B0

R/W

3

-

2

-

1

PWM11

R/W

0

PWM10

R/W

0

$2F ($4F)

Read/Write

Initial value

TCCR1A

R

0

R

0

• Bits 7,6 - COM1A1, COM1A0: Compare Output Mode1A,

bits 1 and 0

rupt Enable bits in the TIMSK Register. Otherwise an

interrupt can occur when the bits are changed.

The COM1A1 and COM1A0 control bits determine any out-

put pin action following a compare match in

Timer/Counter1. Any output pin actions affect pin OC1A -

Output CompareA pin 1. Since this is an alternative func-

tion to an I/O port, the corresponding direction control bit

must be set (one) to control an output pin. The control con-

figuration is shown in Table 7.

• Bits 3..2 - Res: Reserved bits

These bits are reserved bits in the AT90S8515 and always

read zero.

• Bits 1..0 - PWM11, PWM10: Pulse Width Modulator Select

Bits

These bits select PWM operation of Timer/Counter1 as

specified in Table 8. This mode is described on page 29.

• Bits 5,4 - COM1B1, COM1B0: Compare Output Mode1B,

bits 1 and 0

Table 8. PWM Mode Select

PWM11 PWM10 Description

PWM operation of Timer/Counter1 is

The COM1B1 and COM1B0 control bits determine any out-

put pin action following a compare match in

Timer/Counter1. Any output pin actions affect pin OC1B -

Output CompareB. The following control configuration is

given:

0

disabled

0

1

0

1

Timer/Counter1 is an 8-bit PWM

Timer/Counter1 is a 9-bit PWM

Timer/Counter1 is a 10-bit PWM

Table 7. Compare 1 Mode Select

COM1X1 COM1X0 Description

Timer/Counter1 disconnected from

0

output pin OC1X

0

1

0

1

Toggle the OC1X output line.

Clear the OC1X output line (to zero).

Set the OC1X output line (to one).

X = A or B

In PWM mode, these bits have a different function. Refer to

Table 11 for a detailed description.

When changing the COM1X1/COM1X0 bits, Output Com-

pare Interrupts 1 must be disabled by clearing their Inter-

AT90S8515

26

AT90S8515

The Timer/Counter1 Control Register B - TCCR1B

Bit

7

ICNC1

R/W

0

6

ICES1

R/W

0

5

-

4

-

3

CTC1

R/W

0

2

CS12

R/W

0

1

CS11

R/W

0

$2E ($4E)

Read/Write

Initial value

CS10

R/W

0

TCCR1B

R

0

R

0

• Bit 7 - ICNC1: Input Capture1 Noise Canceler (4 CKs)

... | C-1 | C | C+1 | 0 | 1 | ...

When the ICNC1 bit is cleared (zero), the input capture trig-

ger noise canceler function is disabled. The input capture is

triggered at the first rising/falling edge sampled on the ICP -

input capture pin - as specified. When the ICNC1 bit is set

(one), four successive samples are measures on the ICP -

input capture pin, and all samples must be high/low accord-

ing to the input capture trigger specification in the ICES1

bit. The actual sampling frequency is XTAL clock fre-

quency.

When the prescaler is set to divide by 8, the timer will count

like this:

... | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, C, C, C, C,

C, C, C | C+1, 0, 0, 0, 0, 0, 0, 0, 0 | ...

In PWM mode, this bit has no effect.

• Bits 2,1,0 - CS12, CS11, CS10: Clock Select1, bit 2,1 and 0

The Clock Select1 bits 2,1 and 0 define the prescaling

source of Timer/Counter1.

• Bit 6 - ICES1: Input Capture1 Edge Select

Table 9. Clock 1 Prescale Select

While the ICES1 bit is cleared (zero), the Timer/Counter1

contents are transferred to the Input Capture Register -

ICR1 - on the falling edge of the input capture pin - ICP.

While the ICES1 bit is set (one), the Timer/Counter1 con-

tents are transferred to the Input Capture Register - ICR1 -

on the rising edge of the input capture pin - ICP.

CS12 CS11 CS10 Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Stop, the Timer/Counter1 is stopped.

CK

CK / 8

• Bits 5, 4 - Res: Reserved bits

These bits are reserved bits in the AT90S8515 and always

read zero.

CK / 64

CK / 256

CK / 1024

• Bit 3 - CTC1: Clear Timer/Counter1 on Compare Match

When the CTC1 control bit is set (one), the Timer/Counter1

is reset to $0000 in the clock cycle after a compareA

match. If the CTC1 control bit is cleared, Timer/Counter1

continues counting and is unaffected by a compare match.

Since the compare match is detected in the CPU clock

cycle following the match, this function will behave differ-

ently when a prescaling higher than 1 is used for the timer.

When a prescaling of 1 is used, and the compareA register

is set to C, the timer will count as follows i CTC1 is set:

External Pin T1, falling edge

External Pin T1, rising edge

The Stop condition provides a Timer Enable/Disable func-

tion. The CK down divided modes are scaled directly from

the CK oscillator clock. If the external pin modes are used,

the corresponding setup must be performed in the actual

direction control register (cleared to zero gives an input

pin).

The Timer/Counter1 - TCNT1H AND TCNT1L

Bit

15

14

13

12

11

10

9

8

$2D ($4D)

$2C ($4C)

MSB

TCNT1H

TCNT1L

LSB

0

7

R/W

0

6

R/W

0

5

R/W

0

4

R/W

0

3

R/W

0

2

R/W

0

1

R/W

0

Read/Write

Initial value

R/W

0

This 16-bit register contains the prescaled value of the 16-

bit Timer/Counter1. To ensure that both the high and low

bytes are read and written simultaneously when the CPU

accesses these registers, the access is performed using an

8-bit temporary register (TEMP). This temporary register is

also used when accessing OCR1A, OCR1B and ICR1. If

the main program and also interrupt routines perform

access to registers using TEMP, interrupts must be dis-

abled during access from the main program.

• TCNT1 Timer/Counter1 Write:

When the CPU writes to the high byte TCNT1H, the

written data is placed in the TEMP register. Next, when

the CPU writes the low byte TCNT1L, this byte of data

is combined with the byte data in the TEMP register,

27

and all 16 bits are written to the TCNT1

Timer/Counter1 register simultaneously. Conse-

quently, the high byte TCNT1H must be accessed first

for a full 16-bit register write operation.

TCNT1H, the CPU receives the data in the TEMP reg-

ister. Consequently, the low byte TCNT1L must be

accessed first for a full 16-bit register read operation.

The Timer/Counter1 is realized as an up or up/down (in

PWM mode) counter with read and write access. If

Timer/Counter1 is written to and a clock source is selected,

the Timer/Counter1 continues counting in the timer clock

cycle after it is preset with the written value.

• TCNT1 Timer/Counter1 Read:

When the CPU reads the low byte TCNT1L, the data of

the low byte TCNT1L is sent to the CPU and the data of

the high byte TCNT1H is placed in the TEMP register.

When the CPU reads the data in the high byte

Timer/Counter1 Output Compare Register - OCR1AH AND OCR1AL

Bit

15

14

13

12

11

10

9

8

$2B ($4B)

$2A ($4A)

MSB

OCR1AH

OCR1AL

LSB

0

7

R/W

0

6

R/W

0

5

R/W

0

4

R/W

0

3

R/W

0

2

R/W

0

1

R/W

0

Read/Write

Initial value

R/W

0

Timer/Counter1 Output Compare Register - OCR1BH AND OCR1BL

Bit

15

14

13

12

11

10

9

8

$29 ($49)

$28 ($48)

MSB

OCR1BH

OCR1BL

LSB

0

7

R/W

0

6

R/W

0

5

R/W

0

4

R/W

0

3

R/W

0

2

R/W

0

1

R/W

0

Read/Write

Initial value

R/W

0

The output compare registers are 16-bit read/write regis-

ters.

Since the Output Compare Registers - OCR1A and

OCR1B - are 16-bit registers, a temporary register TEMP is

used when OCR1A/B are written to ensure that both bytes

are updated simultaneously. When the CPU writes the high

byte, OCR1AH or OCR1BH, the data is temporarily stored

in the TEMP register. When the CPU writes the low byte,

OCR1AL or OCR1BL, the TEMP register is simultaneously

written to OCR1AH or OCR1BH. Consequently, the high

byte OCR1AH or OCR1BH must be written first for a full

16-bit register write operation.

The Timer/Counter1 Output Compare Registers contain

the data to be continuously compared with Timer/Counter1.

Actions on compare matches are specified in the

Timer/Counter1 Control and Status register.A compare

match does only occur if Timer/Counter1 counts to the

OCR value. A software write that sets TCNT1 and OCR1A

or OCR1B to the same value does not generate a compare

match.

The TEMP register is also used when accessing TCNT1,

and ICR1. If the main program and also interrupt routines

perform access to registers using TEMP, interrupts must

be disabled during access from the main program.

A compare match will set the compare interrupt flag in the

CPU clock cycle following the compare event.

AT90S8515

28

AT90S8515

The Timer/Counter1 Input Capture Register - ICR1H AND ICR1L

Bit

15

14

13

12

11

10

9

8

$25 ($45)

$24 ($44)

MSB

ICR1H

LSB

0

ICR1L

7

R

0

6

R

0

5

R

0

4

R

0

3

R

0

2

R

0

1

R

0

Read/Write

Initial value

R

0

The input capture register is a 16-bit read-only register.

Table 11. Compare1 Mode Select in PWM Mode

When the rising or falling edge (according to the input cap-

ture edge setting - ICES1) of the signal at the input capture

pin - ICP - is detected, the current value of the

Timer/Counter1 is transferred to the Input Capture Register

- ICR1. At the same time, the input capture flag - ICF1 - is

set (one).

COM1X1 COM1X0 Effect on OCX1

0

1

Not connected

Cleared on compare match,

1

0

upcounting. Set on compare match,

downcounting (non-inverted PWM).

Since the Input Capture Register - ICR1 - is a 16-bit regis-

ter, a temporary register TEMP is used when ICR1 is read

to ensure that both bytes are read simultaneously. When

the CPU reads the low byte ICR1L, the data is sent to the

CPU and the data of the high byte ICR1H is placed in the

TEMP register. When the CPU reads the data in the high

byte ICR1H, the CPU receives the data in the TEMP regis-

ter. Consequently, the low byte ICR1L must be accessed

first for a full 16-bit register read operation.

Cleared on compare match,

downcounting. Set on compare

match, upcounting (inverted PWM).

1

Note:

X = A or B

Note that in the PWM mode, the 10 least significant

OCR1A/OCR1B bits, when written, are transferred to a

temporary location. They are latched when Timer/Counter1

reaches the value TOP. This prevents the occurrence of

odd-length PWM pulses (glitches) in the event of an unsyn-

chronized OCR1A/OCR1B write. See Figure 35 for an

example.

The TEMP register is also used when accessing TCNT1,

OCR1A and OCR1B. If the main program and also interrupt

routines perform access to registers using TEMP, inter-

rupts must be disabled during access from the main pro-

gram.

Timer/Counter1 In PWM Mode

When the PWM mode is selected, Timer/Counter1 and the

Output Compare Register1A - OCR1A and the Output

Compare Register1B - OCR1B, form a dual 8, 9 or 10-bit,

free-running, glitch-free and phase correct PWM with out-

puts on the PD5(OC1A) and OC1B pins. Timer/Counter1

acts as an up/down counter, counting up from $0000 to

TOP (see Table 10) , when it turns and counts down again

to zero before the cycle is repeated. When the counter

value matches the contents of the 10 least significant bits

of OCR1A or OCR1B, the PD5(OC1A)/OC1B pins are set

or cleared according to the settings of the

COM1A1/COM1A0 or COM1B1/COM1B0 bits in the

Timer/Counter1 Control Register TCCR1A. Refer to Table

11 for details.

Table 10. Timer TOP Values and PWM Frequency

PWM Resolution

Timer TOP value

$00FF (255)

Frequency

_TC1/510

8-bit

9-bit

f

$01FF (511)

f

_TC1/1022

_TC1/2046

10-bit

$03FF(1023)

29

Figure 35. Effects on Unsynchronized OCR1 Latching

During the time between the write and the latch operation,

a read from OCR1A or OCR1B will read the contents of the

temporary location. This means that the most recently writ-

ten value always will read out of OCR1A/B

cutes from the reset vector. For timing details on the

Watchdog reset, refer to page 18.

To prevent unintentional disabling of the watchdog, a spe-

cial turn-off secuence must be followed when the watchdog

is disabled.Refer to the description of the Watchdog Timer

Control Register for details.

When OCR1 contains $0000 or TOP, the output

OC1A/OC1B is held low or high according to the settings of

COM1A1/COM1A0 or COM1B1/COM1B0. This is shown in

Table 12:

Figure 36. Watchdog Timer

Table 12. PWM Outputs OCR1X = $0000 or TOP

COM1X1

COM1X0

OCR1X

$0000

TOP

Output OC1X

1

0

1

L

H

L

$0000

TOP

Note:

X = A or B

In PWM mode, the Timer Overflow Flag1, TOV1, is set

when the counter changes direction at $0000. Timer Over-

flow Interrupt1 operates exactly as in normal Timer/Counter

mode, i.e. it is executed when TOV1 is set provided that

Timer Overflow Interrupt1 and global interrupts are

enabled. This does also apply to the Timer Output

Compare1 flags and interrupts.

The Watchdog Timer

The Watchdog Timer is clocked from a separate on-chip

oscillator which runs at 1MHz This is the typical value at

V_CC= 5V. See characterization data for typical values at

other V_CClevels. By controlling the Watchdog Timer pres-

caler, the Watchdog reset interval can be adjusted from

16K to 2,048K cycles (nominally 16 - 2048 ms). The WDR -

Watchdog Reset - instruction resets the Watchdog Timer.

Eight different clock cycle periods can be selected to deter-

mine the reset period. If the reset period expires without

another Watchdog reset, the AT90S8515 resets and exe-

AT90S8515

30

AT90S8515

The Watchdog Timer Control Register - WDTCR

Bit

7

-

6

-

5

-

4

WDTOE

R/W

0

3

WDE

R/W

0

2

WDP2

R/W

0

1

WDP1

R/W

0

$21 ($41)

Read/Write

Initial value

WDP0

R/W

0

WDTCR

R

0

R

0

R

0

• Bits 7..5 - Res: Reserved bits

These bits are reserved bits in the AT90S8515 and will

always read as zero.

EEPROM Read/Write Access

The EEPROM access registers are accessible in the I/O

space.

• Bit 4 - WDTOE: Watch Dog Turn-Off Enable

The write access time is in the range of 2.5 - 4ms, depend-

ing on the V_CCvoltages. A self-timing function, however,

lets the user software detect when the next byte can be

written. If the user code contains code that writes the

EEPROM, some precaution must be taken. In heavily fil-

tered power supplies, V_CCis likely to rise or fall slowly on

power-up/down. This causes the device for some period of

time to run at a voltage lower than specified as minimum for

the clock frequency used. CPU operation under these con-

ditions is likely cause the program counter to perform unin-

tentional jumps and eventually execute the EEPROM write

code. To secure EEPROM integrity, the user is advised to

use an external under-voltage reset circuit in this case.

This bit must be set (one) when the WDE bit is cleared.

Otherwise, the watchdog will not be disabled. Once set,

hardware will clear this bit to zero after four clock cycles.

Refer to the description of the WDE bit for a watchdog dis-

able procedure.

• Bit 3 - WDE: Watch Dog Enable

When the WDE is set (one) the Watchdog Timer is

enabled, and if the WDE is cleared (zero) the Watchdog

Timer function is disabled. WDE can only be cleared if the

WDTOE bit is set(one). To disable an enabled watchdog

timer, the following procedure must be followed:

1. In the same operation, write a logical one to

WDTOE and WDE. A logcal one must be written to

WDE even though it is set to one before the disable

operation starts.

In order to prevent unintentional EEPROM writes, a spe-

cific write procedure must be followed. Refer to the descrip-

tion of the EEPROM Control Register for details on this.

2. Within the next four clock cycles, write a logical 0 to

WDE. This disables the watchdog.

When the EEPROM is read or written, the CPU is halted for

two clock cycles before the next instruction is executed.

• Bits 2..0 - WDP2, WDP1, WDP0: Watch Dog Timer Prescaler

2, 1 and 0

The WDP2, WDP1 and WDP0 bits determine the Watch-

dog Timer prescaling when the Watchdog Timer is

enabled. The different prescaling values and their corre-

sponding Timeout Periods are shown in Table 13.

Table 13. Watch Dog Timer Prescale Select

WDP2

WDP1

WDP0

Timeout Period

16K cycles

0

1

0

1

0

1

0

1

0

1

0

1

0

1

32K cycles

64K cycles

128K cycles

256K cycles

512K cycles

1,024K cycles

2,048K cycles

31

The EEPROM Address Register - EEARH and EEARL

Bit

15

14

13

12

11

10

9

8

EEAR8

EEAR0

0

$1F ($3F)

$1E ($3E)

-

EEAR7

7

-

EEAR6

6

-

EEAR5

5

-

EEAR4

4

-

EEAR3

3

-

EEAR2

2

-

EEAR1

1

EEARH

EEARL

Read/Write

Initial value

R/W

8

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

8

0

The EEPROM Address Registers - EEARH and EEARL

specify the EEPROM address in the 512 bytes EEPROM

space. The EEPROM data bytes are addressed linearly

between 0 and 512.

The EEPROM Data Register - EEDR

Bit

7

MSB

R/W

0

6

5

4

3

2

1

0

$1D ($3D)

Read/Write

Initial value

LSB

R/W

0

EEDR

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bits 7..0 - EEDR7..0: EEPROM Data

For the EEPROM write operation, the EEDR register con-

tains the data to be written to the EEPROM in the address

given by the EEAR register. For the EEPROM read opera-

tion, the EEDR contains the data read out from the

EEPROM at the address given by EEAR.

The EEPROM Control Register - EECR

Bit

7

-

6

-

5

-

4

-

3

-

2

EEMWE

R/W

0

1

EEWE

R/W

0

EERE

R/W

0

$1C ($3C)

Read/Write

Initial value

EECR

R

0

R

0

R

0

R

0

R

0

• Bit 7..3 - Res: Reserved bits

These bits are reserved bits in the AT90S8515 and will

always read as zero.

3. Write new EEPROM data to EEDR (optional)

4. Write a logical one to the EEMWE bit in EECR

5. Within four clock cycles after setting EEMWE, write

a logical one to EEWE.

• Bit 2 - EEMWE: EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to one

causes the EEPROM to be written. When EEMWE is

set(one) setting EEWE will write data to the EEPROM at

the selected address If EEMWE is zero, setting EEWE will

have no effect. When EEMWE has been set (one) by soft-

ware, hardware clears the bit to zero after four clock cycles.

See the description of the EEWE bit for a EEPROM write

procedure.

When the write access time (typically 2.5 ms at V_CC= 5V or

4 ms at V_CC= 2.7V) has elapsed, the EEWE bit is cleared

(zero) by hardware. The user software can poll this bit and

wait for a zero before writing the next byte. When EEWE

has been set, the CPU is halted for two cycles before the

next instruction is executed.

• Bit 0 - EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read

strobe to the EEPROM. When the correct address is set up

in the EEAR register, the EERE bit must be set. When the

EERE bit is cleared (zero) by hardware, requested data is

found in the EEDR register. The EEPROM read access

takes one instruction and there is no need to poll the EERE

bit. When EERE has been set, the CPU is halted for two

cycles before the next instruction is executed.

• Bit 1 - EEWE: EEPROM Write Enable

The EEPROM Write Enable Signal EEWE is the write

strobe to the EEPROM. When address and data are cor-

rectly set up, the EEWE bit must be set to write the value

into the EEPROM. The EEMWE bit must be set when the

logical one is written to EEWE, otherwise no EEPROM

write takes place. The following procedure should be fol-

lowed when writing the EEPROM (the order of steps 2 and

3 is unessential):

The user should poll the EEWE bit before starting the read

operation. If a write operation is in progress when new data

or address is written to the EEPROM I/O registers, the

write operation will be interrupted, and the result is unde-

fined.

1. Wait until EEWE becomes zero.

2. Write new EEPROM address to EEARL and

EEARH (optional)

AT90S8515

32

AT90S8515

The Serial Peripheral Interface - SPI

The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90S8515 and peripheral

devices or between several AT90S8515 devices. The AT90S8515 SPI features include the following:

• Full-Duplex, 3-Wire Synchronous Data Transfer

• Master or Slave Operation

• End of Transmission Interrupt Flag

• Write Collision Flag Protection

• LSB First or MSB First Data Transfer

• Four Programmable Bit Rates

• Wakeup from Idle Mode (Slave Mode Only)

Figure 37. SPI Block Diagram

The interconnection between master and slave CPUs with

SPI is shown in Figure 38. The PB7(SCK) pin is the clock

output in the master mode and is the clock input in the

slave mode. Writing to the SPI data register of the master

CPU starts the SPI clock generator, and the data written

shifts out of the PB5(MOSI) pin and into the PB5(MOSI) pin

of the slave CPU. After shifting one byte, the SPI clock gen-

erator stops, setting the end of transmission flag (SPIF). If

the SPI interrupt enable bit (SPIE) in the SPCR register is

set, an interrupt is requested. The Slave Select input,

PB4(SS), is set low to select an individual SPI device as a

slave. The two shift registers in the Master and the Slave

can be considered as one distributed 16-bit circular shift

register. This is shown in Figure 38. When data is shifted

from the master to the slave, data is also shifted in the

opposite direction, simultaneously. This means that during

one shift cycle, data in the master and the slave are inter-

changed.

33

Figure 38. SPI Master-Slave Interconnection

The system is single buffered in the transmit direction and

double buffered in the receive direction. This means that

characters to be transmitted cannot be written to the SPI

Data Register before the entire shift cycle is completed.

When receiving data, however, a received character must

be read from the SPI Data Register before the next charac-

ter has been completely shifted in. Otherwise, the first char-

acter is lost.

driven low by peripheral circuitry, the SPI system inter-

pretes this as another master selecting the SPI as a slave

and starting to send data to it. To avoid bus contention, the

SPI system takes the following actions:

1. The MSTR bit in SPCR is cleared and the SPI sys-

tem becomes a slave. As a result of the SPI becom-

ing a slave, the MOSI and SCK pins become inputs.

2. The SPIF flag in SPSR is set, and if the SPI inter-

rupt is enabled, the interrupt routine will be exe-

cuted.

When the SPI is enabled, the data direction of the MOSI,

MISO, SCK and SS pins is overriden according to the fol-

lowing table:

Thus, when interrupt-driven SPI transmittal is used in mas-

ter mode, and there exists a possibility that SS is driven

low, the interrupt should always check that the MSTR bit is

still set. Once the MSTR bit has been cleared by a slave

select, it must be set by the user.

Table 14. SPI Pin Overrides

MOSI

MISO

SCK

SS

Direction, Master SPI

User Defined

Input

Direction, Slave SPI

Input

User Defined

Input

When the SPI is configured as a slave, the SS pin is always

input. When SS is held low, the SPI is activated and MISO

becomes an output if configured so by the user. All other

pins are inputs. When SS is driven high, all pins are inputs,

and the SPI is passive, which means that it will not receive

incoming data.

User Defined

Input

SS Pin Functionality

When the SPI is configured as a master (MSTR in SPCR is

set), the user can determine the direction of the SS pin. If

SS is configured as an output, the pin is a general output

pin which does not affect the SPI system. If SS is config-

ured as an input, it must be hold high to ensure Master SPI

operation. If, in master mode, the SS pin is input, and is

Data Modes

There are four combinations of SCK phase and polarity

with respect to serial data, which are determined by control

bits CPHA and CPOL. The SPI data transfer formats are

shown in Figure 39 and Figure 40.

AT90S8515

34

AT90S8515

Figure 39. SPI Transfer Format with CPHA = 0

Figure 40. SPI Transfer Format with CPHA = 1

The SPI Control Register - SPCR

Bit

7

SPIE

R/W

0

6

5

DORD

R/W

0

4

MSTR

R/W

0

3

CPOL

R/W

0

2

CPHA

R/W

1

SPR1

R/W

0

$0D ($2D)

Read/Write

Initial value

SPE

R/W

0

SPR0

R/W

0

SPCR

• Bit 7 - SPIE: SPI Interrupt Enable

• Bit 2 - CPHA: Clock Phase

This bit causes setting of the SPIF bit in the SPSR register

to execute the SPI interrupt provided that global interrupts

are enabled.

Refer to Figure 39 or Figure 40 for the functionality of this

bit.

• Bits 1,0 - SPR1, SPR0: SPI Clock Rate Select 1 and 0

These two bits control the SCK rate of the device config-

ured as a master. SPR1 and SPR0 have no effect on the

slave. The relationship between SCK and the Oscillator

Clock frequency f_clis shown in the following table:

• Bit 6 - SPE: SPI Enable

When the SPE bit is set (one), the SPI is enabled. This bit

must be set to enable any SPI operations.

• Bit 5 - DORD: Data Order

When the DORD bit is set (one), the LSB of the data word

is transmitted first.

Table 15. Relationship Between SCK and the Oscillator

Frequency

When the DORD bit is cleared (zero), the MSB of the data

word is transmitted first.

SPR1

SPR0

SCK Frequency

f_cl/ 4

0

1

0

1

0

1

• Bit 4 - MSTR: Master/Slave Select

f_cl/ 16

This bit selects Master SPI mode when set (one), and

Slave SPI mode when cleared (zero). If SS is configured as

an input and is driven low whil MSTR is set, MSTR will be

cleared, and SPIF in SPSR will become set. The user will

then have to set MSTR to re-enable SPI master mode.

f_cl/ 64

f_cl/ 128

• Bit 3 - CPOL: Clock Polarity

When this bit is set (one), SCK is high when idle. When

CPOL is cleared (zero), SCK is low when idle. Refer to Fig-

ure 39 and Figure 40 for additional information.

35

The SPI Status Register - SPSR

Bit

7

SPIF

R

6

5

-

4

-

3

-

2

-

1

-

0

-

$0E ($2E)

Read/Write

Initial value

WCOL

SPSR

R

0

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 7 - SPIF: SPI Interrupt Flag

reading the SPDR register may be incorrect, and writing to

it will have no effect. The WCOL bit (and the SPIF bit) are

cleared (zero) by first reading the SPI Status Register with

WCOL set (one), and then accessing the SPI Data Regis-

ter.

When a serial transfer is complete, the SPIF bit is set (one)

and an interrupt is generated if SPIE in SPCR is set (one)

and global interrupts are enabled. If SS is an input and is

driven low when the SPI is in master mode, this will also set

the SPIF flag. SPIF is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively,

the SPIF bit is cleared by first reading the SPI status regis-

ter with SPIF set (one), then accessing the SPI Data Regis-

ter (SPDR).

• Bit 5..0 - Res: Reserved bits

These bits are reserved bits in the AT90S8515 and will

always read as zero.

The SPI interface on the AT90S8515 is also used for pro-

gram memory and EEPROM downloading or uploading.

See page 62 for serial programming and verification.

• Bit 6 - WCOL: Write Collision Flag

The WCOL bit is set if the SPI data register (SPDR) is writ-

ten during a data transfer. During data transfer, the result of

The SPI Data Register - SPDR

Bit

7

MSB

R/W

0

6

5

4

3

2

1

0

$0F ($2F)

Read/Write

Initial value

LSB

R/W

0

SPDR

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The SPI Data Register is a read/write register used for data

transfer between the register file and the SPI Shift register.

Writing to the register initiates data transmission. Reading

the register causes the Shift Register Receive buffer to be

read.

AT90S8515

36

AT90S8515

The UART

The AT90S8515 features a full duplex Universal Asynchronous Receiver and Transmitter (UART). The main features are:

• Baud rate generator generates any baud rate

• High baud rates at low XTAL frequencies

• 8 or 9 bits data

• Overrun detection

• Framing Error detection

• False Start Bit detection

• Noise filtering

• Three separate interrupts on TX Complete, TX Data

Register Empty and RX Complete

Data Transmission

A block schematic of the UART transmitter is shown in Figure 41.

Figure 41. UART Transmitter

Data transmission is initiated by writing the data to be

transmitted to the UART I/O Data Register, UDR. Data is

transferred from UDR to the Transmit shift register when:

If the 10(11)-bit Transmitter shift register is empty or when,

data is transferred from UDR to the shift register. At this

time the UDRE (UART Data Register Empty) bit in the

UART Status Register, USR, is set. When this bit is set

(one), the UART is ready to receive the next character. At

the same time as the data is transferred from UDR to the

10(11)-bit shift register, bit 0 of the shift register is cleared

(start bit) and bit 9 or 10 is set (stop bit). If 9 bit data word is

selected (the CHR9 bit in the UART Control Register, UCR

is set), the TXB8 bit in UCR is transferred to bit 9 in the

Transmit shift register.

• A new character has been written to UDR after the stop

bit from the previous character has been shifted out. The

shift register is loaded immediately.

• A new character has been written to UDR before the stop

bit from the previous character has been shifted out. The

shift register is loaded when the stop bit of the character

currently being transmitted has been shifted out.

37

On the Baud Rate clock following the transfer operation to

the shift register, the start bit is shifted out on the TXD pin.

Then follows the data, LSB first. When the stop bit has

been shifted out, the shift register is loaded if any new data

has been written to the UDR during the transmission. Dur-

ing loading, UDRE is set. If there is no new data in the UDR

register to send when the stop bit is shifted out, the UDRE

flag will remain set until UDR is written again. When no new

data has been written, and the stop bit has been present on

TXD for one bit length, the TX Complete Flag, TXC, in USR

is set.

The TXEN bit in UCR enables the UART transmitter when

set (one). When this bit is cleared (zero), the PD1 pin can

be used for general I/O. When TXEN is set, the UART

Transmitter will be connected to PD1, which is forced to be

an output pin regardless of the setting of the DDD1 bit in

DDRD.

Data Reception

Figure 42 shows a block diagram of the UART Receiver.

Figure 42. UART Receiver

The receiver front-end logic samples the signal on the RXD

pin at a frequency 16 times the baud rate. While the line is

idle, one single sample of logical zero will be interpreted as

the falling edge of a start bit, and the start bit detection

sequence is initiated. Let sample 1 denote the first zero-

sample. Following the 1 to 0-transition, the receiver sam-

ples the RXD pin at samples 8, 9 and 10. If two or more of

these three samples are found to be logical ones, the start

bit is rejected as a noise spike and the receiver starts look-

ing for the next 1 to 0-transition.

If however, a valid start bit is detected, sampling of the data

bits following the start bit is performed. These bits are also

sampled at samples 8, 9 and 10. The logical value found in

at least two of the three samples is taken as the bit value.

All bits are shifted into the transmitter shift register as they

are sampled. Sampling of an incoming character is shown

in Figure 43.

AT90S8515

38

AT90S8515

Figure 43. Sampling Received Data

When the stop bit enters the receiver, the majority of the

three samples must be one to accept the stop bit. If two or

more samples are logical zeros, the Framing Error (FE) flag

in the UART Status Register (USR) is set. Before reading

the UDR register, the user should always check the FE bit

to detect Framing Errors.

If, after having received a character, the UDR register has

not been read since the last receive, the OverRun (OR) flag

in UCR is set. This means that the last data byte shifted

into to the shift register could not be transferred to UDR

and has been lost. The OR bit is buffered, and is updated

when the valid data byte in UDR is read. Thus, the user

should always check the OR bit after reading the UDR reg-

ister in order to detect any overruns.

Whether or not a valid stop bit is detected at the end of a

character reception cycle, the data is transferred to UDR

and the RXC flag in USR is set. UDR is in fact two physi-

cally separate registers, one for transmitted data and one

for received data. When UDR is read, the Receive Data

register is accessed, and when UDR is written, the Trans-

mit Data register is accessed. If 9 bit data word is selected

(the CHR9 bit in the UART Control Register, UCR is set),

the RXB8 bit in UCR is loaded with bit 9 in the Transmit

shift register when data is transferred to UDR.

When the RXEN bit in the UCR register is cleared (zero),

the receiver is disabled. This means that the PD0 pin can

be used as a general I/O pin. When RXEN is set, the UART

Receiver will be connected to PD0, which is forced to be an

input pin regardless of the setting of the DDD0 bit in DDRD.

When PD0 is forced to input by the UART, the PORTD0 bit

can still be used to control the pull-up resistor on the pin.

UART Control

The UART I/O Data Register - UDR

Bit

7

MSB

R/W

0

6

5

4

3

2

1

0

$0C ($2C)

Read/Write

Initial value

LSB

R/W

0

UDR

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The UDR register is actually two physically separate regis-

ters sharing the same I/O address. When writing to the reg-

ister, the UART Transmit Data register is written. When

reading from UDR, the UART Receive Data register is

read.

The UART Status Register - USR

Bit

7

RXC

R

6

5

UDRE

R

4

FE

R

3

OR

R

2

-

1

-

0

-

$0B ($2B)

Read/Write

Initial value

TXC

R/W

0

USR

R

0

R

0

R

0

1

0

The USR register is a read-only register providing informa-

tion on the UART Status.

and no new data has been written to UDR. This flag is

especially useful in half-duplex communications interfaces,

where a transmitting application must enter receive mode

and free the communications bus immediately after com-

pleting the transmission.

• Bit 7 - RXC: UART Receive Complete

This bit is set (one) when a received character is trans-

ferred from the Receiver Shift register to UDR. The bit is

set regardless of any detected framing errors. When the

RXCIE bit in UCR is set, the UART Receive Complete

interrupt will be executed when RXC is set(one). RXC is

cleared by reading UDR. When interrupt-driven data recep-

tion is used, the UART Receive Complete Interrupt routine

must read UDR in order to clear RXC, otherwise a new

interrupt will occur once the interrupt routine terminates.

When the TXCIE bit in UCR is set, setting of TXC causes

the UART Transmit Complete interrupt to be executed.

TXC is cleared by hardware when executing the corre-

sponding interrupt handling vector. Alternatively, the TXC

bit is cleared (zero) by writing a logical one to the bit.

• Bit 5 - UDRE: UART Data Register Empty

This bit is set (one) when a character written to UDR is

transferred to the Transmit shift register. Setting of this bit

indicates that the transmitter is ready to receive a new

character for transmission.

• Bit 6 - TXC : UART Transmit Complete

This bit is set (one) when the entire character (including the

stop bit) in the Transmit Shift register has been shifted out

39

• Bit 3 - OR: Overrun

When the UDRIE bit in UCR is set, the UART Transmit

Complete interrupt to be executed as long as UDRE is set.

UDRE is cleared by writing UDR. When interrupt-driven

data transmittal is used, the UART Data Register Empty

Interrupt routine must write UDR in order to clear UDRE,

otherwise a new interrupt will occur once the interrupt rou-

tine terminates.

This bit is set if an Overrun condition is detected, i.e. when

a character already present in the UDR register is not read

before the next character has been shifted into the

Receiver Shift register. The OR bit is buffered, which

means that it will be set once the valid data still in UDRE is

read.

The OR bit is cleared (zero) when data is received and

transferred to UDR.

UDRE is set (one) during reset to indicate that the transmit-

ter is ready.

• Bits 2..0 - Res: Reserved bits

• Bit 4 - FE: Framing Error

These bits are reserved bits in the AT90S8515 and will

always read as zero.

This bit is set if a Framing Error condition is detected, i.e.

when the stop bit of an incoming character is zero.

The FE bit is cleared when the stop bit of received data is

one.

The UART Control Register - UCR

Bit

7

RXCIE

R/W

0

6

TXCIE

R/W

0

5

UDRIE

R/W

0

4

RXEN

R/W

0

3

TXEN

R/W

0

2

CHR9

R/W

0

1

RXB8

R

0

TXB8

W

$0A ($2A)

Read/Write

Initial value

UCR

0

• Bit 7 - RXCIE: RX Complete Interrupt Enable

• Bit 0 - TXB8: Transmit Data Bit 8

When this bit is set (one), a setting of the RXC bit in USR

will cause the Receive Complete interrupt routine to be

executed provided that global interrupts are enabled.

When CHR9 is set (one), TXB8 is the 9th data bit in the

character to be transmitted.

The BAUD Rate Generator

The baud rate generator is a frequency divider which gen-

erates baud-rates according to the following equation:

• Bit 6 - TXCIE: TX Complete Interrupt Enable

When this bit is set (one), a setting of the TXC bit in USR

will cause the Transmit Complete interrupt routine to be

executed provided that global interrupts are enabled.

f_CK

BAUD = ------------------------------------

16(UBRR + 1)

• Bit 5 - UDRIE: UART Data Register Empty Interrupt Enable

When this bit is set (one), a setting of the UDRE bit in USR

will cause the UART Data Register Empty interrupt routine

to be executed provided that global interrupts are enabled.

• BAUD = Baud-Rate

• Bit 4 - RXEN: Receiver Enable

• fck= Crystal Clock frequency

This bit enables the UART receiver when set (one). When

the receiver is disabled, the TXC, OR and FE status flags

cannot become set. If these flags are set, turning off RXEN

does not cause them to be cleared.

• UBRR= Contents of the UART Baud Rate register,

UBRR (0-255)

For standard crystal frequencies, the most commonly used

baud rates can be generated by using the UBRR settings in

Table 16. UBRR values which yield an actual baud rate dif-

fering less than 2% from the target baud rate, are bolded in

the table.

• Bit 3 - TXEN: Transmitter Enable

This bit enables the UART transmitter when set (one).

When disabling the transmitter while transmitting a charac-

ter, the transmitter is not disabled before the character in

the shift register plus any following character in UDR has

been completely transmitted.

• Bit 2 - CHR9: 9 Bit Characters

When this bit is set (one) transmitted and received charac-

ters are 9 bit long plus start and stop bits. The 9th bit is

read and written by using the RXB8 and TXB8 bits in UCR,

respectively. The 9th data bit can be used as an extra stop

bit or a parity bit.

• Bit 1 - RXB8: Receive Data Bit 8

When CHR9 is set (one), RXB8 is the 9th data bit of the

received character.

AT90S8515

40

AT90S8515

Table 16. UBRR Settings at Various Crystal Frequencies

Baud Rate

2400

%Error

0.2

%Error

0.0

%Error

2.4576 MHz

1 MHz

1.8432 MHz

2 MHz

UBRR=

25

12

6

47

23

11

7

51

25

12

8

6

3

0.2

63

31

15

10

7

0.0

3.1

0.0

UBRR=

4800

9600

0.2

0.0

7.5 UBRR=

7.8 UBRR=

22.9 UBRR=

7.8 UBRR=

22.9 UBRR=

84.3 UBRR=

3

2

1

3.7 UBRR=

7.5 UBRR=

7.8 UBRR=

22.9 UBRR=

7.8 UBRR=

14400

19200

28800

38400

57600

76800

115200

5

3

2

1

0

4

6.3

2

1

3

0.0

0

2

1

12.5

0.0

33.3 UBRR=

0.0

1

UBRR=

0

25.0

Baud Rate

2400

%Error

0.0

%Error

0.0

3.2768 MHz

3.6864 MHz

4 MHz

4.608 MHz

UBRR=

84

42

20

13

10

6

4

3

2

1

0.4

0.8

1.6

95

47

23

15

11

7

103

51

25

16

12

8

0.2

119

59

29

19

14

9

4800

9600

0.0

6.7

0.0

6.7

2.1 UBRR=

UBRR=

14400

19200

28800

38400

57600

76800

115200

3.1 UBRR=

UBRR=

0.2

3.7 UBRR=

7.5 UBRR=

7.8 UBRR=

1.6

6.3 UBRR=

12.5 UBRR=

6

3

2

1

7

4

3

2

5

3

2

1

20.0

0.0

Baud Rate

2400

%Error

0.2

%Error

0.0

%Error

-

7.3728 MHz

8 MHz

9.216 MHz

11.059 MHz

UBRR= 287

UBRR=

191

95

47

31

23

15

11

7

0.0

207

103

51

34

25

16

12

8

239

119

59

39

29

19

14

9

UBRR=

4800

9600

0.2

0.8

0.2

0.0

6.7 UBRR=

143

71

47

35

23

17

11

8

0.0

14400

19200

28800

38400

57600

76800

115200

2.1 UBRR=

UBRR=

0.2

3.7 UBRR=

7.5 UBRR=

7.8 UBRR=

6

3

7

4

5

3

UBRR=

0.0

5

The UART BAUD Rate Register - UBRR

Bit

7

MSB

R/W

0

6

5

4

3

2

1

0

$09 ($29)

Read/Write

Initial value

LSB

UBRR

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The UBRR register is an 8-bit read/write register which specifies the UART Baud Rate according to the equation on the

previous page.

41

The Analog Comparator

The analog comparator compares the input values on the

positive pin PB2 (AIN0) and negative pin PB3 (AIN1).

When the voltage on the positive pin PB2 (AIN0) is higher

than the voltage on the negative pin PB3 (AIN1), the Ana-

log Comparator Output, ACO is set (one). The compara-

tor’s output can be set to trigger the Timer/Counter1 Input

Capture function. In addition, the comparator can trigger a

separate interrupt, exclusive to the Analog Comparator.

The user can select Interrupt triggering on comparator out-

put rise, fall or toggle. A block diagram of the comparator

and its surrounding logic is shown in Figure 44.

Figure 44. Analog Comparator Block Diagram

The Analog Comparator Control And Status Register - ACSR

Bit

7

6

-

5

ACO

R

4

ACI

R/W

0

3

ACIE

R/W

0

2

ACIC

R/W

0

1

ACIS1

R/W

0

ACIS0

R/W

0

$08 ($28)

Read/Write

Initial value

ACD

R/W

0

ACSR

R

0

• Bit 7 - ACD: Analog Comparator Disable

• Bit 3 - ACIE: Analog Comparator Interrupt Enable

When this bit is set(one), the power to the analog compara-

tor is switched off. This bit can be set at any time to turn off

the analog comparator. This will reduce power consump-

tion in active and idle mode. When changing the ACD bit,

the Analog Comparator Interrupt must be disabled by clear-

ing the ACIE bit in ACSR. Otherwise an interrupt can occur

when the bit is changed.

When the ACIE bit is set (one) and the I-bit in the Status

Register is set (one), the analog comparator interrupt is

activated. When cleared (zero), the interrupt is disabled.

• Bit 2 - ACIC: Analog Comparator Input Capture Enable

When set (one), this bit enables the Input Capture function

in Timer/Counter1 to be triggered by the analog compara-

tor. The comparator output is in this case directly con-

nected to the Input Capture front-end logic, making the

comparator utilize the noise canceler and edge select fea-

tures of the Timer/Counter1 Input Capture interrupt. When

cleared (zero), no connection between the analog compar-

ator and the Input Capture function is given. To make the

comparator trigger the Timer/Counter1 Input Capture inter-

rupt, the TICIE1 bit in the Timer Interrupt Mask Register

(TIMSK) must be set (one).

• Bit 6 - Res: Reserved bit

This bit is a reserved bit in the AT90S8515 and will always

read as zero.

• Bit 5 - ACO: Analog Comparator Output

ACO is directly connected to the comparator output.

• Bit 4 - ACI: Analog Comparator Interrupt Flag

This bit is set (one) when a comparator output event trig-

gers the interrupt mode defined by ACI1 and ACI0. The

Analog Comparator Interrupt routine is executed if the

ACIE bit is set (one) and the I-bit in SREG is set (one). ACI

is cleared by hardware when executing the corresponding

interrupt handling vector. Alternatively, ACI is cleared by

writing a logic one to the flag.

AT90S8515

42

AT90S8515

• Bits 1,0 - ACIS1, ACIS0: Analog Comparator Interrupt Mode

Select

These bits determine which comparator events that trigger

the Analog Comparator interrupt. The different settings are

shown in Table 17.

Three data memory address locations are allocated for the

Port A, one each for the Data Register - PORTA, $1B($3B),

Data Direction Register - DDRA, $1A($3A) and the Port A

Input Pins - PINA, $19($39). The Port A Input Pins address

is read only, while the Data Register and the Data Direction

Register are read/write.

Table 17. ACIS1/ACIS0 Settings

All port pins have individually selectable pull-up resistors.

The PORT A output buffers can sink 20mA and thus drive

LED displays directly. When pins PA0 to PA7 are used as

inputs and are externally pulled low, they will source cur-

rent if the internal pull-up resistors are activated.

ACIS1 ACIS0 Interrupt Mode

0

1

Comparator Interrupt on Output Toggle

Reserved

Comparator Interrupt on Falling Output

Edge

1

0

1

The PORT A pins have alternate functions related to the

optional external data SRAM. PORT A can be configured to

be the multiplexed low-order address/data bus during

accesses to the external data memory. In this mode, PORT

A has internal pull-up resistors.

Comparator Interrupt on Rising Output

Edge

1

Note:

When changing the ACIS1/ACIS0 bits, The Analog Com-

parator Interrupt must be disabled by clearing its Inter-

rupt Enable bit in the ACSR register. Otherwise an

interrupt can occur when the bits are changed.

When PORT A is set to the alternate function by the SRE -

External SRAM Enable - bit in the MCUCR - MCU Control

Register, the alternate settings override the data direction

register.

I/O-Ports

Port A

PORT A is an 8-bit bi-directional I/O port.

The Port A Data Register - PORTA

Bit

7

PORTA7

R/W

6

PORTA6

R/W

5

PORTA5

R/W

4

PORTA4

R/W

3

PORTA3

R/W

2

PORTA2

R/W

1

PORTA1

R/W

0

PORTA0

R/W

$1B ($3B)

Read/Write

Initial value

PORTA

DDRA

PINA

0

The Port A Data Direction Register - DDRA

Bit

7

DDA7

R/W

0

6

DDA6

R/W

0

5

DDA5

R/W

0

4

DDA4

R/W

0

3

DDA3

R/W

0

2

DDA2

R/W

0

1

DDA1

R/W

0

DDA0

R/W

0

$1A ($3A)

Read/Write

Initial value

The Port A Input Pins Address - PINA

Bit

7

PINA7

R

6

PINA6

R

5

PINA5

R

4

PINA4

R

3

PINA3

R

2

PINA2

R

1

PINA1

R

0

PINA0

R

$19 ($39)

Read/Write

Initial value

Hi-Z

The Port A Input Pins address - PINA - is not a register,

and this address enables access to the physical value on

each Port A pin. When reading PORTA the PORTA Data

Latch is read, and when reading PINA, the logical values

present on the pins are read.

is configured as an input pin. If PORTAn is set (one) when

the pin configured as an input pin, the MOS pull up resistor

is activated. To switch the pull up resistor off, the PORTAn

has to be cleared (zero) or the pin has to be configured as

an output pin.

Port A As General Digital I/O

All 8 bits in PORT A are equal when used as digital I/O

pins.

PAn, General I/O pin: The DDAn bit in the DDRA register

selects the direction of this pin, if DDAn is set (one), PAn is

configured as an output pin. If DDAn is cleared (zero), PAn

43

Table 18. DDAn Effects on PORT A Pins

DDAn

PORTAn

I/O

Pull up

No

Comment

0

1

0

1

0

1

Input

Tri-state (Hi-Z)

Input

Yes

PAn will source current if ext. pulled low.

Push-Pull Zero Output

Push-Pull One Output

Output

No

n: 7,6…0, pin number.

Port A Schematics

Note that all port pins are synchronized. The synchronization latch is however, not shown in the figure.

Figure 45. PORTA Schematic Diagrams (Pins PA0 - PA7)

Port B

Port B is an 8-bit bi-directional I/O port.

inputs and are externally pulled low, they will source cur-

rent if the internal pull-up resistors are activated.

Three data memory address locations are allocated for the

Port B, one each for the Data Register - PORTB, $18($38),

Data Direction Register - DDRB, $17($37) and the Port B

Input Pins - PINB, $16($36). The Port B Input Pins address

is read only, while the Data Register and the Data Direction

Register are read/write.

The Port B pins with alternate functions are shown in the

following table:

All port pins have individually selectable pull-up resistors.

The Port B output buffers can sink 20mA and thus drive

LED displays directly. When pins PB0 to PB7 are used as

AT90S8515

44

AT90S8515

Table 19. Port B Pins Alternate Functions

Port Pin

PB0

Alternate Functions

T0 (Timer/Counter 0 external counter input)

T1 (Timer/Counter 1 external counter input)

AIN0 (Analog comparator positive input)

AIN1 (Analog comparator negative input)

SS (SPI Slave Select input)

PB1

PB2

PB3

PB4

PB5

MOSI (SPI Bus Master Output/Slave Input)

MISO (SPI Bus Master Input/Slave Output)

SCK (SPI Bus Serial Clock)

PB6

PB7

When the pins are used for the alternate function the DDRB and PORTB register has to be set according to the alternate

function description.

The Port B Data Register - PORTB

Bit

7

PORTB7

R/W

6

PORTB6

R/W

5

PORTB5

R/W

4

PORTB4

R/W

3

PORTB3

R/W

2

PORTB2

R/W

1

PORTB1

R/W

0

PORTB0

R/W

$18 ($38)

Read/Write

Initial value

PORTB

DDRB

PINB

0

The Port B Data Direction Register - DDRB

Bit

7

DDB7

R/W

0

6

DDB6

R/W

0

5

DDB5

R/W

0

4

DDB4

R/W

0

3

DDB3

R/W

0

2

DDB2

R/W

0

1

DDB1

R/W

0

DDB0

R/W

0

$17 ($37)

Read/Write

Initial value

The Port B Input Pins Address - PINB

Bit

7

PINB7

R

6

PINB6

R

5

PINB5

R

4

PINB4

R

3

PINB3

R

2

PINB2

R

1

PINB1

R

0

PINB0

R

$16 ($36)

Read/Write

Initial value

Hi-Z

The Port B Input Pins address - PINB - is not a register,

and this address enables access to the physical value on

each Port B pin. When reading PORTB, the PORTB Data

Latch is read, and when reading PINB, the logical values

present on the pins are read.

PBn, General I/O pin: The DDBn bit in the DDRB register

selects the direction of this pin, if DDBn is set (one), PBn is

configured as an output pin. If DDBn is cleared (zero), PBn

is configured as an input pin. If PORTBn is set (one) when

the pin configured as an input pin, the MOS pull up resistor

is activated. To switch the pull up resistor off, the PORTBn

has to be cleared (zero) or the pin has to be configured as

an output pin.

PortB As General Digital I/O

All 8 bits in port B are equal when used as digital I/O pins.

Table 20. DDBn Effects on Port B Pins

DDBn

PORTBn

I/O

Pull up

No

Comment

0

1

0

1

0

1

Input

Tri-state (Hi-Z)

Input

Yes

PBn will source current if ext. pulled low.

Push-Pull Zero Output

Output

No

Push-Pull One Output

n: 7,6…0, pin number.

45

Alternate Functions of PortB

The alternate pin configuration is as follows:

data direction of this pin is controlled by DDB5. When the

pin is forced to be an input, the pull-up can still be con-

trolled by the PORTB5 bit. See the description of the SPI

port for further detatils.

SCK - PORTB, Bit 7

SCK: Master clock output, slave clock input pin for SPI

channel. When the SPI is enabled as a slave, this pin is

configured as an input regardless of the setting of DDB7.

When the SPI is enabled as a master, the data direction of

this pin is controlled by DDB7. When the pin is forced to be

an input, the pull-up can still be controlled by the PORTB7

bit. See the description of the SPI port for further detatils.

AIN1 - PORTB, Bit 3

AIN1, Analog Comparator Negative Input. When config-

ured as an input (DDB3 is cleared (zero)) and with the

internal MOS pull up resistor switched off (PB3 is cleared

(zero)), this pin also serves as the negative input of the on-

chip analog comparator.

AIN0 - PORTB, Bit 2

MISO - PORTB, Bit 6

AIN0, Analog Comparator Positive Input. When configured

as an input (DDB2 is cleared (zero)) and with the internal

MOS pull up resistor switched off (PB2 is cleared (zero)),

this pin also serves as the positive input of the on-chip ana-

log comparator.

MISO: Master data input, slave data output pin for SPI

channel. When the SPI is enabled as a master, this pin is

configured as an input regardless of the setting of DDB6.

When the SPI is enabled as a slave, the data direction of

this pin is controlled by DDB6. When the pin is forced to be

an input, the pull-up can still be controlled by the PORTB6

bit. See the description of the SPI port for further detatils.

T1 - PORTB, Bit 1

T1, Timer/Counter1 counter source. See the timer descrip-

tion for further details

MOSI - PORTB, Bit 5

MOSI: SPI Master data output, slave data input for SPI

channel. When the SPI is enabled as a slave, this pin is

configured as an input regardless of the setting of DDB5.

When the SPI is enabled as a master, the data direction of

this pin is controlled by DDB5. When the pin is forced to be

an input, the pull-up can still be controlled by the PORTB5

bit. See the description of the SPI port for further detatils.

T0 - PORTB, Bit 0

T0: Timer/Counter0 counter source. See the timer descrip-

tion for further details.

Port B Schematics

Note that all port pins are synchronized. The synchroniza-

tion latches are however, not shown in the figures.

SS - PORTB, Bit 4

SS: Slave port select input. When the SPI is enabled as a

slave, this pin is configured as an input regardless of the

setting of DDB5. As a slave, the SPI is activated when this

pin is driven low. When the SPI is enabled as a master, the

AT90S8515

46

AT90S8515

Figure 46. PORTB Schematic Diagram (Pins PB0 and PB1)

Figure 47. PORTB Schematic Diagram (Pins PB2 and PB3)

47

Figure 48. PORTB Schematic Diagram (Pin PB4)

RD

MOS

PULL-

UP

RESET

Q

D

DDB4

C

WD

RESET

Q

D

PB4

PORTB4

C

RL

WP

RP

MSTR

SPE

WP:

WD:

RL:

RP:

RD:

WRITE PORTB

WRITE DDRB

READ PORTB LATCH

READ PORTB PIN

READ DDRB

MSTR: SPI MASTER ENABLE

SPE: SPI ENABLE

SPI SS

Figure 49. PORTB Schematic Diagram (Pin PB5)

RD

MOS

PULL-

UP

RESET

R

DDB5

C

Q

D

WD

RESET

R

Q

D

PB5

PORTB5

C

RL

WP

RP

WRITE PORTB

WRITE DDRB

READ PORTB LATCH

READ PORTB PIN

READ DDRB

WP:

WD:

RL:

RP:

RD:

MSTR

SPE

SPI MASTER

OUT

SPI ENABLE

MASTER SELECT

SPE:

MSTR

SPI SLAVE

IN

AT90S8515

48

AT90S8515

Figure 50. PORTB Schematic Diagram (Pin PB6)

RD

MOS

PULL-

UP

RESET

R

DDB6

C

Q

D

WD

RESET

R

Q

D

PB6

PORTB6

C

RL

WP

RP

WRITE PORTB

WRITE DDRB

READ PORTB LATCH

READ PORTB PIN

READ DDRB

WP:

WD:

RL:

RP:

RD:

MSTR

SPE

SPI SLAVE

OUT

SPI ENABLE

MASTER SELECT

SPE:

MSTR

SPI MASTER

IN

Figure 51. PORTB Schematic Diagram (Pin PB7)

RD

MOS

PULL-

UP

RESET

R

DDB7

C

Q

D

WD

RESET

R

Q

D

PB7

PORTB7

C

RL

WP

RP

WRITE PORTB

WRITE DDRB

READ PORTB LATCH

READ PORTB PIN

READ DDRB

WP:

WD:

RL:

RP:

RD:

MSTR

SPE

SPI ClLOCK

OUT

SPI ENABLE

MASTER SELECT

SPE:

MSTR

SPI CLOCK

IN

49

Port C

PORT C is an 8-bit bi-directional I/O port.

inputs and are externally pulled low, they will source cur-

rent if the internal pull-up resistors are activated.

Three data memory address locations are allocated for the

Port C, one each for the Data Register - PORTC, $15($35),

Data Direction Register - DDRC, $14($34) and the Port C

Input Pins - PINC, $13($33). The Port C Input Pins address

is read only, while the Data Register and the Data Direction

Register are read/write.

The PORT C pins have alternate functions related to the

optional external data SRAM. PORT C can be configured

to be the high-order address byte during accesses to exter-

nal data memory.

When PORT C is set to the alternate function by the SRE -

External SRAM Enable - bit in the MCUCR - MCU Control

Register, the alternate settings override the data direction

register.

All port pins have individually selectable pull-up resistors.

The PORT C output buffers can sink 20mA and thus drive

LED displays directly. When pins PC0 to PC7 are used as

The Port C Data Register - PORTC

Bit

7

PORTC7

R/W

6

PORTC6

R/W

5

PORTC5

R/W

4

PORTC4

R/W

3

PORTC3

R/W

2

PORTC2

R/W

1

PORTC1

R/W

0

PORTC0

R/W

$15 ($35)

Read/Write

Initial value

PORTC

DDRC

PINC

0

The Port C Data Direction Register - DDRC

Bit

7

DDC7

R/W

0

6

DDC6

R/W

0

5

DDC5

R/W

0

4

DDC4

R/W

0

3

DDC3

R/W

0

2

DDC2

R/W

0

1

DDC1

R/W

0

DDC0

R/W

0

$14 ($34)

Read/Write

Initial value

The Port C Input Pins Address - PINC

Bit

7

PINC7

R

6

PINC6

R

5

PINC5

R

4

PINC4

R

3

PINC3

R

2

PINC2

R

1

PINC1

R

0

PINC0

R

$13 ($33)

Read/Write

Initial value

Hi-Z

The Port C Input Pins address - PINC - is not a register,

and this address enables access to the physical value on

each Port C pin. When reading PORTC, the PORTC Data

Latch is read, and when reading PINC, the logical values

present on the pins are read.

PCn, General I/O pin: The DDCn bit in the DDRC register

selects the direction of this pin, if DDCn is set (one), PCn is

configured as an output pin. If DDCn is cleared (zero), PCn

is configured as an input pin. If PORTCn is set (one) when

the pin configured as an input pin, the MOS pull up resistor

is activated. To switch the pull up resistor off, PORTCn has

to be cleared (zero) or the pin has to be configured as an

output pin.

PortC As General Digital I/O

All 8 bits in PORT C are equal when used as digital I/O

pins.

Table 21. DDCn Effects on PORT C Pins

DDCn

PORTCn

I/O

Pull up

No

Comment

0

1

0

1

0

1

Input

Tri-state (Hi-Z)

Input

Yes

PCn will source current if ext. pulled low.

Push-Pull Zero Output

Output

No

Push-Pull One Output

n: 7…0, pin number

AT90S8515

50

AT90S8515

Port C Schematics

Note that all port pins are synchronized. The synchronization latch is however, not shown in the figure.

Figure 52. PORTC Schematic Diagram (Pins PC0 - PC7)

Port D

Port D is an 8 bit bi-directional I/O port with internal pull-up

resistors.

is read only, while the Data Register and the Data Direction

Register are read/write.

Three data memory address locations are allocated for the

Port D, one each for the Data Register - PORTD, $12($32),

Data Direction Register - DDRD, $11($31) and the Port D

Input Pins - PIND, $10($30). The Port D Input Pins address

The Port D output buffers can sink 20 mA. As inputs, Port D

pins that are externally pulled low will source current if the

pull-up resistors are activated.

Some Port D pins have alternate functions as shown in the

following table:

Table 22. Port D Pins Alternate Functions

Port Pin

PD0

Alternate Function

RDX (UART Input line )

PD1

TDX (UART Output line)

INT0 (External interrupt 0 input)

INT1 (External interrupt 1 input)

PD2

PD3

PD5

OC1A (Timer/Counter1 Output compareA match output)

WR (Write strobe to external memory)

PD6

PD7

RD (Read strobe to external memory)

When the pins are used for the alternate function the

DDRD and PORTD register has to be set according to the

alternate function description.

51

The Port D Data Register - PORTD

Bit

7

PORTD7

R/W

6

PORTD6

R/W

5

PORTD5

R/W

4

PORTD4

R/W

3

PORTD3

R/W

2

PORTD2

R/W

1

PORTD1

R/W

0

PORTD0

R/W

$12 ($32)

Read/Write

Initial value

PORTD

DDRD

PIND

0

The Port D Data Direction Register - DDRD

Bit

7

DDD7

R/W

0

6

DDD6

R/W

0

5

DDD5

R/W

0

4

DDD4

R/W

0

3

DDD3

R/W

0

2

DDD2

R/W

0

1

DDD1

R/W

0

DDD0

R/W

0

$11 ($31)

Read/Write

Initial value

The Port D Input Pins Address - PIND

Bit

7

PIND7

R

6

PIND6

R

5

PIND5

R

4

PIND4

R

3

PIND3

R

2

PIND2

R

1

PIND1

R

0

PIND0

R

$10 ($30)

Read/Write

Initial value

Hi-Z

The Port D Input Pins address - PIND - is not a register,

and this address enables access to the physical value on

each Port D pin. When reading PORTD, the PORTD Data

Latch is read, and when reading PIND, the logical values

present on the pins are read.

PortD As General Digital I/O

PDn, General I/O pin: The DDDn bit in the DDRD register

selects the direction of this pin. If DDDn is set (one), PDn is

configured as an output pin. If DDDn is cleared (zero), PDn

is configured as an input pin. If PDn is set (one) when con-

figured as an input pin the MOS pull up resistor is activated.

To switch the pull up resistor off the PDn has to be cleared

(zero) or the pin has to be configured as an output pin.

Table 23. DDDn Bits on Port D Pins

DDDn

PORTDn

I/O

Pull up

No

Comment

0

1

0

1

0

1

Input

Tri-state (Hi-Z)

Input

Yes

PDn will source current if ext. pulled low.

Push-Pull Zero Output

Output

No

Push-Pull One Output

n: 7,6…0, pin number.

rupt description for further details, and how to enable the

source.

Alternate Functions Of PORTD

RD - PORTD, Bit 7

INT0 - PORTD, Bit 2

INT0, External Interrupt source 0: The PD2 pin can serve

as an external interrupt source to the MCU. See the inter-

rupt description for further details, and how to enable the

source.

RD is the external data memory read control strobe.

WR - PORTD, Bit 6

WR is the external data memory write control strobe.

OC1- PORTD, Bit 5

TXD - PORTD, Bit 1

OC1, Output compare match output: The PD5 pin can

serve as an external output when the Timer/Counter1 com-

pare matches. The PD5 pin has to be configured as an out-

put (DDD5 set (one)) to serve this function. See the

Timer/Counter1 description for further details, and how to

enable the output. The OC1 pin is also the output pin for

the PWM mode timer function.

Transmit Data (Data output pin for the UART). When the

UART transmitter is enabled, this pin is configured as an

output regardless of the value of DDRD1.

RXD - PORTD, Bit 0

Receive Data (Data input pin for the UART). When the

UART receiver is enabled this pin is configured as an out-

put regardless of the value of DDRD0. When the UART

forces this pin to be an input, a logical one in PORTD0 vill

turn on the internal pull-up.

INT1 - PORTD, Bit 3

INT1, External Interrupt source 1: The PD3 pin can serve

as an external interrupt source to the MCU. See the inter-

AT90S8515

52

AT90S8515

PortD Schematics

Note that all port pins are synchronized. The synchronization latches are however, not shown in the figures.

Figure 53. PORTD Schematic Diagram (Pin PD0)

RD

MOS

PULL-

UP

RESET

Q

D

DDD0

C

WD

RESET

Q

D

PD0

PORTD0

C

RL

WP

RP

RXEN

RXD

WP: WRITE PORTD

WD: WRITE DDRD

RL:

RP:

RD:

READ PORTD LATCH

READ PORTD PIN

READ DDRD

RXD: UART RECEIVE DATA

RXEN: UART RECEIVE ENABLE

Figure 54. PORTD Schematic Diagram (Pin PD1)

RD

MOS

PULL-

UP

RESET

R

DDD1

C

Q

D

WD

RESET

R

Q

D

PD1

PORTD1

C

RL

WP

RP

WRITE PORTD

WRITE DDRD

READ PORTD LATCH

READ PORTD PIN

READ DDRD

WP:

WD:

RL:

RP:

RD:

TXEN

TXD

UART TRANSMIT DATA

UART TRANSMIT ENABLE

TXD:

TXEN:

53

Figure 55. PORTD Schematic Diagram (Pins PD2 and PD3)

Figure 56. PORTD Schematic Diagram (Pin PD4)

AT90S8515

54

AT90S8515

Figure 57. PORTD Schematic Diagram (Pin PD5)

Figure 58. PORTD Schematic Diagram (Pin PD6)

55

Figure 59. PORTD Schematic Diagram (Pin PD7)

Parts with this bit pre-programmed (‘0’) can be delivered

on demand.

Memory Programming

Program Memory Lock Bits

These bits are not accessible in Serial Programming Mode

and are not affected by a chip erase.

The AT90S8515 MCU provides two lock bits which can be

left unprogrammed (‘1’) or can be programmed (‘0’) to

obtain the additional features listed in Table 24.

Signature Bytes

All Atmel microcontrollers have a three-byte signature code

which identifies the device. This code can be read in both

seria⁽¹⁾land parallel mode. The three bytes reside in a sep-

arate address space, and for the AT90S8515 they are:

Table 24. Lock Bit Protection Modes

Program Lock Bits

Protection Type

Mode

LB1

LB2

1. $00: $1E (indicates manufactured by Atmel)

2. $01: $93 (indicates 8kB Flash memory)

1

No program lock features

Further programming of the Flash

and EEPROM is disabled

2

3

0

1

0

3. $02: $01 (indicates 90S8515 device when $01 is

$93)

Same as mode 2, but verify is also

disabled.

Note:

1. When both lock bits are programmed (lock mode 3),

the signature bytes can not be read in serial mode

Note:

The Lock Bits can only be erased with the Chip Erase

operation.

Programming the Flash and EEPROM

Atmel’s AT90S8515 offers 8K bytes of in-system repro-

grammable Flash Program memory and 512 bytes of

EEPROM Data memory.

Fuse Bits

The AT90S8515 has two fuse bits, SPIEN and FSTRT.

• When SPIEN is programmed (‘0’), Serial Program

Downloading is enabled. Default value is programmed

(‘0’).

The AT90S8515 is normally shipped with the on-chip Flash

Program and EEPROM Data memory arrays in the erased

state (i.e. contents = $FF) and ready to be programmed.

This device supports a High-Voltage (12V) Parallel pro-

gramming mode and a Low-Voltage Serial programming

• When FSTRT is programmed (‘0’), the short start-up

time is selected. Default value is unprogrammed (‘1’).

AT90S8515

56

AT90S8515

mode. The +12V is used for programming enable only, and

no current of significance is drawn by this pin. The serial

programming mode provides a convenient way to down-

load the Program and Data into the AT90S8515 inside the

user’s system.

The XA1/XA0 bits determine the action taken when the

XTAL1 pin is given a positive pulse. The bit settings are

shown in the following table:

Table 26. XA1 and XA0 Coding

XA1 XA0 Action when XTAL1 is Pulsed

The Program and Data memory arrays on the AT90S8515

are programmed byte-by-byte in either programming

modes. For the EEPROM, an auto-erase cycle is provided

with the self-timed programming operation in the serial pro-

gramming mode.

Load Flash or EEPROM Address (High or Low

address byte for Flash determined by BS)

0

1

Load Data (High or Low data byte for Flash

determined by BS)

Parallel Programming

1

0

1

Load Command

No Action, Idle

This section describes how to parallel program and verify

Flash Program memory, EEPROM Data memory + Pro-

gram Memory Lock bits and Fuse bits in the AT90S8515.

When pulsing WR or OE, the command loaded determines

the action on input or output. The command is a byte where

the different bits are assigned functions as shown in the fol-

lowing table:

Figure 60. Parallel Programming

Table 27. Command Byte Bit Coding

Bit#

7

Meaning when Set

Chip Erase

6

Write Fuse Bits. Located in the data byte at the

following bit positions: D5–SPIEN Fuse, D0–FSTRT

Fuse (Note: Write ‘0’ to program, ‘1’ to erase)

5

Write Lock Bits. Located in the data byte at the

following bit positions: D1–LB1, D0: LB2 (Note:

write ‘0’ to program)

4

3

2

Write Flash or EEPROM (determined by bit 0)

Read signature row

Read Lock and Fuse Bits. Located in the data byte

at the following bits positions: D7–LB1, D6–LB2,

D5–SPIEN Fuse, D0: FSTRT Fuse (Note: ‘0’

means programmed)

Signal Names

In this section, some pins of the AT908515 are referenced

by signal names describing their functionality during paral-

lel programming rather than their pin names. Pins not

described in the following table are referenced by pin

names.

1

0

Read from Flash or EEPROM (determined by bit 0)

0: Flash Access, 1: EEPROM Access

Table 25. Pin Name Mapping

Enter Programming Mode

The following algorithm puts the device in parallel program-

ming mode:

Signal Name in

Programming

Mode

Name I/O Function

1. Apply 4.5 - 5.5 V between V_CCand GND.

RDY / BSY

PD1

O

0: Device is busy

programming, 1: Device is

ready for new command

2. Set RESET and BS pins to ‘0’ and wait at least

100 ns.

3. Apply 11.5 - 12.5V to RESET. Any activity on BS

within 100 ns after +12V has been applied to

RESET will cause the device to fail entering pro-

gramming mode.

OE

WR

BS

PD2

PD3

PD4

PD5

PD6

I

Output Enable (Active Low)

Write Pulse (Active Low)

Byte Select

XA0

XA1

XTAL Action Bit 0

XTAL Action Bit 1

57

Chip Erase

Load Address High byte

The chip erase will erase the Flash and EEPROM memo-

ries plus Lock bits. The lock bits are not reset until the pro-

gram memory has been completely erased. The Fuse bits

are not changed. A chip erase must be performed before

the Flash is programmed.

1. Set XA1, XA0 to ‘00’. This enables address loading.

2. Set BS to ‘1’. This selects High address.

3. Set PB(7:0) = Address High byte ($00 - $0F)

4. Give XTAL1 a positive pulse. This loads the Address

High byte.

Load Command “Chip Erase”

Load Data byte

1. Set XA1, XA0 to ‘10’. This enables command load-

ing.

1. Set XA1, XA0 to ‘01’. This enables data loading.

2. Set PB(7:0) = Data Low byte ($00 - $FF)

2. Set BS to ‘0’.

3. Give XTAL1 a positive pulse. This loads the Data

byte.

3. Set PB(7:0) to ‘1000 0000’. This is the command for

Chip erase.

Write Data Low byte

1. Set BS to (‘0’).

4. Give XTAL1 a positive pulse. This loads the com-

mand, and starts the erase of the Flash and

EEPROM arrays. After pulsing XTAL1, give WR a

negative pulse to enable lock bit erase at the end of

the erase cycle, then wait for at least 10 ms. Chip

erase does not generate any activity on the

RDY/BSY pin.

2. Give WR a negative pulse. This starts programming

of the data byte. RDY/BSY goes low.

3. Wait until RDY/BSY goes high to program the next

byte.

Load Data byte

Programming The Flash

1. Set XA1, XA0 to ‘01’. This enables data loading.

2. Set PB(7:0) = Data High byte ($00 - $FF)

Load Command “Program Flash”

1. Set XA1, XA0 to ‘10’. This enables command load-

ing.

3. Give XTAL1 a positive pulse. This loads the Data

byte.

2. Set BS to ‘0’

Write Data High byte

1. Set BS to ‘1’.

3. Set PB(7:0) to ‘0001 0000’. This is the command for

Flash programming.

4. Give XTAL1 a positive pulse. This loads the com-

mand.

2. Give WR a negative pulse. This starts programming

of the data byte. RDY / BSY goes low.

3. Wait until RDY / BSY goes high to program the next

byte.

Load Address Low byte

1. Set XA1, XA0 to ‘00’. This enables address loading.

2. Set BS to ‘0’. This selects Low address.

3. Set PB(7:0) = Address Low byte ($00 - $FF)

The loaded command and address are retained in the

device during programming. To simplify programming, the

following should be considered.

4. Give XTAL1 a positive pulse. This loads the Address

Low byte.

• The command for Flash programming needs only be

loaded before programming of the first byte.

• Address High byte needs only be loaded before

programming a new 256 word page in the Flash.

AT90S8515

58

AT90S8515

Figure 61. Programming Flash Low Byte

PB0 - PB7

$10

ADDR. LOW

ADDR. HIGH

DATA LOW

XA1

XA2

BS

XTAL 1

WR

RDY/BSY

RESET

OE

+12V

Figure 62. Programming Flash High Byte

PB0 - PB7

DATA HIGH

XA1

XA0

BS

XTAL1

WR

RDY/BSY

RESET

OE

+12V

59

Programming The EEPROM

1. Load Command ‘0100 0000’.

The programming algorithm for the EEPROM data memory

is as follows (refer to Flash Programming for details on

Command, Address and Data loading):

2. Load Data.

Bit 5 = ‘0’ programs the SPIEN Fuse bit. Bit 5 = ‘1’

erases the SPIEN Fuse bit.

Bit 0 = ‘0’ programs the FSTRT fuse bit. Bit 5 = ‘1’

erases the FSTRT fuse bit.

1. Load Command ‘0001 0001’.

2. Load Low EEPROM Address ($00 - $FF)

3. Load High EEPROM Address ($00 - $01)

4. Load Low EEPROM Data ($00 - $FF)

3. Give WR a negative pulse and wait for RDY/BSY to

go high.

Programming The Lock Bits

5. Give WR a negative pulse and wait for RDY/BSY to

go high.

The algorithm for programming the Lock bits is as follows

(refer to Flash Programming for details on Command,

Address and Data loading):

The Command needs only be loaded before programming

the first byte.

1. Load Command ‘0010 0000’.

Reading The Flash

2. Load Data.

The algorithm for reading the Flash memory is as follows

(refer to Flash Programming for details on Command,

Address and Data loading):

Bit 2 = ’0’ programs Lock Bit2

Bit 1 = ’0’ programs Lock Bit1

3. Give WR a negative pulse and wait for RDY/BSY to

go high.

1. Load Command ‘0000 0010’.

2. Load Low Address ($00 - $FF)

3. Load High Address ($00 - $0F)

The lock bits can only be cleared by executing a chip

erase.

4. Set OE to ‘0’, and BS to ‘0’. The Low Data byte can

now be read at PB(7:0)

Reading The Fuse And Lock Bits

The algorithm for reading the Fuse and Lock bits is as fol-

lows (refer to Flash Programming for details on Command,

Address and Data loading):

5. Set BS to ‘1’. The High Data byte can now be read

from PB(7:0)

6. Set OE to ‘1’.

1. Load Command ‘0000 0100’.

The Command needs only be loaded before reading the

first byte.

2. Set OE to ‘0’, and BS to ‘1’. The Status of Fuse and

Lock bits can now be read at PB(7:0)

Bit 7: Lock Bit1 (‘0’ means programmed)

Bit 6: Lock Bit2 (‘0’ means programmed)

Bit 5: SPIEN Fuse (‘0’ means programmed, ‘1’

means erased)

Reading The EEPROM

The algorithm for reading the EEPROM memory is as fol-

lows (refer to Flash Programming for details on Command,

Address and Data loading):

Bit 0: FSTRT Fuse (‘0’ means programmed, ‘1’

means erased)

1. Load Command ‘0000 0011’.

2. Load Low EEPROM Address ($00 - $FF)

3. Load High EEPROM Address ($00 - $01)

3. Set OE to ‘1’.

Observe especially that BS needs to be set to ‘1’.

4. Set OE to ‘0’, and BS to ‘0’. The EEPROM Data

byte can now be read at PB(7:0)

Reading The Signature Bytes

The algorithm for reading the Signature Bytes bits is as fol-

lows (refer to Flash Programming for details on Command,

Address and Data loading):

5. Set OE to ‘1’.

The Command needs only be loaded before reading the

first byte.

1. Load Command ‘0000 1000’.

2. Load Low address ($00 - $02)

Programming The Fuse Bits

The algorithm for programming the Fuse bits is as follows

(refer to Flash Programming for details on Command,

Address and Data loading):

3. Set OE to ‘0’, and BS to ‘0’. The Selected Signature

byte can now be read at PB(7:0)

4. Set OE to ‘1’.

The command needs only be programmed before reading

the first byte.

AT90S8515

60

AT90S8515

Parallel Programming Characteristics

Figure 63. Parallel Programming Timing

t_XHXL

XTAL1

t_XHDXt_BVWL

Data & Contol

(PB0-7, XA0/1, BS)

t_DVXH

t_WLWH

t_XLWL

WR

t_WHRL

RDY/BSY

t_WLRH

OE

t_XLOL

t_OLDV

Data

Table 28. Parallel Programming Characteristics

T_A= 21°C to 27°C, V_CC= 4.5 - 5.5V

Symbol

t_DVXH

t_XHXL

Parameter

Min

67

Typ

Max

Units

ns

Data and Control Setup before XTAL1 High

XTAL1 Pulse Width High

ns

t_XLDH

t_BVWL

t_WLWH

t_WHRL

t_XLOL

Data and Control Hold after XTAL1 High

BS Valid to WR Low

ns

WR Pulse Width Low

ns

WR High to RDY/BSY Low⁽¹⁾

20

ns

XTAL1 Low to OE Low

67

ns

t_OLDV

t_WLRH

Note:

OE Low to Data Valid

20

ns

WR Low to RDY/BSY High⁽¹⁾

0.5

0.7

0.9

ms

1. If t_WPWLis held longer than t_WLRH, no RDY/BSY pulse will be seen.

61

Serial Downloading

Both the Program and Data memory arrays can be pro-

grammed using the serial SPI bus while RESET is pulled to

GND. The serial interface consists of pins SCK, MOSI

(input) and MISO (output). After RESET is set low, the Pro-

gramming Enable instruction needs to be executed first

before program/erase operations can be executed.

2. Wait for at least 20 ms and enable serial program-

ming by sending the Programming Enable serial

instruction to pin MOSI/PB5.

3. When issuing the third byte in Programming Enable,

the value sent as byte number two ($53), will echo

back during transmission of byte number three. In

any case, all four bytes in programming enable must

be transmitted. If the $53 did not echo back, give

SCK a positive pulse and issue a new Programming

Enable command. If the $53 is not seen within 32

attempts, there is no functional device connected.

When programming the EEPROM, an auto-erase cycle is

built into the self-timed programming operation (in the

serial mode ONLY) and there is no need to first execute the

Chip Erase instruction. The Chip Erase operation turns the

content of every memory location in both the Program and

EEPROM arrays into $FF.

4. If a chip erase is performed (must be done to erase

the Flash), wait 10 ms, give RESET a positive

pulse, and start over from Step 2.

The Program and EEPROM memory arrays have separate

address spaces:

$0000 to $0FFF for Program memory and $0000 to $01FF

for EEPROM memory.

5. The Flash or EEPROM array is programmed one

byte at a time by supplying the address and data

together with the appropriate Write instruction. An

EEPROM memory location is first automatically

erased before new data is written. Use Data Polling

to detect when the next byte in the Flash or

EEPROM can be written. In a chip erased device,

no $FFs in the data file(s) need to be programmed.

When programming locations with $7F, wait 4 ms

before writing the next byte.

Either an external system clock is supplied at pin XTAL1 or

a crystal needs to be connected across pins XTAL1 and

XTAL2.The minimum low and high periods for the serial

clock (SCK) input are defined as follows:

Low:> 2 XTAL1 clock cycle

High:> 2 XTAL1 clock cycles

Data Polling

When a new byte has been written and is being pro-

grammed into the Flash or EEPROM, reading the address

location being programmed will give the value $7F. At the

time the device is ready for a new byte, the programmed

value will read correctly. This is used to determine when

the next byte can be written. This will not work for the value

$7F, so when programming this value, the user will have to

wait for at least 4 ms before programming the next byte. As

a chip-erased device contains $FF in all locations, pro-

gramming of addresses that are meant to contain $FF, can

be skipped. This does not apply if the EEPROM is re-pro-

grammed without chip-erasing the device. In this case,

data polling cannot be used for the values $7F and $FF,

and the user will have to wait at least 4ms before program-

ming the next byte.

6. Any memory location can be verified by using the

Read instruction which returns the content at the

selected address at serial output MISO/PB6.

7. At the end of the programming session, RESET can

be set high to commence normal operation.

8. Power-off sequence (if needed):

Set XTAL1 to ‘0’ (if a crystal is not used).

Set RESET to ‘1’.

Tur n V_CCpower off

Serial Programming Algorithm

To program and verify the AT90S8515 in the serial pro-

gramming mode, the following sequence is recommended

(See four byte instruction formats in Table 29):

1. Power-up sequence:

Apply power between V_CCand GND while RESET and

SCK are set to ‘0’. If a crystal is not connected across

pins XTAL1 and XTAL2, apply a clock signal to the

XTAL1 pin. In some systems, the programmer can not

guarantee that SCK is held low during power-up. In this

case, RESET must be given a positive pulse of at least

two XTAL1 cycles duration after SCK has been set to

‘0’.

AT90S8515

62

AT90S8515

Table 29. Serial Programming Instruction Set

Instruction

Instruction Format

Byte 2 Byte 3

Operation

Byte 1

Byte4

Enable Serial Programming after

RESET goes low.

1010 1100

0101 0011

100x xxxx

xxxx aaaa

xxxx xxxx

bbbb bbbb

xxxx xxxx

Programming Enable

Chip Erase

Chip erase both 8K & 512byte

memory arrays

1010 1100

xxxx xxxx

Read H(high or low) data o from

Program memory at word address

a:b

0010 H000

oooo oooo

Read Program Memory

Write Program Memory

Write H(high or low) data i to Program

memory at word address a:b

0100 H000

1010 0000

1100 0000

xxxx aaaa

xxxx xxx0

bbbb bbbb

iiii iiii

oooo oooo

iiii iiii

Read EEPROM

Memory

Read data o from EEPROM memory

at address a:b

Write EEPROM

Memory

Write data i to EEPROM memory at

address a:b

Write lock bits. Set bits 1,2=’0’ to

program lock bits.

1010 1100

0011 0000

111x x21x

xxxx xxxx

Write Lock Bits

xxxx xxxx

xxxx xxbb

oooo oooo

Read Device Code

Read Device Code o at address b

Note:

a = address high bits

b = address low bits

H = 0 - Low byte, 1 - High Byte

o = data out

i = data in

x = don’t care

1 = lock bit 1

2 = lock bit 2

Figure 64. Serial Programming and Verify

When writing serial data to the AT90S8515, data is clocked

on the rising edge of CLK.

When reading data from the AT90S8515, data is clocked

on the falling edge of CLK. See Figure 65 for an explana-

tion.

63

Figure 65. Serial Programming Waveforms

Serial Programming Characteristics

Figure 66. Serial Programming Timing

MOSI

t_SLSH

t_OVSH

t_SHOX

SCK

t_SHSL

MISO

t_SLIV

Table 30. Serial Programming Characteristics

T_A= -40°C to 85°C, V_CC= 2.7 - 6.0V (Unless otherwise noted)

Symbol

1/t_CLCL

t_CLCL

Parameter

Min

0

Typ

Max

Units

MHz

ns

Oscillator Frequency (V_CC= 2.7 - 4.0V)

Oscillator Period (V_CC= 2.7 - 4.0V)

Oscillator Frequency (V_CC= 4.0 - 6.0V)

Oscillator Period (V_CC= 4.0 - 6.0V)

SCK Pulse Width High

4

250

1/t_CLCL

t_CLCL

0

8

MHz

ns

125

t_SHSL

2 t_CLCL

t_CLCL

2 t_CLCL

10

ns

t_SLSH

SCK Pulse Width Low

ns

t_OVSH

t_SHOX

t_SLIV

MOSI Setup to SCK High

ns

MOSI Hold after SCK High

SCK Low to MISO Valid

ns

16

32

ns

Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

Operating Temperature ................................. -40°C to +105°C

Storage Temperature .................................... -65°C to +150°C

Voltage on any Pin except RESET

with respect to Ground ......................................-1.0V to +7.0V

Maximum Operating Voltage ............................................ 6.6V

I/O Pin Maximum Current ........................................... 40.0 mA

Maximum Current V_CCand GND .............................. 140.0 mA

AT90S8515

64

AT90S8515

DC Characteristics

T_A= -40°C to 85°C, V_CC= 2.7V to 6.0V (unless otherwise noted)

Symbol

V_IL

Parameter

Condition

Min

-0.5

Typ

Max

Units

Input Low Voltage

Input High Voltage

0.2 V_CC- 0.1

V_CC+ 0.5

V

V_IH

(Except XTAL1, RESET)

(XTAL1, RESET)

0.2 V_CC+ 0.9

0.7 V_CC

V_IH1

Output Low Voltage⁽¹⁾

(Ports B,C,D)

I_OL= 20 mA, V_CC= 5V

V_OL

V_OH

I_OH

I_OL

0.5

V

I

_OL= 10 mA, V_CC= 2.7V

Output High Voltage

(Ports B,C,D)

I_HI= 10 mA, V_CC= 5V

I_HI= 5 mA, V_CC= 2.7V

4.5

V

Output Source Current

(Ports B,C,D)

V_CC= 5V

V_CC= 2.7V

10

5

mA

Output Sink Current

(Port B,C,D)

V_CC= 5V

20

10

mA

V

_CC= 2.7V

RRST

R_I/O

Reset Pulldown Resistor

I/O Pin Pull-Up Resistor

10

35

50

kΩ

mA

µA

120

Active Mode, 3V, 4MHz

Idle Mode 3V, 4MHz

WDT enabled, 3V

3.5

1000

50

I_CC

Power Supply Current

Power Down Mode⁽²⁾

I_CC

WDT disabled, 3V

<1

Analog Comparator

Input Offset Voltage

V_ACIO

I_ACLK

t_ACPD

V_CC= 5V

20

10

mV

nA

ns

Analog Comparator

Input Leakage Current

1

5

Analog Comparator

Propagation Delay

V_CC= 2.7V

V_CC= 4.0V

750

500

Notes: 1. Under steady state (non-transient) conditions, I_OLmust be externally limited as follows:

Maximum I_OLper port pin: 10 mA

Maximum total I_OLfor all output pins: 80 mA

Port A: 26 mA

Ports A, B, D: 15 mA

Maximum total I_OLfor all output pins: 70 mA

If I_OLexceeds the test condition, V_OLmay exceed the related specification.

Pins are not guaranteed to sink current greater than the listed test conditions.

2. Minimum V_CCfor Power Down is 2V.

65

External Clock Drive Waveforms

External Clock Drive

V_CC= 2.7V to 6.0V

V_CC= 4.0V to 6.0V

Min Max

Symbol

1/t_CLCL

t_CLCL

Parameter

Oscillator Frequency

Clock Period

High Time

Min

0

Max

Units

MHz

ns

4

0

8

250

0

125

0

t_CHCX

t_CLCX

ns

Low Time

0

ns

t_CLCH

Rise Time

1.6

0.5

µs

t_CHCL

Fall Time

µs

Figure 67. External RAM Timing

T1

0

T2

T3

T4

System Clock O

ALE

1

4

7

6

Prev. Address

Address

Address [15..8]

Data / Address [7..0]

WR

2

13

15

Prev. Address

Address

3b

Data

16

Addr.

14

3a

11

Prev. Address

Data

Address

Addr.

Data / Address [7..0]

RD

5

10

9

8

12

T3 is only present when wait-state is enabled.

AT90S8515

66

AT90S8515

External Data Memory Timing

Table 31. External Data Memory Characteristics, 4.0 - 6.0 Volts, No Wait State

8 MHz Oscillator

Variable Oscillator

Symbol

1/t_CLCL

t_LHLL

Parameter

Min

Max

Min

Max

Unit

MHz

ns

0

1

2

Oscillator Frequency

ALE Pulse Width

0.0

8.0

32.5

22.5

0.5t_CLCL-30.0

0.5t_CLCL-40.0

t_AVLL

Address Valid A to ALE Low

ns

Address Hold After ALE Low,

ST/STD/STS Instructions

67.5

15.0

0.5t_CLCL+5.0

15.0

3a t_{LLAX_ST}

ns

Address Hold after ALE Low,

LD/LDD/LDS Instructions

3b t_{LLAX_LD}

ns

4

5

6

7

8

9

t_AVLLC

t_AVRL

t_AVWL

t_LLWL

t_LLRL

Address Valid C to ALE Low

Address Valid to RD Low

Address Valid to WR Low

ALE Low to WR Low

ALE Low to RD Low

22.5

95.0

0.5t_CLCL-40.0

1.0t_CLCL-30.0

1.5t_CLCL-30.0

1.0t_CLCL-20.0

0.5t_CLCL-20.0

60.0

157.5

105.0

42.5

145

1.0t_CLCL+20.0

0.5t_CLCL+20.0

82.5

t_DVRH

Data Setup to RD High

Read Low to Data Valid

Data Hold After RD High

RD Pulse Width

60.0

10 t_RLDV

11 t_RHDX

12 t_RLRH

13 t_DVWL

14 t_WHDX

15 t_DVWH

16 t_WLWH

70.0

1.0t_CLCL-55.0

0.0

105.0

27.5

0.0

1.0t_CLCL-20.0

0.5t_CLCL-35.0

0.0

Data Setup to WR Low

Data Hold After WR High

Data Valid to WR High

WR Pulse Width

95.0

42.5

1.0t_CLCL-30.0

0.5t_CLCL-20.0

Table 32. External Data Memory Characterizatics, 4.0 - 6.0 Volts, 1 Cycle Wait State

8 MHz Oscillator

Variable Oscillator

Symbol

Parameter

Min

Max

Min

Max

8.0

Unit

MHz

ns

0

1/t_CLCL

Oscillator Frequency

Read Low to Data Valid

RD Pulse Width

0.0

10 t_RLDV

12 t_RLRH

15 t_DVWH

16 t_WLWH

195.0

2.0t_CLCL-55.0

230.0

220.0

167.5

2.0t_CLCL-20.0

2.0t_CLCL-30.0

1.5t_CLCL-20.0

ns

Data Valid to WR High

WR Pulse Width

ns

67

Table 33. External Data Memory Characteristics, 2.7 - 6.0 Volts, No Wait State

8 MHz Oscillator

Variable Oscillator

Symbol

1/t_CLCL

t_LHLL

Parameter

Min

Max

Min

Max

Unit

MHz

ns

0

1

2

Oscillator Frequency

ALE Pulse Width

0.0

4.0

70.0

60.0

0.5t_CLCL-55.0

0.5t_CLCL-65.0

t_AVLL

Address Valid A to ALE Low

ns

Address Hold After ALE Low,

ST/STD/STS Instructions

130.0

15.0

0.5t_CLCL+5.0

15.0

3a t_{LLAX_ST}

ns

Address Hold after ALE Low,

LD/LDD/LDS Instructions

3b t_{LLAX_LD}

ns

4

5

6

7

8

9

t_AVLLC

t_AVRL

t_AVWL

t_LLWL

t_LLRL

Address Valid C to ALE Low

Address Valid to RD Low

Address Valid to WR Low

ALE Low to WR Low

ALE Low to RD Low

60.0

200.0

325.0

230.0

105.0

95.0

0.5t_CLCL-65.0

1.0t_CLCL-50.0

1.5t_CLCL-50.0

1.0t_CLCL-20.0

0.5t_CLCL-20.0

95.0

270.0

145.0

1.0t_CLCL+20.0

0.5t_CLCL+20.0

t_DVRH

Data Setup to RD High

Read Low to Data Valid

Data Hold After RD High

RD Pulse Width

10 t_RLDV

11 t_RHDX

12 t_RLRH

13 t_DVWL

14 t_WHDX

15 t_DVWH

16 t_WLWH

170.0

1.0t_CLCL-80.0

0.0

230.0

70.0

0.0

1.0t_CLCL-20.0

0.5t_CLCL-55.0

0.0

Data Setup to WR Low

Data Hold After WR High

Data Valid to WR High

WR Pulse Width

210.0

105.0

1.0t_CLCL-40.0

0.5t_CLCL-20.0

Table 34. External Data Memory Characteristics, 2.7 - 6.0 Volts, 1 Cycle Wait State

8 MHz Oscillator

Variable Oscillator

Symbol

Parameter

Min

Max

Min

Max

8.0

Unit

MHz

ns

0

1/t_CLCL

Oscillator Frequency

Read Low to Data Valid

RD Pulse Width

0.0

10 t_RLDV

12 t_RLRH

15 t_DVWH

16 t_WLWH

420.00

2.0t_CLCL-80.0

480.0

460.0

355.0

2.0t_CLCL-20.0

2.0t_CLCL-40.0

1.5t_CLCL-20.0

ns

Data Valid to WR High

WR Pulse Width

ns

AT90S8515

68

AT90S8515

POWER DOWN SUPPLY CURRENT vs. VCC

WATCHDOG TIMER DISABLED

ACTIVE SUPPLY CURRENT vs. FREQUENCY

T_A= 25˚C

12

10

8

25

20

15

10

5

V_CC= 6.0V

V_CC= 5.5V

T_A= 85˚C

V_CC= 5.0V

V_CC= 4.5V

V_CC= 4.0V

6

T_A= 70˚C

T_A= 45˚C

V_CC= 3.6V

V_CC= 3.3V

V_CC= 3.0V

V_CC= 2.7V

4

2

T_A= 25˚C

T_A= -40˚C

6

0

3

4

5

2

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

V_CC(V)

Frequency (MHz)

POWER DOWN SUPPLY CURRENT vs. VCC

WATCHDOG TIMER ENABLED

IDLE SUPPLY CURRENT vs. FREQUENCY

T_A= 25˚C

140

120

100

80

12

V_CC= 6.0V

10

8

T_A= 85˚C

V_CC= 5.5V

V_CC= 5.0V

T_A= 25˚C

6

V_CC= 4.5V

V_CC= 4.0V

V_CC= 3.6V

V_CC= 3.3V

V_CC= 3.0V

V_CC= 2.7V

60

40

4

20

2

0

2.5

3

3.5

4

4.5

5

5.5

6

2

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

0

V_CC(V)

Frequency (MHz)

ANALOG COMPARATOR SUPPLY CURRENT vs. VCC

0.8

ACTIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE

FREQUENCY = 4 MHz

14

12

10

8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

T_A= -40˚C

T_A= 85˚C

6

4

2

0

2

3

4

5

6

2

2.5

3

3.5

4

4.5

5

5.5

6

V_CC(V)

IDLE SUPPLY CURRENT vs. SUPPLY VOLTAGE

FREQUENCY = 4 MHz

RC OSCILLATOR FREQUENCY vs. VCC

1600

4

1400

1200

1000

800

3.5

3

T_A= -40˚C

T_A= 85˚C

T_A= 25˚C

2.5

2

T_A= 85˚C

600

1.5

1

400

200

0.5

0

2

3

4

5

6

2

2.5

3

3.5

4

4.5

5

5.5

6

V_CC(V)

69

ANALOG COMPARATOR

TYPICAL MAX. OPERATING FREQUENCY

INPUT LEAKAGE CURRENT

16

14

12

10

8

T_A= 0˚C

V_CC= 6V, T_A= 25˚C

60

50

40

30

20

10

0

T_A= 25˚C

T_A= 85˚C

6

4

2

-10

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

6.5

7

2

3

4

5

6

V_IN(V)

V_CC(V)

ANALOG COMPARATOR OFFSET VOLTAGE vs.

COMMON MODE VOLTAGE

V_CC= 2.7V

ANALOG COMPARATOR OFFSET VOLTAGE vs.

COMMON MODE VOLTAGE

V_CC= 5V

10

9

8

7

6

5

4

3

2

1

0

18

16

14

12

10

8

T = 25˚C

T^A_A= 45˚C

T_A= 25˚C

T = 45˚C

A

T = 70˚C

A

T_A= 70˚C

T_A= 85˚C

T = 80˚C

A

6

4

2

0

0.5

1

1.5

2

2.5

0

1

2

3

4

5

Common Mode Voltage (V)

AT90S8515

70

AT90S8515

PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

V_CC= 2.7V

PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

V_CC= 5V

120

30

25

20

15

10

5

T_A= 25˚C

T_A= 85˚C

T_A= 25˚C

T_A= 85˚C

100

80

60

40

20

0

1

2

3

4

5

0

0.5

1

1.5

2

2.5

V_IN(V)

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

V_CC= 2.7V

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

V_CC= 5V

20

6

T_A= 25˚C

T_A= 85˚C

T_A= 25˚C

18

16

14

12

10

5

4

3

2

1

0

T_A= 85˚C

8

6

4

2

0

0.5

1

1.5

2

2.5

0

1

2

3

4

5

V_OH(V)

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

V_CC= 2.7V

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

V_CC= 5V

25

20

15

10

70

60

50

40

30

20

10

0

T_A= 25˚C

T_A= 85˚C

T_A= 25˚C

T_A= 85˚C

5

0

0.5

1

1.5

2

2.5

0

0.5

1

1.5

2

V_OL(V)

I/O PIN INPUT THRESHOLD vs. VCC

I/O PIN INPUT HYSTERESIS vs. VCC

2.5

2

0.18

0.16

0.14

0.12

0.1

1.5

1

0.08

0.06

0.04

0.02

0

0.5

0

2.7V

4.0V

V_CC

5.0V

4.0V

V_CC

5.0V

Note:

Charts show typical values.

71

AT90S8515 Register Summary

Address

Name

SREG

SPH

SPL

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

$3F ($5F)

$3E ($5E)

$3D ($5D)

$3C ($5C)

$3B ($5B)

$3A ($5A)

$39 ($59)

$38 ($58)

$37 ($57)

$36 ($56)

$35 ($55)

$34 ($54)

$33 ($53)

$32 ($52)

$31 ($51)

$30 ($50)

$2F ($4F)

$2E ($4E)

$2D ($4D)

$2C ($4C)

$2B ($4B)

$2A ($4A)

$29 ($49)

$28 ($48)

$27 ($47)

$26 ($46)

$25 ($45)

$24 ($44)

$23 ($43)

$22 ($42)

$21 ($41)

$20 ($40)

$1F ($3F)

$1E ($3E)

$1D ($3D)

$1C ($3C)

$1B ($3B)

$1A ($3A)

$19 ($39)

$18 ($38)

$17 ($37)

$16 ($36)

$15 ($35)

$14 ($34)

$13 ($33)

$12 ($32)

$11 ($31)

$10 ($30)

$0F ($2F)

$0E ($2E)

$0D ($2D)

$0C ($2C)

$0B ($2B)

$0A ($2A)

$09 ($29)

$08 ($28)

…

I

T

H

SP13

SP5

S

SP12

SP4

V

SP11

SP3

N

SP10

SP2

Z

SP9

SP1

C

SP8

SP0

18

19

SP15

SP7

SP14

SP6

Reserved

GIMSK

GIFR

TIMSK

TIFR

INT1

INTF1

TOIE1

TOV1

INT0

INTF0

OCIE1A

OCF1A

-

24

25

OCIE1B

OCF1B

-

TICIE1

ICF1

-

TOIE0

TOV0

-

Reserved

MCUCR

Reserved

TCCR0

TCNT0

Reserved

TCCR1A

TCCR1B

TCNT1H

TCNT1L

OCR1AH

OCR1AL

OCR1BH

OCR1BL

Reserved

ICR1H

SRE

-

SRW

-

SE

-

SM

-

ISC11

-

ISC10

CS02

ISC01

CS01

ISC00

CS00

26

29

30

Timer/Counter0 (8 Bit)

COM1A1

ICNC1

COM1A0

ICES1

COM1B1

-

COM1B0

-

PWM11

CS11

PWM10

CS10

32

33

34

35

CTC1

CS12

Timer/Counter1 - Counter Register High Byte

Timer/Counter1 - Counter Register Low Byte

Timer/Counter1 - Output Compare Register A High Byte

Timer/Counter1 - Output Compare Register A Low Byte

Timer/Counter1 - Output Compare Register B High Byte

Timer/Counter1 - Output Compare Register B Low Byte

Timer/Counter1 - Input Capture Register High Byte

Timer/Counter1 - Input Capture Register Low Byte

36

ICR1L

Reserved

WDTCR

Reserved

EEARL

EEDR

-

WDTOE

-

WDE

-

WDP2

-

WDP1

-

WDP0

38

EEAR8

39

40

54

56

61

63

45

44

48

49

51

52

EEPROM Address Register Low Byte

EEPROM Data Register

EECR

PORTA

DDRA

PINA

PORTB

DDRB

-

EEMWE

PORTA2

DDA2

PINA2

PORTB2

DDB2

EEWE

PORTA1

DDA1

PINA1

PORTB1

DDB1

EERE

PORTA0

DDA0

PINA0

PORTB0

DDB0

PORTA7

DDA7

PINA7

PORTB7

DDB7

PORTA6

DDA6

PINA6

PORTB6

DDB6

PORTA5

DDA5

PINA5

PORTB5

DDB5

PORTA4

DDA4

PINA4

PORTB4

DDB4

PORTA3

DDA3

PINA3

PORTB3

DDB3

PINB

PORTC

DDRC

PINC

PORTD

DDRD

PINB7

PORTC7

DDC7

PINC7

PORTD7

DDD7

PINB6

PORTC6

DDC6

PINC6

PORTD6

DDD6

PINB5

PORTC5

DDC5

PINC5

PORTD5

DDD5

PINB4

PORTC4

DDC4

PINC4

PORTD4

DDD4

PINB3

PORTC3

DDC3

PINC3

PORTD3

DDD3

PINB2

PORTC2

DDC2

PINC2

PORTD2

DDD2

PINB1

PORTC1

DDC1

PINC1

PORTD1

DDD1

PINB0

PORTC0

DDC0

PINC0

PORTD0

DDD0

PIND

SPDR

SPSR

SPCR

UDR

USR

PIND7

SPI Data Register

SPIF

SPIE

UART I/O Data Register

RXC

PIND6

PIND5

PIND4

PIND3

PIND2

PIND1

PIND0

WCOL

SPE

-

DORD

MSTR

CPOL

CPHA

SPR1

SPR0

TXC

UDRE

FE

OR

-

UCR

UBRR

ACSR

Reserved

RXCIE

UART Baud Rate Register

ACD

TXCIE

UDRIE

RXEN

TXEN

CHR9

RXB8

TXB8

-

ACO

ACI

ACIE

ACIC

ACIS1

ACIS0

$00 ($20)

AT90S8515

72

AT90S8515

AT90S8515 Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

ADC

ADIW

SUB

SUBI

SBC

SBCI

SBIW

AND

ANDI

OR

Rd, Rr

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add two Registers

Rd ← Rd + Rr

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

1

2

1

2

1

Add with Carry two Registers

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rdh:Rdl ← Rdh:Rdl - K

Rd ← Rd • Rr

Rd ← Rd • K

Rd ← Rd v Rr

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Rd ← Rd v K

EOR

COM

NEG

SBR

CBR

INC

Rd ← Rd Rr

Rd ← $FF − Rd

Rd ← $00 − Rd

Rd ← Rd v K

Rd ← Rd • ($FF - K)

Rd ← Rd + 1

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

Set Bit(s) in Register

Clear Bit(s) in Register

Increment

Decrement

Test for Zero or Minus

Clear Register

Set Register

Rd,K

Rd

DEC

TST

Rd ← Rd − 1

Z,N,V

Rd ← Rd • Rd

Rd ← Rd Rd

Rd ← $FF

CLR

SER

Rd

Z,N,V

None

BRANCH INSTRUCTIONS

RJMP

IJMP

RCALL

ICALL

RET

k

Relative Jump

Indirect Jump to (Z)

Relative Subroutine Call

Indirect Call to (Z)

Subroutine Return

PC ← PC + k + 1

PC ← Z

PC ← PC + k + 1

PC ← Z

PC ← STACK

None

I

2

3

k

3

4

RETI

Interrupt Return

CPSE

CP

CPC

Rd,Rr

Compare, Skip if Equal

Compare

Compare with Carry

if (Rd = Rr) PC ← PC + 2 or 3

Rd − Rr

Rd − Rr − C

None

1 / 2

1

Z, N,V,C,H

None

CPI

Rd,K

Rr, b

P, b

s, k

k

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Branch if Not Equal

Branch if Carry Set

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

Rd − K

1

SBRC

SBRS

SBIC

SBIS

if (Rr(b)=0) PC ← PC + 2 or 3

if (Rr(b)=1) PC ← PC + 2 or 3

if (P(b)=0) PC ← PC + 2 or 3

if (P(b)=1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC←PC+k + 1

if (SREG(s) = 0) then PC←PC+k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N V= 0) then PC ← PC + k + 1

if (N V= 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

if ( I = 1) then PC ← PC + k + 1

if ( I = 0) then PC ← PC + k + 1

1 / 2

None

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

BRID

None

k

None

Branch if Minus

Branch if Plus

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

Branch if T Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

k

None

k

None

73

AT90S8515 Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

DATA TRANSFER INSTRUCTIONS

MOV

LDI

LD

Rd, Rr

Rd, K

Move Between Registers

Load Immediate

Rd ← Rr

Rd ← K

None

1

2

3

1

2

Rd, X

Load Indirect

Rd ← (X)

Rd, X+

Rd, - X

Rd, Y

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

In Port

Rd ← (X), X ← X + 1

X ← X - 1, Rd ← (X)

Rd ← (Y)

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

Rd ← (Z)

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

Rd ← (k)

LDD

LD

LDD

LDS

ST

X, Rr

(X) ← Rr

X+, Rr

- X, Rr

Y, Rr

Y+, Rr

- Y, Rr

Y+q,Rr

Z, Rr

Z+, Rr

-Z, Rr

Z+q,Rr

k, Rr

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

STD

ST

(Z) ← Rr

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

ST

STD

STS

LPM

IN

OUT

PUSH

POP

(k) ← Rr

R0 ← (Z)

Rd ← P

P ← Rr

STACK ← Rr

Rd ← STACK

Rd, P

P, Rr

Rr

Out Port

Push Register on Stack

Pop Register from Stack

Rd

BIT AND BIT-TEST INSTRUCTIONS

SBI

CBI

LSL

P,b

Rd

s

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

Logical Shift Right

Rotate Left Through Carry

Rotate Right Through Carry

Arithmetic Shift Right

Swap Nibbles

Flag Set

Flag Clear

Bit Store from Register to T

Bit load from T to Register

Set Carry

I/O(P,b) ← 1

I/O(P,b) ← 0

Rd(n+1) ← Rd(n), Rd(0) ← 0

Rd(n) ← Rd(n+1), Rd(7) ← 0

Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

None

Z,C,N,V

2

1

3

1

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Rd(n) ← Rd(n+1), n=0..6

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

Z,C,N,V

None

SREG(s)

T

None

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

C ← 0

N ← 1

N ← 0

Z ← 1

s

Rr, b

Rd, b

C

N

Z

Clear Carry

Set Negative Flag

Clear Negative Flag

Set Zero Flag

Clear Zero Flag

Z ← 0

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow.

Clear Twos Complement Overflow

Set T in SREG

I ← 1

I ← 0

S ← 1

S ← 0

V ← 1

V ← 0

I

S

V

CLI

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

NOP

SLEEP

WDR

T ← 1

T ← 0

H ← 1

H ← 0

T

H

None

Clear T in SREG

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

No Operation

Sleep

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

Watchdog Reset

AT90S8515

74

AT90S8515

Ordering Information

Speed (MHz)

Power Supply

Ordering Code*

Package

Operation Range

4

2.7 - 6.0V

AT90S8515-4AC

AT90S8515-4JC

AT90S8515-4PC

44A

44J

Commercial

(0°C to 70°C)

40P6

AT90S8515-4AI

AT90S8515-4JI

AT90S8515-4PI

44A

44J

Industrial

(-40°C to 85°C)

40P6

8

4.0 - 6.0V

AT90S8515-8AC

AT90S8515-8JC

AT90S8515-8PC

44A

44J

Commercial

(0°C to 70°C)

40P6

AT90S8515-8AI

AT90S8515-8JI

AT90S8515-8PI

44A

44J

Industrial

(-40°C to 85°C)

40P6

Package Type

44A

44J

44-Lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

44-Lead, Plastic J-Leaded Chip Carrier (PLCC)

40P6

40-Lead, 0.600” Wide, Plastic Dual Inline Package (PDIP)

75

Packaging Information

44A, 44-Lead, Thin (1.0 mm) Plastic Gull Wing Quad

Flat Package (TQFP)

44J, 44-Lead, Plastic J-Leaded Chip Carrier (PLCC)

Dimensions in Inches and (Millimeters)

Dimensions in Millimeters and (Inches)*

.045(1.14) X 30° - 45°

.045(1.14) X 45°

PIN NO. 1

IDENTIFY

.012(.305)

.008(.203)

.630(16.0)

.590(15.0)

.656(16.7)

.650(16.5)

SQ

.032(.813)

.026(.660)

.021(.533)

.013(.330)

.695(17.7)

.685(17.4)

SQ

.043(1.09)

.020(.508)

.120(3.05)

.050(1.27) TYP

.500(12.7) REF SQ

.090(2.29)

.180(4.57)

.165(4.19)

.022(.559) X 45° MAX (3X)

*Controlling dimension: millimeters

40P6, 40-Lead, 0.600" Wide,

Plastic Dual Inline Package (PDIP)

Dimensions in Inches and (Millimeters)

JEDEC STANDARD MS-011 AC

2.07(52.6)

2.04(51.8)

1

.566(14.4)

.530(13.5)

.090(2.29)

MAX

1.900(48.26) REF

.220(5.59)

MAX

.005(.127)

MIN

SEATING

PLANE

.065(1.65)

.015(.381)

.161(4.09)

.125(3.18)

.022(.559)

.014(.356)

.065(1.65)

.041(1.04)

.110(2.79)

.090(2.29)

.630(16.0)

.590(15.0)

0

15

REF

.012(.305)

.008(.203)

.690(17.5)

.610(15.5)

AT90S8515

76


型号：	AT90S8515-4AC
厂家：	ATMEL
描述：	8-Bit Microcontroller with 8K bytes In-System Programmable Flash 8位微控制器具有8K字节的系统内可编程闪存闪存微控制器和处理器外围集成电路静态存储器异步传输模式 ATM 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总76页 (文件大小：2724K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT90S8515-4AC [ATMEL]

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