AT90S4434-8PC_技术文档

Features

• AVR^®- High-performance and Low-power RISC Architecture

– 118 Powerful Instructions - Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Up to 8 MIPS Throughput at 8 MHz

• Data and Nonvolatile Program Memories

– 4K/8K Bytes of In-System Programmable Flash

SPI Serial Interface for In-System Programming

Endurance: 1,000 Write/Erase Cycles

– 256/512 Bytes EEPROM

Endurance: 100,000 Write/Erase Cycles

– 256/512 Bytes Internal SRAM

– Programming Lock for Software Security

• Peripheral Features

8-bit

Microcontroller

with 4K/8K

BytesIn-System

Programmable

Flash

– 8-channel, 10-bit ADC

– Programmable UART

– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode

– One 16-bit Timer/Counter with Separate Prescaler, Compare and

Capture Modes, and dual 8-, 9-, or 10-bit PWM

– Programmable Watchdog Timer with On-chip Oscillator

– On-chip Analog Comparator

• Special Microcontroller Features

– Power-on Reset Circuit

– Real Time Clock (RTC) with Separate Oscillator and Counter Mode

– External and Internal Interrupt Sources

– Three Sleep Modes: Idle, Power Save, and Power Down

• Power Consumption at 4 MHz, 3V, 20°C

– Active: 6.4 mA

– Idle Mode: 1.9 mA

– Power Down Mode: <1 µA

• I/O and Packages

AT90S4434

AT90LS4434

AT90S8535

AT90LS8535

– 32 Programmable I/O Lines

– 40-pin PDIP, 44-pin PLCC and 44-pin TQFP

• Operating Voltages

– V_CC: 4.0 - 6.0V AT90S4434/AT90S8535

– V_CC: 2.7 - 6.0V AT90LS4434/AT90LS8535

• Speed Grades:

Preliminary

– 0 - 8 MHz AT90S4434/AT90S8535

– 0 - 4 MHz AT90LS4434/AT90LS8535

Pin Configurations

Rev. 1041ES–04/99

Note: This is a summary document. For the complete 113 page

document, please visit out Website at www.atmel.com or e-mail

1

at literature@atmel.com and request literature number 1041E.

Description

The AT90S4434/8535 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing pow-

erful instructions in a single clock cycle, the AT90S4434/8535 achieves throughputs approaching 1 MIPS per MHz allowing

the system designer to optimize power consumption versus processing speed.

Block Diagram

Figure 1. The AT90S4434/8535 Block Diagram

PA0 - PA7

PC0 - PC7

VCC

PORTA DRIVERS

PORTC DRIVERS

GND

DATA REGISTER

DATA DIR.

DATA REGISTER

DATA DIR.

PORTA

REG. PORTA

PORTC

REG. PORTC

8-BIT DATA BUS

AVCC

ANALOG MUX

ADC

OSCILLATOR

AGND

AREF

XTAL1

XTAL2

INTERNAL

OSCILLATOR

PROGRAM

COUNTER

STACK

POINTER

WATCHDOG

TIMER

TIMING AND

CONTROL

RESET

PROGRAM

FLASH

MCU CONTROL

REGISTER

SRAM

INSTRUCTION

REGISTER

GENERAL

PURPOSE

REGISTERS

TIMER/

COUNTERS

X

Y

Z

INSTRUCTION

DECODER

INTERRUPT

UNIT

CONTROL

LINES

ALU

EEPROM

STATUS

REGISTER

PROGRAMMING

LOGIC

SPI

UART

DATA REGISTER

PORTB

DATA DIR.

REG. PORTB

DATA REGISTER

PORTD

DATA DIR.

REG. PORTD

PORTB DRIVERS

PORTD DRIVERS

PB0 - PB7

PD0 - PD7

AT90S/LS4434 and AT90S/LS8535

2

AT90S/LS4434 and AT90S/LS8535

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly

connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction

executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times

faster than conventional CISC microcontrollers.

The AT90S4434/8535 provides the following features: 4K/8K bytes of In-System Programmable Flash, 256/512 bytes

EEPROM, 256/512 bytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, Real Time Clock

(RTC), three flexible timer/counters with compare modes, internal and external interrupts, a programmable serial UART, 8-

channel, 10-bit ADC, programmable Watchdog Timer with internal oscillator, an SPI serial port, and three software select-

able power saving modes. The Idle mode stops the CPU while allowing the SRAM, timer/counters, SPI port, and interrupt

system to continue functioning. The Power Down mode saves the register contents but freezes the oscillator, disabling all

other chip functions until the next interrupt or hardware reset. In Power Save mode, the timer oscillator continues to run,

allowing the user to maintain a timer base while the rest of the device is sleeping.

The device is manufactured using Atmel’s high density nonvolatile memory technology. The on-chip ISP Flash allows the

program memory to be reprogrammed in-system through an SPI serial interface or by a conventional nonvolatile memory

programmer. By combining an 8-bit RISC CPU with In-System Programmable Flash on a monolithic chip, the Atmel

AT90S4434/8535 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded

control applications.

The AT90S4434/8535 AVR is supported with a full suite of program and system development tools including: C compilers,

macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

Comparison between AT90S4434 and AT90S8535

The AT90S4434 has 4K bytes of In-System Programmable Flash, 256 bytes of EEPROM, and 256 bytes of internal SRAM.

The AT90S8535 has 8K bytes of In-System Programmable Flash, 512 bytes of EEPROM, and 512 bytes of internal SRAM.

Table 1 summarizes the different memory sizes for the two devices.

Table 1. Memory Size Summary

Part

Flash

EEPROM

256 bytes

512 bytes

SRAM

AT90S4434

AT90S8535

4K bytes

8K bytes

256 bytes

512 bytes

Pin Descriptions

VCC

Digital supply voltage

GND

Digital ground

Port A (PA7..PA0)

Port A is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors (selected for each bit). The Port A

output buffers can sink 20mA and can drive LED displays directly. When pins PA0 to PA7 are used as inputs and are exter-

nally pulled low, they will source current if the internal pull-up resistors are activated.

Port A also serves as the analog inputs to the A/D Converter.

The Port A pins are tristated when a reset condition becomes active, even if the clock is not running.

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port B output buffers can sink 20 mA. As inputs,

Port B pins that are externally pulled low will source current if the pull-up resistors are activated. Port B also serves the

functions of various special features of the AT90S4434/8535 as listed on page 68.

3

The Port B pins are tristated when a reset condition becomes active, even if the clock is not running.

Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pullup resistors. The Port C output buffers can sink 20 mA. As inputs,

Port C pins that are externally pulled low will source current if the pull-up resistors are activated. Two Port C pins can alter-

natively be used as oscillator for Timer/Counter2.

The port C pins are tristated when a reset condition becomes active, even if the clock is not running.

Port D (PD7..PD0)

Port D is an 8-bit bidirectional I/O port with internal pull-up resistors. The Port D output buffers can sink 20 mA. As inputs,

Port D pins that are externally pulled low will source current if the pull-up resistors are activated.

Port D also serves the functions of various special features of the AT90S4434/8535 as listed on page 76.

The port D pins are tristated when a reset condition becomes active, even if the clock is not running.

RESET

Reset input. An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate

a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.

XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier

AVCC

This is the supply voltage pin for the A/D Converter. It should be externally connected to V_CCvia a low-pass filter. See

page 59 for details on operation of the ADC.

AREF

This is the analog reference input for the A/D Converter. For ADC operations, a voltage in the range AGND to AV_CCmust

be applied to this pin.

AGND

Analog ground. If the board has a separate analog ground plane, this pin should be connected to this ground plane. Other-

wise, connect to GND.

AT90S/LS4434 and AT90S/LS8535

4

AT90S/LS4434 and AT90S/LS8535

Architectural Overview

The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access

time. This means that during one single clock cycle, one Arithmetic Logic Unit (ALU) operation is executed. Two operands

are output from the register file, the operation is executed, and the result is stored back in the register file - in one clock

cycle.

Six of the 32 registers can be used as three 16-bits indirect address register pointers for Data Space addressing - enabling

efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table

look up function. These added function registers are the 16-bits X-register, Y-register and Z-register.

Figure 2. The AT90S4434/8535 AVR RISC Architecture

AVR AT90S4434/8535 Architecture

Data Bus 8-bit

Program

Counter

Status

and Control

Interrupt

Unit

2K/4K X 16

Program

Memory

SPI

Unit

32 x 8

General

Purpose

Registrers

Instruction

Register

Serial

UART

Instruction

Decoder

8-bit

Timer/Counter

ALU

Control Lines

16-bit

Timer/Counter

with PWM

8-bit

Timer/Counter

with PWM

256/512 x 8

Data

SRAM

Watchdog

Timer

256/512 x 8

EEPROM

Analog to Digital

Converter

32

I/O Lines

Analog

Comparator

The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register

operations are also executed in the ALU. Figure 2 shows the AT90S4434/8535 AVR RISC microcontroller architecture.

In addition to the register operation, the conventional memory addressing modes can be used on the register file as well.

This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing

them to be accessed as though they were ordinary memory locations.

5

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, A/D-

converters, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following

those of the register file, $20 - $5F.

The AVR uses a Harvard architecture concept - with separate memories and buses for program and data. The program

memory is executed with a two stage pipeline. While one instruction is being executed, the next instruction is pre-fetched

from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is

in-system downloadable Flash memory.

With the relative jump and call instructions, the whole 2K/4K address space is directly accessed. Most AVR instructions

have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.

During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is effec-

tively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the

usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are exe-

cuted). The 9/10-bit stack pointer SP is read/write accessible in the I/O space.

The 256/512 bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR

architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

Figure 3. Memory Maps

Program Memory

Data Memory

$0000

$000

32 Gen. Purpose

Working Registers

$001F

$0020

64 I/O Registers

EEPROM

Program Flash

(2K/4K x 16)

(256/512 x 8)

$005F

$0060

$0FF/$1FF

Internal SRAM

(256/512 x 8)

$015F/$025F

$7FF/$FFF

A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status

register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the pro-

gram memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the

interrupt vector address, the higher the priority.

AT90S/LS4434 and AT90S/LS8535

6

AT90S/LS4434 and AT90S/LS8535

Register Summary

Address

Name

SREG

SPH

SPL

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

$3F ($5F)

$3E ($5E)

$3D ($5D)

$3C ($5C)

$3B ($5B)

$3A ($5A)

$39 ($59)

$38 ($58)

$37 ($57)

$36 ($56)

$35 ($55)

$34 ($54)

$33 ($53)

$32 ($52)

$31 ($51)

$30 ($50)

$2F ($4F)

$2E ($4E)

$2D ($4D)

$2C ($4C)

$2B ($4B)

$2A ($4A)

$29 ($49)

$28 ($48)

$27 ($47)

$26 ($46)

$25 ($45)

$24 ($44)

$23 ($43)

$22 ($42)

$21 ($41)

$20 ($40)

$1F ($3F)

$1E ($3E)

$1D ($3D)

$1C ($3C)

$1B ($3B)

$1A ($3A)

$19 ($39)

$18 ($38)

$17 ($37)

$16 ($36)

$15 ($35)

$14 ($34)

$13 ($33)

$12 ($32)

$11 ($31)

$10 ($30)

$0F ($2F)

$0E ($2E)

$0D ($2D)

$0C ($2C)

$0B ($2B)

$0A ($2A)

$09 ($29)

$08 ($28)

$07 ($27)

$06 ($26)

$05 ($25)

$04 ($24)

I

-

T

-

SP6

H

-

SP5

S

-

SP4

V

-

SP3

N

-

SP2

Z

SP9

SP1

C

SP8

SP0

page 17

page 18

SP7

Reserved

GIMSK

GIFR

TIMSK

TIFR

INT1

INTF1

OCIE2

OCF2

INT0

INTF0

TOIE2

TOV2

-

page 23

page 24

page 25

TICIE1

ICF1

OCIE1A

OCF1A

OCIE1B

OCF1B

TOIE1

TOV1

-

TOIE0

TOV0

Reserved

MCUCR

MCUSR

TCCR0

TCNT0

Reserved

TCCR1A

TCCR1B

TCNT1H

TCNT1L

OCR1AH

OCR1AL

OCR1BH

OCR1BL

ICR1H

ICR1L

-

SE

-

SM1

-

SM0

-

ISC11

-

ISC10

-

CS02

ISC01

EXTRF

CS01

ISC00

PORF

CS00

page 26

page 22

page 30

page 31

Timer/Counter0 (8 Bits)

COM1A1

ICNC1

COM1A0

ICES1

COM1B1

-

COM1B0

-

PWM11

CS11

PWM10

CS10

page 33

page 34

page 35

page 36

page 40

page 41

page 42

page 44

CTC1

CS12

Timer/Counter1 - Counter Register High Byte

Timer/Counter1 - Counter Register Low Byte

Timer/Counter1 - Output Compare Register A High Byte

Timer/Counter1 - Output Compare Register A Low Byte

Timer/Counter1 - Output Compare Register B High Byte

Timer/Counter1 - Output Compare Register B Low Byte

Timer/Counter1 - Input Capture Register High Byte

Timer/Counter1 - Input Capture Register Low Byte

TCCR2

TCNT2

OCR2

-

PWM2

Timer/Counter2 (8 Bits)

Timer/Counter2 Output Compare Register

COM21

COM20

CTC2

CS22

CS21

CS20

ASSR

-

AS2

WDE

TCN2UB

WDP2

OCR2UB

WDP1

TCR2UB

WDP0

WDTCR

Reserved

EEARH

EEARL

EEDR

EECR

PORTA

DDRA

WDTOE

EEAR9

EEAR0

page 46

page 67

page 69

page 74

page 77

page 51

page 50

page 55

page 56

page 57

page 58

page 63

page 64

EEAR7

EEPROM Data Register

EEAR6

EEAR5

EEAR4

EEAR3

EEAR2

EEAR1

-

EERIE

PORTA3

DDA3

EEMWE

PORTA2

DDA2

EEWE

PORTA1

DDA1

EERE

PORTA0

DDA0

PORTA7

DDA7

PINA7

PORTB7

DDB7

PINB7

PORTC7

DDC7

PINC7

PORTD7

DDD7

PORTA6

DDA6

PINA6

PORTB6

DDB6

PINB6

PORTC6

DDC6

PINC6

PORTD6

DDD6

PORTA5

DDA5

PINA5

PORTB5

DDB5

PINB5

PORTC5

DDC5

PINC5

PORTD5

DDD5

PORTA4

DDA4

PINA4

PORTB4

DDB4

PINB4

PORTC4

DDC4

PINC4

PORTD4

DDD4

PINA

PINA3

PINA2

PINA1

PINA0

PORTB

DDRB

PINB

PORTC

DDRC

PINC

PORTB3

DDB3

PINB3

PORTC3

DDC3

PINC3

PORTD3

DDD3

PORTB2

DDB2

PINB2

PORTC2

DDC2

PINC2

PORTB1

DDB1

PINB1

PORTC1

DDC1

PINC1

PORTD1

DDD1

PORTB0

DDB0

PINB0

PORTC0

DDC0

PINC0

PORTD0

DDD0

PORTD

DDRD

PIND

SPDR

SPSR

PORTD2

DDD2

PIND2

PIND7

SPI Data Register

SPIF

SPIE

PIND6

PIND5

PIND4

PIND3

PIND1

PIND0

WCOL

SPE

-

SPCR

DORD

MSTR

CPOL

CPHA

SPR1

SPR0

UDR

USR

UCR

UBRR

UART I/O Data Register

RXC

RXCIE

UART Baud Rate Register

ACD

-

TXC

TXCIE

UDRE

UDRIE

FE

RXEN

OR

TXEN

-

CHR9

RXB8

TXB8

ACSR

-

ACO

-

ACI

-

ACIE

-

ACIC

MUX2

ADPS2

-

ACIS1

MUX1

ADPS1

ADC9

ADC1

ACIS0

MUX0

ADPS0

ADC8

ADC0

ADMUX

ADCSR

ADCH

ADEN

-

ADC7

ADSC

-

ADC6

ADFR

-

ADC5

ADIF

-

ADC4

ADIE

-

ADC3

ADCL

ADC2

7

Register Summary (Continued)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

$03 ($20)

$02 ($22)

$01 ($21)

$00 ($20)

Reserved

Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on

all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions

work with registers $00 to $1F only.

AT90S/LS4434 and AT90S/LS8535

8

AT90S/LS4434 and AT90S/LS8535

Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

ADC

ADIW

SUB

SUBI

SBC

SBCI

SBIW

AND

ANDI

OR

Rd, Rr

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add two Registers

Rd ← Rd + Rr

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

1

2

1

2

1

Add with Carry two Registers

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rdh:Rdl ← Rdh:Rdl - K

Rd ← Rd • Rr

Rd ← Rd • K

Rd ← Rd v Rr

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Rd ← Rd v K

EOR

COM

NEG

SBR

CBR

INC

Rd ← Rd Rr

Rd ← $FF − Rd

Rd ← $00 − Rd

Rd ← Rd v K

Rd ← Rd • ($FF - K)

Rd ← Rd + 1

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

Set Bit(s) in Register

Clear Bit(s) in Register

Increment

Decrement

Test for Zero or Minus

Clear Register

Set Register

Rd,K

Rd

DEC

TST

Rd ← Rd − 1

Z,N,V

Rd ← Rd • Rd

Rd ← Rd Rd

Rd ← $FF

CLR

SER

Rd

Z,N,V

None

BRANCH INSTRUCTIONS

RJMP

IJMP

RCALL

ICALL

RET

k

Relative Jump

Indirect Jump to (Z)

Relative Subroutine Call

Indirect Call to (Z)

Subroutine Return

PC ← PC + k + 1

PC ← Z

PC ← PC + k + 1

None

I

2

3

PC ← Z

PC ← STACK

3

4

RETI

Interrupt Return

CPSE

CP

CPC

Rd,Rr

Compare, Skip if Equal

Compare

Compare with Carry

if (Rd = Rr) PC ← PC + 2 or 3

Rd − Rr

Rd − Rr − C

None

Z, N,V,C,H

None

1 / 2 / 3

1

CPI

Rd,K

Rr, b

P, b

s, k

k

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Branch if Not Equal

Branch if Carry Set

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

Rd − K

1

SBRC

SBRS

SBIC

SBIS

if (Rr(b)=0) PC ← PC + 2 or 3

if (Rr(b)=1) PC ← PC + 2 or 3

if (P(b)=0) PC ← PC + 2 or 3

if (P(b)=1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC←PC+k + 1

if (SREG(s) = 0) then PC←PC+k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N V= 0) then PC ← PC + k + 1

if (N V= 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

if ( I = 1) then PC ← PC + k + 1

if ( I = 0) then PC ← PC + k + 1

1 / 2 / 3

1 / 2

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

BRID

k

Branch if Minus

Branch if Plus

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

Branch if T Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

k

9

Instruction Set Summary (Continued)

Mnemonics

Operands

Description

Operation

Flags

#Clocks

DATA TRANSFER INSTRUCTIONS

MOV

LDI

LD

Rd, Rr

Rd, K

Rd, X

Rd, X+

Rd, - X

Rd, Y

Move Between Registers

Load Immediate

Load Indirect

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Rd ← Rr

Rd ← K

Rd ← (X)

Rd ← (X), X ← X + 1

X ← X - 1, Rd ← (X)

Rd ← (Y)

None

1

2

3

1

2

LD

LDD

LD

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

Rd ← (Z)

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

Rd ← (k)

LD

LDD

LDS

ST

X, Rr

(X) ← Rr

X+, Rr

- X, Rr

Y, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

ST

STD

ST

Y+, Rr

- Y, Rr

Y+q,Rr

Z, Rr

Z+, Rr

-Z, Rr

Z+q,Rr

k, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

In Port

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

(Z) ← Rr

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

(k) ← Rr

R0 ← (Z)

Rd ← P

P ← Rr

STACK ← Rr

Rd ← STACK

ST

STD

STS

LPM

IN

OUT

PUSH

POP

Rd, P

P, Rr

Rr

Out Port

Push Register on Stack

Pop Register from Stack

Rd

BIT AND BIT-TEST INSTRUCTIONS

SBI

CBI

LSL

P,b

Rd

s

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

Logical Shift Right

Rotate Left Through Carry

Rotate Right Through Carry

Arithmetic Shift Right

Swap Nibbles

I/O(P,b) ← 1

I/O(P,b) ← 0

Rd(n+1) ← Rd(n), Rd(0) ← 0

Rd(n) ← Rd(n+1), Rd(7) ← 0

None

Z,C,N,V

2

1

3

1

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

Rd(n) ← Rd(n+1), n=0..6

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

Z,C,N,V

None

SREG(s)

Flag Set

Flag Clear

s

Rr, b

Rd, b

Bit Store from Register to T

Bit load from T to Register

Set Carry

Clear Carry

Set Negative Flag

Clear Negative Flag

Set Zero Flag

Clear Zero Flag

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow.

Clear Twos Complement Overflow

Set T in SREG

T

None

C

N

C ← 0

N ← 1

N ← 0

Z ← 1

Z ← 0

I ← 1

I ← 0

S ← 1

S ← 0

Z

I

S

CLI

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

NOP

SLEEP

WDR

V ← 1

V ← 0

T ← 1

T ← 0

H ← 1

H ← 0

V

T

H

Clear T in SREG

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

No Operation

Sleep

Watchdog Reset

None

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

AT90S/LS4434 and AT90S/LS8535

10

AT90S/LS4434 and AT90S/LS8535

Ordering Information

Power Supply

Speed (MHz)

Ordering Code

Package

Operation Range

2.7 - 6.0V

4

8

4

8

AT90LS4434-4AC

AT90LS4434-4JC

AT90LS4434-4PC

44A

44J

Commercial

(0°C to 70°C)

40P6

AT90LS4434-4AI

AT90LS4434-4JI

AT90LS4434-4PI

44A

44J

Industrial

(-40°C to 85°C)

40P6

4.0 - 6.0V

2.7 - 6.0V

4.0 - 6.0V

AT90S4434-8AC

AT90S4434-8JC

AT90S4434-8PC

44A

44J

Commercial

(0°C to 70°C)

40P6

AT90S4434-8AI

AT90S4434-8JI

AT90S4434-8PI

44A

44J

Industrial

(-40°C to 85°C)

40P6

AT90LS8535-4AC

AT90LS8535-4JC

AT90LS8535-4PC

44A

44J

Commercial

(0°C to 70°C)

40P6

AT90LS8535-4AI

AT90LS8535-4JI

AT90LS8535-4PI

44A

44J

Industrial

(-40°C to 85°C)

40P6

AT90S8535-8AC

AT90S8535-8JC

AT90S8535-8PC

44A

44J

Commercial

(0°C to 70°C)

40P6

AT90S8535-8AI

AT90S8535-8JI

AT90S8535-8PI

44A

44J

Industrial

(-40°C to 85°C)

40P6

Package Type

44A

40P6

44J

44-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP)

40-lead, 0.600" Wide, Plastic Dual in Line Package (PDIP)

44-lead, Plastic J-Ledded Chip Carrier (PLCC)

11

Packaging Information

44A, 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad

Flat Package (TQFP)

Dimensions in Millimeters and (Inches)

40P6, 40-lead, 0.600" Wide,

Plastic Dual Inline Package (PDIP)

Dimensions in Inches and (Millimeters)

JEDEC STANDARD MS-011 AC

2.07(52.6)

2.04(51.8)

12.21(0.478)

11.75(0.458)

SQ

PIN 1 ID

1

0.45(0.018)

0.30(0.012)

.566(14.4)

.530(13.5)

0.80(0.031) BSC

.090(2.29)

MAX

1.900(48.26) REF

.220(5.59)

MAX

.005(.127)

MIN

10.10(0.394)

9.90(0.386)

SEATING

PLANE

SQ

.065(1.65)

.015(.381)

1.20(0.047) MAX

.161(4.09)

.125(3.18)

0

7

.022(.559)

.014(.356)

0.20(.008)

0.09(.003)

.065(1.65)

.041(1.04)

.110(2.79)

.090(2.29)

.630(16.0)

.590(15.0)

0.75(0.030) 0.15(0.006)

0.45(0.018) 0.05(0.002)

0

REF

*Controlling dimension: millimeters

15

.012(.305)

.008(.203)

.690(17.5)

.610(15.5)

44J, 44-lead, Plastic J-Leaded Chip Carrier (PLCC)

Dimensions in Inches and (Millimeters)

.045(1.14) X 30° - 45°

.045(1.14) X 45°

PIN NO. 1

IDENTIFY

.012(.305)

.008(.203)

.630(16.0)

.590(15.0)

.656(16.7)

.650(16.5)

SQ

.032(.813)

.026(.660)

.021(.533)

.013(.330)

.695(17.7)

.685(17.4)

SQ

.043(1.09)

.020(.508)

.120(3.05)

.050(1.27) TYP

.500(12.7) REF SQ

.090(2.29)

.180(4.57)

.165(4.19)

.022(.559) X 45° MAX (3X)

AT90S/LS4434 and AT90S/LS8535

12

Atmel Headquarters

Atmel Operations

Corporate Headquarters

2325 Orchard Parkway

San Jose, CA 95131

TEL (408) 441-0311

FAX (408) 487-2600

Atmel Colorado Springs

1150 E. Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TEL (719) 576-3300

FAX (719) 540-1759

Europe

Atmel Rousset

Zone Industrielle

13106 Rousset Cedex

France

Atmel U.K., Ltd.

Coliseum Business Centre

Riverside Way

Camberley, Surrey GU15 3YL

England

TEL (33) 4-4253-6000

FAX (33) 4-4253-6001

TEL (44) 1276-686-677

FAX (44) 1276-686-697

Asia

Atmel Asia, Ltd.

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimhatsui

East Kowloon

Hong Kong

TEL (852) 2721-9778

FAX (852) 2722-1369

Japan

Atmel Japan K.K.

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

TEL (81) 3-3523-3551

FAX (81) 3-3523-7581

Fax-on-Demand

North America:

1-(800) 292-8635

International:

1-(408) 441-0732

e-mail

literature@atmel.com

Web Site

http://www.atmel.com

BBS

1-(408) 436-4309

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-

ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for

any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without

notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop-

erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are

not authorized for use as critical components in life support devices or systems.

®

™

Marks bearing and/or are registered trademarks and trademarks of Atmel Corporation.

Terms and product names in this document may be trademarks of others.

Printed on recycled paper.

1041ES–04/99/xM


型号：	AT90S4434-8PC
厂家：	ETC
描述：	(641.00 k) 外围集成电路静态存储器光电二极管微控制器异步传输模式 ATM 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总13页 (文件大小：625K)
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