AT90S2313-4SJ_技术文档

Features

• Utilizes the AVR^®RISC Architecture

• AVR – High-performance and Low-power RISC Architecture

– 118 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General-purpose Working Registers

– Up to 10 MIPS Throughput at 10 MHz

• Data and Nonvolatile Program Memory

– 2K Bytes of In-System Programmable Flash

Endurance 1,000 Write/Erase Cycles

– 128 Bytes of SRAM

– 128 Bytes of In-System Programmable EEPROM

Endurance: 100,000 Write/Erase Cycles

– Programming Lock for Flash Program and EEPROM Data Security

• Peripheral Features

8-bit

Microcontroller

with 2K Bytes

of In-System

Programmable

Flash

– One 8-bit Timer/Counter with Separate Prescaler

– One 16-bit Timer/Counter with Separate Prescaler,

Compare, Capture Modes and 8-, 9- or 10-bit PWM

– On-chip Analog Comparator

– Programmable Watchdog Timer with On-chip Oscillator

– SPI Serial Interface for In-System Programming

– Full Duplex UART

• • Special Microcontroller Features

– Low-power Idle and Power-down Modes

– External and Internal Interrupt Sources

• • Specifications

– Low-power, High-speed CMOS Process Technology

– Fully Static Operation

AT90S2313

• Power Consumption at 4 MHz, 3V, 25°C

– Active: 2.8 mA

– Idle Mode: 0.8 mA

– Power-down Mode: <1 µA

• I/O and Packages

– 15 Programmable I/O Lines

– 20-pin PDIP and SOIC

• Operating Voltages

– 2.7 - 6.0V (AT90S2313-4)

– 4.0 - 6.0V (AT90S2313-10)

• Speed Grades

– 0 - 4 MHz (AT90S2313-4)

– 0 - 10 MHz (AT90S2313-10)

Pin Configuration

PDIP/SOIC

Rev. 0839G–08/01

1

Description

The AT90S2313 is a low-power CMOS 8-bit microcontroller based on the AVR RISC

architecture. By executing powerful instructions in a single clock cycle, the AT90S2313

achieves throughputs approaching 1 MIPS per MHz allowing the system designer to

optimize power consumption versus processing speed.

The AVR core combines a rich instruction set with 32 general-purpose working regis-

ters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),

allowing two independent registers to be accessed in one single instruction executed in

one clock cycle. The resulting architecture is more code efficient while achieving

throughputs up to ten times faster than conventional CISC microcontrollers.

Figure 1. The AT90S2313 Block Diagram

The AT90S2313 provides the following features: 2K bytes of In-System Programmable

Flash, 128 bytes EEPROM, 128 bytes SRAM, 15 general-purpose I/O lines, 32 general-

purpose working registers, flexible timer/counters with compare modes, internal and

external interrupts, a programmable serial UART, programmable Watchdog Timer with

internal oscillator, an SPI serial port for Flash memory downloading and two software

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AT90S2313

selectable power-saving modes. The Idle Mode stops the CPU while allowing the

SRAM, timer/counters, SPI port and interrupt system to continue functioning. The

Power-down Mode saves the register contents but freezes the oscillator, disabling all

other chip functions until the next external interrupt or hardware reset.

The device is manufactured using Atmel’s high-density nonvolatile memory technology.

The on-chip In-System Programmable Flash allows the program memory to be repro-

grammed in-system through an SPI serial interface or by a conventional nonvolatile

memory programmer. By combining an enhanced RISC 8-bit CPU with In-System Pro-

grammable Flash on a monolithic chip, the Atmel AT90S2313 is a powerful

microcontroller that provides a highly flexible and cost-effective solution to many embed-

ded control applications.

The AT90S2313 AVR is supported with a full suite of program and system development

tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit

emulators and evaluation kits.

Pin Descriptions

VCC

Supply voltage pin.

Ground pin.

GND

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors

(selected for each bit). PB0 and PB1 also serve as the positive input (AIN0) and the

negative input (AIN1), respectively, of the on-chip analog comparator. The Port B output

buffers can sink 20 mA and can drive LED displays directly. When pins PB0 to PB7 are

used as inputs and are externally pulled low, they will source current if the internal pull-

up resistors are activated. The Port B pins are tri-stated when a reset condition

becomes active, even if the clock is not active.

Port B also serves the functions of various special features of the AT90S2313 as listed

on page 53.

Port D (PD6..PD0)

Port D has seven bi-directional I/O ports with internal pull-up resistors, PD6..PD0. The

Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled

low will source current if the pull-up resistors are activated. The Port D pins are tri-stated

when a reset condition becomes active, even if the clock is not active.

Port D also serves the functions of various special features of the AT90S2313 as listed

on page 58.

RESET

Reset input. A low level on this pin for more than 50 ns will generate a reset, even if the

clock is not running. Shorter pulses are not guaranteed to generate a reset.

XTAL1

XTAL2

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting oscillator amplifier.

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Crystal Oscillator

XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier that can

be configured for use as an on-chip oscillator, as shown in Figure 2. Either a quartz

crystal or a ceramic resonator may be used. To drive the device from an external clock

source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 3.

Figure 2. Oscillator Connections

MAX 1 HC BUFFER

HC

C2

XTAL2

C1

XTAL1

GND

Note:

When using the MCU Oscillator as a clock for an external device, an HC buffer should be

connected as indicated in the figure.

Figure 3. External Clock Drive Configuration

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AT90S2313

Architectural

Overview

The fast-access register file concept contains 32 x 8-bit general-purpose working regis-

ters with a single clock cycle access time. This means that during one single clock cycle,

one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from

the register file, the operation is executed, and the result is stored back in the register

file – in one clock cycle.

Figure 4. The AT90S2313 AVR RISC Architecture

Six of the 32 registers can be used as three 16-bit indirect address register pointers for

Data Space addressing – enabling efficient address calculations. One of the three

address pointers is also used as the address pointer for the constant table look-up func-

tion. These added function registers are the 16-bit X-register, Y-register and Z-register.

The ALU supports arithmetic and logic functions between registers or between a con-

stant and a register. Single register operations are also executed in the ALU. Figure 4

shows the AT90S2313 AVR RISC microcontroller architecture.

In addition to the register operation, the conventional memory addressing modes can be

used on the register file as well. This is enabled by the fact that the register file is

assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be

accessed as though they were ordinary memory locations.

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The I/O memory space contains 64 addresses for CPU peripheral functions such as

control registers, timer/counters, A/D converters and other I/O functions. The I/O mem-

ory can be accessed directly or as the Data Space locations following those of the

register file, $20 - $5F.

The AVR has Harvard architecture – with separate memories and buses for program

and data. The program memory is accessed with a 2-stage pipeline. While one instruc-

tion is being executed, the next instruction is pre-fetched from the program memory.

This concept enables instructions to be executed in every clock cycle. The program

memory is In-System Programmable Flash memory.

With the relative jump and call instructions, the whole 1K address space is directly

accessed. Most AVR instructions have a single 16-bit word format. Every program

memory address contains a 16- or 32-bit instruction.

During interrupts and subroutine calls, the return address Program Counter (PC) is

stored on the stack. The stack is effectively allocated in the general data SRAM, and

consequently the stack size is only limited by the total SRAM size and the usage of the

SRAM. All user programs must initialize the SP in the reset routine (before subroutines

or interrupts are executed). The 8-bit stack pointer (SP) is read/write accessible in the

I/O space.

The 128 bytes data SRAM + register file and I/O registers can be easily accessed

through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

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Figure 5. Memory Maps

A flexible interrupt module has its control registers in the I/O space with an additional

global interrupt enable bit in the Status Register. All the different interrupts have a sepa-

rate interrupt vector in the interrupt vector table at the beginning of the

program memory. The different interrupts have priority in accordance with their interrupt

vector position. The lower the interrupt vector address, the higher the priority.

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General-purpose

Register File

Figure 6 shows the structure of the 32 general-purpose registers in the CPU.

Figure 6. AVR CPU General-purpose Working Registers

7

0

Addr.

$00

$01

R0

R1

R2

$02

…

R13

R14

R15

R16

R17

…

$0D

$0E

$0F

$10

$11

General

Purpose

Working

Registers

R26

R27

R28

R29

R30

R31

$1A

$1B

$1C

$1D

$1E

$1F

X-register low byte

X-register high byte

Y-register low byte

Y-register high byte

Z-register low byte

Z-register high byte

All the register operating instructions in the instruction set have direct and single-cycle

access to all registers. The only exception is the five constant arithmetic and logic

instructions SBCI, SUBI, CPI, ANDI, ORI between a constant and a register and the LDI

instruction for load immediate constant data. These instructions apply to the second half

of the registers in the register file (R16..R31). The general SBC, SUB, CP, AND, OR and

all other operations between two registers or on a single register apply to the entire reg-

ister file.

As shown in Figure 6, each register is also assigned a data memory address, mapping

them directly into the first 32 locations of the user Data Space. Although the register file

is not physically implemented as SRAM locations, this memory organization provides

great flexibility in access of the registers, as the X, Y and Z registers can be set to index

any register in the file.

X-register, Y-register, and Z-

register

The registers R26..R31 have some added functions to their general-purpose usage.

These registers are the address pointers for indirect addressing of the Data Space. The

three indirect address registers X, Y and Z are defined in Figure 7.

Figure 7. X, Y and Z Registers

15

7

0

X-register

0

7

R27 ($1B)

R26 ($1A)

15

7

0

Y-register

Z-register

0

7

R29 ($1D)

R31 ($1F)

R28 ($1C)

R30 ($1E)

15

7

0

7

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In the different addressing modes these address registers have functions as fixed dis-

placement, automatic increment and decrement (see the descriptions for the different

instructions).

ALU – Arithmetic Logic

Unit

The high-performance AVR ALU operates in direct connection with all the 32 general-

purpose working registers. Within a single clock cycle, ALU operations between regis-

ters in the register file are executed. The ALU operations are divided into three main

categories – arithmetic, logical and bit functions.

In-System

The AT90S2313 contains 2K bytes on-chip In-System Programmable Flash memory for

program storage. Since all instructions are 16- or 32-bit words, the Flash is organized as

1K x 16. The Flash memory has an endurance of at least 1,000 write/erase cycles.

Programmable Flash

Program Memory

The AT90S2313 Program Counter (PC) is 10 bits wide, thus addressing the 1,024 pro-

gram memory addresses.

See page 62 for a detailed description on Flash data downloading. See page 11 for the

different addressing modes.

EEPROM Data Memory

The AT90S2313 contains 128 bytes of EEPROM data memory. It is organized as a sep-

arate data space in which single bytes can be read and written. The EEPROM has an

endurance of at least 100,000 write/erase cycles. The access between the EEPROM

and the CPU is described on page 40, specifying the EEPROM address register, the

EEPROM data register and the EEPROM control register.

For the SPI data downloading, see page 69 for a detailed description.

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SRAM Data Memory

Figure 8 shows how the AT90S2313 data memory is organized.

Figure 8. SRAM Organization

Register File

Data Address Space

R0

R1

R2

…

$00

$01

$02

…

R29

R30

R31

$1D

$1E

$1F

I/O Registers

$00

$20

$21

$22

…

$01

$02

…

$3D

$3E

$3F

$5D

$5E

$5F

Internal SRAM

$60

$61

$62

…

$DD

$DE

$DF

The 224 data memory locations address the Register file, I/O memory and the data

SRAM. The first 96 locations address the Register File + I/O Memory, and the next 128

locations address the data SRAM.

The five different addressing modes for the data memory cover: Direct, Indirect with Dis-

placement, Indirect, Indirect with Pre-decrement and Indirect with Post-increment. In the

register file, registers R26 to R31 feature the indirect addressing pointer registers.

The Direct addressing reaches the entire data address space.

The Indirect with Displacement mode features 63 address locations reached from the

base address given by the Y and Z registers.

When using register indirect addressing modes with automatic pre-decrement and post-

increment, the address registers X, Y and Z are used and decremented and

incremented.

The 32 general-purpose working registers, 64 I/O registers and the 128 bytes of data

SRAM in the AT90S2313 are all directly accessible through all these addressing modes.

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AT90S2313

Program and Data

Addressing Modes

The AT90S2313 AVR RISC microcontroller supports powerful and efficient addressing

modes for access to the program memory (Flash) and data memory. This section

describes the different addressing modes supported by the AVR architecture. In the fig-

ures, OP means the operation code part of the instruction word. To simplify, not all

figures show the exact location of the addressing bits.

Register Direct, Single

Register Rd

Figure 9. Direct Single Register Addressing

The operand is contained in register d (Rd).

Register Direct, Two

Registers Rd and Rr

Figure 10. Direct Register Addressing, Two Registers

Operands are contained in register r (Rr) and d (Rd). The result is stored in register d

(Rd).

I/O Direct

Figure 11. I/O Direct Addressing

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Operand address is contained in 6 bits of the instruction word. n is the destination or

source register address.

Data Direct

Figure 12. Direct Data Addressing

A 16-bit data address is contained in the 16 LSBs of a 2-word instruction. Rd/Rr specify

the destination or source register.

Data Indirect with

Displacement

Figure 13. Data Indirect with Displacement

Operand address is the result of the Y- or Z-register contents added to the address con-

tained in 6 bits of the instruction word.

Data Indirect

Figure 14. Data Indirect Addressing

Operand address is the contents of the X-, Y- or Z-register.

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Data Indirect with Pre-

decrement

Figure 15. Data Indirect Addressing with Pre-decrement

The X-, Y- or Z-register is decremented before the operation. Operand address is the

decremented contents of the X-, Y- or Z-register.

Data Indirect with Post-

increment

Figure 16. Data Indirect Addressing with Post-increment

The X-, Y- or Z-register is incremented after the operation. Operand address is the con-

tents of the X-, Y- or Z-register prior to incrementing.

Constant Addressing Using

the LPM Instruction

Figure 17. Code Memory Constant Addressing

Constant byte address is specified by the Z-register contents. The 15 MSBs select word

address (0 - 1K), the LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB =

1).

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Indirect Program Addressing, Figure 18. Indirect Program Memory Addressing

IJMP and ICALL

Program execution continues at address contained by the Z-register (i.e., the PC is

loaded with the contents of the Z-register).

Relative Program Addressing, Figure 19. Relative Program Memory Addressing

RJMP and RCALL

Program execution continues at address PC + k + 1. The relative address k is -2048 to

2047.

Memory Access and

Instruction Execution

Timing

This section describes the general access timing concepts for instruction execution and

internal memory access.

The AVR CPU is driven by the System Clock Ø, directly generated from the external

clock crystal for the chip. No internal clock division is used.

Figure 20 shows the parallel instruction fetches and instruction executions enabled by

the Harvard architecture and the fast-access register file concept. This is the basic pipe-

lining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for

functions per cost, functions per clocks and functions per power-unit.

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AT90S2313

Figure 20. The Parallel Instruction Fetches and Instruction Executions

T1

T2

T3

T4

System Clock Ø

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

Figure 21 shows the internal timing concept for the register file. In a single clock cycle

an ALU operation using two register operands is executed, and the result is stored back

to the destination register.

Figure 21. Single-cycle ALU Operation

T1

T2

T3

T4

System Clock Ø

Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

The internal data SRAM access is performed in two System Clock cycles as described

in Figure 22.

Figure 22. On-chip Data SRAM Access Cycles

T1

T2

T3

T4

System Clock Ø

Prev. Address

Address

Data

WR

Data

RD

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I/O Memory

The I/O space definition of the AT90S2313 is shown in Table 1.

Table 1. AT90S2313 I/O Space

Address Hex

$3F ($5F)

$3D ($5D)

$3B ($5B)

$3A ($5A)

$39 ($59)

$38 ($58)

$35 ($55)

$33 ($53)

$32 ($52)

$2F ($4F)

$2E ($4E)

$2D ($4D)

$2C ($4C)

$2B ($4B)

$2A ($4A)

$25 ($45)

$24 ($44)

$21 ($41)

$1E ($3E)

$1D ($3D)

$1C ($3C)

$18 ($38)

$17 ($37)

$16 ($36)

$12 ($32)

$11 ($31)

$10 ($30)

$0C ($2C)

$0B ($2B)

$0A ($2A)

$09 ($29)

$08 ($28)

Name

SREG

SPL

Function

Status Register

Stack Pointer Low

GIMSK

GIFR

General Interrupt MaSK register

General Interrupt Flag Register

Timer/Counter Interrupt MaSK register

Timer/Counter Interrupt Flag register

MCU general Control Register

Timer/Counter 0 Control Register

Timer/Counter 0 (8-bit)

TIMSK

TIFR

MCUCR

TCCR0

TCNT0

TCCR1A

TCCR1B

TCNT1H

TCNT1L

OCR1AH

OCR1AL

ICR1H

ICR1L

WDTCR

EEAR

Timer/Counter 1 Control Register A

Timer/Counter 1 Control Register B

Timer/Counter 1 High Byte

Timer/Counter 1 Low Byte

Output Compare Register 1 High Byte

Output Compare Register 1 Low Byte

T/C 1 Input Capture Register High Byte

T/C 1 Input Capture Register Low Byte

Watchdog Timer Control Register

EEPROM Address Register

EEPROM Data Register

EEDR

EECR

PORTB

DDRB

PINB

EEPROM Control Register

Data Register, Port B

Data Direction Register, Port B

Input Pins, Port B

PORTD

DDRD

PIND

Data Register, Port D

Data Direction Register, Port D

Input Pins, Port D

UDR

UART I/O Data Register

USR

UART Status Register

UCR

UART Control Register

UBRR

UART Baud Rate Register

ACSR

Analog Comparator Control and Status Register

Note:

Reserved and unused locations are not shown in the table.

All AT90S2313 I/O and peripherals are placed in the I/O space. The I/O locations are

accessed by the IN and OUT instructions transferring data between the 32 general-pur-

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pose working registers and the I/O space. I/O registers within the address range $00 -

$1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the

value of single bits can be checked by using the SBIS and SBIC instructions. Refer to

the instruction set section for more details. When using the I/O specific commands IN

and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as

SRAM, $20 must be added to this address. All I/O register addresses throughout this

document are shown with the SRAM address in parentheses.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the status flags are cleared by writing a logical “1” to them. Note that the CBI

and SBI instructions will operate on all bits in the I/O register, writing a “1” back into any

flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers

$00 to $1F only.

The I/O and peripherals control registers are explained in the following sections.

Status Register – SREG

The AVR Status Register (SREG) at I/O space location $3F ($5F) is defined as:

Bit

7

I

R/W

0

6

T

R/W

0

5

H

R/W

0

4

S

R/W

0

3

V

R/W

0

2

N

R/W

0

1

Z

R/W

0

C

R/W

0

$3F ($5F)

Read/Write

Initial value

SREG

• Bit 7 – I: Global Interrupt Enable

The global interrupt enable bit must be set (one) for the interrupts to be enabled. The

individual interrupt enable control is then performed in separate control registers. If the

global interrupt enable bit is cleared (zero), none of the interrupts are enabled indepen-

dent of the individual interrupt enable settings. The I-bit is cleared by hardware after an

interrupt has occurred, and is set by the RETI instruction to enable subsequent

interrupts.

• Bit 6 – T: Bit Copy Storage

The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source

and destination for the operated bit. A bit from a register in the register file can be copied

into T by the BST instruction, and a bit in T can be copied into a bit in a register in the

register file by the BLD instruction.

• Bit 5 – H: Half-carry Flag

The half-carry flag H indicates a half-carry in some arithmetic operations. See the

Instruction Set description for detailed information.

• Bit 4 – S: Sign Bit, S = N ⊕ V

The S-bit is always an exclusive or between the negative flag N and the two’s comple-

ment overflow flag V. See the Instruction Set description for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The two’s complement overflow flag V supports two’s complement arithmetics. See the

Instruction Set description for detailed information.

• Bit 2 – N: Negative Flag

The negative flag N indicates a negative result after the different arithmetic and logic

operations. See the Instruction Set description for detailed information.

• Bit 1 – Z: Zero Flag

The zero flag Z indicates a zero result after the different arithmetic and logic operations.

See the Instruction Set description for detailed information.

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• Bit 0 – C: Carry Flag

The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction

Set description for detailed information.

Note that the Status Register is not automatically stored when entering an interrupt rou-

tine and restored when returning from an interrupt routine. This must be handled by

software.

Stack Pointer – SP

An 8-bit register at I/O address $3D ($5D) forms the stack pointer of the AT90S2313. 8

bits are used to address the 128 bytes of SRAM in locations $60 - $DF.

Bit

7

6

5

4

3

2

1

0

$3D ($5D)

Read/Write

Initial value

SP7

R/W

0

SP6

R/W

0

SP5

R/W

0

SP4

R/W

0

SP3

R/W

0

SP2

R/W

0

SP1

R/W

0

SP0

R/W

0

SPL

The Stack Pointer points to the data SRAM stack area where the Subroutine and Inter-

rupt stacks are located. This stack space in the data SRAM must be defined by the

program before any subroutine calls are executed or interrupts are enabled. The Stack

Pointer must be set to point above $60. The Stack Pointer is decremented by 1 when

data is pushed onto the stack with the PUSH instruction, and it is decremented by 2

when an address is pushed onto the stack with subroutine calls and interrupts. The

Stack Pointer is incremented by 1 when data is popped from the stack with the POP

instruction, and it is incremented by 2 when an address is popped from the stack with

return from subroutine RET or return from interrupt RETI.

Reset and Interrupt

Handling

The AT90S2313 provides 10 different interrupt sources. These interrupts and the sepa-

rate reset vector each have a separate program vector in the program memory space.

All the interrupts are assigned individual enable bits that must be set (one) together with

the I-bit in the Status Register in order to enable the interrupt.

The lowest addresses in the program memory space are automatically defined as the

Reset and Interrupt vectors. The complete list of vectors is shown in Table 2. The list

also determines the priority levels of the different interrupts. The lower the address, the

higher the priority level. RESET has the highest priority, and next is INT0 (the External

Interrupt Request 0), etc.

Table 2. Reset and Interrupt Vectors

Vector No. Program Address Source

Interrupt Definition

Hardware Pin, Power-on Reset and

Watchdog Reset

1

2

3

4

5

6

7

8

$000

$001

$002

$003

$004

$005

$006

$007

RESET

INT0

External Interrupt Request 0

External Interrupt Request 1

Timer/Counter1 Capture Event

Timer/Counter1 Compare Match

Timer/Counter1 Overflow

Timer/Counter0 Overflow

UART, RX Complete

INT1

TIMER1 CAPT1

TIMER1 COMP1

TIMER1 OVF1

TIMER0 OVF0

UART, RX

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Table 2. Reset and Interrupt Vectors (Continued)

Vector No. Program Address Source

Interrupt Definition

9

$008

$009

$00A

UART, UDRE

UART, TX

UART Data Register Empty

UART, TX Complete

10

11

ANA_COMP

Analog Comparator

The most typical and general program setup for the Reset and Interrupt vector

addresses are:

Address Labels Code

Comments

$000

$001

$002

$003

$004

$005

$006

$007

$008

$009

$00a

;

rjmp RESET

; Reset Handler

rjmp EXT_INT0

rjmp EXT_INT1

rjmp TIM_CAPT1

rjmp TIM_COMP1

rjmp TIM_OVF1

rjmp TIM_OVF0

rjmp UART_RXC

rjmp UART_DRE

rjmp UART_TXC

rjmp ANA_COMP

; IRQ0 Handler

; IRQ1 Handler

; Timer1 Capture Handler

; Timer1 Compare Handler

; Timer1 Overflow Handler

; Timer0 Overflow Handler

; UART RX Complete Handler

; UDR Empty Handler

; UART TX Complete Handler

; Analog Comparator Handler

$00b

MAIN:

…

ldi r16,low(RAMEND); Main program start

$00c

$00d

…

out SPL,r16

<instr> xxx

…

Reset Sources

The AT90S2313 has three sources of reset:

•

Power-on Reset. The MCU is reset when the supply voltage is below the Power-on

Reset threshold (V_POT).

External Reset. The MCU is reset when a low level is present on the RESET pin for

more than 50 ns.

Watchdog Reset. The MCU is reset when the Watchdog timer period expires and

the Watchdog is enabled.

During reset, all I/O registers are then set to their initial values, and the program starts

execution from address $000. The instruction placed in address $000 must be an RJMP

(relative jump) instruction to the reset handling routine. If the program never enables an

interrupt source, the interrupt vectors are not used, and regular program code can be

placed at these locations. The circuit diagram in Figure 23 shows the reset logic. Table 3

defines the timing and electrical parameters of the reset circuitry.

19

0839G–08/01

Figure 23. Reset Logic

Table 3. Reset Characteristics (V_CC= 5.0V)

Symbol

Parameter

Min

1.0

0.4

Typ

1.4

0.6

–

Max

1.8

Units

Power-on Reset Threshold Voltage (rising)

Power-on Reset Threshold Voltage (falling)

RESET Pin Threshold Voltage

V

(1)

V_POT

0.8

V_RST

t_TOUT

0.85 V_CC

Reset Delay Time-out Period

FSTRT Unprogrammed

11.0

0.25

16.0

21.0

ms

Reset Delay Time-out Period

FSTRT Programmed

t_TOUT

0.28

0.31

ms

Note:

1. The Power-on Reset will not work unless the supply voltage has been below V_POT

(falling).

The user can select the start-up time according to typical oscillator start-up. The number

of WDT oscillator cycles used for each time-out is shown in Table 4. The frequency of

the Watchdog Oscillator is voltage-dependent, as shown in “Typical Characteristics” on

page 75.

Table 4. Number of Watchdog Oscillator Cycles

FSTRT

Time-out at V_CC= 5V

0.28 ms

Number of WDT Cycles

Programmed

Unprogrammed

256

16K

16.0 ms

Power-on Reset

A Power-on Reset (POR) circuit ensures that the device is reset from power-on. As

shown in Figure 23, an internal timer is clocked from the Watchdog Timer. This timer

prevents the MCU from starting until after a certain period after V_CChas reached the

Power-on Threshold voltage (V_POT) (see Figure 24). The FSTRT Fuse bit in the Flash

can be programmed to give a shorter start-up time if a ceramic resonator or any other

fast-start oscillator is used to clock the MCU.

If the built-in start-up delay is sufficient, RESET can be connected to V_CCdirectly or via

an external pull-up resistor. By holding the RESET pin low for a period after V_CChas

been applied, the Power-on Reset period can be extended. Refer to Figure 25 for a tim-

ing example of this.

20

AT90S2313

0839G–08/01

AT90S2313

Figure 24. MCU Start-up, RESET Tied to V_CC

.

V_POT

VCC

V_RST

RESET

t_TOUT

TIME-OUT

INTERNAL

RESET

Figure 25. MCU Start-up, RESET Controlled Externally

V_POT

VCC

V_RST

RESET

t_TOUT

TIME-OUT

INTERNAL

RESET

External Reset

An external reset is generated by a low level on the RESET pin. Reset pulses longer

than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not

guaranteed to generate a reset. When the applied signal reaches the Reset Threshold

Voltage (V_RST) on its positive edge, the delay timer starts the MCU after the Time-out

period t_TOUThas expired.

Figure 26. External Reset during Operation

21

0839G–08/01

Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of one XTAL cycle

duration. On the falling edge of this pulse, the delay timer starts counting the Time-out

period t_TOUT. Refer to page 38 for details on operation of the Watchdog.

Figure 27. Watchdog Reset during Operation

Interrupt Handling

The AT90S2313 has two 8-bit Interrupt Mask control registers: the GIMSK (General

Interrupt Mask register) and the TIMSK (Timer/Counter Interrupt Mask register).

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter-

rupts are disabled. The user software can set (one) the I-bit to enable interrupts. The I-

bit is set (one) when a Return from Interrupt instruction (RETI) is executed.

For interrupts triggered by events that can remain static (e.g., the Output Compare

Register1 matching the value of Timer/Counter1), the interrupt flag is set when the event

occurs. If the interrupt flag is cleared and the interrupt condition persists, the flag will not

be set until the event occurs the next time.

When the Program Counter is vectored to the actual interrupt vector in order to execute

the interrupt handling routine, hardware clears the corresponding flag that generated the

interrupt. Some of the interrupt flags can also be cleared by writing a logical “1” to the

flag bit position(s) to be cleared.

If an interrupt condition occurs when the corresponding interrupt enable bit is cleared

(zero), the interrupt flag will be set and remembered until the interrupt is enabled, or the

flag is cleared by software.

If one or more interrupt conditions occur when the global interrupt enable bit is cleared

(zero), the corresponding interrupt flag(s) will be set and remembered until the global

interrupt enable bit is set (one), and will be executed by order of priority.

Note that external level interrupt does not have a flag, and will only be remembered for

as long as the interrupt condition is active.

Note that the Status Register is not automatically stored when entering an interrupt rou-

tine and restored when returning from an interrupt routine. This must be handled by

software.

22

AT90S2313

0839G–08/01

AT90S2313

General Interrupt Mask

Register – GIMSK

Bit

7

6

5

–

R

0

4

–

R

0

3

–

R

0

2

–

R

0

1

–

R

0

–

R

0

$3B ($5B)

Read/Write

Initial value

INT1

R/W

0

INT0

R/W

0

GIMSK

• Bit 7 – INT1: External Interrupt Request 1 Enable

When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and

ISC10) in the MCU general Control Register (MCUCR) defines whether the external

interrupt is activated on rising or falling edge of the INT1 pin or level sensed. Activity on

the pin will cause an interrupt request even if INT1 is configured as an output. The corre-

sponding interrupt of External Interrupt Request 1 is executed from program memory

address $002. See also “External Interrupts”.

• Bit 6 – INT0: External Interrupt Request 0 Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and

ISC00) in the MCU general Control Register (MCUCR) defines whether the external

interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on

the pin will cause an interrupt request even if INT0 is configured as an output. The corre-

sponding interrupt of External Interrupt Request 0 is executed from program memory

address $001. See also “External Interrupts.”

• Bits 5..0 – Res: Reserved Bits

These bits are reserved bits in the AT90S2313 and always read as zero.

General Interrupt FLAG

Register – GIFR

Bit

7

INTF1

R/W

0

6

INTF0

R/W

0

5

–

R

0

4

–

R

0

3

–

R

0

2

–

R

0

1

–

R

0

–

R

0

$3A ($5A)

Read/Write

Initial value

GIFR

• Bit 7 – INTF1: External Interrupt Flag1

When an edge on the INT1 pin triggers an interrupt request, the corresponding interrupt

flag, INTF1, becomes set (one). If the I-bit in SREG and the corresponding interrupt

enable bit, INT1 bit in GIMSK, are set (one), the MCU will jump to the interrupt vector.

The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be

cleared by writing a logical “1” to it. The flag is always cleared when INT1 is configured

as level interrupt.

• Bit 6 – INTF0: External Interrupt Flag0

When an edge on the INT0 pin triggers an interrupt request, the corresponding interrupt

flag, INTF0, becomes set (one). If the I-bit in SREG and the corresponding interrupt

enable bit, INT0 bit in GIMSK, are set (one), the MCU will jump to the interrupt vector.

The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be

cleared by writing a logical “1” to it. The flag is always cleared when INT0 is configured

as level interrupt.

• Bits 5..0 – Res: Reserved Bits

These bits are reserved bits in the AT90S2313 and always read as zero.

Note that external level interrupt does not have a flag, and will only be remembered for

as long as the interrupt condition is active.

23

0839G–08/01

Timer/Counter Interrupt Mask

Register – TIMSK

Bit

7

TOIE1

R/W

0

6

OCIE1A

R/W

0

5

–

R

0

4

–

R

0

3

TICIE1

R/W

0

2

–

R

0

1

TOIE0

R/W

0

–

R

0

$39 ($59)

Read/Write

Initial value

TIMSK

• Bit 7 – TOIE1: Timer/Counter1 Overflow Interrupt Enable

When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Overflow Interrupt is enabled. The corresponding interrupt (at vector

$005) is executed if an overflow in Timer/Counter1 occurs (i.e., when the TOV1 bit is set

in the Timer/Counter Interrupt Flag Register [TIFR]).

• Bit 6 – OCIE1A: Timer/Counter1 Output Compare Match Interrupt Enable

When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Compare Match Interrupt is enabled. The corresponding interrupt (at

vector $004) is executed if a compare match in Timer/Counter1 occurs (i.e., when the

OCF1A bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).

• Bit 5,4 – Res: Reserved Bits

These bits are reserved bits in the AT90S2313 and always read as zero.

• Bit 3 – TICIE1: Timer/Counter1 Input Capture Interrupt Enable

When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt

(at vector $003) is executed if a capture-triggering event occurs on PD6(ICP) (i.e., when

the ICF1 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).

• Bit 2 – Res: Reserved Bit

This bit is a reserved bit in the AT90S2313 and always reads as zero.

• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter0 Overflow Interrupt is enabled. The corresponding interrupt (at vector

$006) is executed if an overflow in Timer/Counter0 occurs (i.e., when the TOV0 bit is set

in the Timer/Counter Interrupt Flag Register [TIFR]).

• Bit 0 – Res: Reserved Bit

This bit is a reserved bit in the AT90S2313 and always read as zero.

Timer/Counter Interrupt FLAG

Register – TIFR

Bit

7

TOV1

R/W

0

6

OCF1A

R/W

0

5

–

R

0

4

–

R

0

3

2

–

R

0

1

TOV0

R/W

0

–

R

0

$38 ($58)

Read/Write

Initial value

ICF1

R/W

0

TIFR

• Bit 7 – TOV1: Timer/Counter1 Overflow Flag

The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by

hardware when executing the corresponding interrupt handling vector. Alternatively,

TOV1 is cleared by writing a logical “1” to the flag. When the I-bit in SREG and TOIE1

(Timer/Counter1 Overflow Interrupt Enable) and TOV1 are set (one), the

Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when

Timer/Counter1 changes counting direction at $0000.

• Bit 6 – OCF1A: Output Compare Flag 1A

The OCF1A bit is set (one) when a compare match occurs between the Timer/Counter1

and the data in OCR1A (Output Compare Register1 A). OCF1A is cleared by hardware

24

AT90S2313

0839G–08/01

AT90S2313

when executing the corresponding interrupt handling vector. Alternatively, OCF1A is

cleared by writing a logical “1” to the flag. When the I-bit in SREG and OCIE1A

(Timer/Counter1 Compare Match Interrupt Enable) and the OCF1A are set (one), the

Timer/Counter1 Compare Match Interrupt is executed.

• Bits 5, 4 – Res: Reserved Bits

These bits are reserved bits in the AT90S2313 and always read as zero.

• Bit 3 – ICF1: Input Capture Flag 1

The ICF1 bit is set (one) to flag an input capture event, indicating that the

Timer/Counter1 value has been transferred to the Input Capture Register (ICR1). ICF1

is cleared by hardware when executing the corresponding interrupt handling vector.

Alternatively, ICF1 is cleared by writing a logical “1” to the flag. When the SREG I-bit

and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable) and ICF1 are set (one), the

Timer/Counter1 Capture Interrupt is executed.

• Bit 2 – Res: Reserved Bit

This bit is a reserved bit in the AT90S2313 and always reads as zero.

• Bit 1 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared

by hardware when executing the corresponding interrupt handling vector. Alternatively,

TOV0 is cleared by writing a logical “1” to the flag. When the SREG I-bit and TOIE0

(Timer/Counter0 Overflow Interrupt Enable) and TOV0 are set (one), the

Timer/Counter0 Overflow Interrupt is executed.

• Bit 0 – Res: Reserved Bit

This bit is a reserved bit in the AT90S2313 and always reads as zero.

External Interrupts

The External Interrupts are triggered by the INT1 and INT0 pins. Observe that, if

enabled, the interrupts will trigger even if the INT0/INT1 pins are configured as outputs.

This feature provides a way of generating a software interrupt. The External Interrupts

can be triggered by a falling or rising edge or a low level. This is set up as indicated in

the specification for the MCU Control Register (MCUCR). When the External Interrupt is

enabled and is configured as level-triggered, the interrupt will trigger as long as the pin

is held low.

The External Interrupts are set up as described in the specification for the MCU Control

Register (MCUCR).

Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles,

minimum. Four clock cycles after the interrupt flag has been set, the program vector

address for the actual interrupt handling routine is executed. During this 4-clock-cycle

period, the Program Counter (2 bytes) is pushed onto the stack, and the Stack Pointer is

decremented by 2. The vector is normally a relative jump to the interrupt routine, and

this jump takes two clock cycles. If an interrupt occurs during execution of a multi-cycle

instruction, this instruction is completed before the interrupt is served.

A return from an interrupt handling routine takes four clock cycles. During these four

clock cycles, the Program Counter (2 bytes) is popped back from the stack, the Stack

Pointer is incremented by 2, and the I-flag in SREG is set. When the AVR exits from an

interrupt, it will always return to the main program and execute one more instruction

before any pending interrupt is served.

25

0839G–08/01

MCU Control Register –

MCUCR

The MCU Control Register contains control bits for general MCU functions.

Bit

7

–

6

–

5

SE

R/W

0

4

SM

R/W

0

3

ISC11

R/W

0

2

ISC10

R/W

0

1

ISC01

R/W

0

ISC00

R/W

0

$35 ($55)

Read/Write

Initial value

MCUCR

R

0

R

0

• Bits 7, 6 – Res: Reserved Bits

These bits are reserved bits in the AT90S2313 and always read as zero.

• Bit 5 – SE: Sleep Enable

The SE bit must be set (one) to make the MCU enter the Sleep Mode when the SLEEP

instruction is executed. To avoid the MCU entering the Sleep Mode unless it is the pro-

grammer’s purpose, it is recommended to set the Sleep Enable (SE) bit just before the

execution of the SLEEP instruction.

• Bit 4 – SM: Sleep Mode

This bit selects between the two available sleep modes. When SM is cleared (zero), Idle

Mode is selected as Sleep Mode. When SM is set (one), Power-down Mode is selected

as Sleep Mode. For details, refer to the paragraph “Sleep Modes”.

• Bits 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0

The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the

corresponding interrupt mask in the GIMSK register is set. The level and edges on the

external INT1 pin that activate the interrupt are defined in Table 5.

Table 5. Interrupt 1 Sense Control

ISC11

ISC10

Description

0

1

0

1

0

1

The low level of INT1 generates an interrupt request.

Reserved

The falling edge of INT1 generates an interrupt request.

The rising edge of INT1 generates an interrupt request.

• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the

corresponding interrupt mask is set. The level and edges on the external INT0 pin that

activate the interrupt are defined in Table 6.

Table 6. Interrupt 0 Sense Control

ISC01

ISC00

Description

0

1

0

1

0

1

The low level of INT0 generates an interrupt request.

Reserved

The falling edge of INT0 generates an interrupt request.

The rising edge of INT0 generates an interrupt request.

The value on the INTn pin is sampled before detecting edges. If edge interrupt is

selected, pulses with a duration longer than one CPU clock period will generate an inter-

rupt. Shorter pulses are not guaranteed to generate an interrupt. If low-level interrupt is

selected, the low level must be held until the completion of the currently executing

instruction to generate an interrupt. If enabled, a level-triggered interrupt will generate

an interrupt request as long as the pin is held low.

26

AT90S2313

0839G–08/01

AT90S2313

Sleep Modes

To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruc-

tion must be executed. If an enabled interrupt occurs while the MCU is in a sleep mode,

the MCU awakes, executes the interrupt routine, and resumes execution from the

instruction following SLEEP. The contents of the register file, SRAM and I/O memory

are unaltered. If a reset occurs during Sleep Mode, the MCU wakes up and executes

from the Reset vector.

Idle Mode

When the SM bit is cleared (zero), the SLEEP instruction forces the MCU into the Idle

Mode, stopping the CPU but allowing Timer/Counters, Watchdog and the interrupt sys-

tem to continue operating. This enables the MCU to wake up from external triggered

interrupts as well as internal ones like Timer Overflow interrupt and Watchdog reset. If

wake-up from the Analog Comparator Interrupt is not required, the Analog Comparator

can be powered down by setting the ACD-bit in the Analog Comparator Control and Sta-

tus Register (ACSR). This will reduce power consumption in Idle Mode. When the MCU

wakes up from Idle Mode, the CPU starts program execution immediately.

Power-down Mode

When the SM bit is set (one), the SLEEP instruction forces the MCU into the Power-

down Mode. In this mode, the external oscillator is stopped while the external interrupts

and the Watchdog (if enabled) continue operating. Only an external reset, a Watchdog

reset (if enabled), an external level interrupt on INT0 or INT1 can wake up the MCU.

Note that when a level-triggered interrupt is used for wake-up from power-down, the low

level must be held for a time longer than the reset delay Time-out period t_TOUT. Other-

wise, the device will not wake up.

Timer/Counters

The AT90S2313 provides two general-purpose Timer/Counters – one 8-bit T/C and one

16-bit T/C. The Timer/Counters have individual prescaling selection from the same 10-

bit prescaling timer. Both Timer/Counters can either be used as a timer with an internal

clock time base or as a counter with an external pin connection that triggers the

counting.

27

0839G–08/01

Timer/Counter Prescaler Figure 28 shows the general Timer/Counter prescaler.

Figure 28. Timer/Counter Prescaler

TCK1

TCK0

The four different prescaled selections are: CK/8, CK/64, CK/256 and CK/1024, where

CK is the oscillator clock. For the two Timer/Counters, added selections such as CK,

external clock source and stop can be selected as clock sources.

8-bit Timer/Counter0

Figure 29 shows the block diagram for Timer/Counter0.

The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK or an external

pin. In addition, it can be stopped as described in the specification for the

Timer/Counter0 Control Register (TCCR0). The overflow status flag is found in the

Timer/Counter Interrupt Flag Register (TIFR). Control signals are found in the

Timer/Counter0 Control Register (TCCR0). The interrupt enable/disable settings for

Timer/Counter0 are found in the Timer/Counter Interrupt Mask Register (TIMSK).

When Timer/Counter0 is externally clocked, the external signal is synchronized with the

oscillator frequency of the CPU. To assure proper sampling of the external clock, the

minimum time between two external clock transitions must be at least one internal CPU

clock period. The external clock signal is sampled on the rising edge of the internal CPU

clock.

The 8-bit Timer/Counter0 features both a high-resolution and a high-accuracy usage

with the lower prescaling opportunities. Similarly, the high prescaling opportunities make

the Timer/Counter0 useful for lower speed functions or exact timing functions with infre-

quent actions.

28

AT90S2313

0839G–08/01

AT90S2313

Figure 29. Timer/Counter0 Block Diagram

T0

Timer/Counter0 Control

Register – TCCR0

Bit

7

–

R

0

6

–

R

0

5

–

R

0

4

–

R

0

3

–

R

0

2

CS02

R/W

0

1

CS01

R/W

0

CS00

R/W

0

$33 ($53)

Read/Write

Initial value

TCCR0

• Bits 7..3 – Res: Reserved Bits

These bits are reserved bits in the AT90S2313 and always read zero.

• Bits 2,1,0 – CS02, CS01, CS00: Clock Select0, Bit 2,1 and 0

The Clock Select0 bits 2, 1 and 0 define the prescaling source of Timer/Counter0.

Table 7. Clock 0 Prescale Select

CS02

CS01

CS00

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Stop, the Timer/Counter0 is stopped.

CK

CK/8

CK/64

CK/256

CK/1024

External Pin T0, falling edge

External Pin T0, rising edge

29

0839G–08/01

The Stop condition provides a Timer Enable/Disable function. The CK down divided

modes are scaled directly from the CK oscillator clock. If the external pin modes are

used for Timer/Counter0, transitions on PD4/(T0) will clock the counter even if the pin is

configured as an output. This feature can give the user software control of the counting.

Timer/Counter0 – TCNT0

Bit

7

MSB

R/W

0

6

5

4

3

2

1

0

$32 ($52)

Read/Write

Initial value

LSB

R/W

0

TCNT0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Timer/Counter0 is realized as an up-counter with read and write access. If the

Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues

counting in the timer clock cycle following the write operation.

16-bit Timer/Counter1

Figure 30 shows the block diagram for Timer/Counter1.

Figure 30. Timer/Counter1 Block Diagram

The 16-bit Timer/Counter1 can select clock source from CK, prescaled CK or an external

pin. In addition, it can be stopped as described in the specification for the Timer/Counter1

Control Register (TCCR1B). The different status flags (Overflow, Compare Match and

Capture Event) and control signals are found in the Timer/Counter Interrupt Flag Register

(TIFR). The interrupt enable/disable settings for Timer/Counter1 are found in the Tim-

er/Counter Interrupt Mask Register (TIMSK).

30

AT90S2313

0839G–08/01

AT90S2313

When Timer/Counter1 is externally clocked, the external signal is synchronized with the

oscillator frequency of the CPU. To assure proper sampling of the external clock, the

minimum time between two external clock transitions must be at least one internal CPU

clock period. The external clock signal is sampled on the rising edge of the internal CPU

clock.

The 16-bit Timer/Counter1 features both a high-resolution and a high-accuracy usage

with the lower prescaling opportunities. Similarly, the high prescaling opportunities

makes the Timer/Counter1 useful for lower speed functions or exact timing functions

with infrequent actions.

The Timer/Counter1 supports an Output Compare function using the Output Compare

Register 1A (OCR1A) as the data source to be compared to the Timer/Counter1 con-

tents. The Output Compare functions include optional clearing of the counter on

compare matches, and actions on the Output Compare pin 1 on compare matches.

Timer/Counter1 can also be used as an 8-, 9- or 10-bit Pulse Width Modulator. In this

mode the counter and the OCR1 register serve as a glitch-free standalone PWM with

centered pulses. Refer to page 36 for a detailed description of this function.

The Input Capture function of Timer/Counter1 provides a capture of the Timer/Counter1

contents to the Input Capture Register (ICR1), triggered by an external event on the

Input Capture Pin (ICP). The actual capture event settings are defined by the

Timer/Counter1 Control Register (TCCR1B). In addition, the Analog Comparator can be

set to trigger the input capture. Refer to “Analog Comparator” on page 50 for details on

this. The ICP pin logic is shown in Figure 31.

Figure 31. ICP Pin Schematic Diagram

If the Noise Canceler function is enabled, the actual trigger condition for the capture

event is monitored over four samples, and all four must be equal to activate the capture

flag.

Timer/Counter1 Control

Register A – TCCR1A

Bit

7

COM1A1

R/W

6

COM1A0

R/W

5

–

4

–

3

–

2

–

1

PWM11

R/W

0

PWM10

R/W

0

TCCR1A

$2F ($4F)

Read/Write

Initial value

R

0

R

0

R

0

R

0

• Bits 7,6 – COM1A1, COM1A0: Compare Output Mode1, Bits 1 and 0

The COM1A1 and COM1A0 control bits determine any output pin action following a

compare match in Timer/Counter1. Any output pin actions affect pin OC1 (Output Com-

pare pin 1) (PB3). This is an alternative function to the I/O port, and the corresponding

31

0839G–08/01

direction control bit must be set (one) to control an output pin. The control configuration

is shown in Table 8.

Table 8. Compare 1 Mode Select

COM1A1

COM1A0

Description

0

1

0

1

0

1

Timer/Counter1 disconnected from output pin OC1

Toggle the OC1 output line.

Clear the OC1 output line (to zero).

Set the OC1 output line (to one).

Note:

In PWM mode, these bits have a different function. Refer to Table 12 for a detailed

description.

• Bits 5..2 – Res: Reserved Bits

These bits are reserved bits in the AT90S2313 and always read zero.

• Bits 1,0 – PWM11, PWM10: Pulse Width Modulator Select Bits

These bits select PWM operation of Timer/Counter1 as specified in Table 9. This mode

is described on page 35.

Table 9. PWM Mode Select

PWM11

PWM10

Description

0

1

0

1

0

1

PWM operation of Timer/Counter1 is disabled

Timer/Counter1 is an 8-bit PWM

Timer/Counter1 is a 9-bit PWM

Timer/Counter1 is a 10-bit PWM

Timer/Counter1 Control

Register B – TCCR1B

Bit

7

6

ICES1

R/W

0

5

–

R

0

4

–

R

0

3

CTC1

R/W

0

2

CS12

R/W

0

1

CS11

R/W

0

CS10

R/W

0

$2E ($4E)

Read/Write

Initial value

ICNC1

R/W

0

TCCR1B

• Bit 7 – ICNC1: Input Capture1 Noise Canceler (4 CKs)

When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is

disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP

(input capture pin) as specified. When the ICNC1 bit is set (one), four successive sam-

ples are measured on the ICP (input capture pin), and all samples must be high/low

according to the input capture trigger specification in the ICES1 bit. The actual sampling

frequency is the XTAL clock frequency.

• Bit 6 – ICES1: Input Capture1 Edge Select

While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the

Input Capture Register (ICR1) on the falling edge of the input capture pin (ICP). While

the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Cap-

ture Register (ICR1) on the rising edge of the input capture pin (ICP).

• Bits 5, 4 – Res: Reserved Bits

These bits are reserved bits in the AT90S2313 and always read zero.

32

AT90S2313

0839G–08/01

AT90S2313

• Bit 3 – CTC1: Clear Timer/Counter1 on Compare Match

When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock

cycle after a compareA match. If the CTC1 control bit is cleared, Timer/Counter1 contin-

ues counting and is unaffected by a compare match. Since the compare match is

detected in the CPU clock cycle following the match, this function will behave differently

when a prescaling higher than 1 is used for the timer. When a prescaling of 1 is used,

and the compareA register is set to C, the timer will count as follows if CTC1 is set:

... | C-2 | C-1 | C | 0 | 1 |...

When the prescaler is set to divide by 8, the timer will count like this:

... | C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, 0,

0, 0, 0, 0, 0, 0 |...

In PWM mode, this bit has no effect.

• Bits 2,1,0 – CS12, CS11, CS10: Clock Select1, Bits 2, 1 and 0

The Clock Select1 bits 2, 1 and 0 define the prescaling source of Timer/Counter1.

Table 10. Clock 1 Prescale Select

CS12

CS11

CS10

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Stop, the Timer/Counter1 is stopped.

CK

CK/8

CK/64

CK/256

CK/1024

External Pin T1, falling edge

External Pin T1, rising edge

The Stop condition provides a Timer Enable/Disable function. The CK down divided

modes are scaled directly from the CK oscillator clock. If the external pin modes are

used for Timer/Counter1, transitions on PD5/(T1) will clock the counter even if the pin is

configured as an output. This feature can give the user software control of the counting.

Timer/Counter1 – TCNT1H

and TCNT1L

Bit

$2D ($4D)

$2C ($4C)

15

MSB

14

13

12

11

10

9

8

TCNT1H

TCNT1L

LSB

0

R/W

0

7

R/W

0

6

R/W

0

5

R/W

0

4

R/W

0

3

R/W

0

2

R/W

0

1

R/W

0

Read/Write

Initial value

0

This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To

ensure that both the high and low bytes are read and written simultaneously when the

CPU accesses these registers, the access is performed using an 8-bit temporary regis-

ter (TEMP). This temporary register is also used when accessing OCR1A and ICR1. If

the main program and interrupt routines perform access to registers using TEMP, inter-

33

0839G–08/01

rupts must be disabled during access from the main program or interrupts if interrupts

are re-enabled.

•

TCNT1 Timer/Counter1 Write:

When the CPU writes to the high byte TCNT1H, the written data is placed in the

TEMP register. Next, when the CPU writes the low byte TCNT1L, this byte of data is

combined with the byte data in the TEMP register, and all 16 bits are written to the

TCNT1 Timer/Counter1 register simultaneously. Consequently, the high byte

TCNT1H must be accessed first for a full 16-bit register write operation.

•

TCNT1 Timer/Counter1 Read:

When the CPU reads the low byte TCNT1L, the data of the low byte TCNT1L is sent

to the CPU and the data of the high byte TCNT1H is placed in the TEMP register.

When the CPU reads the data in the high byte TCNT1H, the CPU receives the data

in the TEMP register. Consequently, the low byte TCNT1L must be accessed first

for a full 16-bit register read operation.

The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read

and write access. If Timer/Counter1 is written to and a clock source is selected, the

Timer/Counter1 continues counting in the timer clock cycle after it is preset with the writ-

ten value.

Timer/Counter1 Output

Compare Register A –

OCR1AH and OCR1AL

Bit

$2B ($4B)

$2A ($4A)

15

MSB

14

13

12

11

10

9

8

OCR1AH

OCR1AL

LSB

0

R/W

0

7

R/W

0

6

R/W

0

5

R/W

0

4

R/W

0

3

R/W

0

2

R/W

0

1

R/W

0

Read/Write

Initial value

0

The output compare register is a 16-bit read/write register.

The Timer/Counter1 Output Compare Register contains the data to be continuously

compared with Timer/Counter1. Actions on compare matches are specified in the

Timer/Counter1 Control and Status registers.

Since the Output Compare Register (OCR1A) is a 16-bit register, a temporary register

TEMP is used when OCR1A is written to ensure that both bytes are updated simulta-

neously. When the CPU writes the high byte, OCR1AH, the data is temporarily stored in

the TEMP register. When the CPU writes the low byte, OCR1AL, the TEMP register is

simultaneously written to OCR1AH. Consequently, the high byte OCR1AH must be writ-

ten first for a full 16-bit register write operation.

The TEMP register is also used when accessing TCNT1, and ICR1. If the main program

and interrupt routines perform access to registers using TEMP, interrupts must be dis-

abled during access from the main program or interrupts if interrupts are re-enabled.

34

AT90S2313

0839G–08/01

AT90S2313

Timer/Counter1 Input Capture

Register – ICR1H and ICR1L

Bit

$25 ($45)

$24 ($44)

15

MSB

14

13

12

11

10

9

8

ICR1H

ICR1L

LSB

0

R

0

7

R

0

6

R

0

5

R

0

4

R

0

3

R

0

2

R

0

1

R

0

Read/Write

Initial value

0

The input capture register is a 16-bit read-only register.

When the rising or falling edge (according to the input capture edge setting [ICES1]) of

the signal at the input capture pin (ICP) is detected, the current value of the

Timer/Counter1 is transferred to the Input Capture Register (ICR1). At the same time,

the input capture flag (ICF1) is set (one).

Since the Input Capture Register (ICR1) is a 16-bit register, a temporary register TEMP

is used when ICR1 is read to ensure that both bytes are read simultaneously. When the

CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte

ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte

ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte

ICR1L must be accessed first for a full 16-bit register read operation.

The TEMP register is also used when accessing TCNT1 and OCR1A. If the main pro-

gram and interrupt routines perform access to registers using TEMP, interrupts must be

disabled during access from the main program or interrupts if interrupts are re-enabled.

Timer/Counter1 in PWM Mode When the PWM mode is selected, Timer/Counter1 and the Output Compare Register1

(OCR1A) form an 8-, 9- or 10-bit, free-running, glitch-free and phase-correct PWM with

output on the PB3(OC1) pin. Timer/Counter1 acts as an up/down counter, counting up

from $0000 to TOP (see Table 11), where it turns and counts down again to zero before

the cycle is repeated. When the counter value matches the contents of the 8, 9 or 10

least significant bits of OCR1A, the PB3(OC1) pin is set or cleared according to the set-

tings of the COM1A1 and COM1A0 bits in the Timer/Counter1 Control Register

(TCCR1). Refer to Table 12 for details.

Table 11. Timer TOP Values and PWM Frequency

PWM Resolution

Timer TOP Value

$00FF (255)

Frequency

_TC1/510

8-bit

9-bit

f

$01FF (511)

f

_TC1/1022

_TC1/2046

10-bit

$03FF(1023)

35

0839G–08/01

Table 12. Compare1 Mode Select in PWM Mode

COM1A1 COM1A0 Effect on OC1

0

1

Not connected

Cleared on compare match, upcounting. Set on compare match,

down-counting (non-inverted PWM).

1

0

1

Cleared on compare match, downcounting. Set on compare match,

up-counting (inverted PWM).

Note that in the PWM mode, the 10 least significant OCR1A bits, when written, are

transferred to a temporary location. They are latched when Timer/Counter1 reaches

TOP. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of

an unsynchronized OCR1A write. See Figure 32 for an example.

Figure 32. Effects on Unsynchronized OCR1 Latching

Compare Value changes

During the time between the write and the latch operations, a read from OCR1A will

read the contents of the temporary location. This means that the most recently written

value always will read out of OCR1A.

When the OCR1 contains $0000 or TOP, the output OC1 is updated to low or high on

the next compare match according to the settings of COM1A1/COM1A0. This is shown

in Table 13.

Note:

If the compare register contains the TOP value and the prescaler is not in use

(CS12..CS10 = 001), the PWM output will not produce any pulse at all, because the up-

counting and down-counting values are reached simultaneously. When the prescaler is

in use (CS12..CS10 ≠ 001 or 000), the PWM output goes active when the counter

reaches the TOP value, but the down-counting compare match is not interpreted to be

reached before the next time the counter reaches the TOP value, making a one-period

PWM pulse.

36

AT90S2313

0839G–08/01

AT90S2313

Table 13. PWM Outputs OCR = $0000 or TOP

COM1A1

COM1A0

OCR1A

$0000

TOP

Output OC1

1

0

1

L

H

L

$0000

TOP

In PWM mode, the Timer Overflow Flag1 (TOV1) is set when the counter advances from

$0000. Timer Overflow Interrupt1 operates exactly as in normal Timer/Counter mode

(i.e., it is executed when TOV1 is set, provided that Timer Overflow Interrupt1 and global

interrupts are enabled). This also applies to the Timer Output Compare1 flag and

interrupt.

37

0839G–08/01

Watchdog Timer

The Watchdog Timer is clocked from a separate on-chip oscillator that runs at 1 MHz.

This is the typical value at V_CC= 5V. See characterization data for typical values at other

V_CClevels. By controlling the Watchdog Timer prescaler, the Watchdog reset interval

can be adjusted. See Table 14 for a detailed description. The WDR (Watchdog Reset)

instruction resets the Watchdog Timer. Eight different clock cycle periods can be

selected to determine the reset period. If the reset period expires without another

Watchdog reset, the AT90S2313 resets and executes from the reset vector. For timing

details on the Watchdog reset, refer to page 22.

To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be

followed when the Watchdog is disabled. Refer to the description of the Watchdog Timer

Control Register for details.

Figure 33. Watchdog Timer

Watchdog Timer Control

Register – WDTCR

Bit

7

–

R

0

6

–

R

0

5

–

R

0

4

WDTOE

R/W

0

3

WDE

R/W

0

2

WDP2

R/W

0

1

WDP1

R/W

0

WDP0

R/W

0

$21 ($41)

Read/Write

Initial value

WDTCR

• Bits 7..5 – Res: Reserved Bits

These bits are reserved bits in the AT90S2313 and will always read as zero.

• Bit 4 – WDTOE: Watchdog Turn-off Enable

This bit must be set (one) when the WDE bit is cleared. Otherwise, the Watchdog will

not be disabled. Once set, hardware will clear this bit to zero after four clock cycles.

Refer to the description of the WDE bit for a Watchdog disable procedure.

• Bit 3 – WDE: Watchdog Enable

When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared

(zero), the Watchdog Timer function is disabled. WDE can only be cleared if the

WDTOE bit is set (one). To disable an enabled Watchdog Timer, the following proce-

dure must be followed:

1. In the same operation, write a logical “1” to WDTOE and WDE. A logical “1” must

be written to WDE even though it is set to 1 before the disable operation starts.

2. Within the next four clock cycles, write a logical “0” to WDE. This disables the

Watchdog.

38

AT90S2313

0839G–08/01

AT90S2313

• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1 and 0

The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the

Watchdog Timer is enabled. The different prescaling values and their corresponding

time-out periods are shown in Table 14.

Table 14. Watchdog Timer Prescale Select

Number of

WDT Oscillator

Typical Time-out

at V_CC= 3.0V

Typical Time-out

at V_CC= 5.0V

WDP2

WDP1

WDP0 Cycles

0

1

0

1

0

1

0

1

0

1

0

1

0

1

16K cycles

47 ms

94 ms

0.19 s

0.38 s

0.75 s

1.5 s

15 ms

30 ms

60 ms

0.12 s

0,24 s

0.49 s

0.97 s

1.9 s

32K cycles

64K cycles

128K cycles

256K cycles

512K cycles

1,024K cycles

2,048K cycles

3.0 s

6.0 s

Note:

The frequency of the Watchdog Oscillator is voltage-dependent, as shown in the Electri-

cal Characteristics section.

The WDR (Watchdog Reset) instruction should always be executed before the Watch-

dog Timer is enabled. This ensures that the reset period will be in accordance with the

Watchdog Timer prescale settings. If the Watchdog Timer is enabled without reset, the

Watchdog Timer may not start counting from zero.

To avoid unintentional MCU reset, the Watchdog Timer should be disabled or reset

before changing the Watchdog Timer Prescale Select.

39

0839G–08/01

EEPROM Read/Write The EEPROM access registers are accessible in the I/O space.

Access

The write access time is in the range of 2.5 - 4 ms, depending on the V_CCvoltages. A

self-timing function, however, lets the user software detect when the next byte can be

written. If the user code contains code that writes the EEPROM, some precaution must

be taken. In heavily filtered power supplies, V_CCis likely to rise or fall slowly on power-

up/down. This causes the device for some period of time to run at a voltage lower than

specified as minimum for the clock frequency used. CPU operation under these condi-

tions may cause the Program Counter to perform unintentional jumps and eventually

execute the EEPROM write code. To secure EEPROM integrity, the user is advised to

use an external under-voltage reset circuit in this case.

In order to prevent unintentional EEPROM writes, a specific write procedure must be fol-

lowed. Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is written, the CPU is halted for two clock cycles before the next

instruction is executed. When the EEPROM is read, the CPU is halted for four clock

cycles before the next instruction is executed.

EEPROM Address Register –

EEAR

Bit

7

–

R

0

6

EEAR6

R/W

0

5

EEAR5

R/W

0

4

EEAR4

R/W

0

3

EEAR3

R/W

0

2

EEAR2

R/W

0

1

EEAR1

R/W

0

EEAR0

R/W

0

$1E ($3E)

Read/Write

Initial value

EEAR

• Bit 7 – Res: Reserved Bit

This bit is a reserved bit in the AT90S2313 and will always read as zero.

• Bit 6..0 – EEAR6..0: EEPROM Address

The EEPROM Address Register (EEAR6..0) specifies the EEPROM address in the 128

bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and

127.

EEPROM Data Register –

EEDR

Bit

7

MSB

R/W

0

6

5

4

3

2

1

0

$1D ($3D)

Read/Write

Initial value

LSB

R/W

0

EEDR

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 7..0 – EEDR7..0: EEPROM Data

For the EEPROM write operation, the EEDR register contains the data to be written to

the EEPROM in the address given by the EEAR register. For the EEPROM read opera-

tion, the EEDR contains the data read out from the EEPROM at the address given by

EEAR.

EEPROM Control Register –

EECR

Bit

7

–

R

0

6

–

R

0

5

–

R

0

4

–

R

0

3

–

R

0

2

EEMWE

R/W

0

1

EEWE

R/W

0

EERE

R/W

0

$1C ($3C)

Read/Write

Initial value

EECR

• Bit 7..3 – Res: Reserved Bits

These bits are reserved bits in the AT90S2313 and will always read as zero.

40

AT90S2313

0839G–08/01

AT90S2313

• Bit 2 – EEMWE: EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be

written. When EEMWE is set (one), setting EEWE will write data to the EEPROM at the

selected address. If EEMWE is zero, setting EEWE will have no effect. When EEMWE

has been set (one) by software, hardware clears the bit to zero after four clock cycles.

See the description of the EEWE bit for a EEPROM write procedure.

• Bit 1 – EEWE: EEPROM Write Enable

The EEPROM Write Enable Signal (EEWE) is the write strobe to the EEPROM. When

address and data are correctly set up, the EEWE bit must be set to write the value into

the EEPROM. The EEMWE bit must be set when the logical “1” is written to EEWE, oth-

erwise no EEPROM write takes place. The following procedure should be followed

when writing the EEPROM (the order of steps 2 and 3 is unessential):

1. Wait until EEWE becomes zero.

2. Write new EEPROM address to EEAR (optional).

3. Write new EEPROM data to EEDR (optional).

4. Write a logical “1” to the EEMWE bit in EECR (to be able to write a logical “1” to

the EEMWE bit, the EEWE bit must be written to zero in the same cycle).

5. Within four clock cycles after setting EEMWE, write a logical “1” to EEWE.

When the write access time (typically 2.5 ms at V_CC= 5V or 4 ms at V_CC= 2.7V) has

elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit

and wait for a zero before writing the next byte. When EEWE has been set, the CPU is

halted for two cycles before the next instruction is executed.

Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the

EEPROM Master Write Enable will time-out. If an interrupt routine accessing the

EEPROM is interrupting another EEPROM access, the EEAR or EEDR register will be

modified, causing the interrupted EEPROM access to fail. It is recommended to have

the global interrupt flag cleared during the last four steps to avoid these problems.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal (EERE) is the read strobe to the EEPROM. When

the correct address is set up in the EEAR register, the EERE bit must be set. When the

EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register.

The EEPROM read access takes one instruction and there is no need to poll the EERE

bit. When EERE has been set, the CPU is halted for four cycles before the next instruc-

tion is executed.

The user should poll the EEWE bit before starting the read operation. If a write operation

is in progress when new data or address is written to the EEPROM I/O registers, the

write operation will be interrupted and the result is undefined.

Prevent EEPROM

Corruption

During periods of low V_CC, the EEPROM data can be corrupted because the supply volt-

age is too low for the CPU and the EEPROM to operate properly. These issues are the

same as for board-level systems using the EEPROM, and the same design solutions

should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too

low. First, a regular write sequence to the EEPROM requires a minimum voltage to

operate correctly. Secondly, the CPU itself can execute instructions incorrectly if the

supply voltage for executing instructions is too low.

EEPROM data corruption can easily be avoided by following these design recommen-

dations (one is sufficient):

41

0839G–08/01

1. Keep the AVR RESET active (low) during periods of insufficient power supply

voltage. This is best done by an external low V_CCReset Protection circuit, often

referred to as a Brown-out Detector (BOD). Please refer to the AVR 180 applica-

tion note for design considerations regarding power-on reset and low-voltage

detection.

2. Keep the AVR core in Power-down Sleep Mode during periods of low V_CC. This

will prevent the CPU from attempting to decode and execute instructions, effec-

tively protecting the EEPROM registers from unintentional writes.

3. Store constants in Flash memory if the ability to change memory contents from

software is not required. Flash memory cannot be updated by the CPU and will

not be subject to corruption.

42

AT90S2313

0839G–08/01

AT90S2313

UART

The AT90S2313 features a full duplex (separate receive and transmit registers) Univer-

sal Asynchronous Receiver and Transmitter (UART). The main features are:

• Baud Rate Generator that can Generate a Large Number of Baud Rates (bps)

• High Baud Rates at Low XTAL Frequencies

• 8 or 9 Bits Data

• Noise Filtering

• Overrun Detection

• Framing Error Detection

• False Start Bit Detection

• Three separate Interrupts on TX Complete, TX Data Register Empty and RX Complete

Data Transmission

A block schematic of the UART transmitter is shown in Figure 34.

Data transmission is initiated by writing the data to be transmitted to the UART I/O Data

Register (UDR). Data is transferred from UDR to the Transmit shift register when:

•

A new character has been written to UDR after the stop bit from the previous

character has been shifted out. The shift register is loaded immediately.

•

A new character has been written to UDR before the stop bit from the previous

character has been shifted out. The shift register is loaded when the stop bit of the

character currently being transmitted has been shifted out.

Figure 34. UART Transmitter

If the 10(11)-bit Transmitter shift register is empty, data is transferred from UDR to the

shift register. At this time the UDRE (UART Data Register Empty) bit in the UART Status

43

0839G–08/01

Register (USR) is set. When this bit is set (one), the UART is ready to receive the next

character. At the same time as the data is transferred from UDR to the 10(11)-bit shift

register, bit 0 of the shift register is cleared (start bit) and bit 9 or 10 is set (stop bit). If 9-

bit data word is selected (the CHR9 bit in the UART Control Register [UCR] is set), the

TXB8 bit in UCR is transferred to bit 9 in the Transmit shift register.

On the Baud Rate clock following the transfer operation to the shift register, the start bit

is shifted out on the TXD pin. Then follows the data, LSB first. When the stop bit has

been shifted out, the shift register is loaded if any new data has been written to the UDR

during the transmission. During loading, UDRE is set. If there is no new data in the UDR

register to send when the stop bit is shifted out, the UDRE flag will remain set until UDR

is written again. When no new data has been written, and the stop bit has been present

on TXD for one bit length, the TX Complete Flag (TXC) in USR is set.

The TXEN bit in UCR enables the UART transmitter when set (one). When this bit is

cleared (zero), the PD1 pin can be used for general I/O. When TXEN is set, the UART

Transmitter will be connected to PD1, which is forced to be an output pin regardless of

the setting of the DDD1 bit in DDRD.

Data Reception

Figure 35 shows a block diagram of the UART Receiver.

Figure 35. UART Receiver

44

AT90S2313

0839G–08/01

AT90S2313

The receiver front-end logic samples the signal on the RXD pin at a frequency of 16

times the baud rate. While the line is idle, one single sample of logical “0” will be inter-

preted as the falling edge of a start bit, and the start bit detection sequence is initiated.

Let sample 1 denote the first zero-sample. Following the 1-to-0 transition, the receiver

samples the RXD pin at samples 8, 9 and 10. If two or more of these three samples are

found to be logical “1”s, the start bit is rejected as a noise spike and the receiver starts

looking for the next 1-to-0 transition.

If, however, a valid start bit is detected, sampling of the data bits following the start bit is

performed. These bits are also sampled at samples 8, 9 and 10. The logical value found

in at least two of the three samples is taken as the bit value. All bits are shifted into the

transmitter shift register as they are sampled. Sampling of an incoming character is

shown in Figure 36.

Figure 36. Sampling Received Data

When the stop bit enters the receiver, the majority of the three samples must be “1” to

accept the stop bit. If two or more samples are logical “0”s, the Framing Error (FE) flag in

the UART Status Register (USR) is set. Before reading the UDR register, the user

should always check the FE bit to detect Framing Errors.

Whether or not a valid stop bit is detected at the end of a character-reception cycle, the

data is transferred to UDR and the RXC flag in USR is set. UDR is in fact two physically

separate registers; one for transmitted data and one for received data. When UDR is

read, the Receive Data register is accessed, and when UDR is written, the Transmit

Data register is accessed. If 9-bit data word is selected (the CHR9 bit in the UART Con-

trol Register [UCR] is set), the RXB8 bit in UCR is loaded with bit 9 in the Transmit shift

register when data is transferred to UDR.

If, after having received a character, the UDR register has not been read since the last

receive, the OverRun (OR) flag in UCR is set. This means that the last data byte shifted

into the shift register could not be transferred to UDR and has been lost. The OR bit is

buffered and is updated when the valid data byte in UDR is read. Thus, the user should

always check the OR bit after reading the UDR register in order to detect any overruns if

the baud rate is high or CPU load is high.

When the RXEN bit in the UCR register is cleared (zero), the receiver is disabled. This

means that the PD0 pin can be used as a general I/O pin. When RXEN is set, the UART

Receiver will be connected to PD0, which is forced to be an input pin regardless of the

setting of the DDD0 bit in DDRD. When PD0 is forced to input by the UART, the

PORTD0 bit can still be used to control the pull-up resistor on the pin.

When the CHR9 bit in the UCR register is set, transmitted and received characters are

nine bits long plus start and stop bits. The ninth data bit to be transmitted is the TXB8 bit

in UCR register. This bit must be set to the wanted value before a transmission is initi-

ated by writing to the UDR register. The ninth data bit received is the RXB8 bit in the

UCR register.

45

0839G–08/01

UART Control

The UART I/O Data Register –

UDR

Bit

7

MSB

R/W

0

6

5

4

3

2

1

0

$0C ($2C)

Read/Write

Initial value

LSB

R/W

0

UDR

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The UDR register is actually two physically separate registers sharing the same I/O

address. When writing to the register, the UART Transmit Data register is written. When

reading from UDR, the UART Receive Data register is read.

UART Status Register – USR

Bit

7

RXC

R

6

5

UDRE

R

4

FE

R

3

OR

R

2

–

R

0

1

–

R

0

–

R

0

$0B ($2B)

Read/Write

Initial value

TXC

R/W

0

USR

0

1

0

The USR register is a read-only register providing information on the UART status.

• Bit 7 – RXC: UART Receive Complete

This bit is set (one) when a received character is transferred from the Receiver Shift reg-

ister to UDR. The bit is set regardless of any detected framing errors. When the RXCIE

bit in UCR is set, the UART Receive Complete interrupt will be executed when RXC is

set (one). RXC is cleared by reading UDR. When interrupt-driven data reception is used,

the UART Receive Complete Interrupt routine must read UDR in order to clear RXC,

otherwise a new interrupt will occur once the interrupt routine terminates.

• Bit 6 – TXC: UART Transmit Complete

This bit is set (one) when the entire character (including the stop bit) in the Transmit

Shift register has been shifted out and no new data has been written to UDR. This flag is

especially useful in half-duplex communications interfaces, where a transmitting appli-

cation must enter receive mode and free the communications bus immediately after

completing the transmission.

When the TXCIE bit in UCR is set, setting of TXC causes the UART Transmit Complete

interrupt to be executed. TXC is cleared by hardware when executing the corresponding

interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical

“1” to the bit.

• Bit 5 – UDRE: UART Data Register Empty

This bit is set (one) when a character written to UDR is transferred to the Transmit shift

register. Setting of this bit indicates that the transmitter is ready to receive a new charac-

ter for transmission.

When the UDRIE bit in UCR is set, the UART Transmit Complete interrupt is executed

as long as UDRE is set. UDRE is cleared by writing UDR. When interrupt-driven data

transmittal is used, the UART Data Register Empty Interrupt routine must write UDR in

order to clear UDRE, otherwise a new interrupt will occur once the interrupt routine

terminates.

UDRE is set (one) during reset to indicate that the transmitter is ready.

• Bit 4 – FE: Framing Error

This bit is set if a Framing Error condition is detected (i.e., when the stop bit of an incom-

ing character is zero).

46

AT90S2313

0839G–08/01

AT90S2313

The FE bit is cleared when the stop bit of received data is one.

• Bit 3 – OR: Overrun

This bit is set if an Overrun condition is detected (i.e., when a character already present

in the UDR register is not read before the next character has been shifted into the

Receiver Shift register). The OR bit is buffered, which means that it will be set once the

valid data still in UDRE is read.

The OR bit is cleared (zero) when data is received and transferred to UDR.

• Bits 2..0 – Res: Reserved Bits

These bits are reserved bits in the AT90S2313 and will always read as zero.

UART Control Register – UCR

Bit

7

RXCIE

R/W

0

6

TXCIE

R/W

0

5

UDRIE

R/W

0

4

RXEN

R/W

0

3

TXEN

R/W

0

2

CHR9

R/W

0

1

RXB8

R

0

TXB8

W

$0A ($2A)

Read/Write

Initial value

UCR

1

0

• Bit 7 – RXCIE: RX Complete Interrupt Enable

When this bit is set (one), a setting of the RXC bit in USR will cause the Receive Com-

plete Interrupt routine to be executed provided that global interrupts are enabled.

• Bit 6 – TXCIE: TX Complete Interrupt Enable

When this bit is set (one), a setting of the TXC bit in USR will cause the Transmit Com-

plete Interrupt routine to be executed provided that global interrupts are enabled.

• Bit 5 – UDRIE: UART Data Register Empty Interrupt Enable

When this bit is set (one), a setting of the UDRE bit in USR will cause the UART Data

Register Empty Interrupt routine to be executed provided that global interrupts are

enabled.

• Bit 4 – RXEN: Receiver Enable

This bit enables the UART receiver when set (one). When the receiver is disabled, the

RXC, OR and FE status flags cannot become set. If these flags are set, turning off

RXEN does not cause them to be cleared.

• Bit 3 – TXEN: Transmitter Enable

This bit enables the UART transmitter when set (one). When disabling the transmitter

while transmitting a character, the transmitter is not disabled before the character in the

shift register plus any following character in UDR has been completely transmitted.

• Bit 2 – CHR9: 9 Bit Characters

When this bit is set (one), transmitted and received characters are nine bits long plus

start and stop bits. The ninth bit is read and written by using the RXB8 and TXB8 bits in

UCR, respectively. The ninth data bit can be used as an extra stop bit or a parity bit.

• Bit 1 – RXB8: Receive Data Bit 8

When CHR9 is set (one), RXB8 is the ninth data bit of the received character.

• Bit 0 – TXB8: Transmit Data Bit 8

When CHR9 is set (one), TXB8 is the ninth data bit in the character to be transmitted.

47

0839G–08/01

Baud Rate Generator

The baud rate generator is a frequency divider that generates baud rates according to

the following equation:

f_CK

BAUD = ------------------------------------

16(UBRR + 1)

•

BAUD = Baud Rate

_CK= Crystal Clock frequency

UBRR = Contents of the UART Baud Rate register (UBRR) (0 - 255)

f

For standard crystal frequencies, the most commonly used baud rates can be generated

by using the UBRR settings in Table 15. UBRR values that yield an actual baud rate dif-

fering less than 2% from the target baud rate, are boldfaced in the table. However, using

baud rates that have more than 1% error is not recommended. High error ratings give

less noise resistance.

48

AT90S2313

0839G–08/01

AT90S2313

Table 15. UBRR Settings at Various Crystal Frequencies

Baud Rate

%Error

0.0

%Error

0.2

%Error

0.0

1 MHz

1.8432 MHz

2 MHz

2.4576 MHz

UBRR=

2400

25

12

6

0.2

47

23

11

7

51

25

12

8

63

31

15

10

7

UBRR=

4800

9600

0.2

0.0

0.2

0.0

7.5 UBRR=

7.8 UBRR=

22.9 UBRR=

7.8 UBRR=

22.9 UBRR=

84.3 UBRR=

0.0

0.2

0.0

3

3.7 UBRR=

7.5 UBRR=

7.8 UBRR=

22.9 UBRR=

7.8 UBRR=

3.1

14400

19200

28800

38400

57600

76800

115200

0.0

2

6

5

0.0

1

3

4

6.3

3

0.0

1

2

0.0

3

0.0

0

1

2

12.5

0.0

1

0.0

0

1

33.3 UBRR=

1

0

UBRR=

0

25.0

0

0.0

Baud Rate

2400

%Error

0.0

%Error

0.0

3.2768 MHz

3.6864 MHz

4 MHz

4.608 MHz

UBRR=

84

42

20

13

10

6

0.4

0.8

1.6

95

47

23

15

11

7

103

51

25

16

12

8

0.2

119

59

29

19

14

9

4800

0.0

9600

0.0

2.1 UBRR=

14400

19200

28800

38400

57600

76800

115200

0.0

3.1 UBRR=

UBRR=

0.0

0.2

0.0

3.7 UBRR=

7.5 UBRR=

7.8 UBRR=

1.6

0.0

4

6.3 UBRR=

12.5 UBRR=

6

7

6.7

5

0.0

3

2

0.0

4

0.0

2

3

6.7

0.0

1

2

20.0

1

0.0

Baud Rate

2400

%Error

0.2

%Error

0.0

%Error

-

7.3728 MHz

8 MHz

9.216 MHz

11.059 MHz

UBRR=

UBRR= 287

191

95

47

31

23

15

11

7

0.0

207

103

51

34

25

16

12

8

239

119

59

39

29

19

14

9

UBRR=

4800

0.2

0.0

143

71

47

35

23

17

11

8

0.0

9600

0.2

0.0

14400

19200

28800

38400

57600

76800

115200

0.8

0.0

0.2

0.0

2.1 UBRR=

0.0

UBRR=

0.2

0.0

3.7 UBRR=

7.5 UBRR=

7.8 UBRR=

0.0

6

7

6.7 UBRR=

5

3

UBRR=

3

4

0.0

5

UART Baud Rate Register –

UBRR

Bit

$09 ($29)

Read/Write

Initial value

7

6

5

4

3

2

1

0

MSB

R/W

0

LSB

R/W

0

UBRR

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The UBRR register is an 8-bit read/write register that specifies the UART Baud Rate

according to the formula on the previous page.

49

0839G–08/01

Analog Comparator

The Analog Comparator compares the input values on the positive input AIN0 (PB0) and

the negative input PB1(AIN1). When the voltage on the positive input PB0 (AIN0) is

higher than the voltage on the negative input PB1 (AIN1), the Analog Comparator Out-

put, ACO is set (one). The comparator’s output can be set to trigger the Timer/Counter1

Input Capture function. In addition, the comparator can trigger a separate interrupt

exclusive to the Analog Comparator. The user can select interrupt triggering on compar-

ator output rise, fall or toggle. A block diagram of the comparator and its surrounding

logic is shown in Figure 37.

Figure 37. Analog Comparator Block Diagram

Analog Comparator Control

and Status Register – ACSR

Bit

7

6

–

R

0

5

ACO

R

4

ACI

R/W

0

3

ACIE

R/W

0

2

ACIC

R/W

0

1

ACIS1

R/W

0

ACIS0

R/W

0

$08 ($28)

Read/Write

Initial value

ACD

R/W

0

ACSR

N/A

• Bit 7 – ACD: Analog Comparator Disable

When this bit is set (one), the power to the Analog Comparator is switched off. This bit

can be set at any time to turn off the Analog Comparator. This will reduce power con-

sumption in active and idle modes. When changing the ACD bit, the Analog Comparator

Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can

occur when the bit is changed.

• Bit 6 – Res: Reserved Bit

This bit is a reserved bit in the AT90S2313 and will always read as zero.

• Bit 5 – ACO: Analog Comparator Output

ACO is directly connected to the comparator output.

• Bit 4 – ACI: Analog Comparator Interrupt Flag

This bit is set (one) when a comparator output event triggers the interrupt mode defined

by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE

bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when exe-

cuting the corresponding interrupt handling vector. Alternatively, ACI is cleared by

writing a logical “1” to the flag. Observe, however, that if another bit in this register is

modified using the SBI or CBI instruction, ACI will be cleared if it has become set before

the operation.

50

AT90S2313

0839G–08/01

AT90S2313

• Bit 3 – ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the Ana-

log Comparator interrupt is activated. When cleared (zero), the interrupt is disabled.

• Bit 2 – ACIC: Analog Comparator Input Capture Enable

When set (one), this bit enables the Input Capture function in Timer/Counter1 to be trig-

gered by the Analog Comparator. The comparator output is, in this case, directly

connected to the Input Capture front-end logic, making the comparator utilize the noise

canceler and edge-select features of the Timer/Counter1 Input Capture interrupt. When

cleared (zero), no connection between the Analog Comparator and the Input Capture

function is given. To make the comparator trigger the Timer/Counter1 Input Capture

interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set (one).

• Bits 1,0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits determine which comparator events trigger the Analog Comparator interrupt.

The different settings are shown in Table 16.

Table 16. ACIS1/ACIS0 Settings

ACIS1

ACIS0

Interrupt Mode

0

1

0

1

0

1

Comparator Interrupt on Output Toggle

Reserved

Comparator Interrupt on Falling Output Edge

Comparator Interrupt on Rising Output Edge

Note:

When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be dis-

abled by clearing its Interrupt Enable bit in the ACSR register. Otherwise an interrupt can

occur when the bits are changed.

51

0839G–08/01

I/O Ports

All AVR ports have true read-modify-write functionality when used as general digital I/O

ports. This means that the direction of one port pin can be changed without unintention-

ally changing the direction of any other pin with the SBI and CBI instructions. The same

applies for changing drive value (if configured as output) or enabling/disabling of pull-up

resistors (if configured as input).

Port B

Port B is an 8-bit bi-directional I/O port.

Three I/O memory address locations are allocated for the Port B, one each for the Data

Register – PORTB, $18 ($38), Data Direction Register – DDRB, $17($37) and the Port

B Input Pins – PINB, $16($36). The Port B Input Pins address is read-only, while the

Data Register and the Data Direction Register are read/write.

All port pins have individually selectable pull-up resistors. The Port B output buffers can

sink 20 mA and thus drive LED displays directly. When pins PB0 to PB7 are used as

inputs and are externally pulled low, they will source current if the internal pull-up resis-

tors are activated.

The Port B pins with alternate functions are shown in Table 17.

Table 17. Port B Pin Alternate Functions

Port Pin

PB0

Alternate Functions

AIN0 (Analog comparator positive input)

AIN1 (Analog comparator negative input)

OC1 (Timer/Counter1 Output compare match output)

MOSI (Data input line for memory downloading)

MISO (Data output line for memory uploading)

SCK (Serial clock input)

PB1

PB3

PB5

PB6

PB7

When the pins are used for the alternate function, the DDRB and PORTB registers have

to be set according to the alternate function description.

Port B Data Register – PORTB

Bit

7

PORTB7

R/W

0

6

PORTB6

R/W

0

5

PORTB5

R/W

0

4

PORTB4

R/W

0

3

PORTB3

R/W

0

2

PORTB2

R/W

0

1

PORTB1

R/W

0

PORTB0

R/W

0

PORTB

DDRB

PINB

$18 ($38)

Read/Write

Initial value

Port B Data Direction Register

– DDRB

Bit

7

DDB7

R/W

0

6

DDB6

R/W

0

5

DDB5

R/W

0

4

DDB4

R/W

0

3

DDB3

R/W

0

2

DDB2

R/W

0

1

DDB1

R/W

0

DDB0

R/W

0

$17 ($37)

Read/Write

Initial value

Port B Input Pins Address –

PINB

Bit

7

PINB7

R

6

PINB6

R

5

PINB5

R

4

PINB4

R

3

PINB3

R

2

PINB2

R

1

PINB1

R

0

PINB0

R

$16 ($36)

Read/Write

Initial value

N/A

52

AT90S2313

0839G–08/01

AT90S2313

The Port B Input Pins address (PINB) is not a register; this address enables access to

the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is

read, and when reading PINB, the logical values present on the pins are read.

Port B as General Digital I/O

All eight pins in Port B have equal functionality when used as digital I/O pins.

PBn, general I/O pin: The DDBn bit in the DDRB register selects the direction of this pin.

If DDBn is set (one), PBn is configured as an output pin. If DDBn is cleared (zero), PBn

is configured as an input pin. If PORTBn is set (one) when the pin is configured as an

input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off, the

PORTBn has to be cleared (zero) or the pin has to be configured as an output pin The

Port B pins are tri-stated when a reset condition becomes active, even if the clock is not

active.

Table 18. DDBn Effects on Port B Pins

DDBn

PORTBn

I/O

Pull-up

No

Comment

0

1

0

1

0

1

Input

Tri-state (High-Z)

Input

Yes

No

PBn will source current if ext. pulled low

Push-pull Zero Output

Push-pull One Output

Output

No

Note:

n: 7,6…0, pin number.

Alternate Functions of Port B The alternate pin functions of Port B are:

• SCK – Port B, Bit 7

SCK, Clock input pin for memory up/downloading.

• MISO – Port B, Bit 6

MISO, Data output pin for memory uploading.

• MOSI – Port B, Bit 5

MOSI, Data input pin for memory downloading.

• OC1 – Port B, Bit 3

OC1, Output Compare Match Output. The PB3 pin can serve as an external output for

timer 1 compare match. The PB3 pin has to be configured as an output (DDB3 is set

[one]) to serve this function. See the timer description for further details, and how to

enable the output.

• AIN1 – Port B, Bit 1

AIN1, Analog Comparator Negative Input. When configured as an input (DDB1 is

cleared [zero]) and with the internal MOS pull-up resistor switched off (PB1 is cleared

[zero]), this pin also serves as the negative input of the on-chip Analog Comparator.

• AIN0 – Port B, Bit 0

AIN0, Analog Comparator Positive Input. When configured as an input (DDB0 is cleared

[zero]) and with the internal MOS pull-up resistor switched off (PB0 is cleared [zero]),

this pin also serves as the positive input of the on-chip Analog Comparator.

53

0839G–08/01

Port B Schematics

Note that all port pins are synchronized. The synchronization latches are, however, not

shown in the figures.

Figure 38. Port B Schematic Diagram (Pins PB0 and PB1)

54

AT90S2313

0839G–08/01

AT90S2313

Figure 39. Port B Schematic Diagram (Pin PB3)

RD

MOS

PULL-

UP

RESET

R

Q

D

DDB3

C

WD

RESET

R

Q

D

PB3

PORTB3

C

RL

RP

WP

COM1A0

COM1A1

WP:

WD:

RL:

RP:

RD:

WRITE PORTB

WRITE DDRB

READ PORTB LATCH

READ PORTB PIN

READ DDRB

OUTPUT

MODE SELECT

COMP. MATCH1

Figure 40. Port B Schematic Diagram (Pins PB2 and PB4)

55

0839G–08/01

Figure 41. Port B Schematic Diagram (Pin PB5)

Figure 42. Port B Schematic Diagram (Pin PB6)

56

AT90S2313

0839G–08/01

AT90S2313

Figure 43. Port B Schematic Diagram (Pin PB7)

Port D

Three I/O memory address locations are allocated for the Port D: one each for the Data

Register – PORTD, $12($32), Data Direction Register – DDRD, $11($31) and the Port D

Input Pins – PIND, $10($30). The Port D Input Pins address is read-only, while the Data

Register and the Data Direction Register are read/write.

Port D has seven bi-directional I/O pins with internal pull-up resistors, PD6..PD0. The

Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled

low will source current if the pull-up resistors are activated.

Some Port D pins have alternate functions as shown in Table 19:

Table 19. Port D Pin Alternate Functions

Port Pin

PD0

Alternate Function

RXD (Receive data input for the UART)

TXD (Transmit data output for the UART)

INT0 (External interrupt 0 input)

INT1 (External interrupt 1 input)

TO (Timer/Counter0 external input)

T1 (Timer/Counter1 external input)

ICP (Timer/Counter1Input Capture pin)

PD1

PD2

PD3

PD4

PD5

PD6

When the pins are used for the alternate function, the DDRD and PORTD registers have

to be set according to the alternate function description.

57

0839G–08/01

Port D Data Register – PORTD

Bit

7

–

6

PORTD6

R/W

0

5

PORTD5

R/W

0

4

PORTD4

R/W

0

3

PORTD3

R/W

0

2

PORTD2

R/W

0

1

PORTD1

R/W

0

PORTD0

R/W

0

PORTD

DDRD

PIND

$12 ($32)

Read/Write

Initial value

R

0

Port D Data Direction Register

– DDRD

Bit

7

–

R

0

6

DDD6

R/W

0

5

DDD5

R/W

0

4

DDD4

R/W

0

3

DDD3

R/W

0

2

DDD2

R/W

0

1

DDD1

R/W

0

DDD0

R/W

0

$11 ($31)

Read/Write

Initial value

Port D Input Pins Address –

PIND

Bit

7

–

R

0

6

PIND6

R

5

PIND5

R

4

PIND4

R

3

PIND3

R

2

PIND2

R

1

PIND1

R

0

PIND0

R

$10 ($30)

Read/Write

Initial value

N/A

The Port D Input Pins address (PIND) is not a register; this address enables access to

the physical value on each Port D pin. When reading PORTD, the Port D Data Latch is

read, and when reading PIND, the logical values present on the pins are read.

Port D as General Digital I/O

PDn, general I/O pin: The DDDn bit in the DDRD register selects the direction of this pin.

If DDDn is set (one), PDn is configured as an output pin. If DDDn is cleared (zero), PDn

is configured as an input pin. If PORTDn is set (one) when configured as an input pin,

the MOS pull-up resistor is activated. To switch the pull-up resistor off, the PORTDn has

to be cleared (zero) or the pin has to be configured as an output pin. The Port D pins are

tri-stated when a reset condition becomes active, even if the clock is not active.

Table 20. DDDn Bits on Port D Pins

DDDn

PORTDn

I/O

Pull-up

No

Comment

0

1

0

1

0

1

Input

Tri-state (High-Z)

Input

Yes

No

PDn will source current if ext. pulled low

Push-pull Zero Output

Push-pull One Output

Output

No

Note:

n: 6…0, pin number.

Alternate Functions of Port D The alternate functions of Port D are:

• ICP – Port D, Bit 6

Timer/Counter1 Input Capture pin. See the Timer/Counter1 description for further

details.

• T1 – Port D, Bit 5

T1, Timer 1 clock source. See the Timer description for further details.

• T0 – Port D, Bit 4

T0, Timer/Counter0 clock source. See the Timer description for further details.

• INT1 – Port D, Bit 3

INT1, External Interrupt Source 1. The PD3 pin can serve as an external interrupt

source to the MCU. See the interrupt description for further details and how to enable

the source.

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AT90S2313

0839G–08/01

AT90S2313

• INT0 – Port D, Bit 2

INT0, External Interrupt Source 0. The PD2 pin can serve as an external interrupt

source to the MCU. See the interrupt description for further details and how to enable

the source.

• TXD – Port D, Bit 1

Transmit Data (Data output pin for the UART). When the UART transmitter is enabled,

this pin is configured as an output regardless of the value of DDRD1.

• RXD – Port D, Bit 0

Receive Data (Data input pin for the UART). When the UART receiver is enabled, this

pin is configured as an input regardless of the value of DDRD0. When the UART forces

this pin to be an input, a logical “1” in PORTD0 will turn on the internal pull-up.

Port D Schematics

Note that all port pins are synchronized. The synchronization latches are, however, not

shown in the figures.

Figure 44. Port D Schematic Diagram (Pin PD0)

RD

MOS

PULL-

UP

RESET

Q

D

DDD0

C

WD

RESET

Q

D

PD0

PORTD0

C

RL

RP

WP

RXEN

RXD

WP: WRITE PORTD

WD: WRITE DDRD

RL:

RP:

RD:

READ PORTD LATCH

READ PORTD PIN

READ DDRD

RXD: UART RECEIVE DATA

RXEN: UART RECEIVE ENABLE

59

0839G–08/01

Figure 45. Port D Schematic Diagram (Pin PD1)

RD

MOS

PULL-

UP

RESET

R

DDD1

C

Q

D

WD

RESET

R

Q

D

PD1

PORTD1

C

RL

RP

WP

WRITE PORTD

WRITE DDRD

READ PORTD LATCH

READ PORTD PIN

READ DDRD

WP:

WD:

RL:

RP:

RD:

TXEN

TXD

UART TRANSMIT DATA

UART TRANSMIT ENABLE

TXD:

TXEN:

Figure 46. Port D Schematic Diagram (Pins PD2 and PD3)

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AT90S2313

0839G–08/01

AT90S2313

Figure 47. Port D Schematic Diagram (Pins PD4 and PD5)

RD

MOS

PULL-

UP

RESET

R

DDDn

C

Q

D

WD

RESET

R

Q

D

PDn

PORTDn

C

RL

WP

RP

WP: WRITE PORTD

WD: WRITE DDRD

RL: READ PORTD LATCH

RP: READ PORTD PIN

RD: READ DDRD

TIMERm CLOCK

SOURCE MUX

SENSE CONTROL

n:

m:

4, 5

0, 1

CSm0

CSm2 CSm1

Figure 48. Port D Schematic Diagram (Pin PD6)

61

0839G–08/01

Memory Programming

Program and Data

Memory Lock Bits

The AT90S2313 MCU provides two Lock bits that can be left unprogrammed (“1”) or can

be programmed (“0”) to obtain the additional features listed in Table 21. The Lock bits

can only be erased with the Chip Erase operation.

Table 21. Lock Bit Protection Modes

Memory Lock Bits

Mode

LB1

1

LB2 Protection Type

1

2

3

1

0

No memory lock features enabled.

Further programming of the Flash and EEPROM is disabled.⁽¹⁾

0

Same as mode 2, and verify is also disabled.

Note:

1. In the Parallel mode, further programming of the Fuse bits are also disabled. Pro-

gram the Fuse bits before programming the Lock bits.

Fuse Bits

The AT90S2313 has two Fuse bits: SPIEN and FSTRT.

•

When the SPIEN Fuse is programmed (“0”), Serial Program and Data Downloading

is enabled. The default value is programmed (“0”).

•

When the FSTRT Fuse is programmed (“0”), the short start-up time is selected. The

default value is unprogrammed (“1”). Parts with this bit pre-programmed (“0”) can be

delivered on demand.

The Fuse bits are not accessible in Serial Programming Mode. The status of the Fuses

are not affected by Chip Erase.

Signature Bytes

All Atmel microcontrollers have a 3-byte signature code that identifies the device. This

code can be read in both serial and parallel mode. The three bytes reside in a separate

address space.

For the AT90S2313⁽¹⁾they are:

1. $000: $1E (indicates manufactured by Atmel)

2. $001: $91 (indicates 2 Kb Flash memory)

3. $002: $01 (indicates AT90S2313 device when signature byte $001 is $91)

Note:

1. When both Lock bits are programmed (Lock mode 3), the signature bytes cannot be

read in serial mode. Reading the signature bytes will return: $00, $01 and $02.

Programming the Flash

and EEPROM

Atmel’s AT90S2313 offers 2K bytes of in-system reprogrammable Flash program mem-

ory and 128 bytes of EEPROM data memory.

The AT90S2313 is shipped with the on-chip Flash program and EEPROM data memory

arrays in the erased state (i.e., contents = $FF) and ready to be programmed. This

device supports a high-voltage (12V) Parallel Programming Mode and a low-voltage

Serial Programming Mode. The +12V is used for programming enable only, and no cur-

rent of significance is drawn by this pin. The Serial Programming Mode provides a

convenient way to download program and data into the AT90S2313 inside the user’s

system.

The program and EEPROM memory arrays in the AT90S2313 are programmed byte-

by-byte in either programming mode. For the EEPROM, an auto-erase cycle is provided

within the self-timed write instruction in the Serial Programming Mode. During program-

ming, the supply voltage must be in accordance with Table 22.

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AT90S2313

Table 22. Supply Voltage during Programming

Part

Serial Programming

Parallel Programming

4.5 - 5.5V

AT90S2313

2.7 - 6.0V

Parallel Programming

This section describes how to parallel program and verify Flash program memory,

EEPROM data memory, Lock bits and Fuse bits in the AT90S2313.

Signal Names

In this section, some pins of the AT90S2313 are referenced by signal names describing

their function during parallel programming. Pins not described in the following table are

referenced by pin names. See Figure 49 and Table 23. Pins not described in Table 23

are referenced by pin names.

The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a posi-

tive pulse. The bit coding is shown in Table 24.

When pulsing WR or OE, the command loaded determines the action executed. The

command is a byte where the different bits are assigned functions as shown in Table 25.

Figure 49. Parallel Programming

.

Table 23. Pin Name Mapping

Signal Name in

Programming Mode Pin Name I/O Function

0: Device is busy programming, 1: Device is ready

RDY/BSY

PD1

O

for new command

OE

PD2

PD3

I

Output Enable (Active low)

Write Pulse (Active low)

WR

Byte Select (“0” selects low byte, “1” selects high

byte)

BS

PD4

I

XA0

XA1

PD5

PD6

I

XTAL Action Bit 0

XTAL Action Bit 1

DATA

PB7-0

I/O Bi-directional Data Bus (Output when OE is low)

63

0839G–08/01

Table 24. XA1 and XA0 Coding

XA1 XA0 Action when XTAL1 is Pulsed

0

1

0

1

0

1

Load Flash or EEPROM Address (High or low address byte determined by BS)

Load Data (High or Low data byte for Flash determined by BS)

Load Command

No Action, Idle

Table 25. Command Byte Bit Coding

Command Byte

1000 0000

Command Executed

Chip Erase

0100 0000

Write Fuse Bits

Write Lock Bits

Write Flash

0010 0000

0001 0000

0001 0001

Write EEPROM

Read Signature Bytes

Read Fuse and Lock Bits

Read Flash

0000 1000

0000 0100

0000 0010

0000 0011

Read EEPROM

Enter Programming Mode

The following algorithm puts the device in Parallel Programming Mode:

1. Apply supply voltage according to Table 22, between V_CCand GND.

2. Set the RESET and BS pin to “0” and wait at least 100 ns.

3. Apply 11.5 - 12.5V to RESET. Any activity on BS within 100 ns after +12V has

been applied to RESET, will cause the device to fail entering Programming

Mode.

Chip Erase

The Chip Erase command will erase the Flash and EEPROM memories, and the Lock

bits. The Lock bits are not reset until the Flash and EEPROM have been completely

erased. The Fuse bits are not changed. Chip Erase must be performed before the Flash

or EEPROM is reprogrammed.

Load Command “Chip Erase”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS to “0”.

3. Set DATA to “1000 0000”. This is the command for Chip Erase.

4. Give XTAL1 a positive pulse. This loads the command.

5. Give WR a t_{WLWH_CE}wide negative pulse to execute Chip Erase. See Table 26

for t_{WLWH_CE}value. Chip Erase does not generate any activity on the RDY/BSY

pin.

Programming the Flash

A: Load Command “Write Flash”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS to “0”.

3. Set DATA to “0001 0000”. This is the command for Write Flash.

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AT90S2313

0839G–08/01

AT90S2313

4. Give XTAL1 a positive pulse. This loads the command.

B: Load Address High Byte

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS to “1”. This selects high byte.

3. Set DATA = Address high byte ($00 - $03).

4. Give XTAL1 a positive pulse. This loads the address high byte.

C: Load Address Low Byte

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS to “0”. This selects low byte.

3. Set DATA = Address low byte ($00 - $FF).

4. Give XTAL1 a positive pulse. This loads the address low byte.

D: Load Data Low Byte

1. Set XA1, XA0 to “01”. This enables data loading.

2. Set DATA = Data low byte ($00 - $FF).

3. Give XTAL1 a positive pulse. This loads the data low byte.

E: Write Data Low Byte

1. Set BS to “0”. This selects low data.

2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY

goes low.

3. Wait until RDY/BSY goes high to program the next byte.

(See Figure 50 for signal waveforms.)

F: Load Data High Byte

1. Set XA1, XA0 to “01”. This enables data loading.

2. Set DATA = Data high byte ($00 - $FF).

3. Give XTAL1 a positive pulse. This loads the data high byte.

G: Write Data High Byte

1. Set BS to “1”. This selects high data.

2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY

goes low.

3. Wait until RDY/BSY goes high to program the next byte.

(See Figure 51 for signal waveforms.)

The loaded command and address are retained in the device during programming. For

efficient programming, the following should be considered:

•

The command needs only be loaded once when writing or reading multiple memory

locations.

Address high byte needs only be loaded before programming a new 256-word page

in the Flash.

Skip writing the data value $FF; that is, the contents of the entire Flash and

EEPROM after a Chip Erase.

These considerations also apply to EEPROM programming and Flash, EEPROM and

signature byte reading.

65

0839G–08/01

Figure 50. Programming the Flash

DATA

$10

ADDR. HIGH

ADDR. LOW

DATA LOW

XA1

XA0

BS

XTAL1

WR

RDY/BSY

RESET

OE

12V

Figure 51. Programming the Flash (Continued)

DATA

DATA HIGH

XA1

XA0

BS

XTAL1

WR

RDY/BSY

RESET

OE

+12V

Reading the Flash

The algorithm for reading the Flash memory is as follows (refer to “Programming the

Flash” for details on command and address loading):

1. A: Load Command “0000 0010”.

2. B: Load Address High Byte ($00 - $03).

3. C: Load Address Low Byte ($00 - $FF).

4. Set OE to “0”, and BS to “0”. The Flash word low byte can now be read at DATA.

5. Set BS to “1”. The Flash word high byte can now be read from DATA.

6. Set OE to “1”.

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AT90S2313

Programming the EEPROM

Reading the EEPROM

The programming algorithm for the EEPROM data memory is as follows (refer to “Pro-

gramming the Flash” for details on command, address and data loading):

1. A: Load Command “0001 0001”.

2. C: Load Address Low Byte ($00 - $7F).

3. D: Load Data Low Byte ($00 - $FF).

4. E: Write Data Low Byte.

The algorithm for reading the EEPROM memory is as follows (refer to “Programming the

Flash” for details on command and address loading):

1. A: Load Command “0000 0011”.

2. C: Load Address Low Byte ($00 - $7F).

3. Set OE to “0”, and BS to “0”. The EEPROM data byte can now be read at DATA.

4. Set OE to “1”.

Programming the Fuse Bits

The algorithm for programming the Fuse bits is as follows (refer to “Programming the

Flash” for details on command and data loading):

1. A: Load Command “0100 0000”.

2. D: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

Bit 5 = SPIEN Fuse bit.

Bit 0 = FSTRT Fuse bit.

Bit 7-6,4-1 = “1”. These bits are reserved and should be left unprogrammed (“1”).

3. Give WR a t_{WLWH_PFB}wide negative pulse to execute the programming; t_{WLWH_PFB}

is found in Table 26. Programming the Fuse bits does not generate any activity

on the RDY/BSY pin.

Programming the Lock Bits

The algorithm for programming the Lock bits is as follows (refer to “Programming the

Flash” on page 64 for details on command and data loading):

1. A: Load Command “0010 0000”.

2. D: Load Data Low Byte. Bit n = “0” programs the Lock bit.

Bit 2 = Lock Bit2

Bit 1 = Lock Bit1

Bit 7-3,0 = “1”. These bits are reserved and should be left unprogrammed (“1”).

3. E: Write Data Low Byte.

The Lock bits can only be cleared by executing Chip Erase.

Reading the Fuse and Lock

Bits

The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming

the Flash” on page 64 for details on command loading):

1. A: Load Command “0000 0100”.

2. Set OE to “0”, and BS to “1”. The status of the Fuse and Lock bits can now be

read at DATA (“0” means programmed).

Bit 7 = Lock Bit1

Bit 6 = Lock Bit2

Bit 5 = SPIEN Fuse bit

Bit 0 = FSTRT Fuse bit

3. Set OE to “1”.

Observe that BS needs to be set to “1”.

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0839G–08/01

Reading the Signature Bytes

The algorithm for reading the signature bytes is as follows (refer to “Programming the

Flash” on page 64 for details on command and address loading):

1. A: Load Command “0000 1000”.

2. C: Load Address Low Byte ($00 - $02).

Set OE to “0”, and BS to “0”. The selected signature byte can now be read at DATA.

3. Set OE to “1”.

Parallel Programming

Characteristics

Figure 52. Parallel Programming Timing

t_XLWL

t_XHXL

XTAL1

t_DVXH

t_XLDXt_BVWL

Data & Contol

(DATA, XA0/1, BS)

t_WLWH

WR

t_RHBX

t_WHRL

RDY/BSY

t_WLRH

t_OHDZ

OE

t_XLOL

t_OLDV

DATA

Table 26. Parallel Programming Characteristics, T_A= 25°C ± 10%, V_CC= 5V ± 10%

Symbol

V_PP

Parameter

Min

Typ

Max

12.5

Units

V

Programming Enable Voltage

Programming Enable Current

Data and Control Setup before XTAL1 High

XTAL1 Pulse Width High

11.5

I_PP

250.0

µA

ns

t_DVXH

t_XHXL

t_XLDX

t_XLWL

t_BVWL

t_RHBX

t_WLWH

t_WHRL

t_WLRH

t_XLOL

67.0

ns

Data and Control Hold after XTAL1 Low

XTAL1 Low to WR Low

ns

BS Valid to WR Low

ns

BS Hold after RDY/BSY High

WR Pulse Width Low⁽¹⁾

WR High to RDY/BSY Low⁽²⁾

WR Low to RDY/BSY High⁽²⁾

XTAL1 Low to OE Low

ns

20.0

0.7

ns

0.5

0.9

ms

ns

67.0

t_OLDV

t_OHDZ

t_{WLWH_CE}

OE Low to DATA Valid

20.0

ns

OE High to DATA Tri-stated

WR Pulse Width Low for Chip Erase

WR Pulse Width Low for Programming the Fuse

20.0

15.0

ns

5.0

1.0

10.0

1.5

ms

t_{WLWH_PFB}Bits

1.8

ms

Notes: 1. Use t_{WLWH_CE}for chip erase and t_{WLWH_PFB}for programming the Fuse bits.

2. If t_WLWHis held longer than t_WLRH, no RDY/BSY pulse will be seen.

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AT90S2313

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AT90S2313

Serial Downloading

Both the program and data memory arrays can be programmed using the serial SPI bus

while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input)

and MISO (output). See Figure 53. After RESET is set low, the Programming Enable

instruction needs to be executed first before program/erase instructions can be

executed.

Figure 53. Serial Programming and Verify

For the EEPROM, an auto-erase cycle is provided within the self-timed write instruction

and there is no need to first execute the Chip Erase instruction. The Chip Erase instruc-

tion turns the content of every memory location in both the program and EEPROM

arrays into $FF.

The program and EEPROM memory arrays have separate address spaces: $0000 to

$03FF for program Flash memory and $000 to $07F for EEPROM data memory.

Either an external clock is supplied at pin XTAL1 or a crystal needs to be connected

across pins XTAL1 and XTAL2. The minimum low and high periods for the serial clock

(SCK) input are defined as follows:

Low: > 2 XTAL1 clock cycle

High: > 2 XTAL1 clock cycles

Serial Programming

Algorithm

When writing serial data to the AT90S2313, data is clocked on the rising edge of SCK.

When reading data from the AT90S2313, data is clocked on the falling edge of SCK.

See Figure 54, Figure and Table 29 for timing details.

To program and verify the AT90S2313 in the Serial Programming Mode, the following

sequence is recommended (See 4-byte instruction formats in Table 28):

1. Power-up sequence:

Apply power between V_CCand GND while RESET and SCK are set to “0”. If a crys-

tal is not connected across pins XTAL1 and XTAL2, apply a clock signal to the

XTAL1 pin. In some systems, the programmer cannot guarantee that SCK is held

low during power-up. In this case, RESET must be given a positive pulse of at least

two XTAL1 cycles duration after SCK has been set to “0”.

69

0839G–08/01

2. Wait for at least 20 ms and enable serial programming by sending the Program-

ming Enable serial instruction to the MOSI (PB5) pin.

3. The serial programming instructions will not work if the communication is out of

synchronization. When in sync, the second byte ($53) will echo back when issu-

ing the third byte of the Programming Enable instruction. Whether the echo is

correct or not, all four bytes of the instruction must be transmitted. If the $53 did

not echo back, give SCK a positive pulse and issue a new Programming Enable

instruction. If the $53 is not seen within 32 attempts, there is no functional device

connected.

4. If a Chip Erase is performed (must be done to erase the Flash), wait t_{WD_ERASE}

after the instruction, give RESET a positive pulse, and start over from step 2.

See Table 30 for t_{WD_ERASE}value.

5. The Flash or EEPROM array is programmed one byte at a time by supplying the

address and data together with the appropriate Write instruction. An EEPROM

memory location is first automatically erased before new data is written. Use

Data Polling to detect when the next byte in the Flash or EEPROM can be writ-

ten. If polling is not used, wait t_{WD_PROG}before transmitting the next instruction.

See Table 31 for t_{WD_PROG}value. In an erased device, no $FFs in the data file(s)

need to be programmed.

6. Any memory location can be verified by using the Read instruction that returns

the content at the selected address at the serial output MISO (PB6) pin.

7. At the end of the programming session, RESET can be set high to commence

normal operation.

8. Power-off sequence (if needed):

Set XTAL1 to “0” (if a crystal is not used).

Set RESET to “1”.

Turn V_CCpower off.

Data Polling EEPROM

When a byte is being programmed into the EEPROM, reading the address location

being programmed will give the value P1 until the auto-erase is finished, and then the

value P2. See Table 27 for P1 and P2 values.

At the time the device is ready for a new EEPROM byte, the programmed value will read

correctly. This is used to determine when the next byte can be written. This will not work

for the values P1 and P2, so when programming these values, the user will have to wait

for at least the prescribed time t_{WD_PROG}before programming the next byte. See Table

30 for t_{WD_PROG}value. As a chip-erased device contains $FF in all locations, program-

ming of addresses that are meant to contain $FF can be skipped. This does not apply if

the EEPROM is reprogrammed without first chip-erasing the device.

Table 27. Read Back Value during EEPROM Polling

Part

P1

P2

AT90S2313

$80

$7F

Data Polling Flash

When a byte is being programmed into the Flash, reading the address location being

programmed will give the value $7F. At the time the device is ready for a new byte, the

programmed value will read correctly. This is used to determine when the next byte can

be written. This will not work for the value $7F, so when programming this value, the

user will have to wait for at least t_{WD_PROG}before programming the next byte. As a chip-

erased device contains $FF in all locations, programming of addresses that are meant

to contain $FF can be skipped.

70

AT90S2313

0839G–08/01

AT90S2313

Figure 54. Serial Programming Waveforms

Table 28. Serial Programming Instruction Set

Instruction Format

Instruction

Byte 1

Byte 2

Byte 3

Byte4

Operation

1010 1100

0101 0011

100x xxxx

xxxx xxaa

xxxx xxxx

Enable serial programming while

RESET is low.

Programming Enable

1010 1100

xxxx xxxx

Chip erase Flash and EEPROM

memory arrays.

Chip Erase

0010 H000

bbbb bbbb

oooo oooo

Read H (high or low) data o from

program memory at word address

a:b.

Read Program Memory

0100 H000

xxxx xxaa

bbbb bbbb

iiii iiii

Write H (high or low) data i to

program memory at word address

a:b.

Write Program Memory

Read EEPROM

Memory

1010 0000

1100 0000

1010 1100

0011 0000

xxxx xxxx

111x x21x

xxxx xxxx

xbbb bbbb

xxxx xxxx

xxxx xxbb

oooo oooo

iiii iiii

xxxx xxxx

oooo oooo

Read data o from EEPROM memory

at address b.

Write EEPROM

Memory

Write data i to EEPROM memory at

address b.

Write Lock bits. Set bits 1,2 = “0” to

Write Lock Bits

program Lock bits.

Read Signature Bytes

Read signature byte o at address b.⁽¹⁾

Note:

a = address high bits

b = address low bits

H = 0 – Low byte, 1 – High Byte

o = data out

i = data in

x = don’t care

1 = Lock bit 1

2 = Lock bit 2

Note:

1. The signature bytes are not readable in lock mode 3, i.e. both Lock bits programmed.

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0839G–08/01

Serial Programming

Characteristics

Figure 55. Serial Programming Timing

MOSI

t_OVSH

t_SLSH

t_SHOX

SCK

t_SHSL

MISO

t_SLIV

Table 29. Serial Programming Characteristics, T_A= -40°C to 85°C, V_CC= 2.7 - 6.0V

(unless otherwise noted)

Symbol

1/t_CLCL

t_CLCL

Parameter

Min

0

Typ

Max

Units

MHz

ns

Oscillator Frequency (V_CC= 2.7 - 6.0V)

Oscillator Period (V_CC= 2.7 - 6.0V)

Oscillator Frequency (V_CC= 4.0 - 6.0V)

Oscillator Period (V_CC= 4.0 - 6.0V)

SCK Pulse Width High

4.0

250.0

0

1/t_CLCL

t_CLCL

10.0

MHz

ns

100.0

2.0 t_CLCL

t_CLCL

t_SHSL

ns

t_SLSH

SCK Pulse Width Low

ns

t_OVSH

t_SHOX

t_SLIV

MOSI Setup to SCK High

ns

MOSI Hold after SCK High

SCK Low to MISO Valid

2.0 t_CLCL

10.0

ns

16.0

32.0

ns

Table 30. Minimum Wait Delay after the Chip Erase Instruction

Symbol

3.2V

3.6V

4.0V

12 ms

5.0V

t_{WD_ERASE}

18 ms

14 ms

8 ms

Table 31. Minimum Wait Delay after Writing a Flash or EEPROM Location

Symbol

3.2V

3.6V

4.0V

5.0V

t_{WD_PROG}

9 ms

7 ms

6 ms

4 ms

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AT90S2313

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AT90S2313

Electrical Characteristics

Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

Operating Temperature.................................. -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

Voltage on Any Pin Except RESET

with Respect to Ground...............................-1.0V to V_CC+0.5V

Voltage on RESET with Respect to Ground ....-1.0V to +13.0V

Maximum Operating Voltage ............................................ 6.6V

DC Current per I/O Pin ............................................... 40.0 mA

DC Current V_CCand GND Pins ................................ 200.0 mA

DC Characteristics

T_A= -40°C to 85°C, V_CC= 2.7V to 6.0V (unless otherwise noted)

Symbol

V_IL

Parameter

Condition

Min

Typ

Max

0.3 V_CC

Units

(1)

Input Low Voltage

Input High Voltage

(Except XTAL1)

(XTAL1)

-0.5

V

V_IL1

(2)

V_IH

(Except XTAL1, RESET)

(XTAL1)

0.6 V_CC

0.7 V_CC

V_CC+ 0.5

V_IH1

V_IH2

(2)

(RESET)

0.85 V_CC

Output Low Voltage⁽³⁾

I

_OL= 20 mA, V_CC= 5V

0.6

0.5

V

V_OL

V_OH

I_IL

(Ports B, D)

I_OL= 10 mA, V_CC= 3V

I_OH= -3 mA, V_CC= 5V

Output High Voltage⁽⁴⁾

(Ports B, D)

4.3

2.3

V

I_OH= -1.5 mA, V_CC= 3V

Input Leakage

Current I/O pin

V_CC= 6V, pin low

(absolute value)

1.5

µA

nA

Input Leakage

Current I/O pin

V_CC= 6V, pin high

(absolute value)

I_IH

980.0

RRST

R_I/O

Reset Pull-up Resistor

I/O Pin Pull-up Resistor

100.0

35.0

500.0

120.0

3.0

kΩ

mA

µA

Active Mode, V_CC= 3V, 4 MHz

Idle Mode V_CC= 3V, 4 MHz

WDT enabled, V_CC= 3V

WDT disabled, V_CC= 3V

I_CC

Power Supply Current

Power-down Mode⁽⁵⁾

1.0

9.0

15.0

2.0

I_CC

<1.0

Analog Comparator

Input Offset Voltage

V_CC= 5V

V_ACIO

I_ACLK

t_ACPD

40.0

50.0

mV

nA

ns

V_in= V_CC/2

Analog Comparator

V_CC= 5V

-50.0

Input Leakage Current

V_in= V_CC/2

Analog Comparator

Propagation Delay

V_CC= 2.7V

V_CC= 4.0V

750.0

500.0

73

0839G–08/01

Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low.

2. “Min” means the lowest value where the pin is guaranteed to be read as high.

3. Although each I/O port can sink more than the test conditions (20 mA at V_CC= 5V,

10 mA at V_CC= 3V) under steady state conditions (non-transient), the following must

be observed:

1] The sum of all I_OL, for all ports, should not exceed 200 mA

2] The sum of all II_OL, for port D0 - D5 and XTAL2 should not exceed 100 mA.

3] The sum of all I_OL, for ports B0 - B7 and D6 should not exceed 100 mA.

If I_OLexceeds the test condition, V_OLmay exceed the related specification. Pins are

not guaranteed to sink current greater than the listed test condition.

4. Although each I/O port can source more than the test conditions (3 mA at V_CC= 5V,

1.5 mA at V_CC= 3V) under steady state conditions (non-transient), the following must

be observed:

1] The sum of all I_OH, for all ports, should not exceed 200 mA

2] The sum of all I_OH, for port D0 - D5 and XTAL2 should not exceed 100 mA.

3] The sum of all I_OH, for ports B0 - B7 and D6 should not exceed 100 mA.

If I_OHexceeds the test condition, V_OHmay exceed the related specification. Pins are

not guaranteed to source current greater than the listed test condition.

5. Minimum V_CCfor power-down is 2V.

External Clock Drive

Waveforms

Figure 56. External Clock

VIH1

VIL1

External Clock Drive

V_CC= 2.7V to 6.0V

V_CC= 4.0V to 6.0V

Symbol

1/t_CLCL

t_CLCL

Parameter

Oscillator Frequency

Clock Period

High Time

Min

0

Max

Min

0

Max

Units

MHz

ns

4

10.0

250.0

100.0

40.0

t_CHCX

t_CLCX

ns

Low Time

ns

t_CLCH

Rise Time

1.6

0.5

µs

t_CHCL

Fall Time

µs

74

AT90S2313

0839G–08/01

AT90S2313

Typical

The following charts show typical behavior. These figures are not tested during manu-

facturing. All current consumption measurements are performed with all I/O pins

configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-

to-rail output is used as clock source.

Characteristics

The power consumption in Power-Down Mode is independent of clock selection.

The current consumption is a function of several factors such as: operating voltage,

operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and

ambient temperature. The dominating factors are operating voltage and frequency.

The current drawn from capacitive loaded pins may be estimated (for one pin) as

C_L• V_CC• f where C_L= load capacitance, V_CC= operating voltage and f = average

switching frequency of I/O pin.

The parts are characterized at frequencies higher than test limits. Parts are not guaran-

teed to function properly at frequencies higher than the ordering code indicates.

The difference between current consumption in Power-down Mode with Watchdog timer

enabled and Power-down Mode with Watchdog timer disabled represents the differen-

tial current drawn by the Watchdog timer.

Figure 57. Active Supply Current vs. Frequency

ACTIVE SUPPLY CURRENT vs. FREQUENCY

T = 25˚C

A

V_cc= 6V

V_cc= 5.5V

V_cc= 5V

V_cc= 4.5V

V_cc= 4V

V_cc= 3.6V

V_cc= 3.3V

V_cc= 3.0V

V_cc= 2.7V

Frequency (MHz)

75

0839G–08/01

Figure 58. Active Supply Current vs. V_CC

ACTIVE SUPPLY CURRENT vs. V_cc

FREQUENCY = 4 MHz

12

10

8

T_A= 25˚C

T_A= 85˚C

6

4

2

0

2

2.5

3

3.5

4

4.5

5

5.5

6

V_cc(V)

Figure 59. Idle Supply Current vs. Frequency

IDLE SUPPLY CURRENT vs. FREQUENCY

T = 25˚C

A

8

7

6

5

4

3

2

1

0

V_cc= 6V

V_cc= 5.5V

V_cc= 5V

V_cc= 4.5V

V_cc= 4V

V_cc= 3.6V

V_cc= 3.3V

V_cc= 3.0V

V_cc= 2.7V

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Frequency (MHz)

76

AT90S2313

0839G–08/01

AT90S2313

Figure 60. Idle Supply Current vs. V_CC

IDLE SUPPLY CURRENT vs. V_cc

FREQUENCY = 4 MHz

T_A= 25˚C

T_A= 85˚C

V_cc(V)

Figure 61. Power-down Supply Current vs. V_CC

POWER DOWN SUPPLY CURRENT vs. V_cc

WATCHDOG TIMER DISABLED

2

1.8

1.6

1.4

1.2

1

T_A= 85˚C

T_A= 70˚C

0.8

0.6

0.4

0.2

0

T_A= 45˚C

T_A= 25˚C

2

2.5

3

3.5

4

4.5

5

5.5

6

V_cc(V)

77

0839G–08/01

Figure 62. Power-down Supply Current vs. V_CC

POWER DOWN SUPPLY CURRENT vs. V_cc

WATCHDOG TIMER ENABLED

160

140

120

100

80

T_A= 25˚C

T_A= 85˚C

60

40

20

0

2

2.5

3

3.5

4

4.5

5

5.5

6

V_cc(V)

Figure 63. Analog Comparator Current vs. V_CC

ANALOG COMPARATOR CURRENT vs. V

cc

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

T_A= 25˚C

T_A= 85˚C

2

2.5

3

3.5

4

4.5

5

5.5

6

V_cc(V)

78

AT90S2313

0839G–08/01

AT90S2313

Note:

Analog Comparator offset voltage is measured as absolute offset.

Figure 64. Analog Comparator Offset Voltage vs. Common Mode Voltage

ANALOG COMPARATOR OFFSET VOLTAGE vs.

COMMON MODE VOLTAGE

V_cc= 5V

T_A= 25˚C

T_A= 85˚C

Common Mode Voltage (V)

Figure 65. Analog Comparator Offset Voltage vs. Common Mode Voltage

ANALOG COMPARATOR OFFSET VOLTAGE vs.

COMMON MODE VOLTAGE

V_cc= 2.7V

T_A= 25˚C

T_A= 85˚C

Common Mode Voltage (V)

79

0839G–08/01

Figure 66. Analog Comparator Input Leakage Current

ANALOG COMPARATOR INPUT LEAKAGE CURRENT

V_CC= 6V

T_A= 25˚C

60

50

40

30

20

10

0

-10

0

0.5

1

1.5

2

2.5

3

3.5

V (V)

4

4.5

5

5.5

6

6.5

7

IN

Figure 67. Watchdog Oscillator Frequency vs. V_CC

WATCHDOG OSCILLATOR FREQUENCY vs. V

cc

T_A= 25˚C

T_A= 85˚C

V_cc(V)

80

AT90S2313

0839G–08/01

AT90S2313

Note:

Sink and source capabilities of I/O ports are measured on one pin at a time.

Figure 68. Pull-up Resistor Current vs. Input Voltage

PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

V_cc= 5V

T_A= 25˚C

T_A= 85˚C

V_OP(V)

Figure 69. Pull-up Resistor Current vs. Input Voltage

PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

V_cc= 2.7V

T_A= 25˚C

T_A= 85˚C

V_OP(V)

81

0839G–08/01

Figure 70. I/O Pin Sink Current vs. Output Voltage

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

V_cc= 5V

T_A= 25˚C

T_A= 85˚C

V_OL(V)

Figure 71. I/O Pin Source Current vs. Output Voltage

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

V_cc= 5V

T_A= 25˚C

T_A= 85˚C

V_OH(V)

82

AT90S2313

0839G–08/01

AT90S2313

Figure 72. I/O Pin Sink Current vs. Output Voltage

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

V_cc= 2.7V

T_A= 25˚C

T_A= 85˚C

V_OL(V)

Figure 73. I/O Pin Source Current vs. Output Voltage

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

V_cc= 2.7V

T_A= 25˚C

T_A= 85˚C

V_OH(V)

83

0839G–08/01

Figure 74. I/O Pin Input Threshold Voltage vs. V_CC

I/O PIN INPUT THRESHOLD VOLTAGE vs. V

cc

T_A= 25˚C

V_cc

Figure 75. I/O Pin Input Hysteresis vs. V_CC

I/O PIN INPUT HYSTERESIS vs. V

cc

T_A= 25˚C

V_cc

84

AT90S2313

0839G–08/01

AT90S2313

Register Summary

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

$3F ($5F)

$3E ($5E)

$3D ($5D)

$3C ($5C)

$3B ($5B)

$3A ($5A)

$39 ($59)

$38 ($58)

$37 ($57)

$36 ($56)

$35 ($55)

$34 ($54)

$33 ($53)

$32 ($52)

$31 ($51)

$30 ($50)

$2F ($4F)

$2E ($4E)

$2D ($4D)

$2C ($4C)

$2B ($4B)

$2A ($4A)

$29 ($49)

$28 ($48)

$27 ($47)

$26 ($46)

$25 ($45)

$24 ($44)

$23 ($43)

$22 ($42)

$21 ($41)

$20 ($40)

$1F ($3F)

$1E ($3E)

$1D ($3D)

$1C ($3C)

$1B ($3B)

$1A ($3A)

$19 ($39)

$18 ($38)

$17 ($37)

$16 ($36)

$15 ($35)

$14 ($34)

$13 ($33)

$12 ($32)

$11 ($31)

$10 ($30)

...

SREG

Reserved

SPL

I

T

H

S

V

N

Z

C

SP0

-

page 17

SP7

SP6

SP5

-

SP4

-

SP3

-

SP2

-

SP1

-

page 18

Reserved

GIMSK

INT1

INTF1

TOIE1

TOV1

INT0

INTF0

OCIE1A

OCF1A

page 23

page 24

GIFR

TIMSK

-

TICIE1

ICF1

-

TOIE0

TOV0

-

TIFR

Reserved

MCUCR

Reserved

TCCR0

TCNT0

-

SE

-

SM

-

ISC11

-

ISC10

CS02

ISC01

CS01

ISC00

CS00

page 26

page 29

page 30

Timer/Counter0 (8 Bits)

Reserved

TCCR1A

TCCR1B

TCNT1H

TCNT1L

OCR1AH

OCR1AL

Reserved

ICR1H

COM1A1

ICNC1

COM1A0

ICES1

-

.

-

PWM11

CS11

PWM10

CS10

page 31

page 32

page 33

page 34

CTC1

CS12

Timer/Counter1 – Counter Register High Byte

Timer/Counter1 – Counter Register Low Byte

Timer/Counter1 – Compare Register High Byte

Timer/Counter1 – Compare Register Low Byte

Timer/Counter1 – Input Capture Register High Byte

Timer/Counter1 – Input Capture Register Low Byte

page 35

ICR1L

Reserved

WDTCR

Reserved

EEAR

-

WDTOE

WDE

WDP2

WDP1

EEWE

WDP0

EERE

page 38

-

EEPROM Address Register

EEPROM Data Register

page 40

EEDR

EECR

-

EEMWE

Reserved

PORTB

DDRB

PORTB7

DDB7

PINB7

PORTB6

DDB6

PINB6

PORTB5

DDB5

PINB5

PORTB4

DDB4

PINB4

PORTB3

DDB3

PINB3

PORTB2

DDB2

PINB2

PORTB1

DDB1

PINB1

PORTB0

DDB0

PINB0

page 52

PINB

Reserved

PORTD

DDRD

-

PORTD6

DDD6

PIND6

PORTD5

DDD5

PIND5

PORTD4

DDD4

PIND4

PORTD3

DDD3

PIND3

PORTD2

DDD2

PIND2

PORTD1

DDD1

PIND1

PORTD0

DDD0

PIND0

page 58

PIND

Reserved

UDR

$0C ($2C)

$0B ($2B)

$0A ($2A)

$09 ($29)

$08 ($28)

…

UART I/O Data Register

page 46

page 47

page 49

page 50

USR

RXC

RXCIE

TXC

TXCIE

UDRE

UDRIE

FE

RXEN

OR

TXEN

-

UCR

CHR9

RXB8

TXB8

UBRR

UART Baud Rate Register

ACSR

ACD

-

ACO

ACI

ACIE

ACIC

ACIS1

ACIS0

Reserved

Note^$s⁰:^{0 ($}1²⁰.⁾For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. Some of the status flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instructions will operate on all

bits in the I/O register, writing a “1” back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work

with registers $00 to $1F only.

85

0839G–08/01

Instruction Set Summary

Mnemonic

Operands

Description

Operation

Flags

# Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

Rd ← Rd + Rr

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd − Rr

ADD

ADC

ADIW

SUB

SUBI

SBIW

SBC

SBCI

AND

ANDI

OR

Rd, Rr

Rdl, K

Rd, Rr

Rd, K

Rdl, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add Two Registers

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,N,V

1

2

1

2

1

Add with Carry Two Registers

Add Immediate to Word

Subtract Two Registers

Subtract Constant from Register

Subtract Immediate from Word

Subtract with Carry Two Registers

Subtract with Carry Constant from Reg.

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd − K

Rdh:Rdl ← Rdh:Rdl − K

Rd ← Rd − Rr − C

Rd ← Rd − K − C

Rd ← Rd • Rr

Rd ← Rd • K

Rd ← Rd v Rr

Z,N,V

Rd ← Rd v K

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Two’s Complement

Set Bit(s) in Register

Clear Bit(s) in Register

Increment

Decrement

Test for Zero or Minus

Clear Register

Set Register

Z,N,V

Rd ← Rd ⊕ Rr

Rd ← $FF − Rd

Rd ← $00 − Rd

Rd ← Rd v K

Rd ← Rd • ($FF − K)

Rd ← Rd + 1

EOR

COM

NEG

SBR

CBR

INC

DEC

TST

CLR

SER

Z,N,V

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Rd, K

Rd

Z,N,V

Rd ← Rd − 1

Rd

Z,N,V

Rd ← Rd • Rd

Rd ← Rd ⊕ Rd

Rd ← $FF

Rd

Z,N,V

Rd

Z,N,V

Rd

None

BRANCH INSTRUCTIONS

RJMP

IJMP

RCALL

ICALL

RET

RETI

CPSE

CP

CPC

CPI

SBRC

SBRS

SBIC

SBIS

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

BRID

PC ← PC + k + 1

PC ← Z

PC ← PC + k + 1

PC ← Z

PC ← STACK

if (Rd = Rr) PC ← PC + 2 or 3

k

Relative Jump

Indirect Jump to (Z)

Relative Subroutine Call

Indirect Call to (Z)

Subroutine Return

Interrupt Return

Compare, Skip if Equal

Compare

Compare with Carry

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Branch if Not Equal

Branch if Carry Set

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

None

I

2

k

3

4

Rd, Rr

None

Z,N,V,C,H

None

1/2

1

Rd, Rr

Rd − Rr

Rd, Rr

Rd − Rr − C

1

Rd, K

Rd − K

if (Rr(b) = 0) PC ← PC + 2 or 3

if (Rr(b) = 1) PC ← PC + 2 or 3

if (P(b) = 0) PC ← PC + 2 or 3

if (R(b) = 1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC ←=PC + k + 1

if (SREG(s) = 0) then PC ←=PC + k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V = 0) then PC ← PC + k + 1

if (N ⊕ V = 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

if (I = 1) then PC ← PC + k + 1

if (I = 0) then PC ← PC + k + 1

Rr, b

1/2

Rr, b

P, b

s, k

k

Branch if Minus

Branch if Plus

k

Branch if Greater or Equal, Signed

Branch if Less than Zero, Signed

Branch if Half-carry Flag Set

Branch if Half-carry Flag Cleared

Branch if T-Flag Set

Branch if T-Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

k

86

AT90S2313

0839G–08/01

AT90S2313

Instruction Set Summary (Continued)

Mnemonic

Operands

Description

Operation

Flags

# Clocks

DATA TRANSFER INSTRUCTIONS

MOV

LDI

LD

Rd, Rr

Rd, K

Move between Registers

Load Immediate

Rd ← Rr

None

1

2

3

1

2

Rd ← K

Rd, X

Load Indirect

Rd ← (X)

LD

Rd, X+

Rd, -X

Rd, Y

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

In Port

Rd ← (X), X ← X + 1

X ← X − 1, Rd ← (X)

Rd ← (Y)

LD

Rd, Y+

Rd, -Y

Rd, Y+q

Rd, Z

Rd ← (Y), Y ← Y + 1

Y ← Y − 1, Rd ← (Y)

Rd ← (Y + q)

Rd ← (Z)

LD

LDD

LD

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

Rd ← (k)

LDD

LDS

ST

X, Rr

(X) ← Rr

ST

X+, Rr

-X, Rr

Y, Rr

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

ST

Y+, Rr

-Y, Rr

Y+q, Rr

Z, Rr

Z+, Rr

-Z, Rr

Z+q, Rr

k, Rr

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

ST

STD

ST

(Z) ← Rr

ST

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

STD

STS

LPM

IN

OUT

PUSH

POP

(k) ← Rr

R0 ← (Z)

Rd, P

P, Rr

Rr

Rd ← P

Out Port

Push Register on Stack

Pop Register from Stack

P ← Rr

STACK ← Rr

Rd ← STACK

Rd

BIT AND BIT-TEST INSTRUCTIONS

SBI

P, b

Rd

s

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

Logical Shift Right

Rotate Left through Carry

Rotate Right through Carry

Arithmetic Shift Right

Swap Nibbles

Flag Set

Flag Clear

Bit Store from Register to T

Bit Load from T to Register

Set Carry

I/O(P,b) ← 1

I/O(P,b) ← 0

None

2

1

CBI

None

LSL

Rd(n+1) ← Rd(n), Rd(0) ← 0

Z,C,N,V

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Rd(n) ← Rd(n+1), Rd(7) ← 0

Z,C,N,V

Rd(0) ←=C, Rd(n+1) ← Rd(n), C ←=Rd(7)

Z,C,N,V

Rd(7) ←=C, Rd(n) ← Rd(n+1), C ←=Rd(0)

Z,C,N,V

Rd(n) ← Rd(n+1), n = 0..6

Z,C,N,V

Rd(3..0) ←=Rd(7..4), Rd(7..4) ←=Rd(3..0)

None

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

s

SREG(s)

Rr, b

Rd, b

T

None

C

Clear Carry

Set Negative Flag

Clear Negative Flag

Set Zero Flag

Clear Zero Flag

C ← 0

C

N ← 1

N

N ← 0

N

Z ← 1

Z

Z ← 0

Z

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Two’s Complement Overflow

Clear Two’s Complement Overflow

Set T in SREG

I ← 1

I

CLI

I ← 0

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

NOP

SLEEP

WDR

S ← 1

S

S ← 0

S

V ← 1

V

V ← 0

V

T ← 1

T

Clear T in SREG

T ← 0

T

Set Half-carry Flag in SREG

Clear Half-carry Flag in SREG

No Operation

Sleep

Watchdog Reset

H ← 1

H

H ← 0

H

None

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

87

0839G–08/01

Ordering Information

Speed (MHz)

Power Supply

Ordering Code

Package

Operation Range

4

2.7 - 6.0V

AT90S2313-4PC

AT90S2313-4SC

20P3

20S

Commercial

(0°C to 70°C)

AT90S2313-4PI

AT90S2313-4SI

20P3

20S

Industrial

(-40°C to 85°C)

10

4.0 - 6.0V

AT90S2313-10PC

AT90S2313-10SC

20P3

20S

Commercial

(0°C to 70°C)

AT90S2313-10PI

AT90S2313-10SI

20P3

20S

Industrial

(-40°C to 85°C)

Package Type

20P3

20S

20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)

88

AT90S2313

0839G–08/01

AT90S2313

Packaging Information

20P3, 20-lead, 0.300" Wide,

Plastic Dual Inline Package (PDIP)

Dimensions in Inches and (Millimeters)

JEDEC STANDARD MS-001 BA

20S, 20-lead, 0.300" Wide,

Plastic Gull Wing Small Outline (SOIC)

Dimensions in Inches and (Millimeters)

0.020 (0.508)

0.013 (0.330)

1.060(26.9)

.980(24.9)

1

.280(7.11)

.240(6.10)

0.420 (10.7)

0.393 (9.98)

0.299 (7.60)

0.291 (7.39)

PIN 1

.090(2.29)

.900(22.86) REF

MAX

.050 (1.27) BSC

.210(5.33)

MAX

.005(.127)

MIN

SEATING

PLANE

0.513 (13.0)

0.497 (12.6)

.015(.381) MIN

0.105 (2.67)

0.092 (2.34)

.150(3.81)

.115(2.92)

.022(.559)

.014(.356)

.070(1.78)

.045(1.13)

.110(2.79)

.090(2.29)

0.012 (0.305)

0.003 (0.076)

.325(8.26)

.300(7.62)

0

15

REF

0

8

REF

0.013 (0.330)

0.009 (0.229)

.014(.356)

.008(.203)

.430(10.92) MAX

0.035 (0.889)

0.015 (0.381)

89

0839G–08/01

Atmel Headquarters

Atmel Product Operations

Corporate Headquarters

2325 Orchard Parkway

San Jose, CA 95131

TEL (408) 441-0311

FAX (408) 487-2600

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Colorado Springs, CO 80906

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FAX (719) 540-1759

Europe

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Atmel SarL

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Route des Arsenaux 41

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FAX (33) 4-7658-3480

TEL (41) 26-426-5555

FAX (41) 26-426-5500

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Asia

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TEL (49) 71 31 67 25 94

FAX (49) 71 31 67 24 23

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TEL (33) 0 2 40 18 18 18

FAX (33) 0 2 40 18 19 60

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Japan

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FAX (33) 4-4253-6001

TEL (81) 3-3523-3551

FAX (81) 3-3523-7581

Atmel Smart Card ICs

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TEL (44) 1355-357-000

FAX (44) 1355-242-743

Fax-on-Demand

e-mail

North America:

literature@atmel.com

1-(800) 292-8635

Web Site

International:

http://www.atmel.com

1-(408) 441-0732

BBS

1-(408) 436-4309

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty

which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors

which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does

not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted

by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical

components in life support devices or systems.

®

™

Marks bearing and/or are registered trademarks and trademarks of Atmel Corporation.

Terms and product names in this document may be trademarks of others.

Printed on recycled paper.

0839G–08/01/xM


型号：	AT90S2313-4SJ
厂家：	ATMEL
描述：	RISC Microcontroller, 8-Bit, FLASH, 4MHz, CMOS, PDSO20, 0.300 INCH, PLASTIC, MS-013, SOIC-20 微控制器
文件：	总90页 (文件大小：2077K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT90S2313-4SJ [ATMEL]

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