AT90S2323-10SL_技术文档

Features

• Utilizes the AVR^®RISC Architecture

• AVR – High-performance and Low-power RISC Architecture

– 118 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General-purpose Working Registers

– Up to 10 MIPS Throughput at 10 MHz

• Data and Nonvolatile Program Memory

– 2K Bytes of In-System Programmable Flash

Endurance: 1,000 Write/Erase Cycles

– 128 Bytes Internal RAM

– 128 Bytes of In-System Programmable EEPROM

Endurance: 100,000 Write/Erase Cycles

– Programming Lock for Flash Program and EEPROM Data Security

• Peripheral Features

– One 8-bit Timer/Counter with Separate Prescaler

– Programmable Watchdog Timer with On-chip Oscillator

– SPI Serial Interface for In-System Programming

• Special Microcontroller Features

– Low-power Idle and Power-down Modes

– External and Internal Interrupt Sources

– Power-on Reset Circuit

8-bit

Microcontroller

with 2K Bytes of

In-System

Programmable

Flash

– Selectable On-chip RC Oscillator

• Specifications

– Low-power, High-speed CMOS Process Technology

– Fully Static Operation

• Power Consumption at 4 MHz, 3V, 25°C

AT90S2323

AT90LS2323

AT90S2343

AT90LS2343

– Active: 2.4 mA

– Idle Mode: 0.5 mA

– Power-down Mode: <1 µA

• I/O and Packages

– Three Programmable I/O Lines for AT90S/LS2323

– Five Programmable I/O Lines for AT90S/LS2343

– 8-pin PDIP and SOIC

• Operating Voltages

– 4.0 - 6.0V for AT90S2323/AT90S2343

– 2.7 - 6.0V for AT90LS2323/AT90LS2343

• Speed Grades

– 0 - 10 MHz for AT90S2323/AT90S2343-10

– 0 - 4 MHz for AT90LS2323/AT90LS2343-4

– 0 - 1 MHz for AT90LS2343-1

Pin Configuration

PDIP/SOIC

RESET

(CLOCK) PB3

PB4

1

2

3

4

8

7

6

5

VCC

RESET

XTAL1

XTAL2

GND

1

2

3

4

8

7

6

5

VCC

PB2 (SCK/T0)

PB1 (MISO/INT0)

PB0 (MOSI)

PB2 (SCK/T0)

PB1 (MISO/INT0)

PB0 (MOSI)

GND

AT90S/LS2323

AT90S/LS2343

Rev. 1004D–09/01

1

Description

The AT90S/LS2323 and AT90S/LS2343 are low-power, CMOS, 8-bit microcontrollers

based on the AVR RISC architecture. By executing powerful instructions in a single

clock cycle, the AT90S2323/2343 achieves throughputs approaching 1 MIPS per MHz

allowing the system designer to optimize power consumption versus processing speed.

The AVR core combines a rich instruction set with 32 general-purpose working regis-

ters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),

allowing two independent registers to be accessed in one single instruction executed in

one clock cycle. The resulting architecture is more code efficient while achieving

throughputs up to ten times faster than conventional CISC microcontrollers.

Block Diagram

Figure 1. The AT90S/LS2343 Block Diagram

VCC

8-BIT DATA BUS

INTERNAL

OSCILLATOR

GND

PROGRAM

COUNTER

STACK

POINTER

WATCHDOG

TIMER

TIMING AND

CONTROL

RESET

PROGRAM

FLASH

MCU CONTROL

REGISTER

SRAM

INSTRUCTION

REGISTER

GENERAL

PURPOSE

REGISTERS

TIMER/

COUNTER

X

Y

Z

INSTRUCTION

DECODER

INTERRUPT

UNIT

CONTROL

LINES

ALU

EEPROM

STATUS

REGISTER

PROGRAMMING

LOGIC

SPI

DATA REGISTER

PORTB

DATA DIR.

REG. PORTB

PORTB DRIVERS

PB0 - PB4

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AT90S/LS2323/2343

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AT90S/LS2323/2343

Figure 2. The AT90S/LS2323 Block Diagram

VCC

8-BIT DATA BUS

INTERNAL

OSCILLATOR

GND

PROGRAM

COUNTER

STACK

POINTER

WATCHDOG

TIMER

TIMING AND

CONTROL

RESET

PROGRAM

FLASH

MCU CONTROL

REGISTER

SRAM

INSTRUCTION

REGISTER

GENERAL

PURPOSE

REGISTERS

TIMER/

COUNTER

X

Y

Z

INSTRUCTION

DECODER

INTERRUPT

UNIT

CONTROL

LINES

ALU

EEPROM

STATUS

REGISTER

PROGRAMMING

LOGIC

SPI

OSCILLATOR

DATA REGISTER

PORTB

DATA DIR.

REG. PORTB

PORTB DRIVERS

PB0 - PB2

The AT90S2323/2343 provides the following features: 2K bytes of In-System Program-

mable Flash, 128 bytes EEPROM, 128 bytes SRAM, 3 (AT90S/LS2323)/5

(AT90S/LS2343) general-purpose I/O lines, 32 general-purpose working registers, an 8-

bit timer/counter, internal and external interrupts, programmable Watchdog Timer with

internal oscillator, an SPI serial port for Flash Memory downloading and two software-

selectable power-saving modes. The Idle mode stops the CPU while allowing the

SRAM, timer/counters, SPI port and interrupt system to continue functioning. The

Power-down mode saves the register contents but freezes the oscillator, disabling all

other chip functions until the next interrupt or hardware reset.

The device is manufactured using Atmel’s high-density nonvolatile memory technology.

The On-chip Flash allows the program memory to be reprogrammed in-system through

an SPI serial interface. By combining an 8-bit RISC CPU with ISP Flash on a monolithic

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chip, the Atmel AT90S2323/2343 is a powerful microcontroller that provides a highly

flexible and cost-effective solution to many embedded control applications.

The AT90S2323/2343 AVR is supported with a full suite of program and system devel-

opment tools including: C compilers, macro assemblers, program debugger/simulators,

in-circuit emulators and evaluation kits.

Comparison between

AT90S/LS2323 and

AT90S/LS2343

The AT90S/LS2323 is intended for use with external quartz crystal or ceramic resonator

as the clock source. The start-up time is fuse-selectable as either 1 ms (suitable for

ceramic resonator) or 16 ms (suitable for crystal). The device has three I/O pins.

The AT90S/LS2343 is intended for use with either an external clock source or the inter-

nal RC oscillator as clock source. The device has five I/O pins.

Table 1 summarizes the differences in features of the two devices.

Table 1. Feature Difference Summary

Part

AT90S/LS2323

yes

AT90S/LS2343

no

On-chip Oscillator Amplifier

Internal RC Clock

PB3 available as I/O pin

PB4 available as I/O pin

Start-up time

no

yes

never

internal clock mode

always

never

1 ms/16 ms

16 µs fixed

Pin Descriptions

AT90S/LS2323

VCC

Supply voltage pin.

Ground pin.

GND

Port B (PB2..PB0)

Port B is a 3-bit bi-directional I/O port with internal pull-up resistors. The Port B output

buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low, will source

current if the pull-up resistors are activated.

Port B also serves the functions of various special features.

Port pins can provide internal pull-up resistors (selected for each bit). The Port B pins

are tri-stated when a reset condition becomes active.

RESET

Reset input. An external reset is generated by a low level on the RESET pin. Reset

pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter

pulses are not guaranteed to generate a reset.

XTAL1

XTAL2

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting oscillator amplifier.

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AT90S/LS2323/2343

Pin Descriptions

AT90S/LS2343

VCC

Supply voltage pin.

Ground pin.

GND

Port B (PB4..PB0)

Port B is a 5-bit bi-directional I/O port with internal pull-up resistors. The Port B output

buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low, will source

current if the pull-up resistors are activated.

Port B also serves the functions of various special features.

Port pins can provide internal pull-up resistors (selected for each bit). The Port B pins

are tri-stated when a reset condition becomes active.

RESET

CLOCK

Reset input. An external reset is generated by a low level on the RESET pin. Reset

pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter

pulses are not guaranteed to generate a reset.

Clock signal input in external clock mode.

Clock Options

Crystal Oscillator

The AT90S/LS2323 contains an inverting amplifier that can be configured for use as an

On-chip oscillator, as shown in Figure 3. XTAL1 and XTAL2 are input and output

respectively. Either a quartz crystal or a ceramic resonator may be used. It is recom-

mended that the AT90S/LS2343 be used if an external clock source is used, since this

gives an extra I/O pin.

Figure 3. Oscillator Connection

External Clock

The AT90S/LS2343 can be clocked by an external clock signal, as shown in Figure 4, or

by the On-chip RC oscillator. This RC oscillator runs at a nominal frequency of 1 MHz

(V_CC= 5V). A fuse bit (RCEN) in the Flash memory selects the On-chip RC oscillator as

the clock source when programmed (“0”). The AT90S/LS2343 is shipped with this bit

programmed. The AT90S/LS2343 is recommended if an external clock source is used,

because this gives an extra I/O pin.

The AT90S/LS2323 can be clocked by an external clock as well, as shown in Figure 4.

No fuse bit selects the clock source for AT90S/LS2323.

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Figure 4. External Clock Drive Configuration

AT90S/LS2343

AT90S/LS2323

XTAL2

NC

EXTERNAL

OSCILATOR

SIGNAL

EXTERNAL

OSCILATOR

SIGNAL

PB3

XTAL1

GND

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AT90S/LS2323/2343

Architectural

Overview

The fast-access register file concept contains 32 x 8-bit general-purpose working regis-

ters with a single clock cycle access time. This means that during one single clock cycle,

one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from

the register file, the operation is executed and the result is stored back in the register file

– in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for

Data Space addressing, enabling efficient address calculations. One of the three

address pointers is also used as the address pointer for the constant table look-up func-

tion. These added function registers are the 16-bit X-, Y-, and Z-register.

Figure 5. The AT90S2323/2343 AVR RISC Architecture

Data Bus 8-bit

Program

Counter

Status

and Test

Control

Registers

1K x 16

Program

Flash

Interrupt

Unit

32 x 8

General

Purpose

Registers

Instruction

Register

SPI

Unit

Instruction

Decoder

8-bit

Timer/Counter

ALU

Control Lines

Watchdog

Timer

I/O Lines

128 x 8

Data

SRAM

128 x 8

EEPROM

The ALU supports arithmetic and logic functions between registers or between a con-

stant and a register. Single register operations are also executed in the ALU. Figure 5

shows the AT90S2323/2343 AVR RISC microcontroller architecture.

In addition to the register operation, the conventional memory addressing modes can be

used on the register file as well. This is enabled by the fact that the register file is

assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be

accessed as though they were ordinary memory locations.

The I/O memory space contains 64 addresses for CPU peripheral functions such as

Control Registers, Timer/Counters, A/D converters and other I/O functions. The I/O

memory can be accessed directly or as the Data Space locations following those of the

register file, $20 - $5F.

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The AVR has Harvard architecture – with separate memories and buses for program

and data. The program memory is accessed with a two-stage pipeline. While one

instruction is being executed, the next instruction is pre-fetched from the program mem-

ory. This concept enables instructions to be executed in every clock cycle. The program

memory is in-system downloadable Flash memory.

With the relative jump and call instructions, the whole 1K address space is directly

accessed. Most AVR instructions have a single 16-bit word format. Every program

memory address contains a 16- or 32-bit instruction.

During interrupts and subroutine calls, the return address Program Counter (PC) is

stored on the stack. The stack is effectively allocated in the general data SRAM and

consequently, the stack size is only limited by the total SRAM size and the usage of the

SRAM. All user programs must initialize the SP in the reset routine (before subroutines

or interrupts are executed). The 8-bit stack pointer (SP) is read/write-accessible in the

I/O space.

The 128 bytes data SRAM + register file and I/O registers can be easily accessed

through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

Figure 6. Memory Maps

EEPROM Data Memory

$000

EEPROM

(128 x 8)

$07F

A flexible interrupt module has its control registers in the I/O space with an additional

global interrupt enable bit in the status register. All the different interrupts have a sepa-

rate interrupt vector in the interrupt vector table at the beginning of the program

memory. The different interrupts have priority in accordance with their interrupt vector

position. The lower the interrupt vector address, the higher the priority.

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AT90S/LS2323/2343

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AT90S/LS2323/2343

General-purpose

Register File

Figure 7 shows the structure of the 32 general-purpose registers in the CPU.

Figure 7. AVR CPU General-purpose Working Registers

7

0

Addr.

$00

R0

R1

$01

R2

$02

…

R13

R14

R15

R16

R17

…

$0D

$0E

$0F

$10

$11

General

Purpose

Working

Registers

R26

R27

R28

R29

R30

R31

$1A

$1B

$1C

$1D

$1E

$1F

X-register low byte

X-register high byte

Y-register low byte

Y-register high byte

Z-register low byte

Z-register high byte

All the register operating instructions in the instruction set have direct and single-cycle

access to all registers. The only exception is the five constant arithmetic and logic

instructions SBCI, SUBI, CPI, ANDI and ORI between a constant and a register and the

LDI instruction for load immediate constant data. These instructions apply to the second

half of the registers in the register file (R16..R31). The general SBC, SUB, CP, AND and

OR and all other operations between two registers or on a single register apply to the

entire register file.

As shown in Figure 7, each register is also assigned a data memory address, mapping

them directly into the first 32 locations of the user Data Space. Although the register file

is not physically implemented as SRAM locations, this memory organization provides

great flexibility in access of the registers, as the X-, Y-, and Z-registers can be set to

index any register in the file.

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X-register, Y-register and Z-

register

The registers R26..R31 have some added functions to their general-purpose usage.

These registers are the address pointers for indirect addressing of the Data Space. The

three indirect address registers X, Y, and Z, are defined in Figure 8.

Figure 8. The X-, Y-, and Z-registers

15

7

0

X-register

0

7

R27 ($1B)

R26 ($1A)

15

7

0

Y-register

Z-register

0

7

R29 ($1D)

R31 ($1F)

R28 ($1C)

R30 ($1E)

15

7

0

In the different addressing modes, these address registers have functions as fixed dis-

placement, automatic increment and decrement (see the descriptions for the different

instructions).

ALU – Arithmetic Logic

Unit

The high-performance AVR ALU operates in direct connection with all the 32 general-

purpose working registers. Within a single clock cycle, ALU operations between regis-

ters in the register file are executed. The ALU operations are divided into three main

categories: arithmetic, logic and bit functions.

In-System

Programmable Flash

Program Memory

The AT90S2323/2343 contains 2K bytes On-chip, In-System Programmable Flash

memory for program storage. Since all instructions are 16- or 32-bit words, the Flash is

organized as 1K x 16. The Flash memory has an endurance of at least 1000 write/erase

cycles.

The AT90S2323/2343 Program Counter (PC) is 10 bits wide, hence addressing the

1024 program memory addresses. See page 42 for a detailed description on Flash data

programming.

Constant tables must be allocated within the address 0 - 2K (see the LPM – Load Pro-

gram Memory instruction description on page 60).

See page 12 for the different addressing modes.

EEPROM Data Memory

The AT90S2323/2343 contains 128 bytes of EEPROM data memory. It is organized as

a separate data space, in which single bytes can be read and written. The EEPROM has

an endurance of at least 100,000 write/erase cycles. The access between the EEPROM

and the CPU is described on page 32, specifying the EEPROM address register, the

EEPROM data register and the EEPROM control register.

For the SPI data downloading, see page 42 for a detailed description.

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AT90S/LS2323/2343

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AT90S/LS2323/2343

SRAM Data Memory

Figure 9 shows how the AT90S2323/2343 Data Memory is organized.

Figure 9. SRAM Organization

Register File

Data Address Space

R0

R1

R2

…

$00

$01

$02

…

R29

R30

$1D

$1E

$1F

R31

I/O Registers

$00

$20

$21

$22

…

$01

$02

…

$3D

$3E

$3F

$5D

$5E

$5F

Internal SRAM

$60

$61

$62

…

$DD

$DE

$DF

The 224 data memory locations address the Register file, I/O memory and the data

SRAM. The first 96 locations address the Register file + I/O memory, and the next 128

locations address the data SRAM.

The five different addressing modes for the data memory cover: Direct, Indirect with Dis-

placement, Indirect, Indirect with Pre-decrement and Indirect with Post-increment. In the

register file, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data address space.

The Indirect with Displacement mode features 63 address locations reached from the

base address given by the Y- and Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-

increment, the address registers X, Y, and Z are used and decremented and

incremented.

The 32 general-purpose working registers, 64 I/O registers and the 128 bytes of data

SRAM in the AT90S2323/2343 are all directly accessible through all these addressing

modes.

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Program and Data

Addressing Modes

The AT90S2323/2343 AVR RISC microcontroller supports powerful and efficient

addressing modes for access to the program memory (Flash) and data memory. This

section describes the different addressing modes supported by the AVR architecture. In

the figures, OP means the operation code part of the instruction word. To simplify, not all

figures show the exact location of the addressing bits.

Register Direct, Single

Register Rd

Figure 10. Direct Single Register Addressing

The operand is contained in register d (Rd).

Register Direct, Two Registers Figure 11. Direct Register Addressing, Two Registers

Rd and Rr

Operands are contained in register r (Rr) and d (Rd). The result is stored in register d

(Rd).

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AT90S/LS2323/2343

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AT90S/LS2323/2343

I/O Direct

Figure 12. I/O Direct Addressing

Operand address is contained in six bits of the instruction word. n is the destination or

source register address.

Data Direct

Figure 13. Direct Data Addressing

A 16-bit data address is contained in the 16 LSBs of a 2-word instruction. Rd/Rr specify

the destination or source register.

Data Indirect with

Displacement

Figure 14. Data Indirect with Displacement

Operand address is the result of the Y- or Z-register contents added to the address con-

tained in six bits of the instruction word.

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Data Indirect

Figure 15. Data Indirect Addressing

Operand address is the contents of the X-, Y-, or the Z-register.

Data Indirect with Pre-

decrement

Figure 16. Data Indirect Addressing with Pre-decrement

The X-, Y-, or the Z-register is decremented before the operation. Operand address is

the decremented contents of the X-, Y-, or the Z-register.

Data Indirect with Post-

increment

Figure 17. Data Indirect Addressing with Post-increment

+1

The X-, Y-, or the Z-register is incremented after the operation. Operand address is the

content of the X-, Y-, or the Z-register prior to incrementing.

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AT90S/LS2323/2343

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AT90S/LS2323/2343

Constant Addressing Using

the LPM Instruction

Figure 18. Code Memory Constant Addressing

Constant byte address is specified by the Z-register contents. The 15 MSBs select word

address (0 - 1K), the LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB =

1).

Indirect Program Addressing, Figure 19. Indirect Program Memory Addressing

IJMP and ICALL

Program execution continues at address contained by the Z-register (i.e., the PC is

loaded with the contents of the Z-register).

Relative Program Addressing, Figure 20. Relative Program Memory Addressing

RJMP and RCALL

+1

Program execution continues at address PC + k + 1. The relative address k is -2048 to

2047.

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Memory Access and

Instruction Execution

Timing

This section describes the general access timing concepts for instruction execution and

internal memory access.

The AVR CPU is driven by the System Clock Ø, directly generated from the external

clock signal applied to the CLOCK pin. No internal clock division is used.

Figure 21. shows the parallel instruction fetches and instruction executions enabled by

the Harvard architecture and the fast-access register file concept. This is the basic pipe-

lining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for

functions per cost, functions per clocks and functions per power unit.

Figure 21. The Parallel Instruction Fetches and Instruction Executions

T1

T2

T3

T4

System Clock Ø

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

Figure 22. shows the internal timing concept for the register file. In a single clock cycle

an ALU operation using two register operands is executed and the result is stored back

to the destination register.

Figure 22. Single Cycle ALU Operation

T1

T2

T3

T4

System Clock Ø

Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

The internal data SRAM access is performed in two System Clock cycles as described

in Figure 23..

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AT90S/LS2323/2343

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AT90S/LS2323/2343

Figure 23. On-chip Data SRAM Access Cycles

T1

T2

T3

T4

System Clock Ø

Prev. Address

Address

Data

WR

Data

RD

I/O Memory

The I/O space definition of the AT90S2323/2343 is shown in Table 2.

Table 2. AT90S2323/2343 I/O Space

Address Hex

$3F ($5F)

$3D ($5D)

$3B ($5B)

$3A ($5A)

$39 ($59)

$38 ($58)

$35 ($55)

$34 ($54)

$33 ($53)

$32 ($52)

$21 ($41)

$1E ($3E)

$1D ($3D)

$1C ($3C)

$18 ($38)

$17 ($37)

$16 ($36)

Name

SREG

SPL

Function

Status REGister

Stack Pointer Low

GIMSK

GIFR

General Interrupt MaSK register

General Interrupt Flag Register

Timer/Counter Interrupt MaSK register

Timer/Counter Interrupt Flag register

MCU Control Register

TIMSK

TIFR

MCUCR

MCUSR

TCCR0

TCNT0

WDTCR

EEAR

EEDR

EECR

PORTB

DDRB

PINB

MCU Status Register

Timer/Counter0 Control Register

Timer/Counter0 (8-bit)

Watchdog Timer Control Register

EEPROM Address Register

EEPROM Data Register

EEPROM Control Register

Data Register, Port B

Data Direction Register, Port B

Input Pins, Port B

Note:

Reserved and unused locations are not shown in the table.

All AT90S2323/2343 I/Os and peripherals are placed in the I/O space. The I/O locations

are accessed by the IN and OUT instructions transferring data between the 32 general-

purpose working registers and the I/O space. I/O registers within the address range $00

- $1F are directly bit-accessible using the SBI and CBI instructions. In these registers,

the value of single bits can be checked by using the SBIS and SBIC instructions. Refer

to the instruction set section for more details. When using the I/O-specific commands IN

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and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as

SRAM, $20 must be added to these addresses. All I/O register addresses throughout

this document are shown with the SRAM address in parentheses.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the status flags are cleared by writing a logical “1” to them. Note that the CBI

and SBI instructions will operate on all bits in the I/O register, writing a “1” back into any

flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers

$00 to $1F only.

The I/O and peripherals control registers are explained in the following sections.

The AVR Status Register (SREG) at I/O space location $3F ($5F) is defined as:

Status Register – SREG

Bit

7

I

6

T

5

H

4

S

3

V

2

N

1

Z

0

C

$3F ($5F)

Read/Write

Initial Value

SREG

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 7 – I: Global Interrupt Enable

The global interrupt enable bit must be set (one) for the interrupts to be enabled. The

individual interrupt enable control is then performed in separate control registers. If the

global interrupt enable register is cleared (zero), none of the interrupts are enabled inde-

pendent of the individual interrupt enable settings. The I-bit is cleared by hardware after

an interrupt has occurred and is set by the RETI instruction to enable subsequent

interrupts.

• Bit 6 – T: Bit Copy Storage

The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source

and destination for the operated bit. A bit from a register in the register file can be copied

into T by the BST instruction and a bit in T can be copied into a bit in a register in the

register file by the BLD instruction.

• Bit 5 – H: Half-carry Flag

The half-carry flag H indicates a half-carry in some arithmetic operations. See the

Instruction Set description for detailed information.

• Bit 4 – S: Sign Bit, S = N ⊕ V

The S-bit is always an exclusive or between the negative flag N and the two’s comple-

ment overflow flag V. See the Instruction Set description for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The two’s complement overflow flag V supports two’s complement arithmetics. See the

Instruction Set description for detailed information.

• Bit 2 – N: Negative Flag

The negative flag N indicates a negative result from an arithmetical or logical operation.

See the Instruction Set description for detailed information.

• Bit 1 – Z: Zero Flag

The zero flag Z indicates a zero result from an arithmetical or logical operation. See the

Instruction Set description for detailed information.

18

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

• Bit 0 – C: Carry Flag

The carry flag C indicates a carry in an arithmetical or logical operation. See the Instruc-

tion Set description for detailed information.

Note that the Status Register is not automatically stored when entering an interrupt rou-

tine and restored when returning from an interrupt routine. This must be handled by

software.

Stack Pointer – SPL

An 8-bit register at I/O address $3D ($5D) forms the stack pointer of the

AT90S2323/2343. Eight bits are used to address the 128 bytes of SRAM in locations

$60 - $DF.

Bit

7

6

5

4

3

2

1

0

$3D ($5D)

Read/Write

Initial Value

SP7

R/W

0

SP6

R/W

0

SP5

R/W

0

SP4

R/W

0

SP3

R/W

0

SP2

R/W

0

SP1

R/W

0

SP0

R/W

0

SPL

The Stack Pointer points to the data SRAM stack area where the Subroutine and Inter-

rupt stacks are located. This stack space in the data SRAM must be defined by the

program before any subroutine calls are executed or interrupts are enabled. The Stack

Pointer must be set to point above $60. The Stack Pointer is decremented by 1 when

data is pushed onto the Stack with the PUSH instruction and it is decremented by 2

when an address is pushed onto the stack with subroutine calls and interrupts. The

Stack Pointer is incremented by 1 when data is popped from the stack with the POP

instruction and it is incremented by 2 when an address is popped from the stack with

return from subroutine RET or return from interrupt RETI.

Reset and Interrupt

Handling

The AT90S2323/2343 provides two interrupt sources. These interrupts and the separate

reset vector each have a separate program vector in the program memory space. Both

interrupts are assigned individual enable bits that must be set (one) together with the

I-bit in the Status Register in order to enable the interrupt.

The lowest addresses in the program memory space are automatically defined as the

Reset and Interrupt vectors. The complete list of vectors is shown in Table 3. The list

also determines the priority levels of the interrupts. The lower the address, the higher

the priority level. RESET has the highest priority, and next is INT0 (the External Interrupt

Request 0), etc.

Table 3. Reset and Interrupt Vectors

Vector No. Program Address Source

Interrupt Definition

Hardware Pin, Power-on Reset and

Watchdog Reset

1

$000

RESET

INT0

2

3

$001

$002

External Interrupt Request 0

TIMER0, OVF0 Timer/Counter0 Overflow

19

1004D–09/01

The most typical program setup for the Reset and Interrupt vector addresses are:

Address

$000

Labels

Code

Comments

rjmp RESET

rjmp EXT_INT0

rjmp TIM_OVF0

; Reset Handler

; IRQ0 Handler

$001

$002

; Timer0 Overflow

; Handler;

$003

...

MAIN:

...

ldi r16, low(RAMEND)

out SPL, r16

<instr> xxx

...

; Main program start

...

Reset Sources

The AT90S2323/2343 provides three sources of reset:

•

Power-on Reset. The MCU is reset when the supply voltage is below the Power-on

Reset threshold (V_POT).

External Reset. The MCU is reset when a low level is present on the RESET pin for

more than 50 ns.

Watchdog Reset. The MCU is reset when the Watchdog timer period expires and

the Watchdog is enabled.

During reset, all I/O registers are set to their initial values and the program starts execu-

tion from address $000. The instruction placed in address $000 must be an RJMP

(relative jump) instruction to the reset handling routine. If the program never enables an

interrupt source, the interrupt vectors are not used and regular program code can be

placed at these locations. The circuit diagram in Figure 24 shows the reset logic.

Table 4 defines the timing and electrical parameters of the reset circuitry.

Figure 24. Reset Logic

POR

Power-On Reset

Circuit

VCC

100 - 500K

RESET

Reset Circuit

S

Q

Watchdog

Timer

On-Chip

RC-Oscillator

14-Stage Ripple Counter

R

Q

Q0

Q3

Q13

The AT90S/LS2323 has a programmable start-up time. A fuse bit (FSTRT) in the Flash

memory selects the shortest start-up time when programmed (“0”). The AT90S/LS2323

is shipped with this bit unprogrammed.

The AT90S/LS2343 has a fixed start-up time.

20

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

Table 4. Reset Characteristics (V_CC= 5.0V)

Symbol Parameter

Min

1.0

0.4

Typ

1.4

Max Units

Power-on Reset Threshold Voltage, rising

1.8

0.8

V

(1)

V_POT

Power-on Reset Threshold Voltage, falling

0.6

V_RST

t_TOUT

RESET Pin Threshold Voltage

0.6 V_CC

Reset Delay Time-out Period AT90S/LS2323

FSTRT Programmed

1.0

1.1

1.2

ms

Reset Delay Time-out Period AT90S/LS2323

FSTRT Unprogrammed

t_TOUT

11.0

16.0

21.0

ms

µs

t_TOUT

Reset Delay Time-out Period AT90S/LS2343

Note:

1. The Power-on Reset will not work unless the supply voltage has been below V_POT

(falling).

Table 5. Reset Characteristics (V_CC= 3.0V)

Symbol Parameter

Min

1.0

0.4

Typ

1.4

Max Units

Power-on Reset Threshold Voltage, rising

1.8

0.8

V

(1)

V_POT

Power-on Reset Threshold Voltage, falling

0.6

V_RST

t_TOUT

RESET Pin Threshold Voltage

0.6 V_CC

Reset Delay Time-out Period AT90S/LS2323

FSTRT Programmed

2.0

2.2

2.4

ms

Reset Delay Time-out Period AT90S/LS2323

FSTRT Unprogrammed

t_TOUT

22.0

32.0

42.0

ms

µs

t_TOUT

Reset Delay Time-out Period AT90S/LS2343

Note:

1. The Power-on Reset will not work unless the supply voltage has been below V_POT

(falling).

Power-on Reset

The AT90S2323/2343 is designed for use in systems where it can operate from the

internal RC oscillator (AT90S/LS2343), on-chip oscillator (AT90S/LS2323), or in appli-

cations where a clock signal is provided by an external clock source. After V_CChas

reached V_POT, the device will start after the time t_TOUT(see Figure 25). If the clock signal

is provided by an external clock source, the clock must not be applied until V_CChas

reached the minimum voltage defined for the applied frequency.

For AT90S2323, the user can select the start-up time according to typical oscillator

start-up. The number of WDT oscillator cycles used for each time-out is shown in

Table 6. For AT90S2343, the start-up time is one Watchdog cycle only. The frequency

of the Watchdog oscillator is voltage-dependent as shown in “Typical Characteristics” on

page 49.

Table 6. Number of Watchdog Oscillator Cycles

FSTRT

Time-out at V_CC= 5V

1.1 ms

Number of WDT Cycles

Programmed

Unprogrammed

1K

16.0 ms

16K

21

1004D–09/01

Figure 25. MCU Start-up, RESET Tied to V_CC

.

V_POT

VCC

V_RST

RESET

t_TOUT

TIME-OUT

INTERNAL

RESET

Figure 26. MCU Start-up, RESET Controlled Externally

V_POT

VCC

V_RST

RESET

t_TOUT

TIME-OUT

INTERNAL

RESET

External Reset

An external reset is generated by a low level on the RESET pin. Reset pulses longer

than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not

guaranteed to generate a reset. When the applied signal reaches the Reset Threshold

Voltage (V_RST) on its positive edge, the delay timer starts the MCU after the Time-out

period t_TOUThas expired.

Figure 27. External Reset during Operation

22

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of 1 CPU clock cycle

duration. On the falling edge of this pulse, the delay timer starts counting the Time-out

period t_TOUT. Refer to page 30 for details on operation of the Watchdog.

Figure 28. Watchdog Reset during Operation

MCU Status Register –

MCUSR

The MCU Status Register provides information on which reset source caused an MCU

reset.

Bit

7

–

6

–

5

–

4

–

3

–

2

–

1

0

$34 ($54)

Read/Write

Initial Value

EXTRF

R/W

PORF

R/W

MCUSR

R

0

R

0

R

0

R

0

R

0

R

0

See Bit Description

• Bits 7..2 – Res: Reserved Bits

These bits are reserved bits in the AT90S2323/2343 and always read as zero.

• Bit 1 – EXTRF: External Reset Flag

After a Power-on Reset, this bit is undefined (X). It will be set by an External Reset. A

Watchdog Reset will leave this bit unchanged.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set by a Power-on Reset. A Watchdog Reset or an External Reset will leave

this bit unchanged.

To summarize, Table 7 shows the value of these two bits after the three modes of reset.

Table 7. PORF and EXTRF Values after Reset

Reset Source

Power-on Reset

External Reset

Watchdog Reset

PORF

1

EXTRF

Undefined

1

Unchanged

To make use of these bits to identify a reset condition, the user software should clear

both the PORF and EXTRF bits as early as possible in the program. Checking the

PORF and EXTRF values is done before the bits are cleared. If the bit is cleared before

an External or Watchdog Reset occurs, the source of reset can be found by using the

following truth table, Table 8.

23

1004D–09/01

Table 8. Reset Source Identification

PORF

EXTRF

Reset Source

Watchdog Reset

External Reset

Power-on Reset

0

1

0

1

0

1

Interrupt Handling

The AT90S2323/2343 has two 8-bit interrupt mask control registers; GIMSK (General

Interrupt Mask register) and TIMSK (Timer/Counter Interrupt Mask register).

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter-

rupts are disabled. The user software can set (one) the I-bit to enable nested interrupts.

The I-bit is set (one) when a Return from Interrupt instruction (RETI) is executed.

When the Program Counter is vectored to the actual interrupt vector in order to execute

the interrupt handling routine, hardware clears the corresponding flag that generated the

interrupt. Some of the interrupt flags can also be cleared by writing a logical “1” to the

flag bit position(s) to be cleared. If an interrupt condition occurs when the corresponding

interrupt enable bit is cleared (zero), the interrupt flag will be set and remembered until

the interrupt is enabled or the flag is cleared by software.

If one or more interrupt conditions occur when the global interrupt enable bit is cleared

(zero), the corresponding interrupt flag(s) will be set and remembered until the global

interrupt enable bit is set (one) and will be executed by order of priority.

Note that external level interrupt does not have a flag and will only be remembered for

as long as the interrupt condition is active.

Note that the Status Register is not automatically stored when entering an interrupt rou-

tine and restored when returning from an interrupt routine. This must be handled by

software.

General Interrupt Mask

Register – GIMSK

Bit

7

–

6

5

–

4

–

3

–

2

–

1

–

0

–

$3B ($5B)

Read/Write

Initial Value

INT0

R/W

0

GIMSK

R

0

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 7 – Res: Reserved Bit

This bit is a reserved bit in the AT90S2323/2343 and always reads as zero.

• Bit 6 – INT0: External Interrupt Request 0 Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and

ISC00) in the MCU general Control Register (MCUCR) define whether the external

interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on

the pin will cause an interrupt request even if INT0 is configured as an output. The corre-

sponding interrupt of External Interrupt Request 0 is executed from program memory

address $001. See also “External Interrupts.”

• Bits 5..0 – Res: Reserved Bits

These bits are reserved bits in the AT90S2323/2343 and always read as zero.

24

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

General Interrupt Flag

Register – GIFR

Bit

7

–

6

INTF0

R/W

0

5

–

4

–

3

–

2

–

1

–

0

–

$3A ($5A)

Read/Write

Initial Value

GIFR

R

0

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 7 – Res: Reserved Bit

This bit is a reserved bit in the AT90S2323/2343 and always reads as zero.

• Bit 6 – INTF0: External Interrupt Flag0

When an edge on the INT0 pin triggers an interrupt request, the corresponding interrupt

flag, INTF0 becomes set (one). If the I-bit in SREG and the corresponding interrupt

enable bit, INT0 in GIMSK, is set (one), the MCU will jump to the interrupt vector. The

flag is cleared when the interrupt routine is executed. Alternatively, the flag is cleared by

writing a logical “1” to it. This flag is always cleared when INT0 is configured as level

interrupt.

• Bits 5..0 – Res: Reserved Bits

These bits are reserved bits in the AT90S2323/2343 and always read as zero.

Timer/Counter Interrupt Mask

Register – TIMSK

Bit

7

–

6

–

5

–

4

–

3

–

2

–

1

TOIE0

R/W

0

–

$39 ($59)

Read/Write

Initial Value

TIMSK

R

0

R

0

R

0

R

0

R

0

R

0

R

0

• Bits 7..2 – Res: Reserved Bits

These bits are reserved bits in the AT90S2323/2343 and always read zero.

• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector

$002) is executed if an overflow in Timer/Counter0 occurs, i.e., when the Overflow Flag

(Timer/Counter0) is set (one) in the Timer/Counter Interrupt Flag Register (TIFR).

• Bit 0 – Res: Reserved Bit

This bit is a reserved bit in the AT90S2323/2343 and always reads as zero.

Timer/Counter Interrupt FLAG

Register – TIFR

Bit

7

–

6

–

5

–

4

–

3

–

2

–

1

TOV0

R/W

0

–

$38 ($58)

Read/Write

Initial Value

TIFR

R

0

R

0

R

0

R

0

R

0

R

0

R

0

• Bits 7..2 – Res: Reserved Bits

These bits are reserved bits in the AT90S2323/2343 and always read zero.

• Bit 1 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared

by hardware when executing the corresponding interrupt handling vector. Alternatively,

TOV0 is cleared by writing a logical “1” to the flag. When the SREG I-bit and TOIE0

(Timer/Counter0 Overflow Interrupt Enable) and TOV0 are set (one), the

Timer/Counter0 Overflow Interrupt is executed.

25

1004D–09/01

• Bit 0 – Res: Reserved Bit

This bit is a reserved bit in the AT90S2323/2343 and always reads zero.

External Interrupt

The external interrupt is triggered by the INT0 pin. Observe that, if enabled, the interrupt

will trigger even if the INT0 pin is configured as an output. This feature provides a way of

generating a software interrupt. The external interrupt can be triggered by a falling or ris-

ing edge or a low level. This is set up as indicated in the specification for the MCU

Control Register (MCUCR). When the external interrupt is enabled and is configured as

level-triggered, the interrupt will trigger as long as the pin is held low.

The external interrupt is set up as described in the specification for the MCU Control

Register (MCUCR).

Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles

minimum. Four clock cycles after the interrupt flag has been set, the program vector

address for the actual interrupt handling routine is executed. During these four clock

cycles, the Program Counter (2 bytes) is popped back from the stack, the Stack Pointer

is incremented by 2 and the I-flag in SREG is set. The vector is a relative jump to the

interrupt routine and this jump takes two clock cycles. If an interrupt occurs during exe-

cution of a multi-cycle instruction, this instruction is completed before the interrupt is

served.

A return from an interrupt handling routine (same as for a subroutine call routine) takes

four clock cycles. During these four clock cycles, the Program Counter (2 bytes) is

popped back from the stack and the Stack Pointer is incremented by 2. When the AVR

exits from an interrupt, it will always return to the main program and execute one more

instruction before any pending interrupt is served.

MCU Control Register –

The MCU Control Register contains control bits for general MCU functions.

MCUCR

Bit

7

–

6

–

5

SE

R/W

0

4

SM

R/W

0

3

–

2

–

1

ISC01

R/W

0

ISC00

R/W

0

$35 ($55)

Read/Write

Initial Value

MCUCR

R

0

R

0

R

0

R

0

• Bits 7, 6 – Res: Reserved Bits

These bits are reserved bits in the AT90S2323/2343 and always read as zero.

• Bit 5 – SE: Sleep Enable

The SE bit must be set (one) to make the MCU enter the Sleep mode when the SLEEP

instruction is executed. To avoid the MCU entering the Sleep mode, unless it is the pro-

grammer’s purpose, it is recommended to set the Sleep Enable (SE) bit just before the

execution of the SLEEP instruction.

• Bit 4 – SM: Sleep Mode

This bit selects between the two available sleep modes. When SM is cleared (zero), Idle

mode is selected as Sleep mode. When SM is set (one), Power-down mode is selected

as sleep mode. For details, refer to the section “Sleep Modes”.

• Bits 3, 2 – Res: Reserved Bits

These bits are reserved bits in the AT90S2323/2343 and always read as zero.

• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the

corresponding interrupt mask are set. The level and edges on the external INT0 pin that

26

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

activate the interrupt are defined in Table 9. The value on the INT01 pin is sampled

before detecting edges. If edge or toggle interrupt is selected, pulses that last longer

than one clock period will generate an interrupt. Shorter pulses are not guaranteed to

generate an interrupt. If low-level interrupt is selected, the low level must be held until

the completion of the currently executing instruction to generate an interrupt.

Table 9. Interrupt 0 Sense Control

ISC01

ISC00

Description

0

1

0

1

0

1

The low level of INT0 generates an interrupt request.

Reserved

The falling edge of INT0 generates an interrupt request.

The rising edge of INT0 generates an interrupt request.

Sleep Modes

To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruc-

tion must be executed. If an enabled interrupt occurs while the MCU is in a sleep mode,

the MCU awakes, executes the interrupt routine and resumes execution from the

instruction following SLEEP. The contents of the register file, SRAM and I/O memory

are unaltered. If a reset occurs during Sleep mode, the MCU wakes up and executes

from the Reset vector.

Idle Mode

When the SM bit is cleared (zero), the SLEEP instruction forces the MCU into the Idle

mode, stopping the CPU but allowing Timer/Counters, Watchdog and the interrupt sys-

tem to continue operating. This enables the MCU to wake up from external triggered

interrupts as well as internal ones like Timer Overflow interrupt and Watchdog reset.

Power-down Mode

When the SM bit is set (one), the SLEEP instruction forces the MCU into the Power-

down mode. In this mode, the external oscillator is stopped while the external interrupts

and the Watchdog (if enabled) continue operating. Only an external reset, a Watchdog

reset (if enabled), or an external level interrupt on INT0 can wake up the MCU.

Note that if a level-triggered interrupt is used for wake-up from Power-down mode, the

changed level must be held for some time to wake up the MCU. This makes the MCU

less sensitive to noise. The changed level is sampled twice by the Watchdog oscillator

clock and if the input has the required level during this time, the MCU will wake up. The

period of the Watchdog oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of

the Watchdog oscillator is voltage-dependent as shown in section “Typical Characteris-

tics” on page 49.

When waking up from Power-down mode, a delay from the wake-up condition occurs

until the wake-up becomes effective. This allows the clock to restart and become stable

after having been stopped. The wake-up period is equal to the clock reset period, as

shown in Table 4 and Table 5 on page 21.

If the wake-up condition disappears before the MCU wakes up and starts to execute,

e.g., a low-level on is not held long enough, the interrupt causing the wake-up will not be

executed.

27

1004D–09/01

Timer/Counter

The AT90S2323/2343 provides one general-purpose 8-bit Timer/Counter –

Timer/Counter0. The Timer/Counter has prescaling selection from the 10-bit prescaling

timer. The Timer/Counter can be used either as a timer with an internal clock time base

or as a counter with an external pin connection that triggers the counting.

Timer/Counter Prescaler Figure 29 shows the Timer/Counter prescaler.

Figure 29. Timer/Counter0 Prescaler

CK

10-BIT T/C PRESCALER

T0

0

CS00

CS01

CS02

TIMER/COUNTER0 CLOCK SOURCE

TCK0

The four different prescaled selections are: CK/8, CK/64, CK/256 and CK/1024, where

CK is the oscillator clock. CK, external source and stop can also be selected as clock

sources.

8-bit Timer/Counter0

Figure 30 shows the block diagram for Timer/Counter0.

The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK or an external

pin. In addition, it can be stopped as described in the specification for the

Timer/Counter0 Control Register (TCCR0). The overflow status flag is found in the

Timer/Counter Interrupt Flag Register (TIFR). Control signals are found in the

Timer/Counter0 Control Register (TCCR0). The interrupt enable/disable settings for

Timer/Counter0 are found in the Timer/Counter Interrupt Mask Register (TIMSK).

When Timer/Counter0 is externally clocked, the external signal is synchronized with the

oscillator frequency of the CPU. To ensure proper sampling of the external clock, the

minimum time between two external clock transitions must be at least one internal CPU

clock period. The external clock signal is sampled on the rising edge of the internal CPU

clock.

The 8-bit Timer/Counter0 features both a high-resolution and a high-accuracy usage

with the lower prescaling opportunities. Similarly, the high prescaling opportunities make

the Timer/Counter0 useful for lower speed functions or exact timing functions with infre-

quent actions.

28

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

Figure 30. Timer/Counter 0 Block Diagram

T0

Timer/Counter0 Control

Register – TCCR0

Bit

7

–

6

–

5

–

4

–

3

–

2

CS02

R/W

0

1

CS01

R/W

0

CS00

R/W

0

$33 ($53)

Read/Write

Initial Value

TCCR0

R

0

R

0

R

0

R

0

R

0

• Bits 7..3 – Res: Reserved Bits

These bits are reserved bits in the AT90S2323/2343 and always read zero.

• Bits 2, 1, 0 – CS02, CS01, CS00: Clock Select0, Bits 2, 1 and 0

The Clock Select0 bits 2, 1 and 0 define the prescaling source of Timer/Counter0.

Table 10. Clock 0 Prescale Select

CS02

CS01

CS00

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Stop, the Timer/Counter0 is stopped.

CK

CK/8

CK/64

CK/256

CK/1024

External Pin T0, falling edge

External Pin T0, rising edge

29

1004D–09/01

The Stop condition provides a Timer Enable/Disable function. The CK down divided

modes are scaled directly from the CK oscillator clock. If the external pin modes are

used for Timer/Counter0, transitions on PB2/(T0) will clock the counter even if the pin is

configured as an output. This feature can give the user software control of the counting.

Timer/Counter0 – TCNT0

Bit

7

MSB

R/W

0

6

5

4

3

2

1

0

$32 ($52)

Read/Write

Initial Value

LSB

R/W

0

TCNT0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Timer/Counter0 is realized as an up-counter with read and write access. If the

Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues

counting in the timer clock cycle following the write operation.

Watchdog Timer

The Watchdog Timer is clocked from a separate On-chip oscillator. By controlling the

Watchdog Timer prescaler, the Watchdog reset interval can be adjusted as shown in

Table 11. See characterization data for typical values at other V_CClevels. The WDR

(Watchdog Reset) instruction resets the Watchdog Timer. Eight different clock cycle

periods can be selected to determine the reset period. If the reset period expires without

another Watchdog reset, the AT90S2323/2343 resets and executes from the reset vec-

tor. For timing details on the Watchdog reset, refer to page 23.

To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be

followed when the Watchdog is disabled. Refer to the description of the Watchdog Timer

Control Register for details.

Figure 31. Watchdog Timer

Oscillator

1 MHz at V_CC= 5V

350 kHz at V_CC= 3V

30

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

Watchdog Timer Control

Register – WDTCR

Bit

7

–

6

–

5

–

4

WDTOE

R/W

0

3

WDE

R/W

0

2

WDP2

R/W

0

1

WDP1

R/W

0

WDP0

R/W

0

$21 ($41)

Read/Write

Initial Value

WDTCR

R

0

R

0

R

0

• Bits 7..5 – Res: Reserved Bits

These bits are reserved bits in the AT90S2323/2343 and will always read as zero.

• Bit 4 – WDTOE: Watchdog Turn-off Enable

This bit must be set (one) when the WDE bit is cleared. Otherwise, the Watchdog will

not be disabled. Once set, hardware will clear this bit to zero after four clock cycles.

Refer to the description of the WDE bit for a Watchdog disable procedure.

• Bit 3 – WDE: Watchdog Enable

When the WDE is set (one) the Watchdog Timer is enabled and if the WDE is cleared

(zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE

bit is set (one). To disable an enabled Watchdog Timer, the following procedure must be

followed:

1. In the same operation, write a logical “1” to WDTOE and WDE. A logical “1” must

be written to WDE even though it is set to “1” before the disable operation starts.

2. Within the next four clock cycles, write a logical “0” to WDE. This disables the

Watchdog.

• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1 and 0

The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the

Watchdog Timer is enabled. The different prescaling values and their corresponding

time-out periods are shown in Table 11.

Table 11. Watchdog Timer Prescale Select

Number of WDT

WDP2 WDP1 WDP0 Oscillator Cycles

Typical Time-out

at V_CC= 3.0V

Typical Time-out

at V_CC= 5.0V

0

1

0

1

0

1

0

1

0

1

0

1

16K cycles

47 ms

94 ms

0.19 s

0.38 s

0.75 s

1.5 s

15 ms

30 ms

60 ms

0.12 s

0.24 s

0.49 s

0.97 s

1.9 s

0

32K cycles

0

64K cycles

0

128K cycles

256K cycles

512K cycles

1,024K cycles

2,048K cycles

1

3.0 s

1

6.0 s

Note:

The frequency of the Watchdog oscillator is voltage-dependent as shown in the Electrical

Characteristics section.

The WDR (Watchdog Reset) instruction should always be executed before the Watchdog

Timer is enabled. This ensures that the reset period will be in accordance with the

Watchdog Timer prescale settings. If the Watchdog Timer is enabled without reset, the

Watchdog Timer may not start counting from zero.

To avoid unintentional MCU resets, the Watchdog Timer should be disabled or reset

before changing the Watchdog Timer Prescale Select.

31

1004D–09/01

EEPROM Read/Write The EEPROM access registers are accessible in the I/O space.

Access

The write access time is in the range of 2.5 - 4 ms, depending on the V_CCvoltages. A

self-timing function, however, lets the user software detect when the next byte can be

written.

In order to prevent unintentional EEPROM writes, a specific write procedure must be fol-

lowed. Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is written, the CPU is halted for two clock cycles before the next

instruction is executed. When the EEPROM is read, the CPU is halted for four clock

cycles before the next instruction is executed.

EEPROM Address Register –

EEAR

Bit

7

–

6

EEAR6

R/W

0

5

EEAR5

R/W

0

4

EEAR4

R/W

0

3

EEAR3

R/W

0

2

EEAR2

R/W

0

1

EEAR1

R/W

0

EEAR0

R/W

0

$1E ($3E)

Read/Write

Initial Value

EEAR

R

0

• Bit 7 – Res: Reserved Bit

This bit is a reserved bit in the AT90S2323/2343 and will always read as zero.

• Bit 6..0 – EEAR6..0: EEPROM Address

The EEPROM Address Register (EEAR6..0) specifies the EEPROM address in the

128-byte EEPROM space. The EEPROM data bytes are addressed linearly between 0

and 127.

EEPROM Data Register –

EEDR

Bit

7

MSB

R/W

0

6

5

4

3

2

1

0

$1D ($3D)

Read/Write

Initial Value

LSB

R/W

0

EEDR

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bits 7..0 – EEDR7..0: EEPROM Data

For the EEPROM write operation, the EEDR register contains the data to be written to

the EEPROM in the address given by the EEAR register. For the EEPROM read opera-

tion, the EEDR contains the data read out from the EEPROM at the address given by

EEAR.

32

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

EEPROM Control Register –

EECR

Bit

7

–

6

–

5

–

4

–

3

–

2

EEMWE

R/W

0

1

EEWE

R/W

0

EERE

R/W

0

$1C ($3C)

Read/Write

Initial Value

EECR

R

0

R

0

R

0

R

0

R

0

• Bits 7..3 – Res: Reserved Bits

These bits are reserved bits in the AT90S2323/2343 and will always read as zero.

• Bit 2 – EEMWE: EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to “1” causes the EEPROM to be

written. When EEMWE is set (one), setting EEWE will write data to the EEPROM at the

selected address. If EEMWE is zero, setting EEWE will have no effect. When EEMWE

has been set (one) by software, hardware clears the bit to zero after four clock cycles.

See the description of the EEWE bit for a EEPROM write procedure.

• Bit 1 – EEWE: EEPROM Write Enable

The EEPROM Write Enable signal (EEWE) is the write strobe to the EEPROM. When

address and data are correctly set up, the EEWE bit must be set to write the value into

the EEPROM. The EEMWE bit must be set when the logical “1” is written to EEWE, oth-

erwise no EEPROM write takes place. The following procedure should be followed

when writing the EEPROM (the order of steps 2 and 3 is unessential):

1. Wait until EEWE becomes zero.

2. Write new EEPROM address to EEAR (optional).

3. Write new EEPROM data to EEDR (optional).

4. Write a logical “1” to the EEMWE bit in EECR (to be able to write a logical “1” to

the EEMWE bit, the EEWE bit must be written to “0” in the same cycle).

5. Within four clock cycles after setting EEMWE, write a logical “1” to EEWE.

Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the

EEPROM Master Write Enable will time-out. If an interrupt routine accessing the

EEPROM is interrupting another EEPROM access, the EEAR and EEDR registers will

be modified, causing the interrupted EEPROM access to fail. It is recommended to have

the global interrupt flag cleared during the four last steps to avoid these problems.

When the write access time (typically 2.5 ms at V_CC= 5V or 4 ms at V_CC= 2.7V) has

elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit

and wait for a zero before writing the next byte. When EEWE has been set, the CPU is

halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable signal (EERE) is the read strobe to the EEPROM. When

the correct address is set up in the EEAR register, the EERE bit must be set. When the

EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register.

The EEPROM read access takes one instruction and there is no need to poll the EERE

bit. When EERE has been set, the CPU is halted for four cycles before the next instruc-

tion is executed.

The user should poll the EEWE bit before starting the read operation. If a write operation

is in progress when new data or address is written to the EEPROM I/O registers, the

write operation will be interrupted and the result is undefined.

33

1004D–09/01

Prevent EEPROM

Corruption

During periods of low V_CC, the EEPROM data can be corrupted because the supply volt-

age is too low for the CPU and the EEPROM to operate properly. These issues are the

same as for board level systems using the EEPROM and the same design solutions

should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too

low. First, a regular write sequence to the EEPROM requires a minimum voltage to

operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the

supply voltage for executing instructions is too low.

EEPROM data corruption can easily be avoided by following these design recommen-

dations (one is sufficient):

1. Keep the AVR RESET active (low) during periods of insufficient power supply

voltage. This is best done by an external low V_CCReset Protection circuit, often

referred to as a Brown-out Detector (BOD). Please refer to application note AVR

180 for design considerations regarding power-on reset and low-voltage

detection.

2. Keep the AVR core in Power-down Sleep mode during periods of low V_CC. This

will prevent the CPU from attempting to decode and execute instructions, effec-

tively protecting the EEPROM registers from unintentional writes.

3. Store constants in Flash memory if the ability to change memory contents from

software is not required. Flash memory cannot be updated by the CPU and will

not be subject to corruption.

34

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

I/O Port B

All AVR ports have true read-modify-write functionality when used as general digital I/O

ports. This means that the direction of one port pin can be changed without unintention-

ally changing the direction of any other pin with the SBI and CBI instructions. The same

applies for changing drive value (if configured as output) or enabling/disabling of pull-up

resistors (if configured as input).

For the AT90S/LS2323, Port B is an 3-bit bi-directional I/O port. For the AT90S/LS2343,

Port B is a 5-bit bi-directional I/O port.

Please note: Bits 3 and 4 in the description of PORTB, DDRB and PINB do not apply to

the AT90S/LS2323. They are read only with a value of 0.

Three I/O memory address locations are allocated for Port B, one each for the Data

Register – PORTB, $18 ($38), Data Direction Register – DDRB, $17($37) and the Port

B Input Pins – PINB, $16($36). The Port B Input Pins address is read-only, while the

Data Register and the Data Direction Register are read/write.

All port pins have individually selectable pull-up resistors. The Port B output buffers can

sink 20 mA and thus drive LED displays directly. When pins PB0 to PB4 are used as

inputs and are externally pulled low, they will source current if the internal pull-up resis-

tors are activated.

The Port B pins with alternate functions are shown in Table 12.

Table 12. Port B Pin Alternate Functions

Port Pin

Alternate Functions

PB0

MOSI (Data input line for memory downloading)

MISO (Data output line for memory uploading)

INT0 (External Interrupt0 Input)

PB1

SCK (Serial clock input for serial programming)

TO (Timer/Counter0 counter clock input)

PB2

PB3

CLOCK (Clock input, AT90S/LS2343 only)

When the pins are used for the alternate function the DDRB and PORTB register has to

be set according to the alternate function description.

Port B Data Register – PORTB

Bit

7

–

6

–

5

–

4

PORTB4

R/W

0

3

PORTB3

R/W

0

2

PORTB2

R/W

0

1

PORTB1

R/W

0

PORTB0

R/W

0

PORTB

$18 ($38)

Read/Write

Initial Value

R

0

R

0

R

0

Port B Data Direction Register

– DDRB

Bit

7

–

6

–

5

–

4

DDB4

R/W

0

3

DDB3

R/W

0

2

DDB2

R/W

0

1

DDB1

R/W

0

DDB0

R/W

0

$17 ($37)

Read/Write

Initial Value

DDRB

R

0

R

0

R

0

35

1004D–09/01

Port B Input Pins Address –

PINB

Bit

7

–

6

–

5

–

4

PINB4

R

3

PINB3

R

2

PINB2

R

1

PINB1

R

0

PINB0

R

$16 ($36)

Read/Write

Initial Value

PINB

R

0

R

0

R

0

N/A

The Port B Input Pins address (PINB) is not a register and this address enables access

to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch

is read and when reading PINB, the logical values present on the pins are read.

Port B as General Digital All pins in port B have equal functionality when used as digital I/O pins.

I/O

PBn, general I/O pin: The DDBn bit in the DDRB register selects the direction of this pin,

if DDBn is set (one), PBn is configured as an output pin. If DDBn is cleared (zero), PBn

is configured as an input pin. If PORTBn is set (one) when the pin is configured as an

input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off, the

PORTBn has to be cleared (zero) or the pin has to be configured as an output pin. The

port pins are tri-stated when a reset condition becomes active, even if the clock is not

running.

Table 13. DDBn Effects on Port B Pins

DDBn

PORTBn

I/O

Pull-up

No

Comment

0

1

0

1

0

1

Input

Tri-state (high-Z)

Input

Yes

PBn will source current if ext. pulled low

Push-pull Zero Output

Push-pull One Output

Output

No

Alternate Functions of Port B The alternate pin functions of Port B are as follows:

• CLOCK – Port B, Bit 3

Clock input: AT90S/LS2343 only. When the RCEN fuse is programmed and the device

runs from the internal RC oscillator, this pin is a general I/O pin. When the RCEN fuse is

unprogrammed, an external clock source must be connected to CLOCK.

• SCK/T0 – Port B, Bit 2

In Serial Programming mode, this bit serves as the serial clock input, SCK.

During normal operation, this pin can serve as the external counter clock input. See the

timer/counter description for further details. If external timer/counter clocking is selected,

activity on this pin will clock the counter even if it is configured as an output.

• MISO/INT0 – Port B, Bit 1

In Serial Programming mode, this bit serves as the serial data output, MISO.

During normal operation, this pin can serve as the external interrupt0 input. See the

interrupt description for details on how to enable this interrupt. Note that activity on this

pin will trigger the interrupt even if the pin is configured as an output.

• MOSI – Port B, Bit 0

In Serial Programming mode, this pin serves as the serial data input, MOSI.

36

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

Memory Programming

Program and Data

Memory Lock Bits

The AT90S2323/2343 MCU provides two Lock bits that can be left unprogrammed (“1”)

or can be programmed (“0”) to obtain the additional features listed in Table 14. The Lock

bits can only be erased with the Chip Erase operation.

Table 14. Lock Bit Protection Modes

Memory Lock Bits

Mode

LB1

1

LB2 Protection Type

1

2

3

1

0

No memory lock features enabled.

0

Further programming of the Flash and EEPROM is disabled.⁽¹⁾

0

Same as mode 2, and verify is also disabled.

Note:

1. In the high-voltage Serial Programming mode, further programming of the Fuse bits

are also disabled. Program the Fuse bits before programming the Lock bits.

Fuse Bits in

The AT90S/LS2323 has two Fuse bits, SPIEN and FSTRT.

AT90S/LS2323

•

When the SPIEN Fuse is programmed (“0”), Serial Program and Data Downloading

are enabled. Default value is programmed (“0”). This bit is not accessible in the low-

voltage Serial Programming mode.

•

When the FSTRT Fuse is programmed (“0”), the shortest start-up time is selected

as indicated in Table 6 on page 21. Default value is programmed (“0”). Changing the

FSTRT Fuse does not take effect until the next Power-on Reset. In AT90S/LS2343

the start-up time is fixed.

The status of the Fuse bits is not affected by Chip Erase.

Fuse Bits in

The AT90S/LS2343 has two Fuse bits, SPIEN and RCEN.

AT90S/LS2343

•

When the SPIEN Fuse is programmed (“0”), Serial Program and Data Downloading

are enabled. Default value is programmed (“0”). This bit is not accessible in the low-

voltage Serial Programming mode.

When the RCEN Fuse is programmed (“0”), the internal RC oscillator is selected as

the MCU clock source. Default value is programmed ("0") in AT90LS2343-1. Default

value is un-programmed ("1") in AT90LS2343-4 and AT90S2343-10. Changing the

RCEN Fuse does not take effect until the next Power-on Reset. AT90S/LS2323

cannot select the internal RC oscillator as the MCU source.

The status of the Fuse bits is not affected by Chip Erase.

Signature Bytes

All Atmel microcontrollers have a three-byte signature code that identifies the device.

The three bytes reside in a separate address space.

For the AT90S/LS2323^(Note:), they are:

1. $000: $1E (indicates manufactured by Atmel)

2. $001: $91 (indicates 2K bytes Flash memory)

3. $002: $02 (indicates AT90S/LS2323 when signature byte $001 is $91)

For AT90S/LS2343^(Note:), they are:

1. $000: $1E (indicates manufactured by Atmel)

2. $001: $91 (indicates 2K bytes Flash memory)

37

1004D–09/01

3. $002: $03 (indicates AT90S/LS2343 when signature byte $001 is $91)

Note:

When both Lock bits are programmed (Lock mode 3), the signature bytes cannot be read

in the low-voltage Serial mode. Reading the signature bytes will return: $00, $01 and

$02.

Programming the Flash

and EEPROM

Atmel’s AT90S2323/2343 offers 2K bytes of In-System Programmable Flash program

memory and 128 bytes of EEPROM data memory.

The AT90S2323/2343 is shipped with the On-chip Flash program and EEPROM data

memory arrays in the erased state (i.e., contents = $FF) and ready to be programmed.

The device supports a high-voltage (12V) Serial Programming mode and a low-voltage

Serial Programming mode. The +12V is used for programming enable only and no cur-

rent of significance is drawn by this pin. The low-voltage Serial Programming mode

provides a convenient way to download program and data into the device inside the

user’s system.

The program and EEPROM memory arrays in the AT90S2323/2343 are programmed

byte-by-byte in either programming modes. For the EEPROM, an auto-erase cycle is

provided within the self-timed write instruction in the low-voltage Serial Programming

mode.

During programming, the supply voltage must be in accordance with Table 15.

Table 15. Supply Voltage during Programming

Part

Low-voltage Serial Programming

High-voltage Serial Programming

AT90S2323

AT90LS2323

AT90S2323

AT90LS2323

4.0 - 6.0V

2.7 - 6.0V

4.0 - 6.0V

2.7 - 6.0V

4.5 - 5.5V

High-voltage Serial

Programming

This section describes how to program and verify Flash program memory, EEPROM

data memory, Lock bits and Fuse bits in the AT90S2323/2343.

Figure 32. High-voltage Serial Programming

11.5 - 12.5V

4.5 - 5.5V

AT90S/LS2323,

AT90S/LS2343

RESET

VCC

PB2

PB1

PB0

XTAL1/PB3

GND

SERIAL CLOCK INPUT

SERIAL DATA OUTPUT

SERIAL INSTR. INPUT

SERIAL DATA INPUT

38

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

High-voltage Serial

Programming Algorithm

To program and verify the AT90S/LS2323 and AT90S/LS234 in the high-voltage Serial

Programming mode, the following sequence is recommended (see instruction formats in

Table 16):

1. Power-up sequence: Apply 4.5 - 5.5V between V_CCand GND. Set RESET and

PB0 to “0” and wait at least 100 ns. Then, if the RCEN Fuse is not programmed,

toggle XTAL1/PB3 at least four times with minimum 100 ns pulse width. Set PB3

to “0”. Wait at least 100 ns. Or, if the RCEN Fuse is programmed, set PB3 to “0”.

Wait for least 4 µs. In both cases, apply 12V to RESET and wait at least 100 ns

before changing PB0. Wait 8 µs before giving any instructions.

2. The Flash array is programmed one byte at a time by supplying first the address,

then the low and high data bytes. The write instruction is self-timed; wait until the

PB2 (RDY/BSY) pin goes high.

3. The EEPROM array is programmed one byte at a time by supplying first the

address, then the data byte. The write instruction is self-timed; wait until the PB2

(RDY/BSY) pin goes high.

4. Any memory location can be verified by using the Read instruction, which returns

the contents at the selected address at serial output PB2.

5. Power-off sequence:Set PB3 to “0”.

Set RESET to “0”.

Turn V_CCpower off.

When writing or reading serial data to the device, data is clocked on the rising edge of

the serial clock. See Figure 33, Figure 34 and Table 17 for details.

Figure 33. High-voltage Serial Programming Waveforms

LSB

SERIAL DATA INPUT

PB0

MSB

SERIAL INSTR. INPUT

PB1

LSB

SERIAL DATA OUTPUT

PB2

MSB

SERIAL CLOCK INPUT

XTAL1/PB3

0

1

2

3

4

5

6

7

8

9

10

39

1004D–09/01

Table 16. High-voltage Serial Programming Instruction Set

Instruction Format

Instruction

Instr.1

Instr.2

Instr.3

Instr.4

Operation Remarks

PB0

PB1

PB2

0_1000_0000_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_0100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0100_1100_00

x_xxxx_xxxx_xx

Wait t_{WLWH_CE}after Instr.3 for

the Chip Erase cycle to finish.

Chip Erase

PB0

PB1

PB2

0_0001_0000_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_00aa_00

0_0001_1100_00

x_xxxx_xxxx_xx

0_bbbb_bbbb_00

0_0000_1100_00

x_xxxx_xxxx_xx

Write Flash

High and Low

Address

Repeat Instr.2 for a new

256-byte page. Repeat Instr.3

for each new address.

Wait after Instr.3 until PB2

goes high. Repeat Instr.1,

Instr. 2 and Instr.3 for each

new address.

PB0

PB1

PB2

0_ i i i i_i i i i _00

0_0010_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_0100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

0_0000_0000_00

Write Flash

Low Byte

Wait after Instr.3 until PB2

goes high. Repeat Instr.1,

Instr. 2 and Instr.3 for each

new address.

PB0

PB1

PB2

0_ i i i i_i i i i _00

0_0010_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_0100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_1100_00

0_0000_0000_00

Write Flash

High Byte

PB0

PB1

PB2

0_0000_0010_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_00aa_00

0_0001_1100_00

x_xxxx_xxxx_xx

0_bbbb_bbbb_00

0_0000_1100_00

x_xxxx_xxxx_xx

Read Flash

High and Low

Address

Repeat Instr.2 and Instr.3 for

each new address.

PB0

PB1

PB2

0_0000_0000_00

0_0110_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

o_oooo_ooox_xx

Read Flash

Low Byte

Repeat Instr.1 and Instr.2 for

each new address.

0_0000_0000_00

0_0111_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_1100_00

o_oooo_ooox_xx

PB0

Read Flash

High Byte

Repeat Instr.1 and Instr.2 for

each new address.

PB1P

B2

PB0

PB1

PB2

0_0001_0001_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_0bbb_bbbb_00

0_0000_1100_00

x_xxxx_xxxx_xx

Write

EEPROM

Low Address

Repeat Instr.2 for each new

address.

PB0

PB1

PB2

0_ i i i i_i i i i _00

0_0010_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_0100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

0_0000_0000_00

Write

EEPROM

Byte

Wait after Instr.3 until PB2

goes high

PB0

PB1

PB2

0_0000_0011_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_0bbb_bbbb_00

0_0000_1100_00

x_xxxx_xxxx_xx

Read

EEPROM

Low Address

Repeat Instr.2 for each new

address.

PB0

PB1

PB2

0_0000_0000_00

0_0110_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

o_oooo_ooox_xx

Read

EEPROM

Byte

Repeat Instr.2 for each new

address

Wait t_{WLWH_PFB}after Instr.3 for

the Write Fuse bits cycle to

finish. Set S,F = “0” to

PB0

PB1

PB2

0_0100_0000_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_11S1_111F_00

0_0010_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_0100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

x_xxxx_xxxx_xx

Write Fuse

Bits (AT90S/

LS2323)

program, “1” to unprogram.

Wait t_{WLWH_PFB}after Instr.3 for

the Write Fuse bits cycle to

finish. Set S,R = “0” to

PB0

PB1

PB2

0_0100_0000_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_11S1_111R_00

0_0010_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_0100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

x_xxxx_xxxx_xx

Write Fuse

Bits (AT90S/

LS2343)

program, “1” to unprogram.

PB0

PB1

PB2

0_0010_0000_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_1111_1211_00

0_0010_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_0100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

0_0000_0000_00

Wait after Instr.4 until PB2

goes high. Write 2, 1 = “0” to

program the Lock bit.

Write Lock

Bits

40

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

Table 16. High-voltage Serial Programming Instruction Set (Continued)

Instruction Format

Instruction

Instr.1

Instr.2

Instr.3

Instr.4

Operation Remarks

Read Fuse

and Lock Bits

(AT90S/

PB0

PB1

PB2

0_0000_0100_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_1100_00

1_2Sxx_xxRx_xx

Reading 1, 2, S, R = “0” means

the Fuse/Lock bit is

programmed.

LS2323)

Read Fuse

and Lock Bits

(AT90S/

PB0

PB1

PB2

0_0000_0100_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_1100_00

1_2Sxx_xxRx_xx

Reading 1, 2, S, R = “0” means

the Fuse/Lock bit is

programmed.

LS2343)

PB0

PB1

PB2

0_0000_1000_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_00bb_00

0_0000_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

o_oooo_ooox_xx

Read

Signature

Bytes

Repeat Instr.2 - Instr.4 for each

signature byte address.

Note:

a = address high bits

b = address low bits

i = data in

o = data out

x = don’t care

1 = Lock Bit1

2 = Lock Bit2

F = FSTRT Fuse

R = RCEN Fuse

S = SPIEN Fuse

41

1004D–09/01

High-voltage Serial Programming Characteristics

Figure 34. High-voltage Serial Programming Timing

SDI (PB0), SII (PB1)

t_SLSH

t_IVSH

t_SHIX

SCI (XTAL1/PB3)

SDO (PB2)

t_SHSL

t_SHOV

Table 17. High-voltage Serial Programming Characteristics, T_A= 25°C 10%, V_CC

5.0V 10% (unless otherwise noted)

=

Symbol

t_SHSL

Parameter

Min

Typ

Max Units

SCI (XTAL1/PB3) Pulse Width High

SCI (XTAL1/PB3) Pulse Width Low

100.0

ns

t_SLSH

SDI (PB0), SII (PB1) Valid to SCI (XTAL1/PB3)

High

t_IVSH

t_SHIX

50.0

ns

SDI (PB0), SII (PB1) Hold after SCI (XTAL1/PB3)

High

t_SHOV

SCI (XTAL1/PB3) High to SDO (PB2) Valid

Wait after Instr.3 for Chip Erase

10.0

5.0

16.0 32.0

10.0 15.0

ns

ms

t_{WLWH_CE}

t_{WLWH_PFB}Wait after Instr.3 for Write Fuse Bits

1.0

1.5

1.8

Low-voltage Serial

Downloading

Both the program and data memory arrays can be programmed using the serial SPI bus

while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input)

and MISO (output) (see Figure 35). After RESET is set low, the Programming Enable

instruction needs to be executed first before program/erase instructions can be

executed.

Figure 35. Low-voltage Serial Programming and Verify

AT90S/LS2323,

AT90S/LS2343

2.7 - 6.0V

GND

RESET

VCC

PB2

PB1

PB0

SCK

MISO

MOSI

GND

42

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

For the EEPROM, an auto-erase cycle is provided within the self-timed Write instruction

and there is no need to first execute the Chip Erase instruction. The Chip Erase instruc-

tion turns the content of every memory location in both the program and EEPROM

arrays into $FF.

The program and EEPROM memory arrays have separate address spaces: $0000 to

$03FF for Flash program memory and $000 to $07F for EEPROM data memory.

Either an external clock is applied to the XTAL1/PB3 pin or the device must be clocked

from the internal RC oscillator (AT90S/LS2343 only). The minimum low and high peri-

ods for the serial clock (SCK) input are defined as follows:

Low: > 2 MCU clock cycles

High: > 2 MCU clock cycles

Low-voltage Serial

Programming Algorithm

When writing serial data to the AT90S2323/2343, data is clocked on the rising edge of

SCK.

When reading data from the AT90S2323/2343, data is clocked on the falling edge of

SCK. See Figure 36, Figure 37 and Table 20 for timing details.

To program and verify the AT90S2323/2343 in the low-voltage Serial Programming

mode, the following sequence is recommended (see 4-byte instruction formats in

Table 19):

1. Power-up sequence:

Apply power between V_CCand GND while RESET and SCK are set to “0”. (If the

programmer cannot guarantee that SCK is held low during power-up, RESET must

be given a positive pulse after SCK has been set to “0”.) If the device is pro-

grammed for external clocking, apply a 0 - 8 MHz clock to the XTAL1/PB3 pin. If the

internal RC oscillator is selected as the clock source, no external clock source

needs to be applied (AT90S/LS2343 only).

2. Wait for at least 20 ms and enable serial programming by sending the Program-

ming Enable serial instruction to the MOSI (PB0) pin. Refer to the above section

for minimum low and high periods for the serial clock input, SCK.

3. The serial programming instructions will not work if the communication is out of

synchronization. When in sync, the second byte ($53) will echo back when issu-

ing the third byte of the Programming Enable instruction. Whether the echo is

correct or not, all four bytes of the instruction must be transmitted. If the $53 did

not echo back, give SCK a positive pulse and issue a new Programming Enable

instruction. If the $53 is not seen within 32 attempts, there is no functional device

connected.

4. If a Chip Erase is performed (must be done to erase the Flash), wait t_{WD_ERASE}

after the instruction, give RESET a positive pulse and start over from step 2. See

Table 21 on page 46 for t_{WD_ERASE}value.

5. The Flash or EEPROM array is programmed one byte at a time by supplying the

address and data together with the appropriate Write instruction. An EEPROM

memory location is first automatically erased before new data is written. Use

Data Polling to detect when the next byte in the Flash or EEPROM can be writ-

ten. If polling is not used, wait t_{WD_PROG}before transmitting the next instruction.

See Table 22 on page 46 for t_{WD_PROG}value. In an erased device, no $FFs in the

data file(s) need to be programmed.

6. Any memory location can be verified by using the Read instruction, which returns

the content at the selected address at the serial output MISO (PB1) pin.

43

1004D–09/01

7. At the end of the programming session, RESET can be set high to commence

normal operation.

8. Power-off sequence (if needed):

Set CLOCK/XTAL1 to “0”.

Set RESET to “1”.

Turn V_CCpower off.

Data Polling EEPROM

When a byte is being programmed into the EEPROM, reading the address location

being programmed will give the value P1 until the auto-erase is finished, and then the

value P2 will be given. See Table 18 for P1 and P2 values.

At the time the device is ready for a new EEPROM byte, the programmed value will read

correctly. This is used to determine when the next byte can be written. This will not work

for the values P1 and P2, so when programming these values, the user will have to wait

for at least the prescribed time t_{WD_PROG}before programming the next byte. See Table 22

for t_{WD_PROG}value. As a chip-erased device contains $FF in all locations, programming

of addresses that are meant to contain $FF can be skipped. This does not apply if the

EEPROM is reprogrammed without first chip-erasing the device.

Table 18. Read Back Value during EEPROM Polling

Part

P1

P2

AT90S2323

AT90S2343

$00

$FF

Data Polling Flash

When a byte is being programmed into the Flash, reading the address location being

programmed will give the value $FF. At the time the device is ready for a new byte, the

programmed value will read correctly. This is used to determine when the next byte can

be written. This will not work for the value $FF, so when programming this value, the

user will have to wait for at least t_{WD_PROG}before programming the next byte. As a chip-

erased device contains $FF in all locations, programming of addresses that are meant

to contain $FF can be skipped.

Figure 36. Low-voltage Serial Downloading Waveforms

SERIAL DATA INPUT

PB0(MOSI)

MSB

LSB

SERIAL DATA OUTPUT

PB1(MISO)

MSB

SERIAL CLOCK INPUT

PB2(SCK)

44

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

Table 19. Low-voltage Serial Programming Instruction Set AT90S2323/2343

Instruction Format

Instruction

Byte 1

Byte 2

Byte 3

Byte 4

Operation

Programming

Enable

1010 1100

0101 0011

xxxx xxxx

Enable Serial programming while

RESET is low.

1010 1100

100x xxxx

xxxx xxxx

Chip erase both Flash and

EEPROM memory arrays.

Chip Erase

0010 H000

0000 00aa

bbbb bbbb

oooo oooo

Read H (high or low) data o from

program memory at word address

a:b.

Read Program

Memory

0100 H000

0000 00aa

bbbb bbbb

iiii iiii

Write H (high or low) data i to

program memory at word address

a:b.

Write Program

Memory

Read

EEPROM Memory

1010 0000

1100 0000

0101 1000

0000 0000

xxxx xxxx

xbbb bbbb

xxxx xxxx

oooo oooo

iiii iiii

12Sx xxxF

Read data o from EEPROM

memory at address b.

Write

EEPROM Memory

Write data i to EEPROM memory at

address b.

Read Lock and

Fuse Bits

Read Lock and Fuse bits.

“0” = programmed,

(AT90S/LS2323)

“1” = unprogrammed

Read Lock and

Fuse Bits

0101 1000

xxxx xxxx

12Sx xxxR

Read Lock and Fuse bits.

“0” = programmed,

(AT90S/LS2343)

“1” = unprogrammed

1010 1100

0011 0000

1111 1211

1011 111F

1011 111R

xxxx xxxx

xxxx xxbb

xxxx xxxx

oooo oooo

Write Lock bits. Set bits 1,2 = “0” to

program Lock bits.

Write Lock Bits

Write FSTRT Bit

(AT90S/LS2323)

Write FSTRT fuse. Set bit F = “0” to

program, “1” to unprogram.⁽²⁾

Write RCEN Bit

(AT90S/LS2343)

Write RCEN Fuse. Set bit R = ‘0’ to

program, ‘1’ to unprogram.⁽²⁾

Read Signature

Bytes

Read signature byte o from

address b.⁽³⁾

Notes: 1. a = address high bits

b = address low bits

H = 0 – Low byte, 1 – High byte

o = data out

i = data in

x = don’t care

1 = lock bit 1

2 = lock bit 2

F = FSTRT Fuse

R = RCEN Fuse

S = SPIEN Fuse

2. When the state of the RCEN/FSTRT bit is changed, the device must be power cycled for the changes to have any effect.

3. The signature bytes are not readable in Lock mode 3, i.e., both Lock bits programmed.

45

1004D–09/01

Low-voltage Serial Programming Characteristics

Figure 37. Low-voltage Serial Programming Timing

MOSI

t_SLSH

t_OVSH

t_SHOX

SCK

t_SHSL

MISO

t_SLIV

Table 20. Low-voltage Serial Programming Characteristics, T_A= -40°C to 85°C, V_CC

2.7 - 6.0V (unless otherwise noted)

=

Symbol

1/t_CLCL

t_CLCL

Parameter

Min

0

Typ

Max

Units

MHz

ns

Oscillator Frequency (V_CC= 2.7 - 4.0V)

Oscillator Period (V_CC= 2.7 - 4.0V)

Oscillator Frequency (V_CC= 4.0 - 6.0V)

Oscillator Period (V_CC= 4.0 - 6.0V)

SCK Pulse Width High

4.0

250.0

0

1/t_CLCL

t_CLCL

8.0

MHz

ns

125.0

2.0 t_CLCL

t_CLCL

t_SHSL

ns

t_SLSH

SCK Pulse Width Low

ns

t_OVSH

t_SHOX

t_SLIV

MOSI Setup to SCK High

ns

MOSI Hold after SCK High

SCK Low to MISO Valid

2.0 t_CLCL

10.0

ns

16.0

32.0

ns

Table 21. Minimum Wait Delay after the Chip Erase Instruction

Symbol

3.2V

3.6V

4.0V

12 ms

5.0V

t_{WD_ERASE}

18 ms

14 ms

8 ms

Table 22. Minimum Wait Delay after Writing a Flash or EEPROM Location

Symbol

3.2V

3.6V

4.0V

5.0V

t_{WD_PROG}

9 ms

7 ms

6 ms

4 ms

46

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

Electrical Characteristics

Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

Operating Temperature.................................. -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

Voltage on Any Pin except RESET

with respect to Ground ..............................-1.0V to V_CC+ 0.5V

Voltage on RESET with Respect to Ground ....-1.0V to +13.0V

Maximum Operating Voltage ............................................ 6.6V

DC Current per I/O Pin ............................................... 40.0 mA

DC Current V_CCand GND Pins................................ 200.0 mA

DC Characteristics

T_A= -40°C to 85°C, V_CC= 2.7V to 6.0V (unless otherwise noted)

Symbol

V_IL

Parameter

Condition

(Except XTAL)

XTAL

Min

-0.5

Typ

Max

0.3 V_CC

0.1⁽¹⁾

Units

(1)

Input Low Voltage

Input High Voltage

V

V_IL1

(2)

V_IH

(Except XTAL, RESET)

XTAL

0.6 V

0.7 V

V_CC+ 0.5

CC

V_IH1

V_IH2

CC

(2)

RESET

0.85 V

CC

I

= 20 mA, V

= 10 mA, V

= 5V

= 3V

0.5

0.4

V

OL

CC

V_OL

V_OH

I_IL

Output Low Voltage Ports B

Output High Voltage Ports B

I

= -3 mA, V

= 5V

4.2

2.4

V

OH

CC

= -1.5 mA, V

= 3V

CC

Input Leakage

Current I/O Pin

V

= 6V, Pin Low

CC

(absolute value)

8.0

µA

Input Leakage

Current I/O Pin

V

= 6V, Pin High

CC

(absolute value)

I_IH

RRST

R_I/O

Reset Pull-up

I/O Pin Pull-up

100.0

30.0

500.0

150.0

3.0

kΩ

Active 4 MHz, V_CC= 3V

Idle 4 MHz, V_CC= 3V

mA

1.1

Power-down 4 MHz⁽³⁾

,

Power Supply Current

AT90S2343

25.0

20.0

µA

V_CC= 3V WDT Enabled

Power-down 4 MHz⁽³⁾

_CC= 3V WDT Disabled

,

V

I_CC

Active 4 MHz, V_CC= 3V

Idle 4 MHz, V_CC= 3V

4.0

1.2

mA

1.0

9.0

Power-down⁽³⁾

,

Power Supply Current

AT90S2323

15.0

2.0

µA

V_CC= 3V WDT Enabled

Power-down⁽³⁾

V_CC= 3V WDT Disabled

,

<1.0

Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low.

2. “Min” means the lowest value where the pin is guaranteed to be read as high.

3. Minimum V_CCfor Power-down is 2V.

47

1004D–09/01

External Clock Drive Waveforms

Figure 38. Waveforms

VIH1

VIL1

External Clock Drive

T_A= -40°C to 85°C

V_CC: 2.7V to 4.0V

V_CC: 4.0V to 6.0V

Symbol

1/t_CLCL

t_CLCL

Parameter

Oscillator Frequency

Clock Period

High Time

Min

0

Max

Min

0

Max

Units

MHz

ns

4.0

10.0

250.0

100.0

40.0

t_CHCX

t_CLCX

ns

Low Time

ns

t_CLCH

Rise Time

1.6

0.5

µs

t_CHCL

Fall Time

µs

48

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

Typical

Characteristics

The following charts show typical behavior. These figures are not tested during manu-

facturing. All current consumption measurements are performed with all I/O pins

configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-

to-rail output is used as clock source.

The current consumption is a function of several factors such as: operating voltage,

operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and

ambient temperature. The dominating factors are operating voltage and frequency.

The current drawn from capacitive loaded pins may be estimated (for one pin) as

C_L•V_CC•f where C_L= load capacitance, V_CC= operating voltage and f = average switch-

ing frequency of I/O pin.

The parts are characterized at frequencies higher than test limits. Parts are not guaran-

teed to function properly at frequencies higher than the ordering code indicates.

The difference between current consumption in Power-down mode with Watchdog

Timer enabled and Power-down mode with Watchdog Timer disabled represents the dif-

ferential current drawn by the Watchdog Timer.

Figure 39. Active Supply Current vs. Frequency

ACTIVE SUPPLY CURRENT vs. FREQUENCY

T = 25˚C

A

20.00

18.00

16.00

14.00

12.00

10.00

8.00

V_cc= 6V

V_cc= 5.5V

V_cc= 5V

V_cc= 4.5V

V_cc= 4V

V_cc= 3.6V

V_cc= 3.3V

6.00

V_cc= 3.0V

V_cc= 2.7V

4.00

2.00

0.00

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Frequency (MHz)

49

1004D–09/01

Figure 40. Active Supply Current vs. V_CC

ACTIVE SUPPLY CURRENT vs. V_cc

FREQUENCY = 4 MHz

10

9

8

7

6

5

4

3

2

1

0

T_A= 25˚C

T_A= 85˚C

2

2.5

3

3.5

4

4.5

5

5.5

6

V_cc(V)

Figure 41. Active Supply Current vs. V_CC

ACTIVE SUPPLY CURRENT vs. V_cc

DEVICE CLOCKED BY INTERNAL RC OSCILLATOR

7

6

5

4

3

2

1

0

T_A= 25˚C

T_A= 85˚C

2

2.5

3

3.5

4

4.5

5

5.5

6

V_cc(V)

50

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

Figure 42. Idle Supply Current vs. Frequency

IDLE SUPPLY CURRENT vs. FREQUENCY

T = 25˚C

A

5

4.5

4

V_cc= 6V

V_cc= 5.5V

V_cc= 5V

3.5

3

V_cc= 4.5V

2.5

2

V_cc= 4V

V_cc= 3.6V

V_cc= 3.3V

1.5

1

V_cc= 3.0V

V_cc= 2.7V

0.5

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Frequency (MHz)

Figure 43. Idle Supply Current vs. V_CC

IDLE SUPPLY CURRENT vs. V_cc

FREQUENCY = 4 MHz

2.5

2

T_A= 25˚C

T_A= 85˚C

1.5

1

0.5

0

2

2.5

3

3.5

4

4.5

5

5.5

6

V_cc(V)

51

1004D–09/01

Figure 44. Idle Supply Current vs. V_CC

IDLE SUPPLY CURRENT vs. V_cc

DEVICE CLOCKED BY INTERNAL RC OSCILLATOR

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

T_A= 25˚C

T_A= 85˚C

0

2

2.5

3

3.5

4

4.5

5

5.5

6

V_cc(V)

Figure 45. Power-down Supply Current vs. V_CC

POWER DOWN SUPPLY CURRENT vs. V_cc

WATCHDOG TIMER DISABLED

25

20

15

10

5

T_A= 85˚C

T_A= 70˚C

T_A= 45˚C

T_A= 25˚C

0

2

2.5

3

3.5

4

4.5

5

5.5

6

V_cc(V)

52

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

Figure 46. Power-down Supply Current vs. V_CC

POWER DOWN SUPPLY CURRENT vs. V_cc

WATCHDOG TIMER ENABLED

180

160

140

120

100

80

T_A= 85˚C

T_A= 25˚C

60

40

20

0

2

2.5

3

3.5

4

4.5

5

5.5

6

V_cc(V)

Figure 47. Watchdog Oscillator Frequency vs. V_CC

WATCHDOG OSCILLATOR FREQUENCY vs. V_cc

1600

1400

1200

1000

800

600

400

200

0

T_A= 25˚C

T_A= 85˚C

2

2.5

3

3.5

4

4.5

5

5.5

6

V_cc(V)

53

1004D–09/01

Note:

Sink and source capabilities of I/O ports are measured on one pin at a time.

Figure 48. Pull-up Resistor Current vs. Input Voltage

PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

V_cc= 5V

120

100

80

60

40

20

0

T_A= 25˚C

T_A= 85˚C

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

V_OP(V)

Figure 49. Pull-up Resistor Current vs. Input Voltage

PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

V_cc= 2.7V

30

25

20

15

10

5

T_A= 25˚C

T_A= 85˚C

0

0.5

1

1.5

2

2.5

3

V_OP(V)

54

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

Figure 50. I/O Pin Sink Current vs. Output Voltage

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

V_cc= 5V

70

60

50

40

30

20

10

0

T_A= 25˚C

T_A= 85˚C

0

0.5

1

1.5

2

2.5

3

V_OL(V)

Figure 51. I/O PIn Source Current vs. Output Voltage

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

V_cc= 5V

20

18

16

14

12

10

8

T_A= 25˚C

T_A= 85˚C

6

4

2

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

V_OH(V)

55

1004D–09/01

Figure 52. I/O Pin Sink Current vs. Output Voltage

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

V_cc= 2.7V

25

20

15

10

5

T_A= 25˚C

T_A= 85˚C

0

0.5

1

1.5

2

V_OL(V)

Figure 53. I/O Pin Source Current vs. Output voltage

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

V_cc= 2.7V

6

5

4

3

2

1

0

T_A= 25˚C

T_A= 85˚C

0

0.5

1

1.5

2

2.5

3

V_OH(V)

56

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

Figure 54. I/O Pin Input Threshold Voltage vs. V_CC

I/O PIN INPUT THRESHOLD VOLTAGE vs. V_cc

T_A= 25˚C

2.5

2

1.5

1

0.5

0

2.7

4.0

5.0

V_cc

Figure 55. I/O Pin Input Hysteresis vs. V_CC

I/O PIN INPUT HYSTERESIS vs. V

cc

T_A= 25˚C

0.18

0.16

0.14

0.12

0.1

0.08

0.06

0.04

0.02

0

2.7

4.0

5.0

V_cc

57

1004D–09/01

AT90S2323/2343 Register Summary

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

$3F ($5F)

$3E ($5E)

$3D ($5D)

$3C ($5C)

$3B ($5B)

$3A ($5A)

$39 ($59)

$38 ($58)

$37 ($57)

$36 ($56)

$35 ($55)

$34 ($54)

$33 ($53)

$32 ($52)

$31 ($51)

$30 ($50)

$2F ($4F)

$2E ($4E)

$2D ($4D)

$2C ($4C)

$2B ($4B)

$2A ($4A)

$29 ($49)

$28 ($48)

$27 ($47)

$26 ($46)

$25 ($45)

$24 ($44)

$23 ($43)

$22 ($42)

$21 ($41)

$20 ($40)

$1F ($3F)

$1E ($3E)

$1D ($3D)

$1C ($3C)

$1B ($3B)

$1A ($3A)

$19 ($39)

$18 ($38)

$17 ($37)

$16 ($36)

$15 ($35)

…

SREG

Reserved

SPL

I

T

H

S

V

N

Z

C

page 18

SP7

SP6

SP5

-

SP4

-

SP3

-

SP2

-

SP1

-

SP0

-

page 19

Reserved

GIMSK

-

INT0

page 24

page 25

GIFR

INTF0

TIMSK

-

TOIE0

TOV0

-

TIFR

Reserved

MCUCR

MCUSR

TCCR0

-

SE

SM

-

ISC01

EXTRF

CS01

ISC00

PORF

CS00

page 26

page 23

page 29

page 30

-

CS02

TCNT0

Timer/Counter0 (8 Bits)

Reserved

WDTCR

Reserved

EEAR

-

WDTOE

WDE

WDP2

WDP1

EEWE

WDP0

EERE

page 31

EEPROM Address Register

page 32

page 33

EEDR

EEPROM Data Register

EECR

-

EEMWE

Reserved

PORTB

-

PORTB4

DDB4

PORTB3

DDB3

PORTB2

DDB2

PORTB1

DDB1

PORTB0

DDB0

page 35

page 36

DDRB

PINB

PINB4

PINB3

PINB2

PINB1

PINB0

Reserved

$00 ($20)

Note:

1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. Some of the status flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instructions will operate on all

bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work

with registers $00 to $1F only.

58

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

Instruction Set Summary

Mnemonic

Operands

Description

Operation

Flags

# Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

ADC

ADIW

SUB

SUBI

SBIW

SBC

SBCI

AND

ANDI

OR

Rd, Rr

Rdl, K

Rd, Rr

Rd, K

Rdl, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add Two Registers

Rd ← Rd + Rr

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd − Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,N,V

1

2

1

2

1

Add with Carry Two Registers

Add Immediate to Word

Subtract Two Registers

Subtract Constant from Register

Subtract Immediate from Word

Subtract with Carry Two Registers

Subtract with Carry Constant from Reg.

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd − K

Rdh:Rdl ← Rdh:Rdl − K

Rd ← Rd − Rr − C

Rd ← Rd − K − C

Rd ← Rd • Rr

Rd ← Rd • K

Z,N,V

Rd ← Rd v Rr

Z,N,V

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Rd ← Rd v K

Z,N,V

EOR

COM

NEG

SBR

CBR

INC

Rd ← Rd ⊕ Rr

Rd ← $FF − Rd

Rd ← $00 − Rd

Rd ← Rd v K

Z,N,V

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

Rd, K

Rd

Set Bit(s) in Register

Clear Bit(s) in Register

Increment

Rd ← Rd • ($FF − K)

Rd ← Rd + 1

Z,N,V

DEC

TST

Rd

Decrement

Rd ← Rd − 1

Z,N,V

Rd

Test for Zero or Minus

Clear Register

Rd ← Rd • Rd

Rd ← Rd ⊕ Rd

Rd ← $FF

Z,N,V

CLR

SER

Rd

Z,N,V

Rd

Set Register

None

BRANCH INSTRUCTIONS

RJMP

IJMP

k

Relative Jump

PC ← PC + k + 1

None

I

2

Indirect Jump to (Z)

PC ← Z

RCALL

ICALL

RET

k

Relative Subroutine Call

Indirect Call to (Z)

PC ← PC + k + 1

3

PC ← Z

3

Subroutine Return

PC ← STACK

4

RETI

Interrupt Return

PC ← STACK

4

CPSE

CP

Rd, Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC ← PC + 2 or 3

Rd − Rr

None

Z,N,V,C,H

None

1/2/3

1

Rd, Rr

CPC

Rd, Rr

Compare with Carry

Rd − Rr − C

1

CPI

Rd, K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd − K

1

SBRC

SBRS

SBIC

Rr, b

if (Rr(b) = 0) PC ← PC + 2 or 3

if (Rr(b) = 1) PC ← PC + 2 or 3

if (P(b) = 0) PC ← PC + 2 or 3

if (R(b) = 1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC ←=PC + k + 1

if (SREG(s) = 0) then PC ←=PC + k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V = 0) then PC ← PC + k + 1

if (N ⊕ V = 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

if (I = 1) then PC ← PC + k + 1

if (I = 0) then PC ← PC + k + 1

1/2/3

1/2

Rr, b

P, b

s, k

k

SBIS

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

k

Branch if Not Equal

k

Branch if Carry Set

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

k

Branch if Minus

k

Branch if Plus

k

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half-carry Flag Set

Branch if Half-carry Flag Cleared

Branch if T-flag Set

k

Branch if T-flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

k

BRID

k

59

1004D–09/01

Instruction Set Summary (Continued)

Mnemonic

Operands

Description

Operation

Flags

# Clocks

DATA TRANSFER INSTRUCTIONS

MOV

LDI

LD

Rd, Rr

Rd, K

Move between Registers

Load Immediate

Rd ← Rr

None

1

2

3

1

2

Rd ← K

Rd, X

Load Indirect

Rd ← (X)

LD

Rd, X+

Rd, -X

Rd, Y

Load Indirect and Post-inc.

Load Indirect and Pre-dec.

Load Indirect

Rd ← (X), X ← X + 1

X ← X − 1, Rd ← (X)

Rd ← (Y)

LD

Rd, Y+

Rd, -Y

Rd,Y+q

Rd, Z

Load Indirect and Post-inc.

Load Indirect and Pre-dec.

Load Indirect with Displacement

Load Indirect

Rd ← (Y), Y ← Y + 1

Y ← Y − 1, Rd ← (Y)

Rd ← (Y + q)

Rd ← (Z)

LD

LDD

LD

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-inc.

Load Indirect and Pre-dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Rd ← (Z), Z ← Z + 1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

Rd ← (k)

LD

LDD

LDS

ST

X, Rr

(X) ← Rr

ST

X+, Rr

-X, Rr

Y, Rr

Store Indirect and Post-inc.

Store Indirect and Pre-dec.

Store Indirect

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

ST

Y+, Rr

-Y, Rr

Y+q, Rr

Z, Rr

Store Indirect and Post-inc.

Store Indirect and Pre-dec.

Store Indirect with Displacement

Store Indirect

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

ST

STD

ST

(Z) ← Rr

ST

Z+, Rr

-Z, Rr

Z+q, Rr

k, Rr

Store Indirect and Post-inc.

Store Indirect and Pre-dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

In Port

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

ST

STD

STS

LPM

IN

(k) ← Rr

R0 ← (Z)

Rd, P

P, Rr

Rr

Rd ← P

OUT

PUSH

POP

Out Port

P ← Rr

Push Register on Stack

Pop Register from Stack

STACK ← Rr

Rd ← STACK

Rd

BIT AND BIT-TEST INSTRUCTIONS

SBI

P, b

Rd

s

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b) ← 1

None

2

1

CBI

I/O(P,b) ← 0

None

LSL

Rd(n+1) ← Rd(n), Rd(0) ← 0

Z,C,N,V

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Logical Shift Right

Rotate Left through Carry

Rotate Right through Carry

Arithmetic Shift Right

Swap Nibbles

Rd(n) ← Rd(n+1), Rd(7) ← 0

Z,C,N,V

Rd(0) ←=C, Rd(n+1) ← Rd(n), C ←=Rd(7)

Z,C,N,V

Rd(7) ←=C, Rd(n) ← Rd(n+1), C ←=Rd(0)

Z,C,N,V

Rd(n) ← Rd(n+1), n = 0..6

Z,C,N,V

Rd(3..0) ←=Rd(7..4), Rd(7..4) ←=Rd(3..0)

None

Flag Set

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

s

Flag Clear

SREG(s)

Rr, b

Rd, b

Bit Store from Register to T

Bit Load from T to Register

Set Carry

T

None

C

Clear Carry

C ← 0

C

Set Negative Flag

N ← 1

N

Clear Negative Flag

Set Zero Flag

N ← 0

N

Z ← 1

Z

Clear Zero Flag

Z ← 0

Z

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Two’s Complement Overflow

Clear Two’s Complement Overflow

Set T in SREG

I ← 1

I

CLI

I ← 0

I

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

NOP

SLEEP

WDR

S ← 1

S

S ← 0

S

V ← 1

V

V ← 0

V

T ← 1

T

Clear T in SREG

T ← 0

T

Set Half-carry Flag in SREG

Clear Half-carry Flag in SREG

No Operation

H ← 1

H

H ← 0

H

None

Sleep

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

Watchdog Reset

60

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

Ordering Information

Power Supply

Speed (MHz)

Ordering Code

Package

Operation Range

2.7 - 6.0V

4

10

1

AT90LS2323-4PC

AT90LS2323-4SC

8P3

8S2

Commercial

(0°C to 70°C)

AT90LS2323-4PI

AT90LS2323-4SI

8P3

8S2

Industrial

(-40°C to 85°C)

4.0 - 6.0V

2.7 - 6.0V

4.0 - 6.0V

AT90S2323-10PC

AT90S2323-10SC

8P3

8S2

Commercial

(0°C to 70°C)

AT90S2323-10PI

AT90S2323-10SI

8P3

8S2

Industrial

(-40°C to 85°C)

AT90LS2343-1PC

AT90LS2343-1SC

8P3

8S2

Commercial

(0°C to 70°C)

AT90LS2343-1PI

AT90LS2343-1SI

8P3

8S2

Industrial

(-40°C to 85°C)

4

AT90LS2343-4PC

AT90LS2343-4SC

8P3

8S2

Commercial

(0°C to 70°C)

AT90LS2343-4PI

AT90LS2343-4SI

8P3

8S2

Industrial

(-40°C to 85°C)

10

AT90S2343-10PC

AT90S2343-10SC

8P3

8S2

Commercial

(0°C to 70°C)

AT90S2343-10PI

AT90S2343-10SI

8P3

8S2

Industrial

(-40°C to 85°C)

Notes: 1. The speed grade refers to maximum clock rate when using an external crystal or external clock drive. The internal RC oscil-

lator has the same nominal clock frequency for all speed grades.

2. In AT90LS2343-1xx, the internal RC oscillator is selected as default MCU clock source (RCEN fuse is programmed) when

the device is shipped from Atmel. In AT90LS2343-4xx and AT90S2343-10xx, the default MCU clock source is the clock

input pin (RCEN fuse is unprogrammed). The fuse settings can be changed by high voltage serial programming.

Package Type

8P3

8S2

8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)

61

1004D–09/01

Packaging Information

8P3

8P3, 8-lead, Plastic Dual Inline

Package (PDIP), 0.300" Wide.

Dimensions in Millimeters and (Inches)*

JEDEC STANDARD MS-001 BA

10.16(0.400)

9.017(0.355)

1

7.11(0.280)

6.10(0.240)

.300 (7.62) REF

254(0.100) BSC

5.33(0.210) MAX

Seating Plane

4.95(0.195)

2.92(0.115)

3.81(0.150)

2.92(0.115)

0.381(0.015)MIN

0.559(0.022)

0.356(0.014)

1.78(0.070)

1.14(0.045)

8.26(0.325)

7.62(0.300)

0.356(0.014)

0.203(0.008)

1.524(0.060)

0.000(0.000)

10.90(0.430) MAX

*Controlling dimension: Inches

REV. A 04/11/2001

62

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

8S2

.020 (.508)

.012 (.305)

.213 (5.41) .330 (8.38)

.205 (5.21) .300 (7.62)

PIN 1

.050 (1.27) BSC

.212 (5.38)

.203 (5.16)

.080 (2.03)

.070 (1.78)

.013 (.330)

.004 (.102)

0

8

REF

.010 (.254)

.007 (.178)

.035 (.889)

.020 (.508)

63

1004D–09/01

Atmel Headquarters

Atmel Product Operations

Corporate Headquarters

2325 Orchard Parkway

San Jose, CA 95131

TEL (408) 441-0311

FAX (408) 487-2600

Atmel Colorado Springs

1150 E. Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TEL (719) 576-3300

FAX (719) 540-1759

Europe

Atmel Grenoble

Atmel SarL

Avenue de Rochepleine

BP 123

Route des Arsenaux 41

Casa Postale 80

CH-1705 Fribourg

Switzerland

38521 Saint-Egreve Cedex, France

TEL (33) 4-7658-3000

FAX (33) 4-7658-3480

TEL (41) 26-426-5555

FAX (41) 26-426-5500

Atmel Heilbronn

Theresienstrasse 2

POB 3535

Asia

Atmel Asia, Ltd.

Room 1219

D-74025 Heilbronn, Germany

TEL (49) 71 31 67 25 94

FAX (49) 71 31 67 24 23

Chinachem Golden Plaza

77 Mody Road Tsimhatsui

East Kowloon

Hong Kong

TEL (852) 2721-9778

FAX (852) 2722-1369

Atmel Nantes

La Chantrerie

BP 70602

44306 Nantes Cedex 3, France

TEL (33) 0 2 40 18 18 18

FAX (33) 0 2 40 18 19 60

Japan

Atmel Japan K.K.

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

Atmel Rousset

Zone Industrielle

13106 Rousset Cedex, France

TEL (33) 4-4253-6000

FAX (33) 4-4253-6001

TEL (81) 3-3523-3551

FAX (81) 3-3523-7581

Atmel Smart Card ICs

Scottish Enterprise Technology Park

East Kilbride, Scotland G75 0QR

TEL (44) 1355-357-000

FAX (44) 1355-242-743

e-mail

literature@atmel.com

Web Site

http://www.atmel.com

BBS

1-(408) 436-4309

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty

which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors

which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does

not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted

by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical

components in life support devices or systems.

ATMEL^®and AVR^®are the registered trademarks of Atmel.

Other terms and product names may be the trademarks of others.

Printed on recycled paper.

1004D–09/01/xM


型号：	AT90S2323-10SL
厂家：	MICROCHIP
描述：	RISC Microcontroller, 8-Bit, FLASH, 10MHz, CMOS, PDSO8, 0.200 INCH, EIAJ, PLASTIC, SOIC-8 微控制器光电二极管
文件：	总64页 (文件大小：1039K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT90S2323-10SL [MICROCHIP]

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