AT90S2313-SL_技术文档

Features

• AVR^®- High Performance and Low Power RISC Architecture

• 118 Powerful Instructions - Most Single Clock Cycle Execution

• 2K bytes of In-System Reprogrammable Flash

– SPI Serial Interface for Program Downloading

– Endurance: 1,000 Write/Erase Cycles

• 128 bytes EEPROM

– Endurance: 100,000 Write/Erase Cycles

• 128 bytes Internal RAM

• 32 x 8 General Purpose Working Registers

• 15 Programmable I/O Lines

• V_CC: 2.7 - 6.0V

8-Bit

• Fully Static Operation

Microcontroller

with 2K bytes

In-System

Programmable

Flash

– 0 - 10 MHz, 4.0 - 6.0V

– 0 - 4 MHz, 2.7 - 6.0V

• Up to 10 MIPS Throughput at 10 MHz

• One 8-Bit Timer/Counter with Separate Prescaler

• One 16-Bit Timer/Counter with Separate Prescaler

and Compare and Capture Modes

• Full Duplex UART

• Selectable 8, 9 or 10 bit PWM

• External and Internal Interrupt Sources

• Programmable Watchdog Timer with On-Chip Oscillator

• On-Chip Analog Comparator

• Low Power Idle and Power Down Modes

• Programming Lock for Software Security

• 20-Pin Device

AT90S2313

Description

The AT90S2313 is a low-power CMOS 8-bit microcontroller based on the AVR

enhanced RISC architecture. By executing powerful instructions in a single clock

cycle, the AT90S2313 achieves throughputs approaching 1 MIPS per MHz allowing

the system designer to optimize power consumption versus processing speed.

The AVR core combines a rich instruction set with 32 general purpose working regis-

ters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),

allowing two independent registers to be accessed in one single instruction executed

in one clock cycle. The resulting architecture is more code efficient while achieving

throughputs up to ten times faster than conventional CISC microcontrollers.

(continued)

Pin Configuration

Rev. 0839DS–07/98

Note: This is a summary document. For the complete 68 page

datasheet, please visit our web site at www.atmel.com or e-

_{mail at literature@atmel.com and request literature #0839D.}1

Block Diagram

Figure 1. The AT90S2313 Block Diagram

The AT90S2313 provides the following features: 2K bytes

of In-System Programmable Flash, 128 bytes EEPROM,

128 bytes SRAM, 15 general purpose I/O lines, 32 general

purpose working registers, flexible timer/counters with

compare modes, internal and external interrupts, a pro-

grammable serial UART, programmable Watchdog Timer

with internal oscillator, an SPI serial port for Flash Memory

downloading and two software selectable power saving

modes. The Idle Mode stops the CPU while allowing the

SRAM, timer/counters, SPI port and interrupt system to

continue functioning. The power down mode saves the reg-

ister contents but freezes the oscillator, disabling all other

chip functions until the next interrupt or hardware reset.

Programmable Flash allows the program memory to be

reprogrammed in-system through an SPI serial interface or

by a conventional nonvolatile memory programmer. By

combining an enhanced RISC 8-bit CPU with In-System

Programmable Flash on a monolithic chip, the Atmel

AT90S2313 is a powerful microcontroller that provides a

highly flexible and cost effective solution to many embed-

ded control applications.

The AT90S2313 AVR is supported with a full suite of pro-

gram and system development tools including: C compil-

ers, macro assemblers, program debugger/simulators, in-

circuit emulators, and evaluation kits.

The device is manufactured using Atmel’s high density

non-volatile memory technology. The on-chip In-System

AT90S2313

2

AT90S2313

Figure 2. Oscillator Connections

Pin Descriptions

VCC

Supply voltage pin.

GND

Ground pin.

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port. Port pins can pro-

vide internal pull-up resistors (selected for each bit). PB0

and PB1 also serve as the positive input (AIN0) and the

negative input (AIN1), respectively, of the on-chip analog

comparator. The Port B output buffers can sink 20mA and

can drive LED displays directly. When pins PB0 to PB7 are

used as inputs and are externally pulled low, they will

source current if the internal pull-up resistors are activated.

Port B also serves the functions of various special features

of the AT90S2313 as listed on page 38.

Figure 3. External Clock Drive Configuration

Port D (PD6..PD0)

Port D has seven bi-directional I/O pins with internal pull-up

resistors, PD6..PD0. The Port D output buffers can sink 20

mA. As inputs, Port D pins that are externally pulled low will

source current if the pull-up resistors are activated.

Port D also serves the functions of various special features

of the AT90S2313 as listed on page 43.

RESET

Reset input. A low on this pin for two machine cycles while

the oscillator is running resets the device.

XTAL1

Input to the inverting oscillator amplifier and input to the

internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier

Crystal Oscillator

XTAL1 and XTAL2 are input and output, respectively, of an

inverting amplifier which can be configured for use as an

on-chip oscillator, as shown in Figure 2. Either a quartz

crystal or a ceramic resonator may be used. To drive the

device from an external clock source, XTAL2 should be left

unconnected while XTAL1 is driven as shown in Figure 3.

3

AT90S2313 Architectural Overview

The fast-access register file concept contains 32 x 8-bit

general purpose working registers with a single clock cycle

access time. This means that during one single clock cycle,

one ALU (Arithmetic Logic Unit) operation is executed. Two

operands are output from the register file, the operation is

executed, and the result is stored back in the register file -

in one clock cycle.

can be accessed directly, or as the Data Space locations

following those of the register file, $20 - $5F.

The AVR has Harvard architecture - with separate memo-

ries and buses for program and data. The program memory

is accessed with a two stage pipeline. While one instruction

is being executed, the next instruction is pre-fetched from

the program memory. This concept enables instructions to

be executed in every clock cycle. The program memory is

In-system Programmable Flash memory.

Six of the 32 registers can be used as three 16-bits indirect

address register pointers for Data Space addressing -

enabling efficient address calculations. One of the three

address pointers is also used as the address pointer for the

constant table look up function. These added function reg-

isters are the 16-bits X-register, Y-register and Z-register.

With the relative jump and call instructions, the whole 1K

address space is directly accessed. Most AVR instructions

have a single 16-bit word format. Every program memory

address contains a 16- or 32-bit instruction.

The ALU supports arithmetic and logic functions between

registers or between a constant and a register. Single reg-

ister operations are also executed in the ALU. Figure 4

shows the AT90S2313 AVR Enhanced RISC microcontrol-

ler architecture.

During interrupts and subroutine calls, the return address

program counter (PC) is stored on the stack. The stack is

effectively allocated in the general data SRAM, and conse-

quently the stack size is only limited by the total SRAM size

and the usage of the SRAM. All user programs must initial-

ize the SP in the reset routine (before subroutines or inter-

rupts are executed). The 8-bit stack pointer SP is read/write

accessible in the I/O space.

In addition to the register operation, the conventional mem-

ory addressing modes can be used on the register file as

well. This is enabled by the fact that the register file is

assigned the 32 lowermost Data Space addresses ($00 -

$1F), allowing them to be accessed as though they were

ordinary memory locations.

The 128 bytes data SRAM + register file and I/O registers

can be easily accessed through the five different address-

ing modes supported in the AVR architecture.

The I/O memory space contains 64 addresses for CPU

peripheral functions as Control Registers, Timer/Counters,

A/D-converters, and other I/O functions. The I/O memory

The memory spaces in the AVR architecture are all linear

and regular memory maps.

AT90S2313

4

AT90S2313

Figure 4. The AT90S2313 AVR Enhanced RISC Architecture

Figure 5. Memory Maps

5

AT90S2313 Register Summary

Address

Name

SREG

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

$3F ($5F)

$3E ($5E)

$3D ($5D)

$3C ($5C)

$3B ($5B)

$3A ($5A)

$39 ($59)

$38 ($58)

$37 ($57)

$36 ($56)

$35 ($55)

$34 ($54)

$33 ($53)

$32 ($52)

$31 ($51)

$30 ($50)

$2F ($4F)

$2E ($4E)

$2D ($4D)

$2C ($4C)

$2B ($4B)

$2A ($4A)

$29 ($49)

$28 ($48)

$27 ($47)

$26 ($46)

$25 ($45)

$24 ($44)

$23 ($43)

$22 ($42)

$21 ($41)

$20 ($40)

$1F ($3F)

$1E ($3E)

$1D ($3D)

$1C ($3C)

$1B ($3B)

$1A ($3A)

$19 ($39)

$18 ($38)

$17 ($37)

$16 ($36)

$15 ($35)

$14 ($34)

$13 ($33)

$12 ($32)

$11 ($31)

$10 ($30)

$0F ($2F)

$0E ($2E)

$0D ($2D)

$0C ($2C)

$0B ($2B)

$0A ($2A)

$09 ($29)

$08 ($28)

…

I

T

H

S

V

N

Z

C

17

Reserved

SPL

Reserved

GIMSK

SP7

SP6

SP5

-

SP4

-

SP3

-

SP2

-

SP1

-

SP0

-

18

INT1

INTF1

TOIE1

TOV1

INT0

INTF0

OCIE1A

OCF1A

23

24

GIFR

TIMSK

TIFR

-

TICIE1

ICF1

-

TOIE0

TOV0

-

Reserved

MCUCR

Reserved

TCCR0

TCNT0

Reserved

TCCR1A

TCCR1B

TCNT1H

TCNT1L

OCR1AH

OCR1AL

Reserved

ICR1H

-

SE

-

SM

-

ISC11

-

ISC10

CS02

ISC01

CS01

ISC00

CS00

25

28

29

Timer/Counter0 (8 Bit)

COM1A1

ICNC1

COM1A0

ICES1

-

.

-

PWM11

CS11

PWM10

CS10

30

31

32

CTC1

CS12

Timer/Counter1 - Counter Register High Byte

Timer/Counter1 - Counter Register Low Byte

Timer/Counter1 - Compare Register High Byte

Timer/Counter1 - Compare Register Low Byte

Timer/Counter1 - Input Capture Register High Byte

Timer/Counter1 - Input Capture Register Low Byte

33

ICR1L

Reserved

WDTCR

Reserved

EEAR

-

WDTOE

WDE

WDP2

WDP1

EEWE

WDP0

EERE

35

EEPROM Address Register

36

37

EEDR

EEPROM Data register

EECR

-

EEMWE

Reserved

PORTB

DDRB

PORTB7

DDB7

PORTB6

DDB6

PORTB5

DDB5

PORTB4

DDB4

PORTB3

DDB3

PORTB2

DDB2

PORTB1

DDB1

PORTB0

DDB0

46

PINB

PINB7

PINB6

PINB5

PINB4

PINB3

PINB2

PINB1

PINB0

Reserved

PORTD

DDRD

-

PORTD6

DDD6

PORTD5

DDD5

PORTD4

DDD4

PORTD3

DDD3

PORTD2

DDD2

PORTD1

DDD1

PORTD0

DDD0

51

PIND

PIND6

PIND5

PIND4

PIND3

PIND2

PIND1

PIND0

Reserved

UDR

UART I/O Data Register

RXC

40

41

43

44

USR

TXC

UDRE

FE

OR

-

UCR

UBRR

ACSR

Reserved

RXCIE

UART Baud Rate Register

ACD

TXCIE

UDRIE

RXEN

TXEN

CHR9

RXB8

TXB8

-

ACO

ACI

ACIE

ACIC

ACIS1

ACIS0

$00 ($20)

AT90S2313

6

AT90S2313

AT90S2313 Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

Rd ← Rd + Rr

ADD

ADC

ADIW

SUB

SUBI

SBIW

SBC

SBCI

AND

ANDI

OR

Rd, Rr

Rdl,K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add two Registers

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,N,V

1

2

1

2

1

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd − Rr

Add with Carry two Registers

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract Immediate from Word

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd − K

Rdh:Rdl ← Rdh:Rdl − K

Rd ← Rd − Rr − C

Rd ← Rd − K − C

Rd ← Rd • Rr

Rd ← Rd • K

Rd ← Rd v Rr

Rd ← Rd v K

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Rd ← Rd Rr

Rd ← $FF − Rd

Rd ← $00 − Rd

Rd ← Rd v K

EOR

COM

NEG

SBR

CBR

INC

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

Set Bit(s) in Register

Clear Bit(s) in Register

Increment

Decrement

Test for Zero or Minus

Clear Register

Set Register

Rd,K

Rd

Rd ← Rd • ($FF − K)

Rd ← Rd + 1

Rd ← Rd − 1

DEC

TST

Z,N,V

Rd ← Rd • Rd

Rd ← Rd Rd

Rd ← $FF

CLR

SER

Rd

Z,N,V

None

BRANCH INSTRUCTIONS

PC ← PC + k + 1

PC ← Z

RJMP

IJMP

k

Relative Jump

Indirect Jump to (Z)

None

2

PC ← PC + k + 1

PC ← Z

RCALL

ICALL

RET

RETI

CPSE

CP

k

Relative Subroutine Call

Indirect Call to (Z)

Subroutine Return

Interrupt Return

Compare, Skip if Equal

Compare

None

3

None

I

3

4

1 / 2

1

PC ← STACK

if (Rd = Rr) PC ← PC + 2 or 3

Rd,Rr

None

Rd − Rr

Z, N,V,C,H

None

CPC

Compare with Carry

Rd − Rr − C

1

CPI

Rd,K

Rr, b

P, b

s, k

k

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Branch if Not Equal

Branch if Carry Set

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

Rd − K

1

if (Rr(b)=0) PC ← PC + 2 or 3

if (Rr(b)=1) PC ← PC + 2 or 3

if (P(b)=0) PC ← PC + 2 or 3

if (R(b)=1) PC ← PC + 2 or 3

SBRC

SBRS

SBIC

SBIS

1 / 2

None

if (SREG(s) = 1) then PC←PC + k + 1

if (SREG(s) = 0) then PC←PC + k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N V= 0) then PC ← PC + k + 1

if (N V= 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

if (I = 1) then PC ← PC + k + 1

if (I = 0) then PC ← PC + k + 1

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

BRID

None

k

Branch if Minus

Branch if Plus

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

Branch if T Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

k

7

Mnemonics

Operands

Description

Operation

Flags

#Clocks

DATA TRANSFER INSTRUCTIONS

MOV

LDI

LD

Rd, Rr

Rd, K

Move Between Registers

Load Immediate

Rd ← Rr

None

1

2

3

1

2

Rd ← K

Rd, X

Load Indirect

Rd ← (X)

Rd, X+

Rd, - X

Rd, Y

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

In Port

Rd ← (X), X ← X + 1

X ← X − 1, Rd ← (X)

Rd ← (Y)

Rd ← (Y), Y ← Y + 1

Y ← Y − 1, Rd ← (Y)

Rd ← (Y + q)

Rd ← (Z)

LDD

LD

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

Rd ← (k)

LD

LDD

LDS

ST

X, Rr

(X) ← Rr

X+, Rr

- X, Rr

Y, Rr

Y+, Rr

- Y, Rr

Y+q,Rr

Z, Rr

Z+, Rr

-Z, Rr

Z+q,Rr

k, Rr

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

STD

ST

(Z) ← Rr

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

ST

STD

STS

LPM

IN

OUT

PUSH

POP

(k) ← Rr

R0 ← (Z)

Rd, P

P, Rr

Rr

Rd ← P

Out Port

Push Register on Stack

Pop Register from Stack

P ← Rr

STACK ← Rr

Rd ← STACK

Rd

BIT AND BIT-TEST INSTRUCTIONS

SBI

CBI

LSL

P,b

Rd

s

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

Logical Shift Right

Rotate Left Through Carry

Rotate Right Through Carry

Arithmetic Shift Right

Swap Nibbles

Flag Set

Flag Clear

Bit Store from Register to T

Bit load from T to Register

Set Carry

I/O(P,b) ← 1

I/O(P,b) ← 0

Rd(n+1) ← Rd(n), Rd(0) ← 0

Rd(n) ← Rd(n+1), Rd(7) ← 0

Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

None

Z,C,N,V

2

1

3

1

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Rd(n) ← Rd(n+1), n=0..6

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

Z,C,N,V

None

SREG(s)

T

None

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

s

Rr, b

Rd, b

C

N

Z

Clear Carry

Set Negative Flag

Clear Negative Flag

Set Zero Flag

Clear Zero Flag

C ← 0

N ← 1

N ← 0

Z ← 1

Z ← 0

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow

Clear Twos Complement Overflow

Set T in SREG

I ← 1

I

S

V

CLI

I ← 0

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

NOP

SLEEP

WDR

S ← 1

S ← 0

V ← 1

V ← 0

T ← 1

T

H

None

Clear T in SREG

T ← 0

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

No Operation

H ← 1

H ← 0

Sleep

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

Watchdog Reset

AT90S2313

8


型号：	AT90S2313-SL
厂家：	ATMEL
描述：	RISC Microcontroller, 8-Bit, FLASH, 16MHz, CMOS, PDSO20, 0.300 INCH, PLASTIC, SOIC-20 闪存微控制器
文件：	总8页 (文件大小：390K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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