AT90S2313-4SL_技术文档

Features

• Utilizes the AVR^®RISC Architecture

• AVR – High-performance and Low-power RISC Architecture

– 118 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Up to 10 MIPS Throughput at 10 MHz

• Data and Non-volatile Program Memory

– 2K Bytes of In-System Programmable Flash

Endurance 1,000 Write/Erase Cycles

– 128 Bytes of SRAM

– 128 Bytes of In-System Programmable EEPROM

Endurance: 100,000 Write/Erase Cycles

– Programming Lock for Flash Program and EEPROM Data Security

• Peripheral Features

8-bit

Microcontroller

with 2K Bytes

of In-System

Programmable

Flash

– One 8-bit Timer/Counter with Separate Prescaler

– One 16-bit Timer/Counter with Separate Prescaler,

Compare, Capture Modes and 8-, 9-, or 10-bit PWM

– On-chip Analog Comparator

– Programmable Watchdog Timer with On-chip Oscillator

– SPI Serial Interface for In-System Programming

– Full Duplex UART

• • Special Microcontroller Features

– Low-power Idle and Power-down Modes

– External and Internal Interrupt Sources

• • Specifications

– Low-power, High-speed CMOS Process Technology

– Fully Static Operation

• Power Consumption at 4 MHz, 3V, 25°C

– Active: 2.8 mA

AT90S2313

– Idle Mode: 0.8 mA

– Power-down Mode: <1 µA

• I/O and Packages

– 15 Programmable I/O Lines

– 20-pin PDIP and SOIC

• Operating Voltages

– 2.7 - 6.0V (AT90S2313-4)

– 4.0 - 6.0V (AT90S2313-10)

• Speed Grades

– 0 - 4 MHz (AT90S2313-4)

– 0 - 10 MHz (AT90S2313-10)

Pin Configuration

PDIP/SOIC

Rev. 0839IS–AVR–06/02

Note: This is a summary document. A complete document is

available on our web site at www.atmel.com.

1

Description

The AT90S2313 is a low-power CMOS 8-bit microcontroller based on the AVR RISC

architecture. By executing powerful instructions in a single clock cycle, the AT90S2313

achieves throughputs approaching 1 MIPS per MHz allowing the system designer to

optimize power consumption versus processing speed.

The AVR core combines a rich instruction set with 32 general purpose working registers.

All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing

two independent registers to be accessed in one single instruction executed in one clock

cycle. The resulting architecture is more code efficient while achieving throughputs up to

ten times faster than conventional CISC microcontrollers.

Figure 1. The AT90S2313 Block Diagram

The AT90S2313 provides the following features: 2K bytes of In-System Programmable

Flash, 128 bytes EEPROM, 128 bytes SRAM, 15 general purpose I/O lines, 32 general

purpose working registers, flexible Timer/Counters with compare modes, internal and

external interrupts, a programmable serial UART, programmable Watchdog Timer with

internal Oscillator, an SPI serial port for Flash memory downloading and two software

2

AT90S2313

0839IS–AVR–06/02

AT90S2313

selectable power-saving modes. The Idle mode stops the CPU while allowing the

SRAM, Timer/Counters, SPI port and interrupt system to continue functioning. The

Power-down mode saves the register contents but freezes the Oscillator, disabling all

other chip functions until the next external interrupt or Hardware Reset.

The device is manufactured using Atmel’s high-density non-volatile memory technology.

The On-chip In-System Programmable Flash allows the Program memory to be repro-

grammed in-system through an SPI serial interface or by a conventional non-volatile

memory programmer. By combining an enhanced RISC 8-bit CPU with In-System Pro-

grammable Flash on a monolithic chip, the Atmel AT90S2313 is a powerful

microcontroller that provides a highly flexible and cost-effective solution to many embed-

ded control applications.

The AT90S2313 AVR is supported with a full suite of program and system development

tools including: C compilers, macro assemblers, program debugger/simulators, In-Cir-

cuit Emulators and evaluation kits.

Pin Descriptions

VCC

Supply voltage pin.

Ground pin.

GND

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors

(selected for each bit). PB0 and PB1 also serve as the positive input (AIN0) and the

negative input (AIN1), respectively, of the On-chip Analog Comparator. The Port B out-

put buffers can sink 20 mA and can drive LED displays directly. When pins PB0 to PB7

are used as inputs and are externally pulled low, they will source current if the internal

pull-up resistors are activated. The Port B pins are tri-stated when a reset condition

becomes active, even if the clock is not active.

Port B also serves the functions of various special features of the AT90S2313 as listed

on page 51.

Port D (PD6..PD0)

Port D has seven bi-directional I/O ports with internal pull-up resistors, PD6..PD0. The

Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled

low will source current if the pull-up resistors are activated. The Port D pins are tri-stated

when a reset condition becomes active, even if the clock is not active.

Port D also serves the functions of various special features of the AT90S2313 as listed

on page 56.

RESET

Reset input. A low level on this pin for more than 50 ns will generate a Reset, even if the

clock is not running. Shorter pulses are not guaranteed to generate a Reset.

XTAL1

XTAL2

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting Oscillator amplifier.

3

0839IS–AVR–06/02

Register Summary

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

$3F ($5F)

$3E ($5E)

$3D ($5D)

$3C ($5C)

$3B ($5B)

$3A ($5A)

$39 ($59)

$38 ($58)

$37 ($57)

$36 ($56)

$35 ($55)

$34 ($54)

$33 ($53)

$32 ($52)

$31 ($51)

$30 ($50)

$2F ($4F)

$2E ($4E)

$2D ($4D)

$2C ($4C)

$2B ($4B)

$2A ($4A)

$29 ($49)

$28 ($48)

$27 ($47)

$26 ($46)

$25 ($45)

$24 ($44)

$23 ($43)

$22 ($42)

$21 ($41)

$20 ($40)

$1F ($3F)

$1E ($3E)

$1D ($3D)

$1C ($3C)

$1B ($3B)

$1A ($3A)

$19 ($39)

$18 ($38)

$17 ($37)

$16 ($36)

$15 ($35)

$14 ($34)

$13 ($33)

$12 ($32)

$11 ($31)

$10 ($30)

...

SREG

Reserved

SPL

I

T

H

S

V

N

Z

C

page 16

SP7

SP6

SP5

–

SP4

–

SP3

–

SP2

–

SP1

–

SP0

–

page 17

Reserved

GIMSK

INT1

INTF1

TOIE1

TOV1

INT0

INTF0

page 22

page 23

page 24

GIFR

TIMSK

OCIE1A

OCF1A

–

TICIE1

ICF1

–

TOIE0

TOV0

–

TIFR

Reserved

MCUCR

Reserved

TCCR0

TCNT0

–

SE

–

SM

–

ISC11

–

ISC10

CS02

ISC01

CS01

ISC00

CS00

page 25

page 29

Timer/Counter0 (8 Bits)

Reserved

TCCR1A

TCCR1B

TCNT1H

TCNT1L

OCR1AH

OCR1AL

Reserved

ICR1H

COM1A1

ICNC1

COM1A0

ICES1

–

.

–

PWM11

CS11

PWM10

CS10

page 31

page 32

page 33

page 34

CTC1

CS12

Timer/Counter1 – Counter Register High Byte

Timer/Counter1 – Counter Register Low Byte

Timer/Counter1 – Compare Register High Byte

Timer/Counter1 – Compare Register Low Byte

Timer/Counter1 – Input Capture Register High Byte

Timer/Counter1 – Input Capture Register Low Byte

page 34

ICR1L

Reserved

WDTCR

Reserved

EEAR

–

WDTOE

WDE

WDP2

WDP1

EEWE

WDP0

EERE

page 37

–

EEPROM Address Register

EEPROM Data Register

page 39

page 40

EEDR

EECR

–

EEMWE

Reserved

PORTB

DDRB

PORTB7

DDB7

PORTB6

DDB6

PORTB5

DDB5

PORTB4

DDB4

PORTB3

DDB3

PORTB2

DDB2

PORTB1

DDB1

PORTB0

DDB0

page 50

PINB

PINB7

PINB6

PINB5

PINB4

PINB3

PINB2

PINB1

PINB0

Reserved

PORTD

DDRD

–

PORTD6

DDD6

PORTD5

DDD5

PORTD4

DDD4

PORTD3

DDD3

PORTD2

DDD2

PORTD1

DDD1

PORTD0

DDD0

page 56

PIND

PIND6

PIND5

PIND4

PIND3

PIND2

PIND1

PIND0

Reserved

UDR

$0C ($2C)

$0B ($2B)

$0A ($2A)

$09 ($29)

$08 ($28)

…

UART I/O Data Register

page 45

page 46

page 48

USR

RXC

TXC

UDRE

FE

OR

–

UCR

RXCIE

TXCIE

UDRIE

RXEN

TXEN

CHR9

RXB8

TXB8

UBRR

UART Baud Rate Register

ACI ACIE

ACSR

ACD

–

ACO

ACIC

ACIS1

ACIS0

Reserved

$00 ($20)

Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. Some of the Status Flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instructions will operate on

all bits in the I/O Register, writing a “1” back into any flag read as set, thus clearing the flag. The CBI and SBI instructions

work with registers $00 to $1F only.

4

AT90S2313

0839IS–AVR–06/02

AT90S2313

Instruction Set Summary

Mnemonic

Operands

Description

Operation

Flags

# Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

Rd, Rr

Rdl, K

Rd, Rr

Rd, K

Rdl, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add Two Registers

Rd ← Rd + Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,N,V

1

2

1

2

1

ADC

Add with Carry Two Registers

Add Immediate to Word

Subtract Two Registers

Subtract Constant from Register

Subtract Immediate from Word

Subtract with Carry Two Registers

Subtract with Carry Constant from Reg.

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd − Rr

ADIW

SUB

SUBI

SBIW

SBC

Rd ← Rd − K

Rdh:Rdl ← Rdh:Rdl − K

Rd ← Rd − Rr − C

Rd ← Rd − K − C

Rd ← Rd • Rr

SBCI

AND

ANDI

OR

Rd ← Rd • K

Z,N,V

Rd ← Rd v Rr

Z,N,V

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Rd ← Rd v K

Z,N,V

EOR

Rd ← Rd ⊕ Rr

Rd ← $FF − Rd

Rd ← $00 − Rd

Rd ← Rd v K

Z,N,V

COM

NEG

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

SBR

Rd, K

Rd

Set Bit(s) in Register

CBR

Clear Bit(s) in Register

Increment

Rd ← Rd • ($FF − K)

Rd ← Rd + 1

Z,N,V

INC

Z,N,V

DEC

Rd

Decrement

Rd ← Rd − 1

Z,N,V

TST

Rd

Test for Zero or Minus

Clear Register

Rd ← Rd • Rd

Rd ← Rd ⊕ Rd

Rd ← $FF

Z,N,V

CLR

Rd

Z,N,V

SER

Rd

Set Register

None

BRANCH INSTRUCTIONS

RJMP

IJMP

k

Relative Jump

PC ← PC + k + 1

None

I

2

Indirect Jump to (Z)

PC ← Z

2

RCALL

ICALL

RET

Relative Subroutine Call

Indirect Call to (Z)

PC ← PC + k + 1

3

PC ← Z

3

Subroutine Return

PC ← STACK

4

RETI

Interrupt Return

PC ← STACK

4

CPSE

CP

Rd, Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC ← PC + 2 or 3

Rd − Rr

None

Z,N,V,C,H

None

1/2

1

Rd, Rr

CPC

Rd, Rr

Compare with Carry

Rd − Rr − C

1

CPI

Rd, K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd − K

1

SBRC

SBRS

SBIC

SBIS

Rr, b

if (Rr(b) = 0) PC ← PC + 2 or 3

if (Rr(b) = 1) PC ← PC + 2 or 3

if (P(b) = 0) PC ← PC + 2 or 3

if (R(b) = 1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC ← PC + k + 1

if (SREG(s) = 0) then PC ← PC + k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V = 0) then PC ← PC + k + 1

if (N ⊕ V = 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

if (I = 1) then PC ← PC + k + 1

if (I = 0) then PC ← PC + k + 1

1/2

Rr, b

P, b

s, k

k

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

BRID

k

Branch if Not Equal

k

Branch if Carry Set

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

k

Branch if Minus

k

Branch if Plus

k

Branch if Greater or Equal, Signed

Branch if Less than Zero, Signed

Branch if Half-carry Flag Set

Branch if Half-carry Flag Cleared

Branch if T-Flag Set

k

Branch if T-Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

k

5

0839IS–AVR–06/02

Instruction Set Summary (Continued)

Mnemonic

Operands

Description

Operation

Flags

# Clocks

DATA TRANSFER INSTRUCTIONS

MOV

LDI

LD

Rd, Rr

Rd, K

Move between Registers

Load Immediate

Rd ← Rr

None

1

2

3

1

2

Rd ← K

Rd, X

Load Indirect

Rd ← (X)

LD

Rd, X+

Rd, -X

Rd, Y

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Rd ← (X), X ← X + 1

X ← X − 1, Rd ← (X)

Rd ← (Y)

LD

Rd, Y+

Rd, -Y

Rd, Y+q

Rd, Z

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Rd ← (Y), Y ← Y + 1

Y ← Y − 1, Rd ← (Y)

Rd ← (Y + q)

Rd ← (Z)

LD

LDD

LD

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

Rd ← (k)

LD

LDD

LDS

ST

X, Rr

(X) ← Rr

ST

X+, Rr

-X, Rr

Y, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

ST

Y+, Rr

-Y, Rr

Y+q, Rr

Z, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

ST

STD

ST

(Z) ← Rr

ST

Z+, Rr

-Z, Rr

Z+q, Rr

k, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

In Port

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

ST

STD

STS

LPM

IN

(k) ← Rr

R0 ← (Z)

Rd, P

P, Rr

Rr

Rd ← P

OUT

PUSH

POP

Out Port

P ← Rr

Push Register on Stack

Pop Register from Stack

STACK ← Rr

Rd ← STACK

Rd

BIT AND BIT-TEST INSTRUCTIONS

SBI

P, b

Rd

s

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b) ← 1

None

2

1

CBI

I/O(P,b) ← 0

None

LSL

Rd(n+1) ← Rd(n), Rd(0) ← 0

Z,C,N,V

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

Logical Shift Right

Rotate Left through Carry

Rotate Right through Carry

Arithmetic Shift Right

Swap Nibbles

Rd(n) ← Rd(n+1), Rd(7) ← 0

Z,C,N,V

Rd(0) ← C, Rd(n+1) ← Rd(n), C ← Rd(7)

Z,C,N,V

Rd(7) ← C, Rd(n) ← Rd(n+1), C ← Rd(0)

Z,C,N,V

Rd(n) ← Rd(n+1), n = 0..6

Z,C,N,V

Rd(3..0) ← Rd(7..4), Rd(7..4) ← Rd(3..0)

None

Flag Set

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

s

Flag Clear

SREG(s)

Rr, b

Rd, b

Bit Store from Register to T

Bit Load from T to Register

Set Carry

T

None

C

Clear Carry

C ← 0

C

Set Negative Flag

N ← 1

N

Clear Negative Flag

Set Zero Flag

N ← 0

N

Z ← 1

Z

Clear Zero Flag

Z ← 0

Z

SEI

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Two’s Complement Overflow

Clear Two’s Complement Overflow

Set T in SREG

I ← 1

I

CLI

I ← 0

I

SES

CLS

SEV

CLV

SET

CLT

S ← 1

S

S ← 0

S

V ← 1

V

V ← 0

V

T ← 1

T

Clear T in SREG

T ← 0

T

SEH

CLH

NOP

SLEEP

WDR

Set Half-carry Flag in SREG

Clear Half-carry Flag in SREG

No Operation

H ← 1

H

H ← 0

H

None

Sleep

(see specific descr. for Sleep function)

(see specific descr. for WDR/Timer)

Watchdog Reset

6

AT90S2313

0839IS–AVR–06/02

AT90S2313

Ordering Information

Speed (MHz)

Power Supply

Ordering Code

Package

Operation Range

4

2.7 - 6.0V

AT90S2313-4PC

AT90S2313-4SC

20P3

20S

Commercial

(0°C to 70°C)

AT90S2313-4PI

AT90S2313-4SI

20P3

20S

Industrial

(-40°C to 85°C)

10

4.0 - 6.0V

AT90S2313-10PC

AT90S2313-10SC

20P3

20S

Commercial

(0°C to 70°C)

AT90S2313-10PI

AT90S2313-10SI

20P3

20S

Industrial

(-40°C to 85°C)

Package Type

20P3

20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)

20S

7

0839IS–AVR–06/02

Packaging Information

20P3

D

1

E1

A

SEATING PLANE

A1

L

B

B1

e

E

COMMON DIMENSIONS

(Unit of Measure = mm)

C

MIN

–

MAX

5.334

–

NOM

NOTE

SYMBOL

eC

A

–

eB

A1

D

0.381

25.984

7.620

6.096

0.356

1.270

2.921

0.203

–

25.493 Note 2

8.255

E

E1

B

7.112 Note 2

0.559

B1

L

1.551

Notes:

1. This package conforms to JEDEC reference MS-001, Variation AD.

2. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

3.810

C

0.356

eB

eC

e

10.922

0.000

1.524

2.540 TYP

09/28/01

DRAWING NO. REV.

20P3

TITLE

2325 Orchard Parkway

San Jose, CA 95131

20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual

Inline Package (PDIP)

B

R

8

AT90S2313

0839IS–AVR–06/02

AT90S2313

20S

20S, 20-lead, Plastic Gull Wing Small

Outline (SOIC), 0.300" body.

Dimensions in Millineters and (Inches)*

JEDEC STANDARD MS-013

0.51(0.020)

0.33(0.013)

10.65 (0.419)

7.60 (0.2992)

7.40 (0.2914)

10.00 (0.394)

PIN 1 ID

PIN 1

1.27 (0.050) BSC

13.00 (0.5118)

12.60 (0.4961)

2.65 (0.1043)

2.35 (0.0926)

0.30(0.0118)

0.10 (0.0040)

0.32 (0.0125)

0.23 (0.0091)

0º ~ 8º

1.27 (0.050)

0.40 (0.016)

*Controlling dimension: Inches

REV. A 04/11/2001

9

0839IS–AVR–06/02

Atmel Headquarters

Atmel Operations

Corporate Headquarters

2325 Orchard Parkway

San Jose, CA 95131

TEL 1(408) 441-0311

FAX 1(408) 487-2600

Memory

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Theresienstrasse 2

Postfach 3535

74025 Heilbronn, Germany

TEL (49) 71-31-67-0

FAX (49) 71-31-67-2340

2325 Orchard Parkway

San Jose, CA 95131

TEL 1(408) 441-0311

FAX 1(408) 436-4314

Europe

Atmel Sarl

Route des Arsenaux 41

Case Postale 80

CH-1705 Fribourg

Switzerland

Microcontrollers

2325 Orchard Parkway

San Jose, CA 95131

TEL 1(408) 441-0311

FAX 1(408) 436-4314

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TEL 1(719) 576-3300

FAX 1(719) 540-1759

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BP 70602

44306 Nantes Cedex 3, France

TEL (33) 2-40-18-18-18

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Asia

Room 1219

Chinachem Golden Plaza

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East Kowloon

BP 123

38521 Saint-Egreve Cedex, France

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FAX (33) 4-76-58-34-80

ASIC/ASSP/Smart Cards

Zone Industrielle

Hong Kong

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13106 Rousset Cedex, France

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FAX (33) 4-42-53-60-01

Japan

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Colorado Springs, CO 80906

TEL 1(719) 576-3300

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

FAX 1(719) 540-1759

TEL (81) 3-3523-3551

FAX (81) 3-3523-7581

Scottish Enterprise Technology Park

Maxwell Building

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TEL (44) 1355-803-000

FAX (44) 1355-242-743

e-mail

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Web Site

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Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty

which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors

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Printed on recycled paper.

0839IS–AVR–06/02 0M


型号：	AT90S2313-4SL
厂家：	ATMEL
描述：	RISC Microcontroller, 8-Bit, FLASH, 4MHz, CMOS, PDSO20, 0.300 INCH, PLASTIC, MS-013, SOIC-20 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟微控制器静态存储器光电二极管外围集成电路
文件：	总10页 (文件大小：216K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT90S2313-4SL [ATMEL]

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