AT73C240_技术文档

Features

• Stereo Audio DAC

– 2.7V to 3.3V Analog Supply Operation

– 2.4V to 3.3V Digital Supply Operation

– 20-bit Stereo Audio DAC

– 90 dB SNR Playback Stereo Channels

– 32 Ohm/20 mW Stereo Headset Drivers with Master Volume and Mute Controls

– Stereo Line Level Input with Volume Control/Mute and Playback through the

Headset Drivers

Power

– Accepts Mixed Signals from All Signal Paths (Line Inputs and DAC Output)

– 8, 11.024, 16, 22.05, 24, 32, 44.1 and 48 kHz Sampling Rates

– 256x or 384xFs Master Clock Frequency

– I2S Serial Audio Interface

Management

and Analog

Companions

(PMAAC)

• Mono Audio Power Amplifier

– Supply Input from Main Li-Ion Battery (3V to 5.5V)

– 440 mW on 8 Ohm Load

– Programmable Volume Control (-22 to +20 dB)

– Fully Differential Structure, Input and Output

– 8 mA Drain Current in Active Mode

– Power-down Mode (Consumption Less than 2 µA)

– Minimum External Components (Direct Connection to the Loudspeaker)

• Applications: Mobile Phones, Digital Cameras, PDAs, SmartPhones, DECT Phones,

Music Players

AT73C240

Audio Interface

for Portable

Handsets

1. Description

The AT73C240 is a fully integrated, low-cost, combined stereo audio DAC and audio

power amplifier circuit targeted for Li-Ion or Ni-Mh battery powered devices such as

mobile phones, smartphones, PDA, DECT phones, digital still cameras, music players

or any other type of handheld device where an audio interface is needed.

The stereo DAC section is a complete high performance, stereo, audio digital-to-ana-

log converter delivering a 90 dB dynamic range. It comprises a multibit sigma-delta

modulator with dither, continuous time analog filters and analog output drive circuitry.

This architecture provides a high insensitivity to clock jitter. The digital interpolation fil-

ter increases the sample rate by a factor of 8 using 3 linear phase half-band filters

cascaded, followed by a first order SINC interpolator with a factor of 8. This filter elim-

inates the images of baseband audio, retaining only the image at 64x the input sample

rate, which is eliminated by the analog post filter. Optionally, a dither signal can be

added that reduces possible noise tones at the output. However, the use of a multibit

sigma-delta modulator already provides extremely low noise tone energy.

Master clock is 256 or 384 times the input data rate, allowing choice of input data rate

up to 48 kHz, including standard audio rates of 48, 44.1, 32, 16 and 8 kHz.

The DAC section is followed by a volume and mute control and can be simultaneously

played back directly through a stereo 32 Ohm headset pair of drivers.

The stereo 32 Ohm headset pair of drivers also includes a mixer of a LINEL and

LINER pair of stereo inputs.

6464A–PMAAC–28-Apr-09

High quality mono output is provided. The DAC output can be connected through a buffer stage

to the input of the audio power amplifier, using 2x coupling capacitors The mono buffer stage

also includes a mixer of the LINEL and LINER inputs which can be, for example, the output of a

voice Codec output driver in mobile phones.

The Audio Power Amplifier is a differential amplifier designed in CMOS technology. It is capa-

ble of driving an 8 Ohm Loudspeaker at maximum power of 440mW, making it suitable as a

hands-free speaker driver in a Wireless Handset Application.

The volume, mute, power down, de-emphasis controls and 16-bit, 18-bit and 20-bit audio for-

mats are digitally programmable via a 4-wire SPI bus or via a 2-wire TWI bus and the digital

audio data are provided through a multi-format I2S interface.

2. Block Diagram

Figure 2-1. AT73C240 Functional Block Diagram

AT73C240

VDIG

AVDD

Voltage

Reference

AVDDHS

-36 to +12dB / 3dB step

SPI_DOUT

LINER

PGA

SPI_DIN / TWD

Status

INGND

SPI

Registers

SPI_CLK / TWCK

SPI_CSB / TW_ADD

-36 to +12dB / 3dB step

LINEL

PGA

-46.5dB to 0dB / 1.5dB step -34.5dB to +12dB / 1.5dB step

MCLK

-6 to +6dB / 3dB step

RSTB

SMODE

SDIN

Volume

+

32

driver

HSL

+

Digital Filter

DAC

Control

VCM

-6 to +6dB / 3dB step

Volume

Control

32

driver

HSR

Volume

Control

LRFS

Digital Filter

+

DAC

BCLK

GNDA

-46.5dB to 0dB / 1.5dB step -34.5dB to +12dB / 1.5dB step

MONOP

GNDD

+

MONO

MONON

2

AT73C240

6464A–PMAAC–28-Apr-09

AT73C240

3. Pin Description

Table 3-1.

Pin Name

VREF

Pin Description

I/O

Type

Analog

Supply

Analog

Supply

Analog

N/A

Function

I

1

Voltage reference pin for decoupling

Analog supply (DAC + Line in + Mono out)

Left channel headset driver output

Right channel headset driver output

Headset driver analog supply

Left channel line in

AVDD

I

2

HSL

O

3

HSR

O

4

AVDDHS

LINEL

LINER

INGND

VCM

I

5

I

6

I

7

Right channel line in

I

8

Line signal ground pin for decoupling

Common mode reference for decoupling

Not Connected

I

9

10

NC

N/A

HPN

O

11

Analog

Supply

Analog

Digital

Ground

Supply

Digital

Analog

N/A

Negative speaker output

VBAT

I

12

Audio amplifier supply

HPP

O

13

Positive speaker output

CBP

O

14

Audio amplifier common mode voltage decoupling

Audio amplifier negative input

Audio amplifier positive input

Audio interface serial data input

Audio interface bit clock

PAINN

PAINP

SDIN

I

15

I

16

I

17

BCLK

I

18

LRFS

I

19

Audio interface left/right channel synchronization frame pulse

Audio interface master clock input

Master reset (active low)

MCLK

RSTB

I

20

I

21

SMODE

GNDD

VDIG

I

GND

I

22

Serial interface selection (to connect to ground)

Digital ground

23

24

Digital supply

SPI_DOUT

SPI_DIN/TWD

O

25

SPI data output

I/O

26

SPI data input / TWI data input

SPI clock / TWI clock

SPI_CLK/TWCK

SPI_CSB/TW_ADD

MONON

MONOP

I

27

28

SPI chip select / TWI address bit

Negative monaural driver output

Positive monaural driver output

Not Connected

O

29

O

30

NC

N/A

GND

31

NC

32

N/A

Not Connected

GNDA

33 (Bottom)

Ground

Analog ground

3

6464A–PMAAC–28-Apr-09

4. Electrical Characteristics

Table 4-1.

Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only and functional operation of

the device at these or other conditions beyond those

indicated in the operational sections of this specification

is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reli-

ability.

Operating Temperature (Industrial)..............-40°C to +85° C

Storage Temperature-...................................55°C to +150°C

Power Supply Input

on VBAT-...........................................................0.3V to +5.5V

on VDIG, AVDD, AVDDHS-...............................0.3V to +3.6V

5. Digital IOs

All the digital IOs: SDIN, BCLK, LRFS, MCLK, RSTB, SMODE, SPI_DOUT, SPI_DIN/TWD, SPI_CLK/TWCK,

SPI_CSB/TW_ADD are referred to as VDIG.

Table 5-1.

Symbol

VIL

Digital IOs

Parameter

Conditions

VDIG

Min

-0.3

Max

0.2 x VDIG

VDIG + 0.3

0.4

Unit

V

Low level input voltage

High level input voltage

Low level output voltage

High level output voltage

Guaranteed input low Voltage

from 2.4Vto 3.3 V

VIH

Guaranteed input high Voltage from 2.4Vto 3.3 V

0.8 x VDIG

V

VOL

IOL = 2 mA

IOH = 2 mA

from 2.4Vto 3.3 V

V

VOH

VDIG - 0.5V

V

4

AT73C240

6464A–PMAAC–28-Apr-09

AT73C240

6. Audio Power Amplifier

6.1

Electrical Specifications

VBAT = 3.6V, T_A= 25°C unless otherwise noted. 100 nF capacitor connected between CBP and GNDA, 470nF input

capacitors, load = 8 Ohms.

Table 6-1.

Symbol

V_DD

Audio Power Amplifier Electrical Specifications (General Conditions: V_DD= 3.6V,T_A= 25°C)

Parameter

Conditions

Min

Typ

3.6

6

Max

5.5

12

Unit

V

Supply voltage

Quiescent current

Standby current

DC reference

3

I_DD

Inputs shorted, no load

mA

µA

V

I_DDstby

V_Cbp

2

VDD/2

0

VOS

Output differential offset

Full gain, capacitive input coupling

Active state, maximum gain

Active state, minimum gain

-20

10K

100K

6

20

20k

200k

32

mV

15k

150k

8

Z_IN

Input impedance

Ohms

Z_LFP

C_L

Output load

Ohms

pF

Capacitive load

Between each output and the ground

200 to 2 kHz differential output

100

PSRR

Power supply rejection ratio

60

25

dB

1 kHz reference frequency

3 dB attenuation

F_CL

Low Frequency Cutoff

High Frequency Cutoff

40

Hz

Maximum gain

1 KHz reference frequency

3 dB attenuation

F_CH

20

kHz

Maximum gain

Off to on mode

t_UP

Output setup time

Output noise

Voltage already settled

Input capacitors precharged

10

500

50

ms

µV_RMS

dB

V_N

Max gain, A weighted

120

440

1 kHz

THD

Output distortion

Pout = 3mW to 300mW

gain = 2dB

1 KHz

P_max

Maximum power

mW

load 8 ohms

G_ACC

Overall Gain accuracy

Gain Step Accuracy

-2

0

2

dB

G_STEP

-0.7

0.7

5

6464A–PMAAC–28-Apr-09

7. Audio DAC

7.1

Electrical Specifications

AVDD, AVDDHS = 2.7 V, T_A= 25°C, typical case, unless otherwise noted.

All noise and distortion specifications are measured in the 20 Hz to 0.425xFs range and A-weighted filtered.

Full-scale levels scale proportionally with the AVDD / AVDDHS supply voltage.

Table 7-1.

Electrical Specifications

Min

Typ

Max

Units

Overall

Operating Temperature (ambient)

Analog Supply Voltage (AVDD, AVDDHS)

Digital Supply Voltage (VDIG)

DIGITAL INPUTS/OUTPUTS

Resolution

-40

2.7

2.4

+25

2.8

+85

3.3

°C

V

20

bits

Logic Family

CMOS

Logic Coding

2's Complement

Analog Performance - DAC to Line-out/Headphone Output

6.20

1.75

mVrms

Vpp

Output level for full scale input (for AVDD, AVDDHS = 2.8 V)

Output common mode voltage

0.5 x

AVDDHS

V

Output load resistance (on HSL, HSR)

Headphone load

16

32

10

Ohms

Line load

kOhms

Output load capacitance (on HSL, HSR)

Headphone load

30

1000

150

pF

Line load

Signal to Noise Ratio (-1dBFS @ 1kHz input and 0dB Gain)

Line and Headphone loads, A-Weighted

90

dB

Total Harmonic Distortion (-1dBFS @ 1kHz input and 0dB Gain)

Line Load

-80

-65

-40

dB

-75

Headphone Load

Headphone Load (16 Ohm)

Dynamic Range (measured with -60 dBFS @ 1kHz input, extrapolated to

full-scale), A Weighted

Line Load

90

80

dB

Headphone Load

Interchannel mismatch

0.1

-65

1

5

dB

Left-channel to right-channel crosstalk (300 Hz to 20kHz)

Output Headset Driver Level Control Range

Output Headset Driver Level Control Step

Maximum output power, headphone 32 Ohms load, 1% THD

-5

dB

2.5

15

dB

mVrms

6

AT73C240

6464A–PMAAC–28-Apr-09

AT73C240

Table 7-1.

Electrical Specifications (Continued)

Min

Typ

Max

Units

Maximum output slope at power up (100 to 220 µF coupling capacitor)

3

V/s

Analog Performance - Line-in/Microphone Input to Line-out/Headphone Output

Output level

@ AVDD, AVDDHS = 2.7 V and 0 dB gain, 500mV Rms

input level, 2 X 10k Ohms loads (HSL, HSR)

@ AVDD, AVDDHS = 2.7 V and 20 dB gain, 500mV Rms

input level, 2 X 32 Ohms loads (HSL, HSR)

1.62

570

1.58

560

Vpp

mVrms

Vpp

mVrms

Input common mode voltage

0.5 x AVDD

10

V

Input impedance

7

kOhm

Signal to Noise Ratio

500mV Rms @ 1kHz input and 0 dB gain

50mV Rms @ 1kHz input and 20 dB gain

80

85

70

dB

Dynamic Range (extrapolated to nominal 500mV level)

-60 dBr (500 mVrms)@ 1kHz input and 0 dB gain (10k Ohms load)

-60 dBr 50 mVrms) @ 1kHz input and 20 dB gain (10k Ohms load)

85

dB

Total Harmonic Distortion, A-Weighted, line 10k Ohms load

500mV Rms @ 1kHz input and 0 dB gain

-85

-78

-80

-70

dB

50mV Rms @ 1kHz input and 20 dB gain

Total Harmonic Distortion, A-Weighted, line 32 Ohms load

500mV Rms @ 1kHz input and 0 dB gain

-70

-65

-60

-55

dB

50mV Rms @ 1kHz input and 20 dB gain

Interchannel mismatch

0.1

-65

1

dB

Left-channel to right-channel crosstalk (300Hz to 20kHz)

Analog Performance - PA Driver

Differential output level for one input 500mV Rms singlel

@ AVDD, AVDDHS = 2.8 V

500

mVrms

Differential output level for stereo inputs 500mV Rms singlel

@ AVDD, AVDDHS = 2.8 V, inputs internally summed

1

0.5xAVDDHS

50

Vrms

V

Output common mode voltage

10

kOhm

pF

Output load (on each input, DC decoupled to the ground)

30

Gain (one single input to differential output), 20Hz to 20kHz

Signal to Noise Ratio (500mV Rms output @ 1kHz)

-05

0

0.5

dB

80

Total Harmonic Distortion (500mV Rms @ 1kHz output)

2 x 10kOhm balanced load

-80

dB

7

6464A–PMAAC–28-Apr-09

Table 7-1.

Electrical Specifications (Continued)

Min

Typ

Max

Units

Master Clock

Master Clock Maximum Long Term Jitter

Digital Filter Performance

1.5

ns_pp

Frequency response (10 Hz to 20 kHz)

Deviation from linear phase (10 Hz to 20 kHz)

Passband 0.1 dB corner

0.1

dB

deg

Fs

0.4535

Stopband

0.5465

65

Fs

Stopband Attenuation

dB

De-emphasis Filter Performance (for 44.1kHz Fs)

MAX deviation from ideal response

POWER PERFORMANCE

-1

1

dB

Current consumption from Analog supply in power on

Current consumption from Analog supply in power down

Power on Settling Time

9

mA

µA

10

500

ms

From full power down to full power up (Vref and VCM decoupling

capacitors charge)

Line in amplifier (line in coupling capacitors charge)

50

ms

Driver amplifier (out driver DC blocking capacitors charge)

500

8

AT73C240

6464A–PMAAC–28-Apr-09

AT73C240

7.2

Digital Filters Transfer Function

Figure 7-1. Channel Filter

Figure 7-2. Channel Filter

Figure 7-3. De-emphasis Filter

FR of DAC Decimator with Deemphasis Fs=44100; OSR=128

0

-2

-4

-6

-8

-10

-12

10³

10⁴

Frequency (Hz)

9

6464A–PMAAC–28-Apr-09

7.3

Data Interface

Normal operation is entered by applying correct LRFS, BCLK and SDIN waveforms to the serial

interface, as illustrated in Figure 7-4, Figure 7-5 and Figure 7-6.

To avoid noise at the output, the reset state is maintained until proper synchronization is

achieved in the serial interface.

The data interface allows three different data transfer modes. See Figure 7-4, Figure 7-5 and

Figure 7-6.

Figure 7-4. 20-bit I2S Justified Mode

BCLK

LRFS

R1

R0

L(N-1)

L(N-2)

L(N-3)

...

L2

...

L2

L1

L0

R(N-1)

R(N-2)

R(N-3)

R(N-1)

R(N-3)

...

R2

...

R2

R1

R0

SDIN

Figure 7-5. 20-bit MSB Justified Mode

BCLK

LRFS

R0

L(N-1)

L(N-2)

L(N-3)

...

R(N-1)

R(N-2)

...

L(N-1)

SDIN

Figure 7-6. 20-bit LSB Justified Mode

BCLK

LRFS

R0

L(N-1)

L(N-2)

R(N-2)

L(N-1)

SDIN

The selection between modes is done using the DINTSEL<1:0> signal.

DINTSEL <1:0>

Format

00

01

1x

I2S Justified

MSB Justified

LSB Justified

The data interface always works in slave mode. This means that the LRFS and the BCLK sig-

nals are provided by the host controller. In order to achieve proper operation, the LRFS and the

BCLK signals must be synchronous with the MCLK master clock signal and their frequency rela-

tionship must reflect the selected data mode. For example, if the data mode selected is the 20-

bit MSB Justified, then the BCLK frequency must be 40 times higher than the LRFS frequency.

10

AT73C240

6464A–PMAAC–28-Apr-09

AT73C240

7.4

Timing Specifications

The timing constraints of the data interface are described in Figure 7-7 and Table 7-2 below.

Figure 7-7. Data Interface Timing Diagram

1

20

M/2+1

M

BCLK

ts1

th1

LRFS

SDIN

ts2

th2

Table 7-2.

Data Interface Timing Parameters

Parameter

Min

Typ

Max

Unit

ts1

th1

ts2

th2

LRFS set-up time before BCLK rising edge

LRFS hold time after BCLK rising edge

DIN set-up time before BCLK rising edge

DIN hold time after BCLK rising edge

10

ns

7.5

SMODE Selection

SMODE input is internally pulled up in the AT73C240. This ensures a TWI communication proto-

cole default mode

When setting SMODE to 0, SPI communication protocol can also be used.

Two cases have to be considered:

SMODE=1, TWI protocole

SMODE=0, SPI protocole

11

6464A–PMAAC–28-Apr-09

8. SPI Interface

8.1

Architecture

The SPI is a three-wire bi-directional asynchronous serial link. It works only in slave mode. The

protocol is the following:

Figure 8-1. SPI Architecture

SPI_CSB

SPI_CLK

d6

rw a6 a5 a4 a3 a2 a1 a0 d7

d5 d4 d3 d2 d1 d0

SPI_DIN

d7 d6 d5 d4 d3 d2 d1 d0

SPI_DOUT

8.2

SPI Protocol

On SPI_DIN, the first bit is a read/write bit. 0 indicates a write operation, while 1 is for a read

operation. The seven following bits are used for the register address and the eight last ones are

the write data. For both address and data, the most significant bit is the first one.

In case of a read operation, SPI_DOUT provides the contents of the read register, MSB first.

The transfer is enabled by the CSB signal active low. When no operation is being carried out,

SPI_DOUT is set high impedance to allow sharing of MCU serial interface with other devices.

The interface is reset at every rising edge of SPI_CSB in order to come back to an idle state,

even if the transfer does not succeed. The SPI is synchronized with the serial clock SPI_CLK.

Falling edge latches SPI_DIN input and rising edge shifts SPI_DOUT output bits.

Note that MCLK must run during any SPI write access from address 0x00 to 0x11.

12

AT73C240

6464A–PMAAC–28-Apr-09

AT73C240

8.3

SPI Interface Timing

Figure 8-2. SPI Timing

SPI_CSB

SPI_CLK

SPI_DIN

Tc

Tssen

Thsen

Twl

Twh

Tssdi

Thsdi

Thsdo

Tdsdo

SPI_DOUT

Table 8-1.

Parameter

Tc

SPI Timing Parameters

Description

Min

150 ns

50 ns

20 ns

-

Max

SPI_CLK min period

-

Twl

SPI_CLK min pulse width low

SPI_CLK min pulse width high

-

Twh

-

Tssen

Thsen

Tssdi

Setup time SPI_CSB falling to SPI_CLK rising

Hold time SPI_CLK falling to SPI_CSB rising

Setup time SPI_DIN valid to SPI_CLK falling

-

Thsdi

Hold time SPI_CLK falling to SPI_DIN not valid

Delay time SPI_CLK rising to SPI_DOUT valid

Hold time SPI_CLK rising to SPI_DOUT not valid

-

20 ns

-

Tdsdo

Thsdo

0 ns

13

6464A–PMAAC–28-Apr-09

9. TWI Interface

9.1

TWI Architecture

The two-wire interface interconnects components on a unique two-wire bus, made up of one

clock line and one data line with speeds up to 400 Kbits per second, based on a byte oriented

transfer format. The TWI is slave only and has single byte access.

The TWI adds flexibility to the power supply solution, enabling LDO regulator and Audio func-

tionnalities and paths to be controlled depending on the instantaneous application requirements.

The AT73C240 has the following 7-bit address: 1001000.

Attempting to read data from register addresses not listed in this section results in 0xFF being

read out.

• TWCK is an input pin for the clock

• TWD is an open-drain pin driving or receiving the serial data

The data put on TWD line must be 8 bits long. Data is transferred MSB first. Each byte must be

followed by an acknowledgement.

Each transfer begins with a START condition and terminates with a STOP condition.

• A high-to-low transition on TWD while TWCK is high defines a START condition.

• A low-to-high transition on TWD while TWCK is high defines a STOP condition..

Figure 9-1. TWI Start and Stop conditions

TWD

TWCK

Start

Stop

Figure 9-2. TWI transfert format

TWD

TWCK

Start

Address

R/W

Ack

Data

Ack

Data

Ack

Stop

After the host initiates a START condition, it sends the 7-bit slave address defined above to

notify the slave device. A read/write bit follows (read = 1, write = 0).

The device acknowledges each received byte. The first byte sent after the device address and

the R/W bit, is the address of the device register the host wants to read or write.

For a write operation the data follows the internal address. For a read operation a repeated

START condition needs to be generated followed by a read on the device.

14

AT73C240

6464A–PMAAC–28-Apr-09

AT73C240

Figure 9-3. TWI Write operation

S

ADDR

W

DATA

A

IADDR

A

P

TWD

Figure 9-4. TWI Read operation

ADDR

W

A

IADDR

A

S

ADDR

R

A

DATA

• S = Start

• P = Stop

• W = Write

• R = Read

• A = Acknowledge

• N = Not Acknowledge

• DADR= Device Address

• IADR = Internal Address

15

6464A–PMAAC–28-Apr-09

10. User Interface

Table 10-1. Register Mapping

Address

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

Register

Name

Access

Reset State

0x00

DAC_CTRL

DAC_LLIG

DAC_RLIG

DAC_LMPG

DAC_RMPG

DAC_LLOG

DAC_RLOG

DAC_OLC

DAC_MC

DAC Control

Read/Write

DAC Left Line In Gain

DAC Right Line In Gain

DAC Left Master Playback Gain

DAC Right Master Playback Gain

DAC Left Line Out Gain

DAC Right Line Out Gain

DAC Output Level Control

DAC Mixer Control

0x05

0x08

0x00

0x22

0x09

DAC Clock and Sampling Frequency

Control

0x09

DAC_CSFC

Read/Write

0x00

0x0A

0x0C

0x10

0x11

DAC_MISC

DAC_PRECH

DAC_RST

PA_CRTL

DAC Miscellaneous

DAC Precharge Control

DAC Reset

Read/Write

0x00

0x0F

Power Amplifier Control

Note:

MSB = Bit 7, LSB = Bit 0

16

AT73C240

6464A–PMAAC–28-Apr-09

AT73C240

10.1 DAC Control Register

Register Name: DAC_CTRL

Register Address: 0x00

Reset State: 0x00

Access: Read/Write

7

6

5

4

3

2

1

0

Not Used

ONPADRV

ONDACR

ONDACL

ONLNOR

ONLNOL

ONLNIR

ONLNIL

• ONLNIL

Left channel line in amplifier (L to power down, H to power up)

• ONLNIR

Right channel line in amplifier (L to power down, H to power up)

• ONLNOL

Left channel line out driver (L to power down, H to power up)

• ONLNOR

Right channel line out driver (L to power down, H to power up)

• ONDACL

Left channel DAC (L to power down, H to power up)

• ONDACR

Right channel DAC (L to power down, H to power up)

• ONPADRV

Differential mono PA driver (L to power down, H to power up)

17

6464A–PMAAC–28-Apr-09

10.2 DAC Left Line In Gain Register

Register Name: DAC_LLIG

Register Address: 0x01

Reset State: 0x05

Access: Read/Write

7

6

5

4

3

2

1

0

Not Used

LLIG

• LLIG: Left channel line in analog gain selector

LLIG<4:0>

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

≥10001

Gain

20

Unit

dB

12

9

6

3

0

-3

-6

-9

-12

-15

-18

-21

-24

-27

-30

-33

< -60

18

AT73C240

6464A–PMAAC–28-Apr-09

AT73C240

10.3 DAC Right Line In Gain Register

Register Name: DAC_RLIG

Register Address: 0x02

Reset State: 0x05

Access: Read/Write

7

6

5

4

3

2

1

0

Not Used

RLIG

• RLIG: Right channel line in analog gain selector

RLIG<4:0>

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

≥10001

Gain

20

Unit

dB

12

9

6

3

0

-3

-6

-9

-12

-15

-18

-21

-24

-27

-30

-33

< -60

19

6464A–PMAAC–28-Apr-09

10.4 DAC Left Master Playback Gain Register

Register Name: DAC_LMPG

Register Address: 0x03

Reset State: 0x08

Access: Read/Write

7

6

5

4

3

2

1

0

Not Used

LMPG

• LMPG: Left channel master playback digital gain selector

LMPG<5:0>

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

Gain

12.0

10.5

9.0

Unit

dB

LMPG<5:0>

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

≥ 100000

Gain

-13.5

-15.0

-16.5

-18.0

-19.5

-21.0

-22.5

-24.0

-25.5

-27.0

-28.5

-30.0

-31.5

-33.0

-34.5

mute

Unit

dB

7.5

6.0

4.5

3.0

1.5

0.0

-1.5

-3.0

-4.5

-6.0

-7.5

-9.0

-10.5

-12.0

20

AT73C240

6464A–PMAAC–28-Apr-09

AT73C240

10.5 DAC Right Master Playback Gain Register

Register Name: DAC_RMPG

Register Address: 0x04

Reset State: 0x08

Access: Read/Write

7

6

5

4

3

2

1

0

Not Used

RMPG

• RMPG: Right channel master playback digital gain selector

RMPG<5:0>

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

Gain

12.0

10.5

9.0

Unit

dB

RMPG<5:0>

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

≥ 100000

Gain

-13.5

-15.0

-16.5

-18.0

-19.5

-21.0

-22.5

-24.0

-25.5

-27.0

-28.5

-30.0

-31.5

-33.0

-34.5

mute

Unit

dB

7.5

6.0

4.5

3.0

1.5

0.0

-1.5

-3.0

-4.5

-6.0

-7.5

-9.0

-10.5

-12.0

21

6464A–PMAAC–28-Apr-09

10.6 DAC Left Line Out Gain Register

Register Name: DAC_LLOG

Register Address: 0x05

Reset State: 0x00

Access: Read/Write

7

6

5

4

3

2

1

0

Not Used

LLOG

• LLOG: Left channel line out digital gain selector

LLOG<5:0>

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

Gain

0

Unit

dB

LLOG<5:0>

010000

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

≥ 100000

Gain

-24.0

-25.5

-27.0

-28.5

-30.0

-31.5

-33.0

-34.5

-36.0

-37.5

-39.0

-40.5

-42.0

-43.5

-45.0

-46.5

mute

Unit

dB

-1.5

-3.0

-4.5

-6.0

-7.5

-9.0

-10.5

-12.0

-13.5

-15.0

-16.5

-18.0

-19.5

-21.0

-22.5

22

AT73C240

6464A–PMAAC–28-Apr-09

AT73C240

10.7 DAC Right Line Out Gain Register

Register Name: DAC_RLOG

Register Address: 0x06

Reset State: 0x00

Access: Read/Write

7

6

5

4

3

2

1

0

Not Used

RLOG

• RLOG: Right channel line out digital gain selector

RLOG<5:0>

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

Gain

0

Unit

dB

RLOG<5:0>

010000

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

≥ 100000

Gain

-24.0

-25.5

-27.0

-28.5

-30.0

-31.5

-33.0

-34.5

-36.0

-37.5

-39.0

-40.5

-42.0

-43.5

-45.0

-46.5

mute

Unit

dB

-1.5

-3.0

-4.5

-6.0

-7.5

-9.0

-10.5

-12.0

-13.5

-15.0

-16.5

-18.0

-19.5

-21.0

-22.5

23

6464A–PMAAC–28-Apr-09

10.8 DAC Output Level Control Register

Register Name: DAC_OLC

Register Address: 0x07

Reset State: 0x22

Access: Read/Write

7

6

5

4

3

2

1

0

RSHORT

ROLC

LSHORT

LOLC

• LOLC: Left channel output level control selector

LOLC

100

Gain

5

Unit

dB

011

2.5

0

dB

010

dB

001

-2.5

-5

000

dB

• LSHORT: Left channel short circuit indicator

Persistent; after being set, bit is not cleared automatically even after the short circuit is eliminated; must be cleared by reset

cycle or direct register write operation.

• ROLC: Right channel output level control selector

ROLC

100

Gain

5

Unit

dB

011

2.5

0

dB

010

dB

001

-2.5

-5

000

dB

• RSHORT: Right channel short circuit indicator

Persistent; after being set, bit is not cleared automatically even after the short circuit is eliminated; must be cleared by reset

cycle or direct register write operation.

24

AT73C240

6464A–PMAAC–28-Apr-09

AT73C240

10.9 DAC Mixer Control Register

Register Name: DAC_MC

Register Address: 0x08

Reset State: 0x09

Access: Read/Write

7

0

6

0

5

4

3

2

1

0

INVR

INVL

RMSMIN2

RMSMIN1

LMSMIN2

LMSMIN1

• LMSMIN1: Left Channel Mono/Stereo Mixer Left Mixed input enable (H to enable, L to disable)

• LMSMIN2: Left Channel Mono/Stereo Mixer Right Mixed input enable (H to enable, L to disable)

• RMSMIN1: Right Channel Mono/Stereo Mixer Left Mixed input enable (H to enable, L to disable)

• RMSMIN2: Right Channel Mono/Stereo Mixer Right Mixed input enable (H to enable, L to disable)

• INVL: Left channel mixer output invert (H to enable, L to disable)

• INVR: Right channel mixer output invert (H to enable, L to disable)

10.9.1

Digital Mixer Control

The Audio DAC features a digital mixer that allows the mixing and selection of multiple input

sources.

The mixing/multiplexing functions are described in Figure 10-1.

Figure 10-1. Digital Mixer Functions

Left channel

1

+

Volume

Control

Volume

Control

2

1

From digital

filters

To DACs

Volume

Control

Volume

Control

+

2

Right channel

Note:

When the two mixer inputs are selected, a -6 dB gain is applied to the output signal. When only

one input is selected, no gain is applied.

25

6464A–PMAAC–28-Apr-09

10.10 DAC Clock and Sampling Frequency Control Register

Register Name: DAC_CSFC

Register Address: 0x09

Reset State: 0x00

Access: Read/Write

7

6

5

4

3

2

1

0

Not Used

OVRSEL

Not Used

• OVRSEL: Master clock selector

L to 256 x Fs, H to 384 x Fs

Master clock and sampling frequency selection

Table 10-2 describes the modes available for master clock and sampling frequency selection.

Table 10-2. Master Clock Modes

OVRSEL

Master Clock

256 x Fs

0

1

384 x Fs

26

AT73C240

6464A–PMAAC–28-Apr-09

AT73C240

10.11 DAC Miscellaneous Register

Register Name: DAC_MISC

Register Address: 0x0A

Reset State: 0x00

Access: Read/Write

7

6

5

4

3

2

1

0

Not Used

VCMCAPSEL

DINTSEL

DITHEN

DEEMPEN

NBITS

• NBITS<1:0>: Data interface word length

The selection of input sample size is done using the NBITS field.

NBITS <1:0>

Format

16 bits

18 bits

20 bits

00

01

10

• DEEMPEN: De-emphasis enable (L to disable, H to enable)

To enable the de-emphasis filtering the DEEMPHEN signal must be set to high.

• DITHEN: Dither enable (L to disable, H to enable)

The dither option (added in the playback channel) is enabled by setting the DITHEN signal to high.

• DINTSEL<1:0>: I2S data format selector

The selection between modes is done using the DINTSEL<1:0> signal.

DINTSEL<1:0>

Format

00

01

1x

I2S Justified

MSB Justified

LSB Justified

• VCMCAPSEL: VCM decoupling capacitor selector

Low for 10 µF, High for 100 µF

27

6464A–PMAAC–28-Apr-09

10.12 DAC Precharge Control Register

Register Name: DAC_PRECH

Register Address: 0x0C

Reset State: 0x00

Access: Read/Write

7

6

5

4

3

2

1

0

Not Used

PRCHGPDRV

PRCHGLNIR

PRCHGLNIL

PRCHG

ONMSTR

• ONMSTR: Master power on control (L to power down, H to power up)

• PRCHG: Master pre-charge (H to charge)

• PRCHGLNIL: Left channel line in pre-charge (H to charge)

• PRCHGLNIR: Right channel line in pre-charge (H to charge)

• PRCHGPDRV: Differential mono PA driver pre-charge (H to charge)

10.13 DAC Reset Register

Register Name: DAC_RST

Register Address: 0x10

Reset State: 0x00

Access: Read/Write

7

6

5

4

3

2

1

0

Not Used

RESFILZ

RSTZ

• RSTZ: Active low reset of the audio codec

• RESFILZ: Active low reset of the audio codec filter

See “Supplies and Start-up” on page 30.

28

AT73C240

6464A–PMAAC–28-Apr-09

AT73C240

10.14 PA Control Register

Register Name: PA_CTRL

Register Address: 0x11

Reset State: 0x0F

Access: Read/Write

7

6

5

4

3

2

1

0

Not Used

APAON

APAPRECH

APAGAIN

• APAGAIN<3:0>: Audio power amplifier gain

APAGAIN<3:0>

0000

Gain db

APAGAIN<3:0>

1000

Gain db

-1

FORBIDDEN

0001

20

17

14

11

8

1001

-4

0010

1010

-7

0011

1011

-10

-13

-16

-19

-22

0100

1100

0101

1101

0110

5

1110

0111

2

1111

• APAPRECH: Audio power amplifier precharge bit

• APAON: Audio power amplifier on bit

APAON

APAPRECH

Operating Mode

Stand-by

0

1

0

1

0

1

Input capacitors precharge

Active mode

Forbidden state

29

6464A–PMAAC–28-Apr-09

11. Supplies and Start-up

In operating mode, VBAT (supply of the audio power amplifier) must be between 3V and 5.5V

and AVDD, AVDDHS and VDIG must be inferior or equal to VBAT and lower than 3.3V.

A typical application is VBAT connected to a battery and AVDD, AVDDHS and VDIG supplied by

regulators. VBAT must be present at the same time or before AVDD, AVDDHS and VDIG.

RSTB must be active (0) until the voltages are stable and reach the proper values.

To avoid noise issues, it is recommended to use ceramic decoupling capacitors for each supply

close to the package as defined in the application diagram. See Figure 13-1 on page 33.

The track of the supplies must be optimized to minimize the resistance, especially on VBAT

where all the current from the power amplifier comes from.

HPN and HPP must be routed symmetrically and the resistance must be minimized, at the

expense of maximum output power capabilities reduction.

11.1 Audio DAC Start-up Sequences

In order to minimize the noise during the start-up, a specific sequence should be applied.

In any audio configuration, always force Bit 2 to high level (“1”) at 0x0B address.

11.1.1

Power on Example

Path DAC to headset output

1. Write @0x10 => 0x03 (deassert the reset)

2. Write @0x0C => 0x1F (precharge + master on)

3. Write @0x00 => 0x0C (ONLNOL and ONLONOR set to 1)

4. Delay 500 ms

5. Write @0x0C => 0x01 (precharge off + master on)

6. Delay 1ms

7. Write @0x00 => 0x3C (ONLNOL, ONLNOR, ONDACR and ONDACL set to 1)

11.1.2

11.1.3

Power off Example

1. Write @0x00 => 0xC0 (ONDACR and ONDACL set to 0)

2. Write @0x0C => 0x00 (master off)

3. Delay 1ms

4. Write @0x00 => 0x00 (all off)

I2S Example

In order to prevent I2S from generating noise at the output (for example a MP3 player switching

from one song to another):

1. Set ONDAC to 0 ((bit 4 and 5 in register @0x00)

2. Stop I2S and MCLK

When I2S is restarted, in order to prevent noise generation at the output:

1. Start MCLK

2. Write @0x10 => 0x00 (RESFILZ=0, RSTZ=0)

3. Write @0x10 => 0x03 (RESFILZ=1, RSTZ=1)

30

AT73C240

6464A–PMAAC–28-Apr-09

AT73C240

4. Delay 5 ms

5. Set ONDAC to 1 (bit 4 and 5 in register @0x00)

6. Reprogram all DAC settings (Audio format, gains, etc.)

7. Start I2S.

11.2 Audio Power Amplifier Power on Sequence

To avoid an audible “click” at start-up, the input capacitors must be pre-charged before the

power amplifier.

1. At start-up, disable APAON, APAGAIN<3:0> set to -22 dB, enable APAPRECH.

2. Wait 50 ms minimum.

3. Then disable APAPRECH and enable APAON.

4. Wait 10 ms min time.

5. Set the gain to the value chosen.

11.2.1

Audio Power Amplifier Power off Sequence

To avoid an audible “click” at power-off, the gain should be set to the minimum gain (-22 dB)

before turning off the power amplifier.

31

6464A–PMAAC–28-Apr-09

12. Current Consumption in Different Modes

Table 12-1. Curent Consumption in Different Modes

Current

Consumption

(typ)

Current

Consumption

(max)

Mode

0: Off

Powered up block

Unit

All blocks off and

RSTB = 0

5

12

µA

total

5

0

12

1

µA

1: Standby

Vref generator

Vcm generator

250

0

350

351

1

2: DAC Playback Through stereo

Headset

Vref generator

Vcm generator

250

850

1600

5150

0

350

1200

2000

6751

1

Left line out amplifier

Right line out amplifier

Left D-to-A converter

Right D-to-A converter

(Current in the load not included)

total

Vref generator

3: Stereo DAC Playback to Audio PA

Vcm generator

250

1600

800

6000

10650

0

350

2000

1200

12000

17551

1

Left D-to-A converter

Right D-to-A converter

(Current in the load not included)

Differential mono PA driver

Audio PA

total

Vref generator

4: Playback From Stereo Line Input to

Stereo Headset

Vcm generator

250

700

850

2500

350

900

1200

3351

Left line in amplifier

Right line in amplifier

Differential mono PA driver

(Current in the load not included)

total

32

AT73C240

6464A–PMAAC–28-Apr-09

AT73C240

13. Application Diagram

Figure 13-1. Application Using One Li-Ion Battery

PAINN

2.8V from LDO

C17

AT73C240

22u

VDIG

3.6 V

VBAT

CBP

Battery

(Li-Ion or 3 x NiMh or

100n

10µF

100n

C7

NiCd)

C16

2.8V from LDO

AVDD

HPP

C18

8 Ohm

Loudspeaker

Audio PA

HPN

AVDDHS

C19

C15

PAINP

C9

470n

VREF

VCM

REF

MONOP

MONON

LINER

10u

C11

10u

C12

C8

C3

R

L

stereo

line input

(e.g. FM Radio)

SPI_DOUT

470n

SPI_DIN/TWD

LINEL

SPI / TWI

SPI_CLK/TWCK

470n

DIG

SPI_CSB/TW_ADD

SMODE

RSTB

Reset active low

I2S

MCLK

SDIN

LRFS

C6

32

HSR

HSL

32 Ohm

Audio

DAC

C5

100u

Headset

BCLK

or Line Out

10u

100u

INGND

GNDA

C10

GNDD

33

6464A–PMAAC–28-Apr-09

14. Components List

Table 14-1. Components List

Reference

Value

470 nF

100 µF

10 µF

Techno

Ceramic

Size

0402

1210

0603

Manufacturer & Reference

C3, C8, C12,

C15

C1005X5R1A474K (TDK) or GRM155R60J474KE19 (Murata)

C3225X5R0J107M (TDK) or GRM32ER60J107ME20 (Murata)

C1608X5R0J106MT (TDK) or GRM188R60J106ME47 (Murata)

C5, C6

C9, C10,

C11, C19

C7, C17, C18

C16

100 nF

22 µF

Ceramic

0402

0805

C1005X5R1C104K (TDK) or GRM155R61A104KA01 (Murata)

C2012X5R0J226MT (TDK) or GRM21BR60J226ME39 (Murata)

34

AT73C240

6464A–PMAAC–28-Apr-09

AT73C240

15. Package Drawing

Figure 15-1.Package OutlineR-QFN032_H

Notes: 1. All dimensions are in mm.

2. Drawing is for general information only. Refer to JEDEC drawing MO-220 for additional

information.

35

6464A–PMAAC–28-Apr-09

Figure 15-2. Package Drawing with Pin 1 and Marking for R-QFN032_H package

36

AT73C240

6464A–PMAAC–28-Apr-09

AT73C240

16. Revision History

Change

Doc. Rev

Comments

First issue

Request Ref.

6464A

37

6464A–PMAAC–28-Apr-09

Headquarters

International

Atmel Corporation

2325 Orchard Parkway

San Jose, CA 95131

USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Atmel Asia

Atmel Europe

Le Krebs

Atmel Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

Unit 1-5 & 16, 19/F

BEA Tower, Millennium City 5

418 Kwun Tong Road

Kwun Tong, Kowloon

Hong Kong

8, Rue Jean-Pierre Timbaud

BP 309

78054 Saint-Quentin-en-

Yvelines Cedex

France

Tel: (852) 2245-6100

Fax: (852) 2722-1369

Tel: (33) 1-30-60-70-00

Fax: (33) 1-30-60-71-11

Product Contact

Web Site

www.atmel.com

Analog Companions (PMAAC)

Technical Support

Atmel techincal support

pmaac@atmel.com

Sales Contacts

www.atmel.com/contacts/

Literature Requests

www.atmel.com/literature

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any

intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-

TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY

WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR

PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-

TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT

OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no

representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifica-

tions and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically pro-

vided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted

for use as components in applications intended to support or sustain life.

trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

6464A–PMAAC–28-Apr-09


型号：	AT73C240
厂家：	ATMEL
描述：	Power Management and Analog Companions 电源管理和模拟同伴电源电路电源管理电路异步传输模式 ATM
文件：	总38页 (文件大小：1128K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT73C240 [ATMEL]

相关型号：

AT73C246

AT73C246-A

AT73C246-B

AT73C260

AT73C500

AT73C500-JC

AT73C501

AT73C501-JC

AT73C502

AT73C502-QC

AT74011-H2B1-4F

AT74011-H2B1-4N