AT73C260_技术文档

Features

• Pin-programmable Mode

• Supply Voltage Range 1.55V to 3.6V

• PHY IC_USB1.0 Downstream Port

• Bridge USB2.0 Section 7 to IC_USB1.0

• Bridge IC_USB1.0 to USB2.0 Section 7

• 3.3V Voltage Reference

• Two 70mA LDO Voltage Regulators

• Less Than 5µA Static Current on Each Supply

• Slew Rate Control to Minimize Radiated EMI

• ESD 4kV Compliant with USB UICC

• Applications:

Power

Management

and Analog

Companions

(PMAAC)

– Mobile USB UICC (ETSI 102 600), PC USB UICC, Token USB

Description

The AT73C260 is an Inter Chip USB transceiver fully compliant with the Universal

Serial Bus Specification, and more specifically with the IC_USB1.0 supplement. The

AT73C260 is a bidirectional differential interface. The AT73C260 is ideal for applica-

tions in mobile devices, PCs and USB tokens making use of an USB UICC.

AT73C260

The AT73C260’s upstream facing port may be connected to three different interfaces:

• Digital

• USB2.0 section 7 with or without cable

• IC_USB1.0

Interchip USB

Transceiver

The AT73C260’s downstream port complies with IC_USB1.0. The AT73C260’s mode

is selected by three pins. When PVCC is powered by 3.3V and pull down resistors are

added on PDM and PDP, the AT73C260’s downstream port complies with USB2.0

section 7.

(PHY - IC_USB1.0,

Voltage Class

Converter,

USB2.0 - IC_USB1.0

Bridges)

The AT73C260 includes a 3.5V Supply Monitor, a Low Power Band-Gap, a 3.3V

70mA Linear Voltage Regulator and a 1.8V-3.0V 70mA Linear Voltage Regulator SIM

FTA compliant Test 27.17.2.1.

The AT73C260 is specified over the industrial temperature range - 40°C to +85°C.

The AT73C260 is available in a 3 X 3 mm, 0.5mm pitch, QFN16 package.

Preliminary

11030A–PMAAC–13-Sep-10

1. Block Diagram

Figure 1-1. AT73C260 functional block diagram

9

AT73C260

PVRF

1

12

HVCC

PVCC

Vref

3.3Volt

4

13

6

V

BUS

RCV

HDMO

HDPO

OE_N

HDP

10

PDM

7

8

2

11

PDP

3

HDM

M<2> M<1> M<0> GND

14 15 16

5

2

AT73C260

11030A–PMAAC–13-Sep-10

AT73C260

2. Package and Pinout

Figure 2-1. AT73C260 QFN16 package pinout - top view

Thermal Pad

(BOTTOM)

8

OE_N

13

14

15

16

RCV

M<2>

M<1>

M<0>

C260B

YYWW

XXXXX

7 HDPO

6 HDMO

GND

5

17 GND

PIN 1 INDICATOR

3

11030A–PMAAC–13-Sep-10

3. Pin Description

Table 3-1.

Pin Name

AT73C260 Pin Description

I/O

Pin Number

Type

Function

Host Side VCC

•When pin 4 (VBUS) is grounded. The LDO on pin HVCC is in

standby and its output is isolated. The Host supplies HVCC with the

appropriate voltage to the AT73C260’s upstream transceiver.

HVCC

Output

1

Analog

•When pin 4 (VBUS) is connected to a voltage source the internal

voltage reference 3.3V and both LDO are activated. The LDO on pin

1 provides power at 3.3V to the AT73C260’s upstream transceiver

and it may source up to 70mA.

HDP

I/O

2

3

Digital

Analog

Digital

Analog

Digital

Bidirectional

HDM

Bidirectional

VBUS

GND

Input

Ground

Output

Input

I/O

4

Supply, provides power to the LDOs on pin 1 and 12

5

GND Ground for Digital and I/Os

Output

HDMO

HDPO

OE_N

PVRF

PDM

6

7

Output

8

Input

9

PVCC LDO input reference

Bidirectional pad

Peripheral Side VCC

10

11

PDP

I/O

•When pin 4 (VBUS) is grounded. The LDO on pin PVCC is in

standby and its output is isolated. The application supplies PVCC

with the appropriate voltage to the AT73C260’s downstream

transceiver.

PVCC

Input

12

Analog

•When pin 4 (VBUS) is connected to a voltage source, the LDO on

pin PVCC follows the voltage on pin PVRF. The LDO on pin PVCC

provides power to the AT73C260’s downstream transceiver and it

may source up to 70mA.

RCV

Output

Input

13

14

15

16

Digital

Output

M<2>

M<1>

M<0>

Input. For mode configuration

Analog Ground. Thermal Pad. Shall be connected to GND for electrical

and power dissipation reasons.

GND

Ground

17

Analog

4

AT73C260

11030A–PMAAC–13-Sep-10

AT73C260

4. Absolute Maximum Ratings

Table 4-1.

Absolute Maximum Ratings

Operating Temperature (Industrial)..................-40°C to + 85°C⁽¹⁾

*NOTICE:

Stresses beyond those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only and functional operation of

the device at these or other conditions beyond those

indicated in the operational sections of this specification

is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reli-

ability.

Storage Temperature........................................-55°C to + 150°C

Power Supply Input on H_VCC............................... -0.3V to + 3.6V

Power Supply Input on VBUS............................. -0.3V to + 5.5V

Digital I/O Input Voltage...................................... -0.3V to + 3.6V

All Other Pins.......................................................-0.3V to + 3.6V

ESD (all pins)..............................................................4 KV HBM

Notes: 1. Refer to Power Dissipation Rating section)

5. Recommended Operating Conditions

Table 5-1.

Parameter

Recommended Operating Conditions

Condition

Min

-40

Max

85

Units

°C

V

Operating Ambient Temperature⁽¹⁾

Power Supply Output

P_VCC

1.55

4.0

3.6

5.5

Power Supply Input

H_VCC

VBUS

V

Power Supply Input

V

Note:

1. Refer to Power Dissipation Rating section

6. Power Dissipation Ratings

Table 6-1.

Parameter

Recommended Operating Conditions

Condition

Min

Typ

Max

Units

Maximum Junction Temperature

-40

--

125

°C

Package thermal junction to ambient

resistance

(1)

R_THjA

--

90

°C / W

mW

Maximum On-chip Power Dissipation

Ambient temperature = 85°C

--

400

Note:

1. According to specification JESD51-5

5

11030A–PMAAC–13-Sep-10

7. Electrical Characteristics

7.1

I/Os DC Characteristics Referred to H_VCC

Table 7-1.

Symbol

H_VCC

H_VCCReferred I/Os: HDP, HDM, RCV, HDMO, HDPO, OE_N and M<2:0>

Parameter

Comments

Min

Typ

Max

Units

Host Side Supply Voltage

220nF ceramic capacitor ⁽¹⁾

1.55

--

3.6

V

Full Speed Transceiver / Receiver

at 12Mbps, C_LOAD= 18pF on HDP

and HDM during transmit

I_HVCC

Operating H_VCCSupply Current

--

2

mA

0.65 x

H_VCC

0.3

+

V_IH

V_IL

Input High-Level Voltage

Input Low-Level Voltage

V_OH> V_{OH_MIN}

V_OH< V_{OL_MAX}

--

V

0.35 x

H_VCC

-0.3

H_VCC

0.45

-

V_OH

V_OL

Output High-Level Voltage

Output Low-Level Voltage

I_OH= - 2mA

I_OL= 2mA

All Cases

--

V

--

0.45

80

Pull-Down Resistors on HDP,

HDM

R_PDP

30

kΩ

M<0> = 0

Upstream Pull-Up Resistors on

HDP

(2)

R_PU1

0.9

1

--

3.09

150

kΩ

M<2:1> = connected to H_VCC

Upstream Pull-Up Resistors on

HDP

(3)

R_PU2

M<2:0> = connected to H_VCC

Notes: 1. A 220nF ceramic capacitor is connected between the pin H_VCCand the pin GND and closest to H_VCCpin.

2. R_PU1Pull Up resistor is as per the ECN “Pull-up/pull-down resistors” published by the USB-IF. R_PU1value is between 900Ω

and 1575Ω when the bus is idle and between 1425Ω and 3090Ω when the upstream device is transmitting

3. R_PU2Pull Up resistor is as per the IC_USB1.0 published by the USB-IF. R_PU2value is between 1kΩ and 3kΩ to attach and

between 30kΩ and 150kΩ during idle.

7.2

I/Os DC Characteristics Referred to P_VCC

Table 7-2.

Symbol

P_VCC

P_VCCReferred I/Os: PDP, PDM

Parameter

Comments

Min

Typ

Max

Units

Peripheral Side Supply Voltage

220nF ceramic capacitor ⁽¹⁾

1.55

--

3.6

V

Full Speed Transceiver / Receiver

at 12Mbps, C_LOAD= 18pF on PDP

and PDM during transmit

I_PVCC

Operating P_VCCSupply Current

--

2

mA

0.65 x

P_VCC

0.3

+

V_IH

V_IL

Input High-Level Voltage

Input Low-Level Voltage

Output High-Level Voltage

V_OH> V_{OH_MIN}

V_OH< V_{OL_MAX}

I_OH= - 2mA

--

V

0.35 x

P_VCC

-0.3

P_VCC

0.45

-

V_OH

--

V_OL

Output Low-Level Voltage

Pull-Down Resistors

I_OL= 2mA

--

0.45

80

V

R_PDH

All Cases for PDP, PDM

30

kΩ

Notes: 1. A 220nF ceramic capacitor is connected between the pin P_VCCand the pin GND and closest to P_VCCpin.

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AT73C260

11030A–PMAAC–13-Sep-10

AT73C260

7.3

Timing Characteristics Table

Table 7-3.

Symbol

Timing Table

Parameter

Comments

Min

--

Typ

37

Max

--

Units

ns

H_VCC= 3.3V and P_VCC= 3.0V

T_DELAY

Propagation Delay Time

H_VCC= 3.3V and P_VCC= 1.8V

--

42

--

ns

10%-90%, C_LOAD=33pF, P_VCC=3.0V

10%-90%, C_LOAD=33pF, P_VCC=1.8V

10%-90%, C_LOAD=33pF, P_VCC=3.0V

10%-90%, C_LOAD=33pF, P_VCC=1.8V

10%-90%, C_LOAD=33pF, P_VCC=3.0V

10%-90%, C_LOAD=33pF, P_VCC=1.8V

10%-90%, C_LOAD=33pF, P_VCC=3.0V

10%-90%, C_LOAD=33pF, P_VCC=1.8V

--

5.7

10.5

5.6

10.6

6.1

7.6

6.1

7.7

--

T_{SLEW_R_P}

T_{SLEW_R_M}

T_{SLEW_F_P}

T_{SLEW_F_M}

Slew Rate, Rise Time on PDP

Slew Rate, Rise Time on PDM

Slew Rate, Fall Time on PDP

Slew Rate, Fall Time on PDM

--

ns

--

M<2:0>=110, H_VCC= 3.3V and P_VCC

= 3.0V

T_ATTACH

Attachment Transit Time

--

400

--

ns

M<2:0>=111, H_VCC= 1.8V and P_VCC

= 3.3V

Notes: 1. External Capacitor is a 1µF or higher ceramic capacitor connected between the pin V_BUSand the pin GND and closest to

V_BUSpin

7.4

V_BUSSupply Characteristics

Table 7-4.

Symbol

V_BUS

V_BUSSupply Monitor

Parameter

Comments

Min

4.0

Typ

5.0

Max

5.5

Units

V

Input Supply Voltage Range

Positive Threshold

Negative Threshold

Hysteresis

1µF ceramic capacitor ⁽¹⁾

V_TP

3.36

3.02

348

3.5

3.64

3.28

374

V

V_TN

3.15

361

V

V_HYS

mV

Notes: 1. External Capacitor is a 1µF or higher ceramic capacitor connected between the pin V_BUSand the pin GND and closest to

V_BUSpin

.

Table 7-5.

Symbol

V_BUS

V_BUSCurrent Consumption

Parameter

Comments

Min

Typ

Max

Units

Input Supply Voltage Range

1µF ceramic capacitor ⁽¹⁾

4.0

5.0

5.5

V

V_BUSactive

• H_VCC= 3.3V nominal

• 1.55V < P_VRF< 3.6V

• Loads = 0mA

• Idle

I_VBUS

V_BUSSupply Current

--

100

150

µA

Notes: 1. External Capacitor is a 1µF or higher ceramic capacitor connected between the pin V_BUSand the pin GND and closest to

V_BUSpin.

7

11030A–PMAAC–13-Sep-10

7.5

H_VCCand P_VCCSupplies Characteristics

7.5.1

H_VCCand P_VCCCurrent Consumption

Table 7-6.

Symbol

H_VCC

P_VCCand H_VCCCurrent Consumption

Parameter

Comments

Min

1.55

Typ

--

Max

3.6

Units

Host Supply Voltage

Peripheral Supply Voltage

V

P_VCC

--

3.6

V_BUS= 0V, P_VRF= 0V

• Loads = 0mA

I_VCC

X_VCCSupply Current

• Idle

--

5

µA

• H_VCCforced at 3.6V

• P_VCCforced at 3.3V

7.5.2

3.3V Supplied on H_VCC

When V_BUSis greater than 3.5V nominal, an internal LDO voltage regulator provides a 3.3V

nominal voltage source on pin H_VCC

.

Table 7-7.

Symbol

H_VCCLDO Characteristics

Parameter

Comments

Min

Typ

Max

Units

- Enabled when V_BUSis greater

than 3.5V typical.

(1)

H_VCC

Output Voltage

3.0

3.3

3.6

V

- Disabled when V_BUSgoes below

3.15V typical

I_O

Output Current

0

--

70

10

mA

mV

• V_BUS> 4.5V

Static Load Regulation

--

• I_O= 10% to 90%

Δ_{VDD_IL}

• V_BUS> 4.5V

Dynamic Load Regulation

Static Line Regulation

• I_O= 10% to 90%

• T_RISE= T_FALL= 5µs

--

50

--

mV

• V_BUSfrom 4.3V to 5.5V

• I_O= Max

--

20

mV

Δ_{VDD_VIN}

• V_BUSfrom 4.0V to 5.5V

• I_O= 7 mA

• V_BUSFrom 0V to 5.0V

• T_RISE= 10µs

• I_O= 0mA

T_START

Start-up Time

--

60

µs

• V_OUT> 3.0V

Notes: 1. When V_BUSis present and greater than V_TP, 10kΩ pull down is removed on H_VCCand on P_VCCand LDO are started. When

V_BUSgoes below V_TP, a 10kΩ pull down is connected on H_VCCand P_VCCand LDO are disabled. When V_BUS= 0V and H_VCC

and P_VCCwithin their normal range the 10kΩ pull down are disconnected.

8

AT73C260

11030A–PMAAC–13-Sep-10

AT73C260

7.5.3

Voltage Supplied on P_VCC

When V_BUSis greater than 3.5V nominal, an internal LDO Follower provides a voltage source on

pin P_VCC. The voltage on pin P_VCCis equal to the voltage on pin P_VRF

.

P_VCCLDO is in accordance with FTA Test 3GPP - 27.17.2.1 dedicated for Subscriber Iden-

tity Module (SIM) application.

Table 7-8.

Symbol

V_BUS

P_VCCLDO Characteristics

Parameter

Comments

Min

Typ

Max

Units

Supply Input Voltage

On pin V_BUS

4.0

5.0

5.5

V

- Enabled when V_BUSis greater

than 3.5V typical.

(1)

P_VCC

Output Voltage

- Disabled when V_BUSgoes below

3.15V typical

1.55

--

3.6

V

- 1.55V < P_VRF< 3.6V

V_OFF

I_O

Follower Offset Voltage

Output Current

P

_VCC- P_VRF

-40

0

--

40

70

mV

mA

• V_BUS> 4.5V

Static Load Regulation

--

10

--

mV

• I_O= 10% to 90%

Δ_{VDD_IL}

• V_BUS> 4.5V

Dynamic Load Regulation

• I_O= 10% to 90%

• T_RISE= T_FALL= 5µs

30

• V_BUSfrom 4.3V to 5.5V

• I_O= Max

--

20

mV

Δ_{VDD_VIN}

Static Line Regulation

• V_BUSfrom 4.0V to 5.5V

• I_O= 7 mA

• V_BUSis set at 5.0V

• P_VRF0V to 1.8V with T_RISE= 5µs

• I_O= 10mA

--

20

32

--

35

50

µs

• V_OUT> 1.62V

T_START

Start-up Time

• V_BUSis set at 5.0V

• P_VRF0V to 3.0V with T_RISE= 5µs

• I_O= 10mA

• V_OUT> 2.7V

• V_BUSis set at 5.0V

• P_VRF3.0V to 0V with T_FALL= 5µs

• R_LOAD= 1KΩ. C_OUT=220nF/ X5R

• V_OUT< 0.4V

525

225

(2)

T_STOP

Power-Off Time

• V_BUSis set at 5.0V

• P_VRF3.0V to 0V with T_FALL= 5µs

• I_O= 7mA. C_OUT=220nF/ X5R

• V_OUT< 0.4V

--

Notes: 1. When V_BUSis present and greater than V_TP, 10kΩ pull down is removed on H_VCCand on P_VCCand LDO are started. When

V_BUSgoes below V_TP, a 10kΩ pull down is connected on H_VCCand P_VCCand LDO are disabled. When V_BUS= 0V and H_VCC

and P_VCCwithin their normal range the 10kΩ pull down are disconnected.

2. Off time is described in Section 9.3.4 on page 16. To reduce T_STOPtime an external reisitor is recommended. This value

depends on C_OUTand load applied on the system.

9

11030A–PMAAC–13-Sep-10

8. Components List.

Table 8-1.

AT73C260 External Components List

Component Name

Component Type

Resistor

Value / Tol.

33 Ω +/- 5%

10 Ω +/- 5%

10kΩ +/- 1%

100kΩ +/- 1%

22kΩ +/- 5%

22pF +/- 20%

1µF +/- 20%

220nF +/- 20%

Reference

R₁, R₂

R₃

CRG0402J33R

CRG0603J10R

Resistor

R₄

Resistor

CPF0402F10KE1

CPF0603F100KC1

CRG0402J22K

R₅

Resistor

R₆, R₇

C₁, C₂

C₃

Resistor

Ceramic Capacitor COG

Ceramic Capacitor X5R

C1005COG1H220J

C1005X5R0J105K

C1005X5R1C224KT

GRM1555C1H220JZ01

GRM155R60J105KE19

GRM155R60J224KE01

C₄

C₅

10

AT73C260

11030A–PMAAC–13-Sep-10

AT73C260

9. Functional Description

9.1

AT73C260’s Upstream and Downstream Ports

This section relates to either upstream or downstream ports with digital, IC_USB1.0 or USB2.0

section 7 electrical characteristics.

Table 9-1 shows the configuration of the upstream and downstream ports based on pins 14, 15

and 16 voltages.

• 0 is when the pin is connected to GND.

• 1 is when the pin is connected to H_VCC

.

Table 9-1.

Upstream and Downstream Ports

M<2>

M<1>

M<0>

Upstream

Port

Downstream

Port

Pin 14

Pin 15

Pin 16

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Digital

IC_USB1.0

Digital

IC_USB1.0

Digital

IC_USB1.0

Not Used

Digital

Not Used

IC_USB1.0

Section 7

IC_USB1.0

Section 7 ⁽¹⁾/ IC_USB1.0

Notes:1. P_VCCis set to 3.3V and external pull down resistors of 22kΩ ± 5% are connected, one between

PDP and GND and the other between PDM and GND.

11

11030A–PMAAC–13-Sep-10

9.2

AT73C260 Pull Up and Pull Down Resistors

Pull down resistors R_PDPand R_PDHvalues and behaviors comply with the IC_USB1.0 specifica-

tion published by the USB-IF.

9.2.1

AT73C260 Upstream Port Connectivity (H_VCC, H_DP, H_DM):

The host, IC_USB1.0 or USB2.0 section 7, is connected to the AT73C260’s upstream port.

When in IC_USB 1.0 R_PU2is selected.

When in USB2.0 section 7 R_PU1is selected.

•

9.2.2

AT73C260 Downstream Port Connectivity (P_VCC, P_DP, P_DM):

The peripheral, IC_USB1.0 or USB2.0 section 7, is connected to the AT73C260’s downstream

port.

•

An IC_USB1.0 peripheral is connected to the AT73C260’s downstream port.

An USB2.0 section 7 peripheral is connected to the AT73C260’s downstream port with

external pull down resistors as per precedent note ⁽¹⁾(See Table 9-1 on page 11).

Figure 9-1. AT73C260 Downstream and Upstream Ports

HVCC

PVCC

SW2

SW1

RPU1

RPU2

HDP

HDM

PDP

PDM

RPDP

SW3

RPDH

SW6

SW5

SW4

GND

12

AT73C260

11030A–PMAAC–13-Sep-10

AT73C260

9.3

Theory Of Operation

9.3.1

Remote Wake Up

The AT73C260 does not support remote wake up.

9.3.2

Slew Rate Control

When the AT73C260 drives an IC_USB bus section the output buffer on each line (Figure 9-2)

drives the pin with a slew rate control to minimize radiated EMI.

Figure 9-2. AT73C260 Output Buffer

Output buffers

CT = 18pF

TxIC_DP

C

T

TxIC_DM

Figure 9-3. AT73C260 Output Buffer Slew Rate

90%

10%

t_R

t_F

Note:

See Table 7-3 on page 7 for timing values.

13

11030A–PMAAC–13-Sep-10

9.3.3

Attach

Figure 9-4. AT73C260 Attach Sequence

HDP

Reset

idle

PDP

idle

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

In the following paragraphs, two different attach sequences are described according the mode

selected. Mode VCC and Mode S7_ICC_TK are explained.

9.3.3.1

Attach Sequence ”Mode VCC”

The following sequence describes the AT73C260 with an IC_USB upstream connection and an

IC_USB downstream connection (Mode VCC). For hardware connection refers to “Mode: Volt-

age Class Converter: VCC” on page 34.

• H_VCCand P_VCCare present and are in their dedicated voltage range.

• R_PU1is not used (SW1 always open). (For more information about switches, refers to Figure

9-1 on page 12)

• Before T₁, R_PDPand R_PDHare connected. R_PU2is disconnected. (For more information about

resistors, refers to Figure 9-1 on page 12)

• T₁: Peripheral event.

Beyond T₁, PDP is driven high by the IC_USB peripheral’s pull-up resistor.

• T₂: AT73C260 event.

The signal is above V_IH. The AT73C260 verifies that the condition PDP is high lasts more

than 200ns nominal. This information is passed to the AT73C260’s Host side.

• T₃: AT73C260 event.

Beyond T₃, R_PU2(2k nominal) is connected while R_PDPon HDP is disconnected.

• T₄: Host event.

From T₄the host drives the reset with SE0.

• T₅: AT73C260 event.

It takes 40 ns nominal beyond T₄for PDP to be driven low.

• T₆: AT73C260 event.

During reset the AT73C260 detects a SE0 for more than 1µs nominal. Beyond T₆both

R

_PDHare disconnected.

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AT73C260

11030A–PMAAC–13-Sep-10

AT73C260

• T₇: Host event.

Host stops driving SE0. The AT73C260 with its 2k nominal resistor, pulls-up HDP.

• T₈: AT73C260 event.

The signal is above V_IH.(on HDP)

• T₉: AT73C260 event.

40ns nominal after T₈. From T₉, the AT73C260 drives high until V_IH(on PDP) is reached

plus 100ns nominal until T₁₁.

• T₁₀: AT73C260 event.

Between T₇and T₁₀. HDP is pulled-up with 2k nominal until V_IH(on HDP) is reached plus

100ns. At T₁₀R_PU2becomes 50k nominal.

9.3.3.2

Attach Sequence Mode S7_ICC_TK

The following sequence describes the AT73C260 with an USB2.0 section 7 upstream connec-

tion and an IC_USB downstream connection (Mode S7_ICC_TK). For hardware connection

refers to “Mode: USB2.0 section 7 to IC_USB1.0 with PVCC fixed by PVRF: S7_ICC_TK” on

page 38.

• H_VCC= 3.3V and P_VCCare present and are in their dedicated voltage range.

• R_PU2is not used (SW2 always open). R_PDPare not used (SW3 and SW4 always open).(For

more information about switches, refers to Figure 9-1 on page 12)

• Before T₁, R_PDHare connected. R_PU2is disconnected. (For more information about resistors,

refers to Figure 9-1 on page 12)

• T₁: Peripheral event.

Beyond T₁, PDP is driven high by the IC_USB peripheral’s pull-up resistor.

• T₂: AT73C260 event.

The signal is above V_IH. The AT73C260 verifies that the condition PDP is high lasts more

than 200ns nominal. This information is passed to the AT73C260’s Host side.

• T₃: AT73C260 event.

Beyond T₃, R_PU11.2k nominal, is connected.

• T₄: Host event.

From T₄the host drives the reset with SE0.

• T₅: AT73C260 event.

R_PU1becomes 2.2k nominal. It takes 40 ns nominal beyond T₄for PDP to be driven low.

• T₆: AT73C260 event.

During reset the AT73C260 detects a SE0 for more than 1µs nominal. Beyond T₆both

R_PDHare disconnected.

• T₇: Host event.

Host stops driving SE0. The AT73C260 with its 2k nominal resistor, pulls-up HDP.

• T₈: AT73C260 event.

The signal is above V_IH.(on HDP)

15

11030A–PMAAC–13-Sep-10

• T₉: AT73C260 event.

40ns nominal after T₈. From T₉, the AT73C260 drives high until V_IH(on PDP) is reached

plus 100ns nominal until T₁₁.

• T₁₀: AT73C260 event.

Between T₇and T₁₀. HDP is pulled-up with 2.2k nominal until V_IH(on HDP) is reached plus

100ns. At T₁₀R_PU1becomes 1.2k nominal.

9.3.4

PVRF Driving PVCC

Figure 9-5. AT73C260 PVRF driving PVCC

PVRF

T_OFF

PVCC

90%

10%

T_START

T_STOP

When V_BUS, pin 4, is providing power to the USB UICC via the LDOs, the voltage on P_VCC(pin

12) is following the voltage on P_VRF(pin 9).

T_STARTis mostly related to the capacitive load on P_VCCand the strength of the LDO’s PMOS.

T_STARTas mentioned in Table 7-8 on page 9 is less than 50µs.

T_STOPis mostly related to the load on P_VCCsince the LDO’s PMOS is off when starts T_OFF

.

Certain applications may require P_VCCto fall below a minimum voltage in less than T_OFFand

guarantee a Power On Reset sequence in the USB UICC when P_VCCis set again. For these

applications an extra load, such as a resistor across P_VCCand GND in parallel with the USB

UICC and the decoupling capacitor C5 may be required.

As an example, for T_OFF= 0.4ms, a decoupling capacitor C5 of 220nF and an USB UICC in

standby (less than 100µA) the extra resistor shall be less than 1kΩ.

16

AT73C260

11030A–PMAAC–13-Sep-10

AT73C260

9.3.5

Reset Signaling

At the end of the Reset signaling on AT73C260’s host side and peripheral sides the pulled up

data line voltage has to reach V_{IH_MIN}in less than T_DDIS, see Figure 9-6. If it is not the case, the

host may see a disconnect condition.

Reset is forced during T2.

If a 100kΩ pull up resistor is used while the capacitive load is more than 20pF, the time constant

is greater than 2µs. To avoid any disconnect condition, the AT73C260 pulls up the appropriate

data line during about one bit duration with extra strength making the disconnect condition

unlikely.

Figure 9-6. AT73C260 Reset Signaling

IC_DP

VIH_MIN

IC_DM

Less than TDDIS min (2µs)

Reset signaling

T1

T2

9.3.6

Resume Signaling

The AT73C260 supports resume signaling. The timings on IC_DP and IC_DM are those on HDP

and HDM delayed by 40ns nominal.

Figure 9-7. AT73C260 Resume Signaling

One J state

EOP (Two Low Speed bit time)

HDP

SOF

T

DRSMND (≥ 20ms minimum)

HDM

3ms max

Idle, J state

The Hub signals resume to the UICC by forcing a K state during TDRSMDN(≥ 20ms)

Notes: 1. J state means that HDP = 1 and HDM = 0.

2. K state means that HDP = 0 and HDM = 1.

3. SOF = Start Of Frame

17

11030A–PMAAC–13-Sep-10

9.4

General Description

The AT73C260 covers four main functions:

•

PHY (described in Section 9.4.3 on page 20)

Bridge (described in Section 9.4.4 on page 30)

IC_USB1.0 Voltage Class Converter (described in Section 9.4.5 on page 34)

Bridge with LDOs for two specific applications (described in Section 9.4.6 on page 36),

and one extra function from many described as an example where the AT73C260 is an inter-

chip PHY in a digital implementation (FPGA) of a peripheral.

9.4.1

Application Modes

The following Table 9-2 lists the applications and pin settings.

Table 9-2.

Mode

AT73C260 Application Modes ⁽⁴⁾

Application

M<2>

M<1>

M<0>

Function

Pin 14

Pin 15

Pin 16

PHY_6_SE0

PHY_4_SE0

PHY_6_DPDM

PHY_4_DPDM

PHY_3_ULPI

S7_ICC

Digital six wires unidirectional DAT_SE0 to IC_USB1.0

Digital four wires bidirectional DAT_SE0 to IC_USB1.0

Digital six wires unidirectional DP_DM to IC_USB1.0

Digital four wires bidirectional DP_DM to IC_USB1.0

Digital three wires bidirectional (DAT, SE0, OE_N) to IC_USB1.0

USB2.0 section 7 without cable to IC_USB1.0

0

1

0

1

0

1

0

1

0

1

0

PHY

Bridge

USB2.0 section 7 with cable to IC_USB1.0, LDOs ON

VCC driven by the Digital Base Band ⁽²⁾

Bridge with

LDOs

S7_ICC_DBB

1

0

USB2.0 section 7 with cable to IC_USB1.0, LDOs ON

VCC fixed by PVRF ⁽³⁾

Bridge with

LDOs

S7_ICC_TK

ICC_S7

1

0

1

IC_USB1.0 to USB2.0 section 7 ⁽¹⁾

Bridge

Voltage

Class

VCC

IC_USB1.0 to IC_USB1.0

1

Converter

Notes: 1. 22kΩ Pull down on pins 10 and 11

2. PC with Digital Base Band

3. Token

4. M<2:0> code”100” is not used

18

AT73C260

11030A–PMAAC–13-Sep-10

AT73C260

9.4.2

Function Descriptions

9.4.2.1

Downstream Port PHY:

A set of digital signals generated by an FPGA or an ASIC with I/O powered by a first power sup-

ply drive the AT73C260 which converts these signals into analog signals IC_DP and IC_DM as

per IC_USB1.0 powered by a second power supply.

9.4.2.2

Bridge:

Two cases are supported: USB2.0 section 7 to IC_USB1.0 and IC_USB1.0 to USB2.0 section 7.

•

USB2.0 section 7 to IC_USB1.0

Downstream D+ and D- signals drive the AT73C260 which converts these signals into analog

signals IC_DP and IC_DM as per IC_USB1.0.

•

IC_USB1.0 to USB2.0 section 7

Downstream IC_USB1.0 signals drive the AT73C260 which converts these signals into analog

signals D+ and D- as per USB2.0 section 7.

9.4.2.3

9.4.2.4

Voltage Class Converter:

The following applications enable communications between an IC_USB1.0 compliant down-

stream port with a first voltage class V₁and an IC_USB1.0 compliant peripheral with a second

voltage class V_CC

.

The range of the supplies, respectively Host and Device, are: H_VCC(1.55V - 3.6V) and P_VCC

(1.55V - 3.6V)

Bridge with LDOs:

Two cases are supported: one for PC with embedded Digital Base Band and one for Token.

•

PC with embedded Digital Base Band

The AT73C260 provides up to 70mA from V_BUSto the UICC under the V_CCrequired by the DBB.

Also the AT73C260 converts D+ and D- signals into analog signals IC_DP and IC_DM as per

IC_USB1.0.

•

Token

The AT73C260 provides up to 70mA from V_BUSto the UICC under V_CC

.

This voltage is generated by P_VCCLDO and set by an external resistor bridge supplied by 3.3V

voltage reference (H_VCC).

Also the AT73C260 converts D+ and D- signals into analog signals IC_DP and IC_DM as per

IC_USB1.0.

19

11030A–PMAAC–13-Sep-10

9.4.3

Downstream Port PHY

In mobile applications, the USB UICC is handled by the user and special care should be taken in

the ESD protection on the downstream port facing the USB UICC. The AT73C260 downstream

port is protected against 4kV ESD.

Also, the host and the USB UICC may not be located on the same board with a flex connecting

the two PCBs. The AT73C260 should be located next to the host. The flex is between the

AT73C260’s downstream port and the USB UICC upstream port. The AT73C260 downstream

port has slew rate control on both P_DMand P_DPto minimize the radiated EMI.

Pins V_BUSand P_VRFare connected to GND and LDO outputs are isolated and in standby.

9.4.3.1

Mode: Digital six wires unidirectional DAT_SE0 to IC_USB1.0: PHY_6_SE0

Description

This application allows a Host, ASIC or FPGA, with the digital unidirectional Philips

PDIUSBP11A (MODE pin = 0) six wires interface to drive an IC_USB downstream port.

Figure 9-8. PHY_6_SE0 Block Diagram

6

IC_USB_1.0

ASIC

FPGA

AT73C260

DAT_SEO

Hardware Configuration

In the following tables, the pin and the hardware configuration are described.

Table 9-3.

AT73C260 Hardware Configuration

M<2>

M<1>

M<0>

Mode

Pin 14

Pin 15

Pin 16

Application

Digital six wires unidirectional DAT_SE0 to

IC_USB1.0

PHY_6_SE0

0

Table 9-4.

AT73C260 Pin description and configuration

Pin Number Pin Name

I/O Type

Polarity

Function

Supply by ASIC FPGA I/O Ring (1.55V

to 3.6V)

1

HVCC

A-Power

--

2

3

TX_DAT

TX_SEO

VBUS

D-Input

A-Input

D-Output

D-Input

A-Input

D-I/O

--

Unidirectional Transmit Data

Unidirectional Transmit Single Ended 0

Not Used and Connected to Ground

Unidirectional Receiving DM

Unidirectional Receiving DP

Tx Enable N

4

--

6

RX_DM

RX_DP

TX_ENABLE_N

PVRF

--

7

--

8

Low

--

9

Connected to Ground

10

PDM

--

Downstream Port for USB Device

20

AT73C260

11030A–PMAAC–13-Sep-10

AT73C260

Table 9-4.

AT73C260 Pin description and configuration

Pin Number Pin Name

I/O Type

Polarity

Function

11

12

PDP

D-I/O

--

Downstream Port for USB Device

Same as peripheral’s power (1.8V or 3V

typical)

PVCC

A-Power

--

13

RX_RCV

M<2:0>

D-Output

D-Inputs

--

Unidirectional Receiving RCV

Connected to Ground

14, 15, 16

Low

Application Diagram

In the following figure, the hardware configuration is described.

Figure 9-9. AT73C260: PHY - 6 wires DAT_SE0 to IC_USB1.0 - application diagram

9

P

VRF

AT73C260

1

12

HVCC

GND

PVCC

H

VCC

BUS

PVCC

C

5

C

4

Vref

3.3Volt

4

13

6

ASIC/FPGA : 6 WIRES DAT_SE0

V

DIGITAL WRAPPER

rx_rcv

rx_dm

RCV

HDMO

HDPO

OE_N

HDP

VCC

10

rx_dm

PDM

IC_DM

7

rx_dp

8

tx_enable_n

2

11

IC_DP

tx_dat

tx_se0

tx_dat

tx_se0

PDP

3

HDM

M<2> M<1> M<0> GND

14 15 16

5

Note:

All external components are defined in component list Table 8-1 on page 10

21

11030A–PMAAC–13-Sep-10

9.4.3.2

Mode: Digital four wires bidirectional DAT_SE0 to IC_USB1.0: PHY_4_SE0

Description

This application allows a Host, ASIC or FPGA, with the digital bidirectional UTMIfs, DAT_SE0,

four wires interface to drive an IC_USB downstream port.

Figure 9-10. PHY_4_SE0 Block Diagram

4

IC_USB_1.0

ASIC

FPGA

AT73C260

DAT_SEO

Hardware Configuration

In the following tables, the pin and the hardware configuration are described.

Table 9-5.

AT73C260 Hardware Configuration

M<2>

M<1>

M<0>

Mode

Pin 14

Pin 15

Pin 16

Application

Digital four wires bidirectional DAT_SE0 to

IC_USB1.0

PHY_4_SE0

0

H_VCC

Table 9-6.

AT73C260 Pin description and configuration

Pin Number Pin Name

I/O Type

Polarity Function

Supply by ASIC FPGA I/O Ring (1.55V to

3.6V)

1

HVCC

A-Power

--

2

3

TX_DAT/RX_DP

TX_SE0/RX_DM

VBUS

D-I/O

--

Bidirectional Rx_Dp/Tx_Data

Bidirectional Rx_DM/Tx_Single Ended 0

Not Used and Connected to Ground

Not Connected

4

A-Input

D-Output

D-Input

A-Input

D-I/O

--

6

HDMO

HiZ

Low

--

7

HDPO

Not Connected

8

TX_ENABLE_N

PVRF

Tx Enable N

9

Connected to Ground

10

11

PDM

--

Downstream Port for USB Device

PDP

D-I/O

--

Same as peripheral’s power (1.8V or 3V

typical)

12

PVCC

A-Power

--

13

14, 15

16

RX_RCV

M<2:1>

M<0>

D-Output

D-Inputs

D-Input

--

Unidirectional Receiving RCV

Connected to Ground

Connected to H_VCC

Low

High

22

AT73C260

11030A–PMAAC–13-Sep-10

AT73C260

Application Diagram

In the following figure, the hardware configuration is described.

Figure 9-11. AT73C260: PHY - 4 wires DAT_SE0 to IC_USB1.0 - application diagram

9

P

VRF

AT73C260

1

12

HVCC

GND

PVCC

H

V

VCC

BUS

PVCC

C

5

C

4

Vref

3.3Volt

4

ASIC/FPGA : 4 WIRES DAT_SE0

DIGITAL WRAPPER

13

rx_rcv

rx_dm

RCV

HDMO

HDPO

OE_N

HDP

VCC

6

nc

10

PDM

IC_DM

7

nc

rx_dp

8

2

3

tx_enable_n

tx_dat/rx_dp

tx_se0/rx_dm

tx_enable_n

11

IC_DP

tx_dat

tx_se0

PDP

HDM

M<2> M<1> M<0> GND

14 15 16

HVCC

5

Note:

All external components are defined in component list Table 8-1 on page 10

23

11030A–PMAAC–13-Sep-10

9.4.3.3

Mode: Digital six wires unidirectional DP_DM to IC_USB1.0: PHY_6_DPDM

Description

This application allows a Host, ASIC or FPGA, with the digital unidirectional Philips

PDIUSBP11A (MODE pin = 1) six wires interface to drive an IC_USB downstream port.

Figure 9-12. PHY_6_DPDM Block Diagram

6

IC_USB_1.0

ASIC

FPGA

AT73C260

DP_DM

Hardware Configuration

In the following tables, the pin and the hardware configuration are described.

Table 9-7.

AT73C260 Hardware Configuration

M<2>

M<1>

M<0>

Mode

Pin 14

Pin 15

Pin 16

Application

Digital six wires unidirectional DP_DM to

IC_USB1.0

PHY_6_DPDM

0

H_VCC

0

Table 9-8.

AT73C260 Pin description and configuration

Pin Number Pin Name

I/O Type

Polarity Function

Supply by ASIC FPGA I/O Ring (1.55V

to 3.6V)

1

HVCC

A-Power

--

2

3

TX_DP

TX_DM

VBUS

D-Input

A-Input

D-Output

D-Input

A-Input

D-I/O

--

Unidirectional Tx DP

Unidirectional Tx DM

Not Used and Connected to Ground

Unidirectional Rx DM

Unidirectional Rx DP

Tx Enable N

4

--

6

RX_DM

RX_DP

TX_ENABLE_N

PVRF

--

7

--

8

Low

--

9

Connected to Ground

Downstream Port for USB Device

10

11

PDM

--

PDP

D-I/O

--

Same as peripheral’s power (1.8V or 3V

typical)

12

PVCC

A-Power

--

13

14

15

16

RX_RCV

M<2>

D-Output

D-Input

--

Unidirectional Receiving RCV

Connected to Ground

Connected to H_VCC

Low

High

Low

M<1>

M<0>

Connected to Ground

24

AT73C260

11030A–PMAAC–13-Sep-10

AT73C260

Application Diagram

In the following figure, the hardware configuration is described.

Figure 9-13. AT73C260: PHY - 6 wires DP_ DM to IC_USB1.0 - application diagram

9

P

VRF

AT73C260

1

12

HVCC

GND

PVCC

C

4

H

VCC

BUS

PVCC

C

5

Vref

3.3Volt

4

13

6

ASIC/FPGA : 6 WIRES DP_DM

V

DIGITAL WRAPPER

rx_rcv

rx_dm

rx_dp

rx_rcv

rx_dm

RCV

HDMO

HDPO

OE_N

HDP

VCC

10

PDM

IC_DM

7

rx_dp

8

tx_enable_n

tx_dp

tx_enable_n

2

11

IC_DP

tx_dat

tx_se0

PDP

3

tx_dm

HDM

M<2> M<1> M<0> GND

14 15 16

5

HVCC

Note:

All external components are defined in component list Table 8-1 on page 10

25

11030A–PMAAC–13-Sep-10

9.4.3.4

Mode: Digital four wires bidirectional DP_DM to IC_USB1.0: PHY_4_DPDM

Description

This application allows a Host, ASIC or FPGA, with the digital bidirectional UTMIfs, DP_DM, four

wires interface to drive an IC_USB downstream port.

Figure 9-14. PHY_4_DPDM Block Diagram

4

IC_USB_1.0

ASIC

FPGA

AT73C260

DP_DM

Hardware Configuration

In the following tables, the pin and the hardware configuration are described.

Table 9-9.

AT73C260 Hardware Configuration

M<2>

M<1>

M<0>

Mode

Pin 14

Pin 15

Pin 16

Application

Digital four wires bidirectional DP_DM to

IC_USB1.0

PHY_4_DPDM

0

H_VCC

Table 9-10. AT73C260 Pin description and configuration

Pin Number Pin Name

I/O Type

Polarity

Function

Supply by ASIC FPGA I/O Ring (1.55V

to 3.6V)

1

HVCC

A-Power

--

2

3

TX_DP/RX_DP

TX_DM/RX_DM

VBUS

D-I/O

--

Bidirectional Tx_Dp/Dx_DP

Bidirectional Tx_Dm/Dx_DM

Not Used and Connected to Ground

Not Connected

4

A-Input

D-Output

D-Input

A-Input

D-I/O

--

6

HDMO

HiZ

Low

--

7

HDPO

Not Connected

8

TX_ENABLE_N

PVRF

Tx Enable N

9

Connected to Ground

10

11

PDM

--

Downstream Port for USB Device

PDP

D-I/O

--

Same as peripheral’s power (1.8V or 3V

typical)

12

PVCC

A-Power

--

13

14

RX_RCV

M<2>

D-Output

D-Input

--

Unidirectional Receiving RCV

Connected to Ground

Connected to H_VCC

Low

High

15,16

M<1:0>

D-Inputs

26

AT73C260

11030A–PMAAC–13-Sep-10

AT73C260

Application Diagram

In the following figure, the hardware configuration is described.

Figure 9-15. AT73C260: PHY - 4 wires DP_ DM to IC_USB1.0 - application diagram

9

P

VRF

AT73C260

C

4

1

12

HVCC

GND

PVCC

H

VCC

BUS

PVCC

C

5

Vref

3.3Volt

4

ASIC/FPGA : 4 WIRES DP_DM

V

DIGITAL WRAPPER

13

rx_rcv

rx_dm

RCV

HDMO

HDPO

OE_N

HDP

VCC

6

nc

10

PDM

IC_DM

7

nc

rx_dp

8

2

3

tx_enable_n

tx_dp/rx_dp

tx_dm/rx_dm

tx_enable_n

11

IC_DP

tx_dat

tx_se0

PDP

HDM

M<2> M<1> M<0> GND

14 15 16

5

HVCC

Note:

All external components are defined in component list Table 8-1 on page 10

27

11030A–PMAAC–13-Sep-10

9.4.3.5

Mode: Digital three wires bidirectional (DAT, SE0, OE_N) to IC_USB1.0: PHY_3_ULPI

Description

This application allows a Host, ASIC or FPGA, with the digital bidirectional ULPI serial support,

DAT, SE0, and OE_N, three wires interface to drive an IC_USB downstream port.

Figure 9-16. PHY_3_ULPI Block Diagram

3

IC_USB_1.0

ASIC

FPGA

AT73C260

ULPI

Hardware Configuration

In the following tables, the pin and the hardware configuration are described.

Table 9-11. AT73C260 Hardware Configuration

M<2>

M<1>

M<0>

Mode

Pin 14

Pin 15

Pin 16

Application

Digital three wires bidirectional DAT, SE0, OE_N to

IC_USB1.0

PHY_3_ULPI

H_VCC

0

H_VCC

Table 9-12. AT73C260 Pin description and configuration

Pin Number Pin Name

I/O Type

Polarity

Function

Supply by ASIC FPGA I/O Ring

(1.55V to 3.6V)

1

HVCC

A-Power

--

2

3

RX_RCV/TX_DAT

RX_SE0/TX_SE0

VBUS

D-I/O

--

Bidirectional Rx_RCV / Tx_Data

Bidirectional Rx_SE0/Tx_SE0

Not Used and Connected to Ground

Not Connected

4

A-Input

D-Output

D-Input

A-Input

D-I/O

--

6

HDMO

HiZ

Low

--

7

HDPO

Not Connected

8

TX_ENABLE_N

PVRF

Tx Enable N

9

Connected to Ground

10

11

PDM

--

Downstream Port for USB Device

PDP

D-I/O

--

Same as peripheral’s power (1.8V or

3V typical)

12

PVCC

A-Power

--

13

14

15

16

RCV

D-Output

D-Input

HiZ

High

Low

High

Not Connected

M<2>

M<1>

M<0>

Connected to H_VCC

Connected to Ground

Connected to H_VCC

D-Inputs

28

AT73C260

11030A–PMAAC–13-Sep-10

AT73C260

Application Diagram

In the following figure, the hardware configuration is described.

Figure 9-17. AT73C260: PHY - 3 wires DAT, SE0, OE_N to IC_USB1.0 - application diagram

9

P

VRF

AT73C260

1

12

HVCC

GND

PVCC

C

4

H

V

VCC

BUS

PVCC

C

5

Vref

3.3Volt

4

ASIC/FPGA : 3 WIRES DAT, SE0, OE_N

DIGITAL WRAPPER

13

nc

rx_rcv

rx_dm

RCV

HDMO

HDPO

OE_N

HDP

VCC

6

nc

10

PDM

IC_DM

7

nc

rx_dp

8

2

3

tx_enable_n

11

IC_DP

rx_rcv/tx_dat

rx_se0/tx_se0

tx_dat

tx_se0

PDP

HDM

M<2> M<1> M<0> GND

14 15 16

5

HVCC

Note:

All external components are defined in component list Table 8-1 on page 10

29

11030A–PMAAC–13-Sep-10

9.4.4

Bridge

Pins V_BUSand P_VRFare connected to GND and LDO outputs are isolated and in standby.

Pin OE_N is connected to H_VCC

The following applications enable communications between.

S7_ICC: an USB2.0 section 7 compliant downstream port and an IC_USB1.0 compliant

peripheral

.

•

ICC_S7: an IC_USB1.0 compliant downstream port and an USB2.0 section 7 compliant

peripheral

9.4.4.1

Mode: USB2.0 section 7 downstream port to IC_USB1.0 peripheral: S7_ICC

Description

This application establishes a communication path between an USB2.0 section 7 downstream

port and an IC_USB peripheral.

An external 3.3V voltage source is applied on H_VCC. AT73C260’s D+ and D- input pins are com-

pliant with USB2.0 core specification.

This application is particularly well suited for mobile devices where the host may not have an

IC_USB1.0 downstream port.

Figure 9-18. S7_ICC Block Diagram

USB 2.0

IC_USB_1.0

AT73C260

Section 7

Hardware Configuration

In the following tables, the pin and the hardware configuration are described.

Table 9-13. AT73C260 Hardware Configuration

M<2>

M<1>

M<0>

Mode

Pin 14

Pin 15

Pin 16

Application

USB2.0 section 7 downstream port to IC_USB1.0

peripheral

S7_ICC

H_VCC

0

Table 9-14. AT73C260 Pin description and configuration

Pin Number Pin Name

I/O Type

A-Power

D-I/O

Polarity

Function

1

2

3

4

6

7

8

HVCC

D+

--

Supplied by host at 3.3V

Bidirectional D+

D-

D-I/O

--

Bidirectional D-

VBUS

HDMO

HDPO

OE_N

A-Input

D-Output

D-Input

--

Not Used and Connected to Ground

Not Connected

HiZ

High

Not Connected

Connected to H_VCC

30

AT73C260

11030A–PMAAC–13-Sep-10

AT73C260

Table 9-14. AT73C260 Pin description and configuration

Pin Number Pin Name

I/O Type

A-Input

D-I/O

Polarity

Function

9

PVRF

PDM

PDP

--

Connected to Ground

10

11

Downstream Port for USB Device

D-I/O

Same as peripheral’s power (1.8V or 3V

typical)

12

PVCC

A-Power

--

13

14

15

16

RCV

D-Output

D-Input

HiZ

High

Low

Not Connected

M<2>

M<1>

M<0>

Connected to H_VCC

Connected to Ground

D-Inputs

Application Diagram

In the following figure, the hardware configuration is described.

Figure 9-19. AT73C260: Bridge - USB2.0 section 7 downstream port to IC_USB1.0 -application diagram

9

P

VRF

AT73C260

1

12

HVCC

GND

PVCC

C

5

H

V

VCC

BUS

PVCC

C

4

Vref

3.3Volt

4

13

nc

RCV

HDMO

HDPO

OE_N

HDP

VCC

6

nc

10

PDM

IC_DM

7

nc

8

2

3

HVCC

11

IC_DP

D +

D -

PDP

HDM

M<2> M<1> M<0> GND

14 15 16

5

HVCC

Note:

All external components are defined in component list Table 8-1 on page 10

31

11030A–PMAAC–13-Sep-10

9.4.4.2

Mode: IC_USB1.0 downstream port to USB2.0 section 7 peripheral: ICC_S7

Description

This application establishes a communication path between an IC_USB1.0 downstream port

and an USB2.0 section 7 peripheral.

Figure 9-20. ICC_S7 Block Diagram

IC_USB_1.0

USB 2.0

µC/ASIC

AT73C260

Section 7

Hardware Configuration

In the following tables, the pin and the hardware configuration are described.

Table 9-15. AT73C260 Hardware Configuration

M<2>

M<1>

M<0>

Mode

Pin 14

Pin 15

Pin 16

Application

IC_USB1.0 downstream port to USB2.0 section 7

peripheral

ICC_S7

H_VCC

Table 9-16. AT73C260 Pin description and configuration

Pin Number Pin Name

I/O Type

Polarity

Function

Same as host I/O Ring Power (1.8V to

3V typical)

1

HVCC

A-Power

--

2

3

IC_DP

IC_DM

VBUS

HDMO

HDPO

OE_N

PVRF

D-

D-I/O

--

Bidirectional IC_DP

Bidirectional IC_DM

Not Used and Connected to Ground

Not Connected

4

A-Input

D-Output

D-Input

A-Input

D-I/O

--

6

HiZ

High

--

7

Not Connected

8

Connected to H_VCC

9

Connected to Ground

Downstream Port for USB Device

Supplied at 3.3V

10

11

12

13

14

15

16

--

D+

D-I/O

--

PVCC

RCV

A-Power

D-Output

D-Input

D-Inputs

--

HiZ

High

Not Connected

M<2>

M<1>

M<0>

Connected to H_VCC

32

AT73C260

11030A–PMAAC–13-Sep-10

AT73C260

Application Diagram

In the following figure, the hardware configuration is described.

Figure 9-21. AT73C260: Bridge - IC_USB1.0 downstream port to USB2.0 section 7 - application diagram

9

PVRF

AT73C260

1

12

H

VCC

PVCC

C

5

C

4

H

VCC

BUS

PVCC

GND

Vref

3.3Volt

4

V

13

nc

RCV

HDMO

HDPO

OE_N

HDP

6

nc

10

D -

PDM

R

6

7

nc

8

2

3

H

VCC

11

D +

IC_DP

IC_DM

PDP

R

7

HDM

M<2> M<1> M<0> GND

14 15 16

5

H

VCC

Note:

R₆and R₇are defined in component list Table 8-1 on page 10

33

11030A–PMAAC–13-Sep-10

9.4.5

Mode: Voltage Class Converter: VCC

Description

Pins V_BUSand P_VRFare connected to GND and LDO outputs are isolated and in standby.

Pin OE_N is connected to H_VCC

.

The following applications enable communications between an IC_USB1.0 compliant down-

stream port with a first voltage class H_VCCand an IC_USB1.0 compliant peripheral with a second

voltage class P_VCC

.

Figure 9-22. Voltage Class Converter Block Diagram

IC_USB_1.0

ASIC

AT73C260

Hardware Configuration

In the following tables, the pin and the hardware configuration are described.

Table 9-17. AT73C260 Hardware Configuration

M<2>

M<1>

M<0>

Mode

Pin 14

Pin 15

Pin 16

Application

VCC

H_VCC

IC_USB1.0 to IC_USB1.0 Voltage Class Converter

Table 9-18. AT73C260 Pin description and configuration

Pin Number Pin Name

I/O Type

Polarity

Function

Same as host I/O Ring Power (1.8V to

3V typical)

1

HVCC

A-Power

--

2

3

IC_DP

IC_DM

VBUS

HDMO

HDPO

OE_N

PVRF

PDM

D-I/O

--

Bidirectional IC_DP

Bidirectional IC_DM

4

A-Input

D-Output

D-Input

A-Input

D-I/O

--

Connected to Ground

Not Connected

6

HiZ

High

--

7

Not Connected

8

Connected to H_VCC

9

Connected to Ground

Downstream Port for USB Device

10

11

--

PDP

D-I/O

--

Same as peripheral’s power (1.8V or 3V

typical)

12

PVCC

A-Power

--

13

14

15

16

RCV

D-Output

D-Input

HiZ

Not Connected

M<2>

M<1>

M<0>

High

Connected to H_VCC

D-Inputs

34

AT73C260

11030A–PMAAC–13-Sep-10

AT73C260

Application Diagram

In the following figure, the hardware configuration is described.

Figure 9-23. AT73C260: Voltage Class Converter - IC_USB1.0 to IC_USB1.0 - application diagram

9

P

VRF

AT73C260

1

12

HVCC

GND

PVCC

H

V

VCC

BUS

PVCC

C

4

C5

Vref

3.3Volt

4

13

nc

RCV

HDMO

HDPO

OE_N

HDP

VCC

6

nc

10

PDM

IC_DM

7

nc

8

2

3

HVCC

11

IC_DP

IC_DM

PDP

HDM

M<2> M<1> M<0> GND

14 15 16

5

HVCC

Note:

All external components are defined in component list Table 8-1 on page 10

35

11030A–PMAAC–13-Sep-10

9.4.6

Bridge With LDOs

LDOs are enabled.

AT73C260’s pin V_BUSis connected to the USB signal V_BUSthrough a low pass filter.

9.4.6.1

Mode: PC’s USB2.0 section 7 to IC_USB1.0 with VCC driven by the DBB: S7_ICC_DBB

Description

The PC’s Digital Base Band may not provide enough power to a USB UICC with mass storage.

The V_BUSpower supply voltage will make available that extra power, up to 70mA, through the

AT73C260’s LDO if needed by the USB UICC.

The PC’s Digital Base Band supplies on pin 9 the power sequence required by ETSI. The

AT73C260 buffers the signal on P_VRFto P_VCC. P_VCCsources power from V_BUSto V_CC

.

On the Host side H_VCCgenerates 3.3V from V_BUS

Figure 9-24. S7_ICC_DBB Block Diagram

DBB

.

ISO7816

VBUS

PVRF

PVCC

USB 2.0

IC_USB_1.0

Phone

µC/ASIC

AT73C260

Hardware Configuration

In the following tables, the pin and the hardware configuration are described.

Table 9-19. AT73C260 Hardware Configuration

M<2>

M<1>

M<0>

Mode

Pin 14

Pin 15

Pin 16

Application

PC’s USB2.0 section 7 to IC_USB1.0 with V_CC

driven by DBB

S7_ICC_DBB

H_VCC

0

Table 9-20. AT73C260 Pin description and configuration

Pin Number Pin Name

I/O Type

Polarity

Function

Delivered by AT73C260 from VBUS at

3.3V

1

HVCC

A-Output

--

2

3

4

6

7

8

9

D+

D-I/O

--

Bidirectional D +

D-

Bidirectional D -

VBUS

HDMO

HDPO

OE_N

PVRF

A-Input

D-Output

D-Input

A-Input

--

Supplied by USB Power Line

Not Connected

HiZ

High

--

Not Connected

Connected to H_VCC

Control by Digital Base Band

36

AT73C260

11030A–PMAAC–13-Sep-10

AT73C260

Table 9-20. AT73C260 Pin description and configuration

Pin Number Pin Name

I/O Type

D-I/O

Polarity

Function

10

11

PDM

PDP

--

Downstream Port for USB Device

D-I/O

Delivered by AT73C260 from VBUS and

control by DBB

12

PVCC

A-Output

--

13

14

15

16

RCV

D-Output

D-Input

HiZ

High

Low

Not Connected

M<2>

M<1>

M<0>

Connected to H_VCC

Connected to Ground

D-Inputs

Application Diagram

In the following figure, the hardware configuration is described.

Figure 9-25. AT73C260: Bridge with LDO - USB2.0 section 7 to IC_USB1.0 with V_CCdriven by DBB - application diagram

RST

Digital

Base Band

CLK

I/O

9

PVRF

AT73C260

1

12

HVCC

GND

H

VCC

BUS

PVCC

C

4

C

5

Vref

3.3Volt

R

3

4

VBUS

V

C

3

13

nc

RCV

HDMO

HDPO

OE_N

HDP

VCC

6

nc

10

PDM

IC_DM

7

nc

8

2

3

HVCC

D +

R

1

11

IC_DP

PDP

C

1

HDM

D -

C

2

R

2

M<2> M<1> M<0> GND

14 15 16

5

HVCC

Notes: 1. P_VCCLDO regulator is compliant with SIM FTA 27.17.2.1 Tests Series.

2. All external components are defined in component list Table 8-1 on page 10

37

11030A–PMAAC–13-Sep-10

9.4.6.2

Mode: USB2.0 section 7 to IC_USB1.0 with PVCC fixed by PVRF: S7_ICC_TK

Description

This is a token application where an USB UICC is connected to an USB2.0 section 7 down-

stream port.

The AT73C260’s LDOs supply H_VCCset at 3.3V and P_VCCset at the power supply voltage

required by the USB UICC.

This application establishes a communication path between a USB2.0 section 7 downstream

port and the USB UICC’s. The power to the USB UICC is provided by V_BUSusing an LDO able to

source up to 70mA.

This is the typical electrical schematic for a USB UICC used in a USB Token to be connected to

a USB2.0 series A receptacle.

The voltage divider R4/R5 generates for example 3.0V buffered by the LDO to the downstream

side of the transceiver and to the USB UICC P_VCC

.

This set up allows passing USB CV tests to the USB UICC under tests.

Figure 9-26. S7_ICC_TK Block Diagram (Token Application)

PVRF

PVCC

VBUS

USB 2.0

IC_USB_1.0

AT73C260

Hardware Configuration

In the following tables, the pin and the hardware configuration are described.

Table 9-21. AT73C260 Hardware Configuration

M<2>

M<1>

M<0>

Mode

Pin 14

Pin 15

Pin 16

Application

USB2.0 section 7 to IC_USB1.0 with P_VCCfixed by

P_VRF

S7_ICC_TK

H_VCC

0

Table 9-22. AT73C260 Pin description and configuration

Pin Number Pin Name

I/O Type

Polarity

Function

Delivered by AT73C260 from VBUS at

3.3V

1

HVCC

A-Output

--

2

3

4

6

7

D+

D-I/O

--

Bidirectional D +

D-

Bidirectional D -

VBUS

HDMO

HDPO

A-Input

D-Output

--

Supplied by USB Power Line

Not Connected

HiZ

Not Connected

38

AT73C260

11030A–PMAAC–13-Sep-10

AT73C260

Table 9-22. AT73C260 Pin description and configuration

Pin Number Pin Name

I/O Type

D-Input

A-Input

D-I/O

Polarity

Function

8

9

OE_N

PVRF

PDM

PDP

High

--

Connected to H_VCC

Fixed by external resistor bridge divider

Downstream Port for USB Device

10

11

--

D-I/O

--

Delivered by AT73C260 from VBUS

according external resistor ratio

12

PVCC

A-Output

--

13

14

15

16

RCV

D-Output

D-Input

HiZ

High

Low

Not Connected

M<2>

M<1>

M<0>

Connected to H_VCC

Connected to Ground

D-Inputs

Application Diagram

In the following figure, the hardware configuration is described.

Figure 9-27. AT73C260: Bridge with LDO - USB2.0 section 7 to IC_USB1.0 with V_CCfixed by P_VRF- application diagram

PVRF = PVCC = HVCC * R5/(R5+R4)

R

4

R5

9

P

VRF

AT73C260

1

4

12

HVCC

GND

H

VCC

PVCC

C

4

C5

Vref

3.3Volt

R

3

VBUS

V

BUS

C

3

13

nc

RCV

VCC

6

nc

10

HDMO

HDPO

OE_N

HDP

PDM

IC_DM

7

nc

8

2

3

HVCC

R

1

11

IC_DP

PDP

D +

C

1

HDM

D -

C

2

R

2

M<2> M<1> M<0> GND

14 15 16

5

HVCC

Notes: 1. P_VCCLDO regulator is compliant with SIM FTA 27.17.2.1 Tests Series.

2. All external components are defined in component list Table 8-1 on page 10

39

11030A–PMAAC–13-Sep-10

3. External resistors shall be in the following range: 100KΩ < R4 + R5 < 330KΩ in order to mini-

mize current consumption and to reach a good accuracy on P_VCC. The bias current of P_VRF

follower is less than +/-100nA.

40

AT73C260

11030A–PMAAC–13-Sep-10

AT73C260

9.4.7

Example of an Extra Function

For an FPGA implementation of a USB device, there is a need for an upstream IC_USB 1.0

PHY.

For this requirement the AT73C260 product can be configured as described below.

Pins V_BUSand P_VRFare connected to GND and LDO outputs are isolated and in standby.

9.4.7.1

Mode: Digital six wires unidirectional DAT_SE0 to IC_USB1.0 upstream: Extra Function

Description

This application allows a peripheral based on an ASIC or an FPGA with the digital unidirectional

six wires interface to be connected to an IC_USB 1.0 downstream port.

Here below, an example is shown. Other digital interfaces are compatible with this upstream

IC_USB 1.0 port.

Figure 9-28. PHY_6_SE0 Block Diagram

pull-up

Control

6

ASIC

FPGA

HOST

AT73C260

IC_USB_1.0

DAT_SEO

Hardware Configuration

In the following tables, the pin and the hardware configuration are described.

Table 9-23. AT73C260 Hardware Configuration

M<2>

M<1>

M<0>

Mode

Pin 14

Pin 15

Pin 16

Application

Extra Mode

(as an

example)

Digital six wires unidirectional DAT_SE0 to

IC_USB1.0 upstream

0

Table 9-24. AT73C260 Pin description and configuration

Pin Number Pin Name

I/O Type

Polarity

Function

Same as peripheral I/O ring (1.55V to

3.6V typical)

1

HVCC

A-Power

--

2

3

4

6

7

8

TX_DAT

TX_SEO

VBUS

D-Input

A-Input

--

Unidirectional Transmit Data

Unidirectional Transmit Single Ended 0

Not Used and Connected to Ground

Unidirectional Receiving DM

Unidirectional Receiving DP

Tx Enable N

--

RX_DM

D-Output

D-Input

--

RX_DP

--

TX_ENABLE_N

Low

41

11030A–PMAAC–13-Sep-10

Table 9-24. AT73C260 Pin description and configuration

Pin Number Pin Name

I/O Type

A-Input

D-I/O

Polarity

Function

9

PVRF

PDM

PDP

--

Connected to Ground

10

11

Downstream Port for USB Device

D-I/O

Same power as host VCC (1.8 or 3V

typical)

12

PVCC

A-Power

--

13

RX_RCV

M<2:0>

D-Output

D-Inputs

--

Unidirectional Receiving RCV

Connected to Ground

14, 15, 16

Low

Application Diagram

In the following figure, the hardware configuration is described.

Figure 9-29. AT73C260: Extra Mode - PHY of a 6-wire FPGA peripheral implementation - application diagram

9

PVRF

AT73C260

1

12

HVCC

GND

C

4

H

VCC

BUS

PVCC

C

5

Vref

3.3Volt

4

13

6

ASIC/FPGA : Peripheral 6 WIRES DAT_SE0

PVCC

V

DIGITAL WRAPPER

rx_rcv

rx_dm

rx_dp

rx_rcv

rx_dm

RCV

HDMO

HDPO

OE_N

HDP

VCC

10

PDM

IC_DM

7

PVCC

R

rx_dp

HOST

EXT

8

tx_enable_n

tx_dp

tx_enable_n

2

11

IC_DP

tx_dat

tx_se0

PDP

3

tx_dm

HDM

Pull-Up

Control

M<2> M<1> M<0> GND

14 15 16

5

Pull-Up Control

HVCC

Notes: 1. All external components are defined in component list Table 8-1 on page 10

2. In Upstream port configuration, the software must drive the R_EXTpull-up resistor.

42

AT73C260

11030A–PMAAC–13-Sep-10

AT73C260

10. Package Information

Figure 10-1. Mechanical Package Drawing for 16-lead Quad Flat No Lead Package

Note: All the dimensions are in mm

43

11030A–PMAAC–13-Sep-10

11. Ordering Information

Table 11-1. Ordering Information

Ordering Code

AT73C260

Package

Package Type

Temperature Operating Range

QFN16 3 x 3 mm

Green

-40°C to +85°C

44

AT73C260

11030A–PMAAC–13-Sep-10

AT73C260

12. Revision History

Change

Request

Ref.

Doc. Rev

Date

Comments

11030A

13-Sep-10

First revision

45

11030A–PMAAC–13-Sep-10

46

AT73C260

11030A–PMAAC–13-Sep-10

AT73C260

1

2

3

4

5

6

7

Block Diagram .......................................................................................... 2

Package and Pinout ................................................................................. 3

Pin Description ......................................................................................... 4

Absolute Maximum Ratings .................................................................... 5

Recommended Operating Conditions .................................................... 5

Power Dissipation Ratings ...................................................................... 5

Electrical Characteristics ........................................................................ 6

7.1I/Os DC Characteristics Referred to HVCC ...............................................................6

7.2I/Os DC Characteristics Referred to PVCC ...............................................................6

7.3Timing Characteristics Table .....................................................................................7

7.4VBUS Supply Characteristics ....................................................................................7

7.5HVCC and PVCC Supplies Characteristics ...............................................................8

8

9

Components List. ................................................................................... 10

Functional Description .......................................................................... 11

9.1AT73C260’s Upstream and Downstream Ports .......................................................11

9.2AT73C260 Pull Up and Pull Down Resistors ...........................................................12

9.3Theory Of Operation ................................................................................................13

9.4General Description .................................................................................................18

10 Package Information .............................................................................. 43

11 Ordering Information ............................................................................. 44

12 Revision History ..................................................................................... 45

i

11030A–PMAAC–13-Sep-10

ii

AT73C260

11030A–PMAAC–13-Sep-10

Headquarters

International

Atmel Corporation

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San Jose, CA 95131

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Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

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www.atmel.com/literature

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11030A–PMAAC–13-Sep-10


型号：	AT73C260
厂家：	ATMEL
描述：	Power Supply Support Circuit, 1 Channel, GREEN, QFN-16
文件：	总49页 (文件大小：2584K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT73C260 [ATMEL]

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