AT73C501_技术文档

Features

• Fulfills IEC 1036, Class 1 Accuracy Requirements

• Fulfills IEC 687, Class 0.5 and Class 0.2 Accuracy, with External Temperature

Compensated Voltage Reference

• Simultaneous Active, Reactive and Apparent Power and Energy Measurement

• Power Factor, Frequency, Voltage and Current Measurement

• Single and Poly Phase Operation

• Three Basic Operating Modes: Stand-Alone Mode, Microprocessor Mode and Multi-

Channel Mode

• Flexible Interfacing, 8-bit Microprocessor Interface, 8-bit Status Output and Eight

Impulse Outputs

• Calibration of Gain and Phase Error

• Compensation of the Non-Linearity of Low Power Measurement

• Adjustable Starting Current and Meter Constant

• Measurement Bandwidth of 1000 Hz

Chip Set

Solution for

Watt-Hour

Meters

• Tamper Proof Design

• Single +5V Supply

Description

A two chip solution, consisting of AT73C500 and AT73C501 (or AT73C502), offers all

main features required for the measurement and calculation of various power and

energy quantities in static Watt-hour meters. The devices operate according to

IEC1036, class 1, specification. IEC 687, class 0.5 and 0.2 requirements are fulfilled

when used with external temperature compensated voltage reference.

AT73C500 with

AT73C501 or

AT73C502

The AT73C501 contains six, high-performance, Sigma-Delta analog-to-digital convert-

ers (ADC). The AT73C500 is based on an efficient digital signal processor (DSP) core

and it supports interfacing both with the AT73C501 and with an external microproces-

sor. The AT73C500 DSP can also be used with the differential input ADC, AT73C502.

With this chipset, only a minimum of discrete components is required to develop prod-

ucts ranging from simple domestic Watt-hour meters to sophisticated industrial

meters. The chipset can be used in single-phase as well as in poly-phase systems.

The DSP core of the AT73C500 is easy to configure. By changing the mode of the

AT73C500, the device can be operated in a stand-alone environment or be used with

a separate control processor. It is also possible to configure the circuit to perform the

functions of three independent single phase Wh meters.

The chips support calibration of gain and phase error. All calibrations are done in the

digital domain and no trimming components are needed. The calibration coefficients

are either stored in an EEPROM memory or supplied by an external microprocessor.

(continued)

Rev. 1035A–08/98

1

Figure 1. Block diagram of the AT73C500 chipset in stand-alone configuration

EXTERNAL CONNECTOR

L1 L2 L3

VDA

VDDA

VCC

VREF

BGD

BRDY

STROBE

RD/WR

ADDR1

ADDR0

PFAIL

-VArh

+VArh

-Wh

+Wh

-Wh

+VArh

-VArh

AT73501

VI1

VI2

VI3

AT73500

IRQ0

IRQ1

SIX SINGLE-ENDED,

INDEPENDENT

SIGMA-DELTA

ACK

SOUT1

SOUT0

&

DATA

CLKR

CLK

CI1

CI2

CI3

SIN

CONVERTERS

DEDICATED DSP

FOR ENERGY

METERING

SCLK

DATA BUS

L1

L2

L3

RESET

CS

STATUS BUS

XRES

AGND

XI

XO

MODE

VSA

VSSA

GND

1

&

1

TAMP

STUP

L3

L2

L1

FAIL

DATRDY

INI

MODE2

MODE1

MODE0

1

&

CS

SK

DI

AT93C46

DO

RESET

EEPROM

128*8 bit

1

The AT73C500 is programmed to measure active, reactive

and apparent phase powers. Phase factors, phase volt-

ages, phase currents and line frequency are also mea-

sured, simultaneously. Based on the individual phase

powers, total active power is determined.

Eight pulse outputs are provided. Each billing quantity

(+Wh, -Wh, +VArh, -Varh) is supplied with its own meter

constant output, as well as a display counter output. In

multi-channel mode, AT73C500 performs the functions of

three independent single phase Wh meters and three

impulse outputs are available, one for each meter element.

The power values are calculated over one-line frequency

cycle. The negative and positive results are accumulated in

different registers, which allows for separate billing of

imported and exported active energy. Also, the reactive

results are sorted depending on whether capacitive or

inductive load is applied.

All measurement information is available on an 8-bit micro-

processor bus. The results are output in six packages, 16

bytes each. Mode and status information of the meter is

also transferred with each data block.

Figure 2. Block diagram of the AT73C500 chipset in microprocessor configuration

L1 L2 L3

VDA

VDDA

VCC

VREF

BGD

BRDY

STROBE

RD/WR

ADDR1

ADDR0

AT90Sxx

PFAIL

AT73501

VI1

VI2

VI3

AT73500

IRQ0

IRQ1

SIX SINGLE-ENDED,

INDEPENDENT

SIGMA-DELTA

MICROCONTROLLER

ACK

SOUT1

SOUT0

D

DATA

CLKR

CLK

DATRDY

CI1

CI2

CI3

SIN

CONVERTERS

DEDICATED DSP

FOR ENERGY

METERING

SCLK

DATA BUS

L1

L2

L3

RESET

CS

STATUS BUS

B9

XRES

AGND

MODEM

LCD

XI

XO

MODE

VSA

VSSA

GND

&

1

MODE2

MODE1

MODE0

B14

B13

B12

1

RESET

1

EEPROM

AT73C500

2

AT73C500

Pin Description

AT73C501 Single-ended ADC

Figure 3. PLCC-28 package pin layout

Analog

Signals

XO

XI

CLK CLKR ACK FSR DATA

17

14

18

15

19

16

I/O

Description

4

3

2

1

28

27

26

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

I

Input to Converter #1

Input to Converter #2

Input to Converter #3

Input to Converter #4

Input to Converter #5

Input to Converter #6

5

25

24

23

22

21

20

19

BGD

CS

RESET

MODE

GND

PD

6

7

VCC

8

PFAIL

AGND

VCIN

VREF

9

VDA

Input to Voltage Monitoring

Block

VCIN

10

I

10

11

VSA

AIN5

12

13

14

15

16

17

18

Digital

Control

Signals

VSSA VDDA AIN2 AIN4 AIN6 AIN1 AIN3

5

I/O

Description

By-pass Control

for Reference Voltage

BGD

CS

I

Power

Supply

Pins

6

Chip Select Input

13

12

21

20

I/O

Description

Power Down Control

for A/D Modulators

PD

22

VDDA

VSSA

VDA

PWR Analog Supply, Positive, +5V

PWR Analog Supply, Negative, 0V

PWR Analog Supply, Positive, +5V

PWR Analog Supply, Negative, 0V

MODE

24

25

I

Mode Selection Control

Reset Input, Active High

RESET

VSA

Status

Flags

Analog Ground Reference

Output

AGND

9

PWR

I/O

Description

Output of Voltage Monitoring

Block

VREF

VCC

11

7

PWR Reference Voltage Output

PWR Digital Supply, Positive, +5V

PWR Digital Supply, Negative, 0V

PFAIL

8

O

VGND

23

Output Bus

Signals

2

I/O

O

Description

Crystal Osc

Signals

CLK

CLKR

DATA

Master Clock Output

Serial Bus Clock Output

Serial Data Output

3

I/O

I

Description

1

O

XI

Crystal Oscillator Input

Crystal Oscillator Output

26

O

XO

4

O

Output Sample Frame

Signal

FSR

ACK

27

28

O

Data Ready Acknowledge

Output

3

AT73C502 Differential-Ended ADC

Figure 4. QFP-44 package pin layout

Analog

Signals

XI

CLK

CLKR

ACK

DATA

RESET

XO

N/C

FSR

18

19

20

21

22

23

24

25

I/O

Description

VINP3

VINN3

IINP1

IINN1

IINP2

IINN2

IINP3

IINN3

I

Input to Converter #3 (+)

Input to Converter #3 (-)

Input to Converter #4 (+)

Input to Converter #4 (-)

Input to Converter #5 (+)

Input to Converter #5 (-)

Input to Converter #6 (+)

Input to Converter #6 (-)

44 43

42

41

40

39

38

37

36

35 34

BGD

CS

MODE

GND

PD

1

2

33

32

3

4

5

6

7

8

9

31

30

29

28

27

26

25

VCC

VDA

PFAIL

AGND

VCIN

VDA

VSA

VREF

IADJUST

VSA

SINGLE

IINN3

IINP3

IINN2

10

11

24

23

Input to Voltage Monitoring

Block

VCIN

7

9

I

VSA

12 13

14

15

16

17

18

19

20

21 22

IADJUST

Must be left floating

VDA

VINP1

VINP2

VINP3

IINP1

IINP2

VDA

VINN1

VINN2

VINN3

IINN1

Digital

Control

Signals

1

I/O

Description

Power

Supply

Pins

By-pass Control for

Reference Voltage

BGD

CS

I

I/O

Description

2

Chip Select Input

12, 13,

29, 30

VDA

VSA

PWR

Analog Supply, Positive, +5V

Power Down Control for A/D

Modulators

PD

31

10, 11,

27, 28

Analog Supply, Negative, 0V

MODE

33

35

I

Mode Selection Control

Reset Input, Active High

Analog Ground Reference

Output

RESET

AGND

6

Single / Differential selector.

· Low: Differential

· High or n/c: Single-ended

VREF

VCC

8

PWR Reference Voltage Output

PWR Digital Supply, Positive, +5V

PWR Digital Supply, Negative, 0V

SINGLE

26

I

3, 4

32

GND

Status

Flags

I/O

Description

Crystal

Osc

Signals

Output of Voltage Monitoring

Block

PFAIL

5

O

43

I/O

I

Description

XI

Crystal Oscillator Input

Crystal Oscillator Output

Output

Bus

XO

44

O

Signals

41

I/O

O

Description

Analog

Signals

CLK

CLKR

DATA

Master Clock Output

Serial Bus Clock Output

Serial Data Output

14

15

16

17

I/O

Description

39

O

VINP1

VINN1

VINP2

VINN2

I

Input to Converter #1 (+)

Input to Converter #1 (-)

Input to Converter #2 (+)

Input to Converter #2 (-)

35

O

Output Sample Frame

Signal

FSR

ACK

36

37

O

Data Ready Acknowledge

Output

AT73C500

4

AT73C500

AT73C500 DSP

Figure 5. PLCC-44 package pin layout

Microprocessor

Bus

IRQ0 /

GND

SOUT1 SOUT0

GND

CLK STROBE VCC

ADDR2 ADDR1

PFAIL

Pin I/O

Description

µP Bus, Bit7

µP Bus, Bit6

µP Bus, Bit5

µP Bus, Bit4

µP Bus, Bit3

µP Bus, Bit2

µP Bus, Bit1

µP Bus, Bit0

6

5

4

3

2

1

44

43

42

41

40

GND

ADDR0

7

39

B7

B6

B5

B4

B3

B2

B1

B0

23

22

21

19

18

10

9

I/O

B0

B1

XRES

BRDY

RD/WR

VCC

8

9

38

37

36

35

34

33

32

31

30

29

B2

10

11

12

13

14

15

16

17

GND

B12

B13

B14

GND

B15

GND

SIN

SCLK

IRQ1 / ACK

GND

8

B11

18

19

20

21

22

23

24

25

26

27

28

B3

B4

GND

B5

B6

B7

N/C

B8

B9

GND

B10

AT73C501 /

AT73C502 and

EEPROM

Power

Supply

Pins

Interface

I/O Description

I/O

Description

Serial Output, used as a

clock for EEPROM

SOUT0

SOUT1

4

O

VCC

35, 42

PWR Digital Supply, Positive, +5V

1, 2, 6, 7,

11, 12,16,

20, 27, 30,

34

Serial Output, used as Chip

Select (CS) for AT73C501

and as Data Input (DI) for

EEPROM

GND

PWR Digital Supply, Negative, 0V

5

O

Serial Data Input, data from

AT73C501 or from EEPROM

SIN

33

32

I

Digital

Inputs

44

I/O

Description

Serial Clock Input, bit clock

from AT73C501

SCLK

CLK

I

Clock Input

XRES

38

Reset Input, active low

Control Signals

of µP Bus and

Status/Mode

Bus

Interrupt Input, usually

connected to PFAIL output

of AT73C501

IRQ0

IRQ1

3

I

I/O Description

Interrupt Input, connected to

ACK Output of AT73C501

31

STROBE

BRDY

43

O

I

Strobe Output

Microprocessor ready for

I/O, Active Low

37

40

Status/

Mode

Bus

Address Output 1, used for

µP bus

ADDR1

O

17

15

14

13

29

28

26

25

I/O

Description

B15

B14

B13

B12

B11

B10

B9

Status/Mode Bus, Bit7

Status/Mode Bus, Bit6

Status/Mode Bus, Bit5

Status/Mode Bus, Bit4

Status/Mode Bus, Bit3

Status/Mode Bus, Bit2

Status/Mode Bus, Bit1

Status/Mode Bus, Bit0

Address Output 0, used for

Status/ Mode bus and for

Impulse Outputs

ADDR0

RD/WR

39

36

O

Read/Write Signal

B8

5

AT73C501 and AT73C502

The AT73C501 consists of six, 16-bit analog-to-digital con-

verters. The converters are equipped with single-ended

inputs. For differential ended applications, the AT73C502

chip is used.

The converters contain a reference voltage generator, volt-

age monitoring block and serial output interface. Both con-

verters are based on high-performance, oversampling

Sigma-Delta modulators and digital decimation filters.

Figure 6. Block diagram of the single-ended ADC chip, AT73C501

VOLTAGE

MONITORING

SIGMA-DELTA

MODULATOR

DECIMATION

FILTER

SIGMA-DELTA

MODULATOR

DECIMATION

FILTER

SIGMA-DELTA

MODULATOR

DECIMATION

FILTER

SERIAL OUTPUT

LOGIC

SIGMA-DELTA

MODULATOR

DECIMATION

FILTER

SIGMA-DELTA

MODULATOR

DECIMATION

FILTER

SIGMA-DELTA

MODULATOR

DECIMATION

FILTER

VOLTAGE

REFERENCE

TIMING AND

CONTROL

In a 50 Hz meter, the nominal decimated sampling rate of

3200 Hz is used. This corresponds to 64 samples per each

line frequency cycle. 60 Hz meters operate with 3840 Hz

sample rate. The master clock frequency of the ADC is

1024 times higher than the above frequencies, i.e. 3.2768

MHz in 50 Hz meters and 3.93216 MHz in 60 Hz systems.

The default meter constant of AT73C500 energy counters

is based on the above sample rates.

100

6.25

I_FS= 5 A_RMS× ----------- = 80 A_RMS

The following current transformer and voltage divider con-

figuration is recommended for a 230V, 3-phase system,

with 5A basic current:

Other sample frequencies can be used, but the energy

results have to be scaled accordingly. If higher sampling

rate is selected, the meter constant will also be increased

by the same ratio.

Voltage Inputs Current Inputs

The three current inputs of AT73C501 are fed from second-

ary outputs of current transformers, from Hall sensors or

other similar sensors. In differential-ended applications,

such as with current shunt resistors, the AT73C502 ADC

can be used. On any of these converters, the voltage

inputs must be equipped with simple external voltage divid-

ers.

Converter full-scale input

2.0V_PP

Corresponding full-scale

line voltage / current

270V_RMS

80A_RMS

With the above settings, the nominal pulse rate of the

meter constant outputs is 1250 impulses/kWh (1250

impulses/kVArh) and the rate of four display outputs 100

impulses/kWh (100 imp/kVArh).

The input voltage range of each converter is 2V_PP. The

characteristics of a Watt-hour meter operating, according to

IEC1036 specification, are based on a certain basic cur-

rent, I_B. As a default, the basic current of AT73C500

chipset is to 6.25% of the current input full scale value. This

means that if a meter is designed for I_B= 5A_RMS, the full

scale range of the current channels will be:

When used in a 5A transformer operated meter, the maxi-

mum current range can be scaled down to 8A for example.

In this case, the meter constant will be ten times higher

than in an 80A meter, i.e. 12500 impulses/kWh. Similarly,

the starting current level will be transferred 2mA from

20mA.

AT73C500

6

AT73C500

If the nominal voltage is chosen to be 120V, the voltage

divider can either have the same configuration as in the

230V meter, or it can be modified to produce 2.0V_ppwith

140V phase voltage. In the latter case, the default meter

constant will be roughly twice the constant of 230V meter,

i.e. 2411 impulses/kWh. The meter constant can be scaled

to an even number value by means of calibration.

compensated external reference instead. The reference is

selected with the BGD input.

BGD

Reference

Internal

0 (V_SS

)

1 (V_DD

)

External

As described above, the configuration of voltage dividers

and current transformers affects to almost all parameters

being metered, like energy counters and impulse outputs.

A calibration coefficient is provided for the adjustment of

the display pulse rates. With this coefficient, the effect of

various voltage divider and current transformer configura-

tions can be compensated. Care should be taken that the

dynamic range of the A/D converters is always effectively

utilized. The use of calibration coefficients is described in

the next section.

There is an integrated voltage monitoring block on the con-

verter chip. The PFAIL output is forced high if the level of

voltage supplied to V_CINinput drops below 4.2V. There is a

hysteresis in the monitoring function and PFAIL returns low

if voltage at V_CINis raised back above 4.3V.

PFAIL output of AT73C501/AT73C502 can be connected

to an interrupt input of AT73C500. AT73C500 detects the

rising edge of PFAIL. To assure reliable power-down pro-

cedure after voltage break, the V_CCsupply of AT73C500

must be equipped with a 470 µF or larger capacitor.

Current and voltage samples of AT73C501/AT73C502 are

multiplexed and transferred to AT73C500 through a serial

interface. The timing of the interface is presented in the

next section.

AT73C500

AT73C500 performs power and energy calculations. It also

controls the interfacing to the AT73C501 (or AT73C502)

and to an external microprocessor. The block diagram of

the DSP is presented below.

AT73C501/AT73C502 contain an internal bandgap voltage

reference. When used in class 0.5 and 0.2 meters, smaller

temperature drift is required. This can be achieved by

bypassing the internal reference and using temperature

Figure 7. Block diagram of DSP software

FREQUENCY

MEASUREMENT

f

CURRENT

DERIVATION

u1(n)

I

VOLTAGE

MEASUREMENT

GAIN

CALIBRATION

u2(n)

U

ACTIVE ENERGY

CALCULATION

u3(n)

W

DC OFFSET

SUPPRESSION

ACTIVE POWER

MEASUREMENT

GAIN AND OFFSET

CALIBRATION

i1(n)

i2(n)

i3(n)

P

PHASE

CALIBRATION

APPARENT POWER

EVALUATION

POWER FACTOR

DERIVATION

PF

Q

HILBERT

TRANSFORM

REACTIVE POWER

MEASUREMENT

GAIN AND OFFSET

CALIBRATION

REACTIVE ENERGY

CALCULATION

Wq

Serial Bus Interface

The timing of the serial bus interface connecting the ADC

and DSP devices is presented in Figure 5. The same bus is

used to read the calibration data from an external

EEPROM. This operation is described in section “Loading

of Calibration Coefficients” on page 19.

When the three current and three voltage samples are

ready, AT73C501/AT73C502 raises the ACK output.

AT73C500 detects the rising edge of ACK, and, after a few

clock cycles, it is ready to read the samples through the

serial bus. The transfer is initiated by CS/SOUT1 signal

and the data bits are strobed in at the falling edge of

CLKR/SCLK clock. Six 16-bit samples is transferred in the

following sequence: I1, U1, I2, U2, I3 and U3.

7

Figure 8. Serial bus timing

CLK

CLKR

ACK

FSR

CS

6 * 16 BITS

DATA

CH1, B15

MSB

CH1, B14

CH1, B0

LSB

CH2, B15

MSB

CH2, B0

LSB

CH6, B1

CH6, B0

Operating Modes of AT73C500

The AT73C500 chipset has six operating modes. The

mode is selected by three mode control inputs which

AT73C500 reads through a bus during the initialization pro-

cedure after a reset state. The operation of

AT73C501/AT73C502 is independent of the mode

selected.

In operating mode 7, the default display pulse rate is 10

impulses per kWh, instead of 100 impulses per kWh, as in

other modes.

Mode Number

Mode Bit 2

Mode Bit 1

Mode Bit 0

Operating Mode

Not in use

Calibration Data Storage

0

1

2

3

4

5

6

7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Normal operation

Multi-channel operation

Normal operation

Multi-channel operation

Test mode

EEPROM

Micro-processor

None

Not in use

Normal operation

EEPROM

Normal Measurement Mode

AT73C500 devices support both stand-alone and micropro-

cessor configuration. The calibration coefficients can either

be supplied by a processor or stored in an 128 x 8-bit

EEPROM. The ROM is interfaced with AT73C500 via three

pin serial bus. AT73C500 and the processor communicate

through an 8-bit bus.

configuration is recommended even in meters equipped

with a separate microprocessor.

The same sequence of basic calculations is performed

both in poly-phase and single-phase meters. This

sequence consists of DC offset suppression, phase, gain

and offset calibration, calculations of measurement quanti-

ties and data transfer to µP bus and pulse outputs.

AT73C500 constantly monitors various tampering and fault

situations, which are indicated by status bits.

The only operational difference between stand-alone and

µP mode is the way of reading calibration coefficients. This

allows various combinations of these two configurations to

be utilized. For example, the calibration data can be stored

in an EEPROM even though the processor reads and dis-

plays the measurement results supplied by AT73C500

device.

After a reset state, AT73C500 goes through an initialization

sequence. The device reads the operating mode and

fetches the calibration coefficients and adjustment factors

for output pulse rate and starting current level, either from a

non-volatile memory or from a microprocessor. After that

the normal measurement starts. The reset state is normally

activated by power-up reset following the recovery from a

voltage interruption.

In most cases, the use of external EEPROM gives flexibility

to the meter testing and calibration, and also makes the

processor interface easier to implement. Therefore, this

AT73C500

8

AT73C500

Measurements and Calculations

Measurement Registers

The first operation performed by AT73C500 is digital high-

pass filtering. The purpose of the filtering is to remove the

DC offset of both current and voltage samples.

For the measurement parameters 25 registers are allo-

cated:

Register Meaning

From offset free samples, active power is calculated

phase-by-phase with simple multiplication and addition

operations.

REG0

REG1

REG2

REG3

REG4

REG5

REG6

REG7

REG8

REG9

REG10

REG11

Phase 1, active power, P1(10T), 32-bit register;

Phase 2, active power, P2(10T), 32-bit register;

Phase 3, active power, P3(10T), 32-bit register;

Phase 1, reactive power, Q1(10T), 32-bit register;

Phase 2, reactive power, Q2(10T), 32-bit register;

Phase 3, reactive power, Q3(10T), 32-bit register;

Phase 1, apparent power, S1(10T), 16-bit register;

Phase 2, apparent power, S2(10T), 16-bit register;

Phase 3, apparent power, S3(10T), 16-bit register;

Phase 1, power factor, PF1, 16-bit register;

First, the current samples are multiplied by voltage sam-

ples. The multiplication results are summed over one line

period and finally the sum value is divided by 64. This dis-

crete time operation gives the average power of one

50/60Hz period and the result corresponds to the following

continuous time formula:

N

T

1

P =

--- × [A × U × sin{n × wt} × A × I × sin{n × wt +

}dt]

∑ ∫

N

T

n = 0

0

N

1

--

2

Phase 2, power factor, PF2, 16-bit register;

=

×

A

×

A

×

U

×

I

×

cos

(

)

n

∑

Phase 3, power factor, PF3, 16-bit register;

n = 0

Active exported energy since the latest reset, +Wp,

32-bit counter;

where

T = 1/50 Hz or 1/60 Hz,

REG12

REG13

REG14

REG15

REG16

Active imported energy since the latest reset, -Wp,

32-bit counter;

n = 1, 2, 3,..., 20 (basic 50/60 Hz frequency and the

harmonics),

Reactive energy, inductive load, Wqind, 32-bit

counter;

A_n= frequency response of calculations.

The total power is calculated by summing the power of

each line phase. Reactive power calculation is based on a

similar procedure. Before multiplying the current and volt-

age samples AT73C500 performs a frequency independent

-90 degree phase shift of the voltage signal. This is realized

with a digital Hilbert transformation filter. The bandwidth of

reactive power measurement is limited to 360 Hz.

Reactive energy, capacitive load, Wqcap, 32-bit

counter;

Number of 10T periods elapsed since the latest

reset, 32-bit counter;

REG17

REG18

REG19

REG20

REG21

REG22

REG23

REG24

Frequency, f, 16-bit register;

Reserved for further use, 16-bit register;

Phase 1, voltage U1, 16-bit register;

Phase 2, voltage U2, 16-bit register;

Phase 3, voltage U3, 16-bit register;

Phase 1, current I1, 16-bit register;

Phase 2, current I2, 16-bit register;

Phase 3, current I3, 16-bit register.

Based on the active and reactive results apparent power

and power factors are determined. RMS phase voltages

are calculated by squaring and summing the voltage sam-

ples and finally taking a square root of the results. Current

is determined by dividing apparent power result by corre-

sponding phase voltage.

Frequency measurement is based on a comparison of the

line frequency and AT73C500 sampling clock frequency.

The measurement range is from 20 Hz to 350 Hz.

All measurements and calculations, except frequency mea-

surement, are made over 10 line cycle periods. The results

are updated and transferred to processor bus once in 200

ms.

The size of the registers is either 16-bit or 32-bit. IEC spec-

ifications apply to the calculations of active and reactive

power and energy (REG 0-5 and REG 12-15). Other results

are intended mainly for demand recording and for various

diagnostic and display functions. The accuracy of those are

limited due to the finite resolution.

9

In multi-channel mode the active exported energy of each

three meters (phases) is stored in registers 12-14. REG15

is not in use.

In the default condition, value 7FFFH of register 17 corre-

sponds to 1.22 Hz frequency, value 0320H represents

50Hz and 0001H 40 kHz. However, in practice, the band-

width of frequency measurement is limited to 20 Hz to 350

Hz.

The maximum value of different power registers differs,

depending on the calculation formulas used. The scaling of

registers is described below.

The frequency measurement is locked with one of the

phase voltages. If this voltage disappears, AT73C500 tries

to track one of the other phases. The frequency measure-

ment works down to about 10% level of the full scale volt-

age range. The harmonics content of phase voltage should

be below 10%. If it is higher, erroneous frequency results

may be obtained.

If a full scale sine signal is applied to voltage and current

inputs and the voltage and current channels are exactly in

the same phase, a value of 258F C2F7H will be produced

in the 32-bit P1, P2 and P3 registers. The LS bit will corre-

spond to about 34 microwatts in nominal input conditions of

270V maximum phase voltage and 80A maximum current.

The voltage registers (REG19-REG21) are scaled so that

full scale sinusoidal input signal at AT73C501/AT73C502

voltage channels will produce 7A8BH value into voltage

registers. This means that the resolution of the registers is

about 8.6 mV. Accordingly, full scale current will produce

7DA4H to current registers (REG22-REG24) providing a

resolution of about 2.5 mA. In practice, the voltage can be

measured down to about 25V level and current down to

about 100mA.

If the load is fully reactive (± 90° phase difference) and full

scale signals are applied, the Q1, Q2 and Q3 register con-

tent will be 2231 594DH positive or negative, and the LSB

will represent about 38 µVAr. The maximum value of the

16-bit S registers is 258EH and this value is obtained if a

full scale amplitude is produced to the current and voltage

inputs. LS bit of the S registers correspond to about 2.25VA

power.

The following formula is used to calculate the power factor:

If either voltage or current, or both, contain a considerable

amount of harmonics producing a square wave type wave-

form, it is recommended to scale the input range so that the

maximum peak-to-peak value is at least 10% below the full

scale range of inputs. This is to avoid overflow in the calcu-

lations performed by AT73C500.

abs(P)

abs(S)

-----------------

PF = sign(Q) ×

The PF register contents 7FFFH represents power factor

value one and the contents 0000H value zero. Negative PF

values are stored correspondingly as negative binary num-

bers. It should be noted that the sign of power factor result

indicates whether the loading is inductive (+) or capacitive

(-).

Energy Counters

Four 32-bit counters (REG12-REG15) measure energy

consumption. In nominal situations, the counters are

always incremented when 0.4Wh (0.4VArh) energy is con-

sumed. The counters can store minimum of 1100 days con-

sumption, provided that AT73C501/AT73C502 and

AT73C500 are used with default settings.

The contents of frequency register (REG17) actually repre-

sents a 16-bit figure which corresponds to the duration of

50 line frequency cycles. The measurement is made by

comparing the line frequency with one of the sampling

clocks of AT73C500 and therefore the result depends on

the crystal frequency used. With default 3.2768 MHz crys-

tal, the resolution of time value is 1.25 ms. To get the fre-

quency, the following calculation has to be made:

Impulse outputs are generated from these counters. The

meter constant rate represents 2 LSBs of a counter which

equals 0.8 Wh (0.8 VArh) and produces 1250

impulses/kWh. (1250 impulses/kVArh). In modes 1 to 4, the

display pulses are generated from 25 LSBs of a counter.

This corresponds to an impulse rate of 100 impulses/kWh

(100 impulses/kVArh). It is possible to adjust this rate with

MCC calibration coefficient. In mode 7, 250 LSBs of the

energy register is needed to generate one impulse (10

impulses/kWh).

40000

-------------------

f =

Hz

REG17

If the master clock frequency (MCLK) of AT73C500 is not

nominal, the following formula gives frequency results:

full scale

The default values above are based on 80A_RMS

40000

------------------- ------------------------------

Hz

MCLK

REG17 3.2768MHz

current, 270V_RMSfull scale voltage and 3.2768 MHz clock

rate.

f =

×

The crystal frequency will affect the values of energy regis-

ters (REG12-REG15) and time register (REG 16). It will

also change the pulse rates of the impulse outputs.

AT73C500

10

AT73C500

It is recommended that 50 Hz meters are operated from

3.2768MHz crystal. In 60 Hz system, a 3.93216 MHz clock

is normally used. Because the clock frequency generates a

time reference for energy calculations, the content of

energy registers and also the pulse rate of impulse outputs

will change when crystal is changed. For example, the

nominal meter constant and display pulse rate of 60 Hz

meter (3.93216 MHz clock) is:

The LSB of energy registers correspond to 0.33Wh instead

of 0.4Wh, as follows:

3.2768MHz

3.93216MHz

---------------------------------

× 0.4Wh = 0.333333…Wh

E_LSB

=

The pulse rate can be scaled to 100 imp/kWh by program-

ming value 5 to MCC coefficient, as below:

60Hz

-------------

50Hz

imp

-----------

kWh

imp

-----------

kWh

MC =

× 1250

= 1500

Wh

---------

imp

1

---------

imp

---------

imp

IMP = (25 + MCC)

× E

= 30

× 0.3333…Wh = 10

LSB

and

which equals 100 impulses per kilowatt hour.

60Hz

50Hz

imp

kWh

imp

kWh

DP = ------------- × 100----------- = 120-----------

The following table summarizes the contents of all mea-

surement registers.

Register

Conditions

Full Scale Output (hex)

258F C2F7

Resolution (hex)

34.276 µW

REG0 - REG2

REG3 - REG5

REG6 - REG8

U = 270V, I = 80A, PF = 1

U = 270V, I = 80A, PF = 0

U = 270V, I = 80A

2231 594D

37.653 µVAr

2.2467 VA

258E

PF = 1

PF = -1

7FFF

8001

0.0000305

-0.0000305

REG9 - REG11

REG12 - REG15

REG16

W = 1.718GWh

∆T = 238609.3h

50*T = 40.959s

U = 270V

FFFF FFFF

7FFF

0.4Wh

0.2s

REG17

1.25 ms

8.6 mV

2.5 mA

REG19 - 21

REG22 - 24

7A8B

I = 80A

7DA4

11

Output Operations

PACKAGE 0

Order

The data output by AT73C500 can be divided into three

categories: data to external processor, status information

and impulse outputs. AT73C500 reads mode information,

and in mode 3 and 4, also calibration data via external bus.

For the I/O operation, two 8-bit buses are allocated.

Byte

1

Data

Sync LS

Sync MS

Mode

Meaning

Single byte

LS byte

Synchronization

2

Synchronization

3

Mode information

The same eight data lines are reserved both for the

impulse outputs and for the processor interface. The sepa-

ration is done with two address pins. When communicating

with the microprocessor, address 1 (pin ADDR1) is acti-

vated (high). Impulses are output combined with a high

level of address 0 (ADDR0). For status information sepa-

rate 8-bit bus is reserved. The table below describes the

use of the two buses of AT73C500.

4

Status

REG0

REG1

REG2

Status information

5

Active power, phase 1

Active power, phase 2

Active power, phase 3

6

(LS+1) byte

(LS+2) byte

MS byte

7

8

9

LS byte

Data bits

Bus

Address

Mode

Usage

10

11

12

13

14

15

16

(LS+1) byte

(LS+2) byte

MS byte

Impulse

Outputs

B0 - B7

Data Bus

ADDR0

Output

Status

Information

B8 - B15

B0 - B7

Status Bus

Data Bus

ADDR0

ADDR1

ADDRx

Output

Input/

LS byte

Processor

(LS+1) byte

(LS+2) byte

MS byte

Output Interface

Mode

Input

B12 - B14 Status Bus

Inputs

For status and impulse outputs, external latches are

needed to store the information while buses are used for

other tasks. In most cases, the data bus of AT73C500 and

processor I/O bus can be connected directly with each

other. The data transfer is controlled by handshake signals,

ADDR1, RD/WR, STROBE and BRDY. One of the status

outputs DATRDY (B9, ADDR0) can be used as an interrupt

signal. Interrupt can be also generated from the handshake

lines.

PACKAGE 1

Order

Byte

1

Data

Sync LS

Sync MS

Mode

Meaning

Single byte

LS byte

Synchronization

2

Synchronization

3

Mode information

4

Status

REG3

REG4

REG5

Status information

In most meters, only some of the I/O operations of

AT73C500 are needed. If a meter contains a separate pro-

cessor, status outputs of AT73C500 are typically not used

since the processor will anyway track the status information

supplied by AT73C500. Often only one or two of the

impulse outputs are wired to the test LED or electrome-

chanical counter.

5

Reactive power, phase 1

Reactive power, phase 2

Reactive power, phase 3

6

(LS+1) byte

(LS+2) byte

MS byte

7

8

9

LS byte

Data Transfer to External Microprocessor

10

11

12

13

14

15

16

(LS+1) byte

(LS+2) byte

MS byte

The calculation results of AT73C500 are transferred to pro-

cessor via 8-bit parallel bus. During normal operation, the

information transfer is divided into six packages which are

written in 200ms intervals after the calculations over ten

line frequency cycles have been completed. There is a time

interval of one line cycle between each individual data

package. The first four bytes of a package contain synchro-

nization, mode and status information, and the rest 12

bytes are reserved for the actual measurement results. The

contents of the six data packages are as follows:

LS byte

(LS+1) byte

(LS+2) byte

MS byte

AT73C500

12

AT73C500

PACKAGE 2

PACKAGE 3

Byte

1

Data

Sync LS

Sync MS

Mode

Order

Single byte

LS byte

Meaning

Byte

1

Data

Sync LS

Sync MS

Mode

Order

Meaning

Synchronization

Single byte

LS byte

Synchronization

Mode information

Status information

Active exported energy

2

Synchronization

2

3

Mode information

3

4

Status

REG6

REG7

REG8

Status information

4

Status

5

Apparent power, phase 1

Apparent power, phase 2

Apparent power, phase 3

Power factor, phase 1

Power factor, phase 2

Power factor, phase 3

5

REG12

REG13

6

MS byte

LS byte

6

(LS+1) byte Active exported energy

(LS+2) byte Active exported energy

7

8

MS byte

LS byte

8

MS byte

LS byte

Active exported energy

Active imported energy

9

10

11

12

13

14

15

16

MS byte

LS byte

10

11

12

(LS+1) byte Active imported energy

(LS+2) byte Active imported energy

REG9

REG10

REG11

MS byte

LS byte

MS byte

LS byte

Active imported energy

Reactive energy, inductive

load

13

14

15

16

REG14

MS byte

LS byte

Reactive energy, inductive

load

(LS+1) byte

(LS+2) byte

MS byte

Reactive energy, inductive

load

Reactive energy, inductive

load

13

PACKAGE 4

PACKAGE 5

Byte

Data

Sync LS

Sync MS

Mode

Order

Meaning

Byte

1

Data

Sync LS

Sync MS

Mode

Order

Single byte

LS byte

Meaning

1

2

3

4

Single byte

Synchronization

Mode information

Status information

Synchronization

Mode information

Status information

Voltage, phase 1

Voltage, phase 2

Voltage, phase 3

Current, phase 1

Current, phase 2

Current, phase 3

2

3

Status

4

Status

Reactive energy,

capacitive load

5

REG19

REG20

REG21

REG22

REG23

REG24

5

6

7

8

REG15

LS byte

6

MS byte

LS byte

Reactive energy,

capacitive load

(LS+1) byte

(LS+2) byte

7

8

MS byte

LS byte

Reactive energy,

capacitive load

9

Reactive energy,

capacitive load

10

11

12

13

14

15

16

MS byte

LS byte

MS byte

LS byte

9

REG16

REG17

REG18

Counter

MS byte

LS byte

10

11

12

13

14

15

16

(LS+1) byte Counter

(LS+2) byte Counter

MS byte

LS byte

MS byte

LS byte

MS byte

LS byte

MS byte

Counter

Frequency

Reserved

MS byte

AT73C500

14

AT73C500

The six data packages arrive as follows:

Figure 9. Data transfer to processor in six packages

20 ms

200ms = 655360 clocks @ 3.2768 MHz

Pack Pack Pack Pack

Pack Pack Pack Pack Pack Pack

0

1

2

3

4

5

0

1

2

3

DATRDY

LINE PERIOD

1

2

3

4

5

6

7

8

9

10

1

2

3

4

5

In normal mode, the Sync LS byte indicates the number of

data package which will follow (value 0...5). There are also

two special situations indicated by this byte. Value six of

Sync LS byte means that the processor is expected to sup-

ply calibration data to AT73C500. Value seven is written by

AT73C500 in case power interruption is detected and bill-

ing information needs to be transferred to microprocessor.

In this case the processor knows that both packages 3 and

4 will follow one after each other as shown in Figure 10.

The Sync MS byte contains a unique 8-bit data, 80H. It can

be used as a synchronization byte by the external control-

ler.

The mode byte contains the following information:

Figure 10. Meaning of bits in mode byte

B7 B6 B5 B4 B3 B2 B1 B0

Mode byte

Not used

State of MODE

input pins of the

DSP

Content of Sync LS byte is described in the following table.

Bits 3-7 of the Sync LS byte are not used.

Sync LS byte

Data

The contents of the status byte equals the content of the

external Status bus as described in the section “Status

Information” on page 17.

B7 - B3

B2 B1 B0 package Mode

In the beginning of I/O operation, AT73C500 writes a high

pulse to B9 pin of the Status bus (ADDR0). This pin can be

externally latched to lengthen the pulse over the whole out-

put operation. It can be used to generate a data ready

(DATRDY) interrupt to processor.

Normal operation,

Data output

X X X X X

0

1

0

1

0

1

0

1

0

1

0

1

0

Normal operation,

Data output

X X X X X

1

Normal operation,

Data output

Figure 11 shows the timing of one data package. In nomi-

nal conditions, it takes 200 clock cycles to transfer all 16

bytes. A high pulse (DATRDY) is written to bit B9

(SMBUS1) of Status bus 11 clocks before the first byte is

available and low pulse 12 clocks after the last byte has

been sent.

2

Normal operation,

Data output

3

Normal operation,

Data output

4

5

Normal operation,

Data output

DSP waiting for

calibration data

(none)

PFAIL active,

X X X X X

1

3 and 4

billing information

to be transferred

15

Figure 11. Contents of a data package

200 clock cycles

45 clock cycles

143 clock cycles

LATCHED

DATRDY

CLK

STROBE

Sync LS

Sync MS

Mode

Status

Data 1

Data 2

Data 11

Data 12

Measurement data, 12 bytes

Synchronisation data

Status data

AT73C500 offers some time for the processor to analyze

the synchronization, status and mode information before

starting to supply the measurement results. The 12 mea-

surement bytes are written on every 11th clock period.

writing to µP bus or reading the bus contents. When used

with slow peripheral, the BRDY input of AT73C500 can be

used to hold the device in write mode until the processor

has finished reading the bus. However, the total length of

one data package should always be less than 300 clock

cycles of AT73C500. Longer I/O periods may result errone-

ous measurement results.

Four handshake signals are provided, ADDR1, RD/WR,

STROBE and BRDY, for interfacing with the microproces-

sor. ADDR1 is always taken high when AT73C500 is either

Figure 12. Handshake signals of the DSP

CLK

SDLY

DATA

FROM DSP

BRS

DDLY

BRDY

SH

STROBE

ASU

ADDR1

RWSU

RWH

RD/WR

Following the falling edge of BRDY, the data can be

strobed into the µP by the rising edge of the STROBE sig-

nal. If the microprocessor is able to read data continuously,

BRDY can be kept constantly low. Also BRDY should be

low whenever DATRDY is inactive allowing AT73C500

freely use its buses.

To avoid conflicts, the processor should always keep its

bus in tri-state mode, unless it is used to write calibration

coefficients to AT73C500.

AT73C500

16

AT73C500

Status Information

AT73C500 provides the following status information

through the Status bus of AT73C500 (B8 - B15, ADDR0).

FAIL flag signifies that something abnormal has been

detected. The following situations may cause a high level of

FAIL: read operation of calibration coefficients is not suc-

cessful, the serial bus of AT73C501 or AT73C502 is not

working properly, the measurement results can't be trans-

ferred to microprocessor, AT73C500 has detected an inter-

nal failure.

Status

Bus Bit

Status

Flag

Meaning

High: Potential event of

tampering detected

B15

B14

B13

B12

B11

TAMP

STUP

L3

If any of the calibration coefficients and corresponding

back-up values do not match, AT73C500 performs two

extra read operations to eliminate the possibility of a trans-

fer error. If the error still exists after the third trial, incorrect

coefficients are replaced by the default values. FAIL flag is

activated indicating that a potential error has been

detected. FAIL is also taken high in case it is not possible

to read calibration coefficients from the µP or EEPROM, or

if the processor supplies too few coefficients. In both cases,

the read operation will finish in a time-out situation.

High: Current of all phases

below starting level

High: Phase 1 voltage above

10% of full-scale

High: Phase 2 voltage above

10% of full-scale

L2

High: Phase 3 voltage above

10% of full-scale

L1

The voltage monitoring block of AT73C501/AT73C502 is

used to detect voltage interruptions before the supply volt-

age of AT73C500 drops. High level of PFAIL output at the

ADC indicates a voltage break situation. The measurement

results supplied by AT73C501/AT73C502 may be errone-

ous, and AT73C500 and microprocessor has to be pre-

pared for supply voltage interruption. A high level of PFAIL

causes an immediate write of data packages 3 and 4

(accumulated energy information) to processor bus. The

timing of this operation is presented in Figure 13. There are

16 clocks between the two 12 byte data packages but the

header bytes are not repeated in the beginning of package

4.

B10

B9

FAIL

High: Operating error detected

DATRDY

High: Data available on the µP bus

Low: AT73C500 in initialization phase,

EEPROM interface in use, AT73C501

(or AT73C502) interface disabled

B8

INI

High level of Lx flags indicates that a phase voltage is

above 10% level of the full scale voltage. If a voltage drop

is detected, the corresponding status bit is written low.

AT73C500 is continuously monitoring the voltage of each

phase.

Figure 13. Transfer of billing information to processor following a PFAIL interrupt

337 clock cycles

45 clock cycles

280 clock cycles

LATCHED

DATDRY

CLK

STROBE

Sync LS

Sync MS

Mode

Status

Status data

Data 1

Data 2

Data 12

Data 1

Data 2

Data 12

Measurement data, 12 bytes + 12 bytes

Synchronisation data

In case of an imminent voltage break, the microprocessor

stores the energy values into a non-volatile memory. The

devices can operate for a short period of time powered by

an electrolytic capacitor or by battery back-up.

STUP output (active high) indicates that the current of each

of the three phases is below the specified starting level and

no energy is accumulated. This status flag is very useful

during the calibration of a meter since immediate feedback

about staring current level is provided.

AT73C500 devices are taken to a soft reset state and nor-

mal operation will be recovered after the supply voltage is

high again. About one line cycle is needed to start normal

measurements. During this initialization phase no calcula-

tions are performed.

TAMP flag informs about potential tampering. It is activated

if one or more phase currents are zero or negative. There-

fore it very effectively indicates current transformer reversal

or short-circuit.

17

Impulse Outputs

active energy of the three single phase channels summed

together as shown in the table below.

AT73C500 provides eight impulse outputs, four meter con-

stant outputs and four pulse outputs to drive electrome-

chanical display counters which can register exported and

imported active energy and capacitive and inductive reac-

tive energy. These outputs use the same output lines as

used for the processor interface. Impulses are combined

with address 0 (ADDR0). The table below shows the

impulse outputs available in modes 1 and 3. Mode 7 offers

the same outputs, but the rate of the display pulses is

10imp/kWh (kVArh).

Output Bit

Impulse

Not Used

Output Type

Not Used

Impulse Rate

B7

B6

B5

-

Meter Constant

Sum of all 3

channels

B4

± Wh

1250imp/kWh

Impulse Outputs in Operating Modes 1 and 3

Display,

Channel 1

B3

B2

± Wh

100imp/kWh

Output Bit

Impulse

- VArh

+ VArh

- Wh

Output Type

Meter Constant

Display

Impulse Rate

1250imp/kVArh

1250imp/kWh

100imp/kWh

Display,

Channel 3

B7

B6

B5

B4

B3

B2

B1

B0

Display,

Channel 2

B1

B0

± Wh

100imp/kVArh

-

Not Used

+ Wh

Test Mode

- Wh

Display

100imp/kWh

This mode can be used for initial calibration purposes or in

a special meter for additional processing of sample data. In

this mode, AT73C501/AT73C502 samples the six inputs

normally and transfers the samples to AT73C500, which

performs DC suppression and further writes the samples to

8-bit processor bus together with header bytes in the fol-

lowing sequence.

+ VArh

- VArh

Display

100imp/kVArh

Display

An external register is needed to latch and buffer the

pulses. The register can further drive both electromechani-

cal display counters and LEDs. In modes 1 to 4, the nomi-

nal pulse rate of display outputs is 100imp/kWh or

100imp/kVArh (U_MAX= 270V, I_MAX= 80A) and meter con-

stant outputs 1250imp/kWh (1250imp/kVArh). The length

of each display pulse is 117ms when operated from 3.2678

MHz crystal. Meter constant pulse stays high for 20 ms.

Byte

1

Contents

Sync LS byte

2

Sync MS byte

3

Mode Byte

If the devices are used in a 5A meter, current inputs can be

scaled to 8A full scale level. In this case, the nominal

impulse rates are ten times higher than the above values.

4

Status Byte

5

I1, LS byte and MS byte

U1, LS byte and MS byte

I2, LS byte and MS byte

U2, LS byte and MS byte

I3, LS byte and MS byte

U3, LS byte and MS byte

6

Multi-channel Mode

Modes 2 and 4 are reserved for multi-channel operation. In

these modes, the chips operate like three independent sin-

gle phase meters and store the calculation results in sepa-

rate registers phase-by-phase (meter-by-meter). The basic

sequence of operation is otherwise similar to the normal

mode.

7

8

9

10

Impulse Outputs

Several input combinations can be measured to check the

gain and phase error in different conditions. An interfacing

computer can be programmed to calculate the calibration

coefficients based on the samples supplied by AT73C500.

At the end of the calibration, the coefficients have to be

stored in a non-volatile memory of the meter as described

in “Loading of Calibration Coefficients” on page 19.

In multichannel operation, three impulse outputs are avail-

able for display counters. The absolute energy value is

measured and the reversal of current flow doesn’t affect to

pulse rates. Meter constant pulse rate corresponds to total

AT73C500

18

AT73C500

Calibration

The calibration coefficients always have to be loaded into

AT73C500 registers after reset state. The coefficients are

either read from an external EEPROM or supplied by a

microprocessor via the 8-bit bus.

four header bytes, Sync LS, Sync MS, mode and status

information on the µP bus and then starts waiting for the

calibration data. The processor reads the status and mode

and after that writes the coefficients on the bus. The con-

tents of AT73C500 header bytes is described in “Data

Transfer to External Microprocessor” on page 12 and “Sta-

tus Information” on page 17.

Loading of Calibration Coefficients

In modes 3 and 4, a microprocessor takes care that the

coefficients are kept in a non-volatile memory during volt-

age break. After the voltage break, the DSP first writes the

Figure 14. Timing of calibration coefficient read operation

CLK

FT500 READY TO

DATRDY

STROBE

READ CALIBRATION DATA

SYNC LS

SYNC MS

MODE

STATUS

COEFFICIENT 0

COEFFICIENT 42

COEFFICIENT 1

COEFFICIENT 43

.

. .

HEADER DATA SUPPLIED BY FT500D

44 COEFFEICIENTS READ

Before using the µP bus, AT73C500 writes a short pulse

(DATRDY) to B9 bit of the Status bus combined with high

level of address 0 (ADDR0 output). This bit can be taken

directly or through an external latch to the interrupt input of

the processor. After writing the status and mode bytes,

AT73C500 goes to a read mode and starts waiting for cali-

bration coefficients from the µP. Processor supplies the

coefficients as 8-bit bytes one after another. The timing of

this sequence is presented in Figure 14.

Nine gain calibration, six offset calibration and three phase

calibration coefficients are read into the AT73C500 mem-

ory. At the same time, a scaling factor for the display pulse

rate and an adjustment value for starting current is stored.

To minimize the risk of erroneous calibration values, a

back-up value of each coefficient is also transferred by the

microprocessor or from the ROM. The back-up value has to

be written as 2’s complement binary number of the actual

calibration figure.

19

The calibration data is transferred in the following sequence:

Byte

0

Calibration Coefficient

PC1

Byte

1

Calibration Coefficient

PC1 back-up

2

PC2

3

PC2 back-up

4

PC3

5

PC3 back-up

6

MCC

7

MCC back-up

Not used

8

Not used

AGC1

9

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

AGC1 back-up

AGC2 back-up

AGC3 back-up

RGC1 back-up

RGC2 back-up

RGC3 back-up

UGC1 back-up

UGC2 back-up

UGC3 back-up

STUPC back-up

AOF1 back-up

AOF2 back-up

AOF3 back-up

ROF1 back-up

ROF2 back-up

ROF3 back-up

OFFMOD back-up

AGC2

AGC3

RGC1

RGC2

RGC3

UGC1

UGC2

UGC3

STUPC

AOF1

AOF2

AOF3

ROF1

ROF2

ROF3

OFFMOD

The meaning of the calibration coefficient mnemonics are as follows:

Mnemonic

PC_N

Meaning

Phase calibration factor, phase N

MCC

Display pulse adjustment factor for active and reactive energy

Gain calibration factor for active power and energy calculation, phase N

Gain calibration factor for reactive power and energy calculation, phase N

Gain calibration factor for phase voltage, phase N

Starting current adjustment factor

AGC_N

RGC_N

UGC_N

STUPC

AOF_N

Offset calibration factor for active power and energy calculation, phase N

Offset calibration factor for reactive power and energy calculation, phase N

Controls the use of offset factors

ROF_N

OFFMOD

AT73C500

20

AT73C500

AT73C500 provides four handshaking signals, ADDR1,

RD/WR, STROBE and BRDY, for interfacing with the

microprocessor. Microprocessor can use the BRDY input of

AT73C500 to extend the read and write cycles. AT73C500

stays in the read or write mode as long as BRDY is high.

BRDY is sampled at the rising edge of AT73C500 master

clock. As soon as BRDY goes low, the read/write cycle of

AT73C500 will end at the first rising edge of CLK clock.

During read operation data is latched into AT73C500 regis-

ter on the rising edge of the STROBE signal following the

low level of BRDY. A more detailed description about the

handshake signals is presented in section “Data Transfer

to External Microprocessor” on page 12.

ibrate the phase voltage values, only the calibration range

is different, 20% for power and 8% for voltage. These cali-

brations will automatically correct the gain error of other

measurement parameters.

The following calculations are done to get the calibrated

results. For active power:

AGC_N

P_N= P_N× 1 + 0.2 × ----------------

128

where PN is the active power of phase N and AGC_Nis the

gain calibration factor of that phase. The valid range for

AGC_Nis -128 to +127. Similarly, for reactive power:

Fifteen idle cycles are inserted by AT73C500 between the

read operation of each calibration byte. This allows the pro-

cessor to prepare the next coefficient for transfer or to raise

the BRDY signal in case it is not ready to write the following

byte. If the data is available, BRDY can be kept constantly

low. Microprocessor has to always supply all 44 calibration

bytes even though some of those may be zero and don't

affect to measurement results.

RGC_N

Q_N= Q_N× 1 + 0.2 × ----------------

128

where QN is the reactive power of phase N and RGC_Nis

the gain calibration coefficient for that phase. RGC_Nvalid

range is -128 to +127.

Gain calibration performed on voltage measurements are:

If AT73C500 detects an error when comparing the calibra-

tion data and corresponding back-up values, it writes the

DATRDY bit high and after that the header bytes on pro-

cessor bus indicating that it is still in initialization routine

and wishes to get the calibration data to be transported

once again. If the error still exists after the third trial,

AT73C500 notifies the situation by a FAIL status bit and

starts normal operation, discarding potentially incorrect cal-

ibration coefficients.

UGC_N

U_N= U_N× 1 + 0.08 × ----------------

128

where UN is the line voltage of phase N and UGC_Nis the

corresponding gain calibration coefficient, ranging from

-128 to +127.

Apparent power and current are automatically gain

adjusted to match the calibrated settings of active power,

reactive power and voltage.

If AT73C500 is programmed to mode 1 or 2, the coeffi-

cients are stored in an EEPROM of type AT93C46. The

ROM has to support communication through a three pin

serial I/O port. The serial ROM interface uses the same

port, which also connects AT73C500 to

AT73C501/AT73C502 sample output. During the initializa-

tion phase, the ADC interface has to be disabled. This can

be done by B8 bit of AT73C500 Status bus (ADDR0). The

output has to be latched by an external flip-flop to keep the

state over the whole initialization period. The same output

can be used as Chip Select input for the EEPROM.

AT73C500 reads, checks and stores automatically all 44

calibration coefficients. After that, B8 bit of Status byte is

written low and normal measurement can start. If the

EEPROM contains erroneous data and one or more coeffi-

cients don’t match with their back-up values, the same pro-

cedure is followed as in the processor mode.

Offset Calibration

The low current response of current sensors is often more

or less non-linear. The error caused by this non-linearity

can be compensated by a small offset factor which is

added in power results. Offset calibration is done for active

and reactive power, separately for each phase. The follow-

ing formulas are used:

AOF_N

---------------

P_N≡ P_N+

× 0.004157 × sign(P_N) × P_FS

128

and

ROF_N

Q_N= Q_N+ --------------- × 0.00457 × sign(Q_N) × Q_FS

128

Gain Calibration

Gain calibration is used to compensate the accumulated

magnitude error of voltage dividers, current transformers

and A/D converters. There is a separate 8-bit gain calibra-

tion coefficient for each phase, and for active and reactive

energy measurement. A similar formula is also used to cal-

where P_Nand Q_Nare the active and reactive power for

phase N, AOF_Nand ROF_Nare the respective offset calibra-

tion coefficients and P_FSand Q_FSare the corresponding full

21

scale values of the powers. The nominal full-scale values

are:

current. The chip set has a preprogrammed starting current

level of

P_FS= 270V × 80A = 21.6kW

Q_FS= 270V × 80A = 21.6VAr

1

I_SU= ------------ × I _FS

4000

The valid range for the offset calibration factors is -128 to

+127.

where I_FSis the full scale current of the meter, i.e. 80A in

nominal conditions. The default startup current corre-

sponds to 0.4% of the 5A I_b, assuming that the full-scale

range is 80A. When the phase current is below the starting

level, the calculated cycle power results are replaced by

zeros and no energy is accumulated.

The scale of offset calibration for active and reactive power

is different, 89W versus 98VAr in nominal conditions of

270V maximum phase voltage and 80A maximum phase

current. Typically, a small offset factor of a few watts is

enough to compensate the non-linearity of current sensing.

It should be noted that offset calibration will also affect the

starting current level of a meter. If the full scale current or

voltage is changed to a non-default value, the range for off-

set calibration will be scaled accordingly.

It is possible to adjust the start-up level in the range of 0.2

to 10 compared with the nominal value. This is performed

with a special calibration factor. The following formula is

used to determine the current:

The same offset value is used independent of phase angle.

However, as default (OFFMOD=0), the sign of power is

taken into account in the calculations so that positive offset

factor will always increase the absolute power value and

negative coefficient will decrease absolute results. This

guarantees that current sensor non-linearity is corrected in

the same way even though the current flow is reversed.

1

I_SU= ------------ × I _FS× (1 + 0.2 × STUPC)

4000

where STUPC is the starting current calibration factor,

allowed to vary in range -4 to +45, only. Care should be

taken that the STUPC is correctly programmed and is not

beyond -4 to 45 range. Also, it should be noted that low

starting thresholds may force the device to a level where

accuracy is restricted due to a finite resolution of converters

and mathematics.

It is possible to change this default condition by program-

ming value one to OFFMOD coefficient. In this case, offset

coefficient will be always added to power result without

checking the sign of the power. Positive coefficient will

increase the absolute value of positive power results and

decrease the absolute value of negative result.

Adjustment of Display Pulse Rate

An 8-bit byte is provided for adjustment of the impulse rate

of display pulses. This coefficient will only affect the display

pulse rate of active and reactive energy but not to the meter

constant rate. The content of all measurement registers will

remain unchanged.

Phase Calibration

The phase difference between voltage and current channel

is compensated with three 8-bit phase calibration figures.

The displacement is usually due to the phase shift in cur-

rent transformers. Based on the calibration values, the

DSP interpolates new current samples with sample instants

coinciding with the corresponding voltage samples. The fol-

lowing formula is used to determine the phase offset to be

used in the interpolation. One 8-bit phase calibration value

is stored for each of the three phases.

The impulse rate can be scaled in the range of 1 to 10 com-

pared to the nominal value. In default conditions (U_max

=

270V, I_max= 80A) the LSB of energy registers REG12-15

(See “Status Information” on page 17.) corresponds to

0.4Wh. This means that accumulated 25 LSBs of energy

will generate one pulse to the display pulse output (25 x

0.4Wh/impulse = 10 Wh/impulse = 100 impulses/kWh).

By using MCC calibration coefficient, the nominal figure 25

can be changed in the range of 25 to 250. The following

formulas are used to calculate the impulse rate.

PC_N

PO_N= ----------- × 5.625°

128

IMP = (25 + MCC) × E_LSB

where PO_Nis the sample phase offset of channel N, mea-

sured as phase(U) - phase (I). The allowed range for phase

calibration factor, PC_N, is -128 to +127.

and

Starting Current Adjustment

1000

PR = -------------------------------------------------

(25 + MCC) × E_LSB

The meter IC is designed to fulfill IEC 1036, class 1 specifi-

cation. This specification is based on a certain basic cur-

rent, I_b. As a default, AT73C500 operates with 5A basic

where ELSB is the energy value of one LSB in the energy

register, 0.4Wh in default conditions. When the meter is

AT73C500

22

AT73C500

operated in non-standard conditions, the energy LSB may

be recalculated as:

example, the line voltage is chosen to be rescaled to 135V,

this is realized with a resistor divider of half the nominal,

and finetuning using the voltage gain coefficients. Also, all

values resulting from voltage calculation, such as the data

transferred via energy registers, should be normalized with

respect to the new voltage setting.

U

_FS× I_FS

------------------------------ ------------------------------

× 0.4Wh

3.2768MHz

E_LSB

=

×

f

270V × 80A

Going back to the calibration of the display pulse rate, the

new LSB value of energy registers is:

where f is the clock frequency used, and U_FSand I_FSare

the full-scale values of voltage and current.

In case the meter is used with a non-default voltage divider

or current sensor, MCC factor is a convenient way to read-

just the impulse rate.

140V

270V

E_LSB= ------------- × 0.4Wh = 0.20741…Wh

Example

To maintain the display pulse rate at 100, the MCC calibra-

tion coefficient must be programmed as:

The meter is to be configured for use in 120V networks,

with a maximum line voltage of 140V. The display pulse

rate is required to remain at 100imp/kWh. To start off, the

front end of the meter must be configured for the new line

voltage. The voltage dividers must be configured to pro-

duce an input signal of 0.707V at the input of the ADC at

maximum line voltage. At nominal meter settings, the volt-

age divider ratio is 270V:0.707V, in this case it must be

140V:0.707V.

1000

= ----------------------------- –

PR × E

1000

= ----------------------------------------------------------- –

imp

MCC

25

23.216… ≈ 23

=

LSB

100----------- × 0.20741Wh

kWh

Note that adjusting the line voltage of the meter will render

the formatting of most calculation registers to alternative

settings. For example, the meter constant pulse rate will

change as follows:

The energy value of each display counter impulse is there-

after:

1

140V

IMP = (25 + 23)--------- × ------------- × 0.4Wh ≈ 10.0---------

imp 270V imp

Wh

270V × 80A

MC = ------------------------------ × ------------------------------ × 1250 -----------

_FS× I_FS3.2768MHz kWh

f

imp

U

In our case of a meter for 120V networks, the new meter

constant pulse rate would be:

In mode 7, the default display pulse rate is 10

impulses/kWh(kVArh) instead of 100 impulses/kWh. This is

convenient for meters where only one decimal digit wants

to be shown. This default rate can also calibrated and the

calibration formulas are:

270V

MC = ------------- × 1250----------- = 2410.714…-----------

140V kWh kWh

imp

To make the meter constant pulse rate to an even number,

say 2500, we may choose to either re-scale the line voltage

or scale the maximum line current. 2500 impulses per kilo-

watt hour is gained by either setting the maximum line volt-

age to:

IMP = (250 + MCC) × E_LSB

and

270V

imp

2500-----------

kWh

imp

kWh

1000

U_FS= ------------------------- × 1250----------- = 135V

PR = -----------------------------------------------------

(250 + MCC) × E_LSB

Master Clock

or by retaining the line voltage at 140V and scaling the

maximum line current to:

The master clock of AT73C500 is generated by a crystal

oscillator with crystal connected between pins XI and XO of

AT73C501/AT73C502. Master clock can also be fed to the

XI input from a separate clock source. The system clock

rate of AT73C500 is the same as the clock of

AT73C501/AT73C502 and is fed to the CLK input of the

device from the CLK output of AT73C501/AT73C502.

270V × 80A

---------------------------------------------

imp

-----------

kWh

I_FS

=

× 1250

= 77.143…A

-----------

140V × 2500

kWh

Regardless of which parameter (or both) is chosen, the

scaling process is a simple matter of gain calibration. If, for

23

Electrical Characteristics

Absolute Maximum Ratings

Measurement Accuracy

The accuracy measurements are based on the usage of

the AT73C500 DSP with the single-ended ADC,

AT73C501. Using the differential-ended ADC, AT73C502,

improves some of the results.

Parameter

Min

Typ

Max

Unit

Supply Voltage V_CC

,

4.75

5.25

V

_DA, V_DDA

Input Conditions

V_DD

+0.3

-0.3

1.25

V

When specifying measurement accuracy, it is assumed

that 80A_RMSphase current will produce 2V_PPfull scale input

voltage to current converters. The basic current, I_B, is sup-

posed to be 5A_RMS

The nominal phase voltage, U_N, is specified to be 230V_RMS

and 2V_PPfull scale input is produced by 270V_RMS

Input Voltage, Digital

Input Voltage, Analog

V_DA

+0.3

.

Input Voltage, CI and

VI inputs

3.75

.

Ambient Operating

Temp.

Overall Accuracy, Active and Reactive Power and

Energy Measurement

Overall accuracy including errors caused by A/D-conver-

sion of current and voltage signals, calibration and calcula-

tions.

-25

-65

+70

C

Storage Temperature

+150

Calibration Characteristics

The accuracy figures are measured in nominal conditions

unless otherwise indicated in the parameter field of the

table below.

Parameter

Min

Typ

Max

Units

Gain Calibration

Calibration Range ±

20

%

Parameter

Nominal Value

230V, ±1%

270V

Calibration

Resolution

Nominal voltage, U_N

Full-scale voltage, U_FS

Full-scale current, I_FS

Base current, I_B

0.16

Phase Calibration

80A

Calibration Range ±

5.625

0.044

degree

5A

Calibration

Resolution

Frequency, f

50.0 Hz, ±0.3%

1

Power factor, PF

Offset Calibration,

Active Power

Harmonic contents of voltage

Harmonic contents of current

Temperature, T

less than 2%

less than 20%

23°C, ±2°C

3.2768 MHz

Calibration Range

89.8

W

Calibration

Resolution

0.7015

AT73C500 master clock

Range,% of Full

Scale Phase Power

0.4157

%

Offset Calibration,

Reactive Power

Calibration Range

98.7

VAr

Calibration

Resolution

0.7712

Range,% of Full

Scale Phase Power

0.457

%

AT73C500

24

AT73C500

The measurements are done according to IEC1036 specifi-

cation. The results are averaged over a period of 10s.

Before measurements, AT73C500 devices have been

operational for minimum 1h.

Effect of Crosstalk

The error caused by crosstalk from one current input to

other two current inputs when the meter is carrying a sin-

gle-phase load.

Measurement Bandwidth

Single-Phase Load Error

Power

Parameter

Min

Typ

Max

Units

Current

Voltage Factor Min Typ Max Units

General, 50 Hz line

frequency

0.1I_B...I_FS

U_N

1.000

-0.5

+0.5

%

- high limit (-3dB)

- low limit (-3dB)

750

Hz

0.5

lagging

0.1I_B...I_FS

30

Reactive Power and

Energy, Voltage and

Current Measurement

Influence Quantities

The additional error caused by different influence quanti-

ties.

- high limit

- low limit

360

350

Hz

Voltage Variation Error

Power

40

20

Current

Voltage

Factor

Min

Typ

Max

Units

Line Frequency

- high limit

- low limit

Hz

0.9U_N...

1.1U_N

0.1I_B

1.000

-0.2

+0.2

%

0.9U_N...

1.1U_N

0.5

lagging

0.1I_B

-0.2

+0.2

%

Maximum Error

Power

Current

0.05I_B

Voltage Factor Min Typ Max Units

U_N

1.000

-0.4

-0.2

-0.4

+0.4

+0.2

+0.4

%

0.1I_B...I_FS

0.5

0.1I_B

U_N

%

lagging

0.5

lagging

-0.4

-1.0

+0.4

+1.0

0.2I_B...I_FS

0.1I_B

0.8

leading

0.8

leading

0.2I_B...I_FS

0.25

lagging

25

Frequency Variation Error

Frequency

0.95f_N...1.05f_N

0.8f_N...5f_N

Current

0.1I_B

Voltage

Power Factor

1.000

Min

-0.2

-5.0

Typ

Max

+0.2

+0.5

Units

%

U_N

0.1I_B

0.5 lagging

1.000

%

0.1I_B

%

0.8f_N...5f_N

0.1I_B

0.5 lagging

%

Harmonic Distortion Error

Current

Voltage

Min

Typ

Max

Units

40% of 5^thharmonic in current

10% of 5^thharmonic in voltage

-0.5

+0.5

%

Reversed Phase Sequence Error

Current

Voltage

Min

Max

Units

0.1I_B

U_N

-0.3

+0.3

%

Voltage Unbalance Error

Voltage

Current

Min

Max

Units

0.1I_B

One or two phases carry 0V

-0.4

+0.4

%

DC Component in Current Error

Current

Voltage

Min

Max

Units

I^DC=0.1I_FS

U_N

-0.5

+0.5

%

AT73C500

26

AT73C500

Starting Current

Table Apparent Power and Energy Measurement

As default, the starting current is based on 5A basic current

and 80A full scale current range.

Apparent Power and Energy Error

Current

Min

-0.5

-2.0

-5.0

Typ

Max

+0.5

+2.0

+5.0

Units

%

Starting Current

0.05I_FS...I_FS

Voltage

Min

Typ

Max

Units

0.005I_FS...0.05I_FS

0.001I_FS...0.005I_FS

%

U_N

0.004

IB

%

Temperature Coefficient

Measured with the internal reference voltage source of

AT73C501/AT73C502.

The accuracy of Power Factor measurements was tested

with PF values 0.5, -0.5, -1 and 1.

Mean Temperature Coefficient

Power

Table Power Factor Measurement

Power Factor Error

Current

Voltage Factor

Min

Typ

Max Units

Current

Min

-0.5

-2.5

Typ

Max

+0.5

+2.5

Units

%

0.1I_B...I_FS

U_N

1.000

0.02 0.04

%/K

0.05I_FS...I_FS

0.005I_FS...0.05I_FS

0.5

lagging

0.1I_B...I_FS

%

Table Phase Voltage Measurement

Phase Voltage Error

Other Parameters

The accuracy of the following parameters is measured in

the conditions below unless otherwise indicated in the

parameter field of the table. The measurement error has

been calculated based on values averaged over 1min

period.

Voltage

Min

Typ

Max

Units

0.2U_FS...U_FS

-0.5

+0.5

%

Table Phase Current Measurement

Parameter

Nominal Value

Power Factor Error

Nominal voltage, U_N

Full-scale voltage, U_FS

Full-scale current, I_FS

Base current, I_B

230V, ±1%

Current

Min

-0.5

-2.5

Typ

Max

+0.5

+2.5

Units

%

270V

0.05I_FS...I_FS

0.005I_FS...0.05I_FS

80A

%

5A

Table Frequency Measurement

Frequency Error

Min

-0.5

Frequency, f

50.0 Hz, ±0.3%

Power factor, PF

1

Frequency

Typ

Max

Units

Harmonic contents of voltage

Harmonic contents of current

Temperature, T

0%

40 Hz...100 Hz

+0.5

%

0%

23C, ±2°C

3.2768 MHz

AT73C500 master clock

27

Digital Characteristics

V_DD= 5V, V_DA= 5V

Parameter

Min

Typ

Max

Units

V

High-Level Input Voltage

4.0

Low-Level Input Voltage

1.0

V

High-Level Output Voltage, I_SOURCE= -100 µA

Low-Level Output Voltage, I_SINK= 0.5 mA

Input Leakage Current

4.0

-10

V

0.4

V

10

µA

Crystal Oscillator

Parameter

Min

Typ

Max

6.0

30

Units

MHz

Crystal Frequency

1.0

Crystal Inaccuracy

ppm

Crystal Temp Coefficient (-25°C...+70°C)

30

ppm/C

AC Parameters

Parameter

Min

1.0

40

Typ

Max

6.0

60

Units

MHz

%

Master Clock Frequency

Clock Duty Cycle at XI pin

Timing of 8-bit Bus

Parameter

DDLY

DH

Parameter

Min

Max

Units

ns

Data Delay from Falling Edge of STROBE

Data Hold Time From Rising Edge of STROBE

Strobe Delay from Falling Edge of Clock

Strobe Hold Time From Rising Edge of Clock

Addr Setup Time to Rising Edge of STROBE

Addr Hold Time From Rising Edge of STROBE

RD/WR Setup to Rising Edge of STROBE

RD/WR Hold from Rising Edge of STROBE

BRDY Set-Up Time to Rising Edge of Clock

25

5

0

ns

SDLY

SH

20

ns

3

ns

ASU

10

3

ns

AH

ns

RWSU

RWH

BRS

10

3

ns

40

ns

Power Supply Characteristics

Parameter

Min

Typ

Max

Units

V_DD, V_DA

Supply Voltage

Supply Current

4.75

5.25

V

I_DD(AT73C501/AT73C502 +

AT73C500)

15

10

22

15

mA

V

I_DA(ADC)

A_GND

Supply Current

Analog Ground Voltage

Reference Voltage

2.45

1.17

2.5

1.27

2.55

1.37

V_REF-A_GND

V

AT73C500

28


型号：	AT73C501
厂家：	ATMEL
描述：	Chip Set Solution for Watt-Hour Meters 芯片集解决方案式电能表
文件：	总28页 (文件大小：249K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT73C501 [ATMEL]

相关型号：

AT73C501-JC

AT73C502

AT73C502-QC

AT74011-H2B1-4F

AT74011-H2B1-4N

AT74013-H2B-4N

AT74013-H2B1-4F

AT74013-H2B1-4N

AT74017-H2B1-4F

AT74017-H2B1-4N

AT746

AT746S26