AT73C246-B_技术文档

Features

• AUDIO CODEC

– 100dB Dynamic Range Stereo Audio DAC - 8 to 96 kHz sampling frequency

– 96dB Dynamic Range Stereo Audio ADC - 8 to 96 kHz sampling frequency

– 16 / 32 Ohms headset amplifier with capless operation

• SNR: 97 dB A-Weighted

• THD: -60 dB (16Ohms / 20mW / 3.3V supply)

• Maximum output power: 55mW (16Ohms / 3.3V supply)

– Stereo line inputs, stereo auxiliary inputs

– Stereo microphone inputs with bias generator for electret device

– Low power Analog Bypass mode (Line / Aux in to Headset Out)

– Low power Analog sidetone mode (Microphone in to Headset Out)

– Automatic Audio path control with smooth fade in / fade out operation

– I²S port

Power

Management

and Analog

Companions

(PMAAC)

• Master / Slave Operation

• I²S / Left / Right justified modes

• 16 / 18 / 20 / 24 bit operation

• 6x SUPPLY CHANNEL VOLTAGE REGULATORS

– DCDC0:

• 1.85V - 600mA. 0.8 to 3.6V / 50mV step.

AT73C246

6 Supply

• 2 MHz switching buck regulator

• Fast load transient response - PWM / PFM modes.

• Efficiency up to 92%

– DCDC1:

Channel PMU

With Audio

Codec

• 1.2V - 600mA. 0.8 to 3.6V / 50mV step.

• 2 MHz switching buck regulator

• Fast load transient response - PWM / PFM modes.

• Efficiency up to 90%

– LDO2: 1V - 300mA. 0.8 to 1.35V / 50mV step - Fast transient response

– LDO3: 3.3V - 200mA. 2.7 to 3.6V / 50mV step - Fast transient response

– LDO4: 3.3V - 200mA. 2.7 to 3.6V / 50mV step - Audio codec supply

– LDO5: 2.5V - 10mA - Backup battery charger and RTC supply

• LOW CONSUMPTION POWER MANAGER

– 2.5V - 5.5V VIN Operation

– 20uA typical consumption OFF mode

– VIN monitor, CPU supplies monitor

– Die temperatue and over-current protections

– Reset and Interrupt generation

– Automatic Voltage Ramping on supply channels for DVS applications

– Standby mode with selectable supplies OFF

• RTC

– Ultra Low power crystal oscillator (<1uA typ.)

– Wake up function with programmable alarm or selectable inputs

• 10-b / 300kS/s ADC with 4 external / 6 int\ernal selectable inputs

• Two-Wire Interface for PMU and Audio controls

• Available in 7.5 x 7.5 x 0.9 mm 64-pin QFN Package

• Applications: Multimedia, Audio + Supply solution for MPU+DDR2 designs.

11050A–PMAAC–07-Apr-10

1. Description

The AT73C246 is an integrated high performance Power Management and Audio IC. It is specif-

ically designed for advanced technology application processors with complex and low voltage

supplies targeting audio applications from low to high end. This System-on-Chip allows signifi-

cant savings in both cost and board area over previous discrete solutions.

Directly operated from a 2.9V to 5.5V input voltage, the PMU generates a set of 4 regulated

power supplies and an associated delayed reset signal. These 4 voltages are built up with 2 high

efficiency DCDC buck converters and 2 low noise LDOs. Featuring ultra fast transient responses

and integrating automatic voltage scaling function, these supplies perfectly fit with modern low

voltage MCU cores and memory supplies (DDR, Flash, ...). An additional 200mA LDO under

software control is provided for auxiliary application functions. The high performances of this

LDO (high PSRR, low noise, fast transient response) makes it ideal for analog front-ends (Audio,

RF...) as well digital peripherals.

Aside from the PMU, the AT73C246 integrates a complete state-of-the art low power audio

codec with headphone amplifier. On the input side, a stereo microphone preamplifier with differ-

ential or single ended connection (MICDIFF / MIC) and 2 selectable stereo inputs (LINE / AUX)

are directed to a 96dB Dynamic Range stereo audio ADC through an input mixer. On the output

side a 100dB dynamic range stereo audio DAC drives, through an output mixer, a 60 mW stereo

headphone amplifier which comes along with a VCM buffer. This VCM buffer allows to save two

large on-board coupling capacitors for area constrained applications. Additionally two fully ana-

log paths called bypass and sidetone from line / aux and microphone inputs to headphone

outputs allow to reduce the audio power consumption to minimum when needed.

The PMU is complemented with a low power RTC system including a recharging LDO, a crystal

oscillator and a programmable alarm that is fully integrated in the PMU digital core. Thus, the

RTC function is able to wake up the PMU, i.e the regulated power supplies, at a programmed

instant.

Also, a 10-bit ADC equipped with a 10:1 analog multiplexer is provided to the application to per-

form voltage measurements.

Finally, to reduce power consumption to minimum, the PMU features a flexible STANDBY mode

where the MCU is placed in reset state with selectable supplies ON, OFF or in low-power mode.

Power consumption in OFF mode is typically 20uA.

2

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

2. Block Diagram

Figure 2-1. AT73C246 functional block diagram

VIN4

LDO4

3.3V

Max: 200mA

(CODEC)

37

36

VIN0

SW0

BUCK0

1.8V

57

VDD4

58

56

59

53

VFB0

Max: 600mA

(CORE + MEM)

LINL

LINR

28

GND0

VIN1

SW1

27

30

29

34

BUCK1

1.2V

AUXL

AUXR

MICL

54

VFB1

Max: 600mA

(CORE)

52

55

AUDIO IN

GND1

+ ADC

MICLN

MICR

31

33

VIN2

LDO2

1V

Max: 300mA

(CORE)

51

VDD2

VIN3

MICRN

32

50

38

LDO3

3.3V

Max: 200mA

(I/O)

AVDD

18

35

MICBIAS

AUDIO

BIAS

VDD3

39

1

VMID

12

17

VBACKUP

AGND

LDO5

2.5V

Max: 10mA

(BACKUP)

AUDIO

CODEC

VINSYS

VDDC

HPDET

HPR

7

8

13

14

DIGITAL

CORE

LDO6

1.8V / 10mA

(Internal

AUDIO OUT

+DAC

HPL

16

15

functions)

HPVCM

REXT

VBG

10

9

PMU

BIAS

MCLK

LRFS

44

43

GNDSYS

11

AUDIO

PORT

BCLK

DAI

42

41

40

RSTB

ITB

20

19

DAO

WAKEUP1

WAKEUP2

23

24

XIN

63

PMU STATE

MACHINES

WAKEUP3

VPAD

XOUT

25

45

64

49

CLK32K

WAKEUP0

VBACKUP

RTC +

OSC

DGND

LED

62

60

65

2

HRST

PWREN

61

DIE TEMP

SENSOR

Internal voltages

DCDC

4MHz RC

OSCILLATOR

ANA0

ANA1

ANA2

ANA3

3

4

5

ANALOG

MUX

10b SAR

ADC

SYSTEM

32KHz RC

OSCILLATOR

TWI

NC

46

6

NC

TWCK

TWD

22

21

26

47

48

3

11050A–PMAAC–07-Apr-10

3. Package and Pinout

Figure 3-1. AT73C246 QFN64 package pinout - Top view

64

49

48

VBACKUP

LED

1

NC

ANA0

NC

ANA1

VPAD

MCLK

LRFS

BCLK

ANA2

ANA3

VINSYS

VDDC

VBG

DAI

DAO

REXT

VDD3

VIN3

GNDSYS

VMID

VIN4

HPDET

HPR

VDD4

MICBIAS

MICL

MICR

HPVCM

HPL

16

17

33

32

4

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

4. Pin Description

Table 4-1.

Pin Name

VBACKUP

Pin Description

I/O

Pin Number

Type

Function

Output

1

Analog

RTC supply

Output for blinking led. Leave not

connected if a LED is not wired.

LED

Output

2

Digital

ANA0

ANA1

ANA2

ANA3

VINSYS

Input

3

4

5

6

7

Analog

Power

Measurement input 0

Measurement Input 1

Measurement Input 2

Measurement Input 3

PMU core supply

PMU / Audio digital supply. Internal use

only. No resistive load.

VDDC

VBG

Output

8

9

Analog

PMU Voltage reference

Resistor connection for PMU bias

current

REXT

10

GNDSYS

VMID

GND

Output

Input

11

12

13

14

15

16

17

18

Analog

Power

PMU ground

Audio Codec Mid-Supply reference

Headset detector

HPDET

HPR

Output

GND

Headset output right

HPVCM

HPL

Headset virtual ground output

Headset output left

AGND

AVDD

Audio Codec ground

Audio Codec supply input

Input

Interrupt request - Active low - Open-

drain

ITB

Output

19

Digital

RSTB

TWD

Output

Input/Output

Input

20

21

22

Digital

CPU reset - Active low - Open drain

Two Wire Interface - Data

TWCK

Two Wire Interface - Clock

Wake up 1 Input - VPAD level - 100k

Pull down

WAKEUP1

WAKEUP2

WAKEUP3

Input

23

24

25

Digital

Wake up 2 Input - VPAD level - 100k

Pull down

Wake up 3 input - VPAD level - 100k

Pull down

NC

-

26

27

28

29

30

-

Connect to DGND

LINR

LINL

AUXR

AUXL

Input

Analog

Audio Line input right

Audio Line input left

Audio auxiliary input right

Audio auxiliary input left

5

11050A–PMAAC–07-Apr-10

Table 4-1.

Pin Name

MICLN

MICRN

MICR

MICL

Pin Description

I/O

Pin Number

31

Type

Analog

Power

Analog

Power

Analog

Digital

Power

-

Function

Input

Audio negative microphone input left

Audio negative microphone input right

Audio positive microphone input right

Audio positive microphone input left

Voltage bias for electret microphone

LDO4 output - 3.3V typ

LDO4 input

Input

32

Input

33

Input

34

MICBIAS

VDD4

VIN4

Output

Input

35

36

37

VIN3

Input

38

LDO3 input

VDD3

DAO

Output

Input

39

LDO3 output - 3.3V typ

Digital audio port data output

Digital audio port data input

Digital audio port bit clock

Digital audio port left/right clock

Audio codec master clock input

PMU I/O ring supply

40

DAI

41

BCLK

LRFS

MCLK

VPAD

NC

Input/Output

Input

42

43

44

Input

45

-

46

Leave open

NC

-

47

-

Connect to DGND

NC

-

48

-

Connect to DGND

MCLK32

VDD2

VIN2

Output

Input

49

Digital

Analog

Power

Analog

Power

Analog

RTC clock output - VPAD level

LDO2 output

50

51

LDO2 input

VFB1

VIN1

Input

52

DCDC1 Voltage feedback input

DCDC1 power stage supply

DCDC1 power stage output

DCDC1 power stage ground

DCDC0 Voltage feedback input

DCDC0 power stage supply

DCDC0 power stage output

DCDC0 power stage ground

Input

53

SW1

Output

Ground

Input

54

GND1

VFB0

VIN0

55

56

Input

57

SW0

Output

Ground

58

GND0

59

Hard reset - VBACKUP level - 100k Pull

down

HRST

Input

60

61

62

Digital

Power on/off - VBACKUP level - 100k

Pull down

PWREN

WAKEUP0

Wake up 0 input - VBACKUP level -

100k Pull down

6

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Table 4-1.

Pin Name

XIN

Pin Description

I/O

Pin Number

Type

Function

Input

63

64

65

Analog

RTC crystal oscillator input

RTC crystal oscillator output

PMU digital ground + Thermal pad.

XOUT

Output

DGND

Ground

7

11050A–PMAAC–07-Apr-10

5. Application Block Diagram

Figure 5-1. AT73C246 Application Block Diagram

37

VIN4

LDO4

3.3V

Max: 200mA

(CODEC)

VIN

C42

10µF

36

VDD4

C41

10µF

57

58

56

59

VIN0

SW0

VIN

BUCK0

1.8V

LINEJACK

AUXJACK

100

R30

C1

28

3.3µF

C39

LINL

L1

10µF

R29

100K

C40

1nF

VDD0

2.2µH

C2

VFB0

R28

Max: 600mA

(CORE + MEM)

22µF

C38

1nF

J1

J2

100K

LINR

27

30

3.3µF

C37

GND0

R31

R27

100

AUXL

3.3µF

C35

R25

100K

R26

C36

1nF

53

54

52

55

VIN1

SW1

VIN

BUCK1

1.2V

R24

C34

1nF

C3

10µF

100K

L2

29

34

AUDIO IN

3.3µF

C33

AUXR

MICL

VDD1

2.2µH

100

+ ADC

C4

22µF

1µF

C31

MIC_L

VFB1

Max: 600mA

(CORE)

C32

1nF

J3

R22

2K

GND1

1µF

C29

31

33

32

MICLN

MICR

R23

C30

1nF

51

50

VIN2

2K

LDO2

1V

Max: 300mA

(CORE)

VDD0

C5

2.2µF

1µF

C27

MIC_R

J4

C28

1nF

R18

2K

VDD2

C6

10µF

1µF

C25

MICRN

R19

2K

C26

1nF

38

39

VIN3

VIN

LDO3

3.3V

Max: 200mA

(I/O)

C7

VDD4

10µF

18

35

12

17

AVDD

MICBIAS

VDD3

AUDIO

BIAS

C8

10µF

VMID

C23

1µF

R1

2K

AGND

1

VBACKUP

LDO5

2.5V

Max: 10mA

(BACKUP)

C9

2.2µF

AUDIO

CODEC

Backup

Battery

BAT1

DIGITAL

CORE

HEADSET 32ohms

HPDET

HPR

VINSYS

13

14

7

8

VINSYS

C10

2.2µF

LDO6

1.8V / 10mA

AUDIO OUT

+DAC

HPL

16

15

J5

(Internal

HPVCM

VDDC

functions)

C11

2.2µF

LINEOUT

C22

3.3µF

C21

3.3µF

R14

100

10

9

REXT

R2

PMU

BIAS

560k

VBG

1%

J6

R13

100K

R12

100

R15

C12

22nF

100K

11

GNDSYS

44

43

42

MCLK

LRFS

VDD0/VDD3

R3

4.7K

AUDIO

PORT

I²S

to MCU

BCLK

DAI

20

RSTB

41

40

C13

10nF

VDD0/VDD3

R4

DAO

4.7K

19

ITB

C19

C14

10nF

12p

23

WAKEUP1

XIN

63

64

49

X1

S3

100K

XOUT

WAKEUP2

WAKEUP3

C20

12p

24

100K

25

100K

45

VBACKUP

PMU STATE

MACHINES

From MCU

CLK32K

WAKEUP0

62

VBACKUP

PUSHBUTTON

S2

100K

RTC +

OSC

VIN

R5

470

HRST

60

VDD0/VDD3

VBACKUP

PUSHBUTTON

S1

VPAD

100K

D1

2

65

LED

PWREN

61

PUSHBUTTON

DGND

100K

DIE TEMP

SENSOR

R8

100

ANA0

ANA1

ANA2

ANA3

3

ANA_0

C15

R9

100

22nF

DCDC

4MHz RC

OSCILLATOR

4

5

ANA_1

C16

22nF

ANALOG

INPUTS

10b SAR

ADC

R10

100

ANA_2

ANA_3

SYSTEM

32KHz RC

OSCILLATOR

C17

22nF

R11

100

6

NC

46

TWI

C18

22nF

26 47 48

22

21

TWCK

TWD

VDD0/VDD3

R6

4.7K

TWD

VDD0/VDD3

R7

4.7K

To MCU TWI

TWCK

8

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Table 5-1.

Typical Application Components Design

Schematic Reference

Value

2kΩ

Description

5% / 0.063W

1% / 0.063W

5% / 0.063W

R1, R18, R19, R22, R23

R2

560kΩ

4.7kΩ

470Ω

R3, R4, R6,R7

R5

R8, R9, R10, R11, R14, R15,

R26, R27, R30, R31

100Ω

5% / 0.063W

R12, R13, R24, R25, R28,

R29

100kΩ

X5R / 6.3V

C1, C3, C6, C7, C8, C10,

C41, C42

10µF

22µF

TDK: C1608X5R0J106MT

MURATA: GRM188R60J106ME47

X5R / 6.3V

C2, C4

TDK: C2012X5R0J226M

MURATA: GRM21BR60J226ME39

C5, C9, C11

2.2µF

1µF

X5R / 6.3V

C23, C25, C27, C29, C31

C13, C14

X5R / 6.3V

10nF

22nF

12pF

X5R / 6.3V

C15, C16, C17, C18, C12

C19, C20

X5R / 6.3V

C0G / 25V

C21, C22, C33, C35, C37,

C39

3.3µF

X5R / 6.3V

C26, C28, C30, C32, C34,

C36, C38, C40

1nF

X5R

L1, L2

2.2µH

COILCRAFT: LPS3314-222

9

11050A–PMAAC–07-Apr-10

10

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

6. Absolute Maximum Ratings

Table 6-1.

Absolute Maximum Ratings

Operating Temperature (Industrial).................-40 C to + 85⋅C⁽¹⁾

*NOTICE:

Stresses beyond those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only and functional operation of

the device at these or other conditions beyond those

indicated in the operational sections of this specification

is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reli-

ability.

Storage Temperature......................................-55°C to + 150°C

Power Supply Input on V_INSYS, V_IN{0,1,3,4},V_PAD.. -0.3V to + 5.5V

Power Supply Input on V_IN2, A_VDD...................... -0.3V to + 3.6V

Digital I/O Input Voltage...................................... -0.3V to + 5.5V

All Other Pins.......................................................-0.3V to + 5.5V

ESD (all pins).........................................2 KV HBM / 100V MM⁽²⁾

Notes: 1. Refer to Power Dissipation Rating section

2. According to specifications MIL-883-Method 3015.7 (HBM - Human Body Model) / JESD22 A115 (MM - Machine Model)

7. Recommended Operating Conditions

Table 7-1.

Parameter

Recommended Operating Conditions

Condition

Min

-40

Max

85

Units

°C

V

Operating Ambiant Temperature⁽¹⁾

Power Supply Input

V_INSYS

V_IN{0,1,3,4}

V_IN2

2.5

5.5

3.6

5.5

Power Supply Input

2.9

V

Power Supply Input

1.65

2.7

V

Power Supply Input

A_VDD

V

Power Supply Input

V_PAD

1.75

V

Note:

1. Refer to Power Dissipation Rating section

8. Power Dissipation Ratings

Table 8-1.

Parameter

Recommended Operating Conditions

Condition

Min

-40

Typ

Max

Units

Junction Temperature (Tj)

125

°C

Package thermal junction to ambient

resistance

(1)

R_THjA

30

35

°C / W

Ambient temperature = 70°C

Ambient temperature = 85°C

1.8

1.3

1.6

1.1

W

Maximum On-chip Power Dissipation

Note:

1. According to specification JESD51-5

11

11050A–PMAAC–07-Apr-10

9. PMU Electrical Characteristics

9.1

Current Consumption Versus Modes

Table 9-1.

Symbol

V_IN

Current Consumption Versus Modes

Parameter

Comments

Min

Typ

Max

Units

Operating Supply Voltage

V_INSYS,V_IN{0,1,3,4}present.

2.9

3.6

5.5

V

All LDOs and DCDC converters

OFF. Audio OFF. RTC running.

POWERDOWN Mode.

RUN Mode.

-

20

7

40

15

µA

All LDOs and DCDC converters

running in PWM. Audio OFF. RTC

running.

mA

I_{DD_VIN}

Default setup: DCDC0 ON in low-

power mode. LDO3 ON. All other

functions OFF.

STANDBY Mode.

All Modes.

-

310

1

500

5

µA

RTC running. Total current

entering pin V_BACKUP

I_{DD_RTC}

9.2

Supply Monitor Thresholds

The following table applies to functional state diagrams of Figure 11-1 “AT73C246 Power Man-

ager Functional State Diagram” on page 25 and Figure 11-2 “AT73C246 Start-up and Shutdown

State Diagram” on page 26.

Table 9-2.

Symbol

Supply Monitor Thresholds

Parameter

Comments

Min

3.070

2.870

2.70

2.60

1.80

1.70

Typ

3.1

Max

3.130

2.930

2.85

2.70

1.90

Units

V_IN> 3.1V

PMU Input 3.1V Rising Threshold

PMU Input 2.9V Falling Threshold

PMU Input 2.7V Rising Threshold

PMU Input 2.7V Falling Threshold

V

V_IN< 2.9V

2.9

V_IN> 2.7V

V_IN< 2.7V

2.75

2.65

1.85

1.75

V_BKP> 1.8V V_BACKUPInput Rising Threshold

V_BKP< 1.8V V_BACKUPInput Falling Threshold

1.80

12

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

9.3

Digital I/Os DC Characteristics

Table 9-3.

Symbol

V_PAD

V_PADReferred Digital I/Os

Parameter

Comments

Min

Typ

Max

Units

Operating Supply Voltage

1.75

3.6

5.5

V

0.3 x

V_PAD

V_IL

Input Low-Level Voltage

Input High-Level Voltage

Output High-Level Voltage

Output Low-Level Voltage

-0.3

-

V

0.7 x

V_PAD

0.3

+

V_IH

V_OH

V_OL

0.75 x

V_PAD

I_Omax.

I_Omax

-

0.25 x

V_PAD

-

I_O

Output Current

-

8

mA

R_P

Pull-Up or Pull-Down Resistance

When applicable.

70

100

145

kΩ

Notes: 1. V_PADreferred pins ITB, RSTB: open drain outputs. Only V_OLand I_Oparameters are applicable.

2. V_PADreferred pins WAKEUP1, WAKEUP2, WAKEUP3, MCLK, DAI, TWCK: CMOS inputs. Only V_IHand V_ILparameters are

applicable.

3. V_PADreferred pins MCLK32K, DAO: CMOS outputs. Only V_OL, V_OHand I_Oparameters are applicable.

4. V_PADreferred pin TWD: CMOS input and open drain output. Only V_IL, V_IH, V_OL, I_Oparameters are applicable.

5. V_PADreferred pins LRFS, BCLK: CMOS BiDir. All parameters applicable

Table 9-4.

V_BACKUPReferred Digital I/Os

Parameter

Symbol

Comments

Min

Typ

Max

Units

V_BACKUP

Operating Supply Voltage

1.75

2.5

2.65

V

0.3 x

V_BACKUP

V_IL

Input Low-Level Voltage

Input High-Level Voltage

Output High-Level Voltage

Output Low-Level Voltage

-0.3

-

V

0.7 x

V_BACKUP

+ 0.3

V_IH

V_OH

V_OL

0.75 x

V_BACKUP

I_Omax.

I_Omax

-

0.25 x

V_BACKUP

-

I_O

Output Current

-

8

mA

R_P

Pull-Up or Pull-Down resistance

When applicable.

70

100

145

kΩ

Note:

V_BACKUPreferred pins PWREN, HRST, WAKEUP0: CMOS inputs. Only V_ILand V_IHparameters are applicable.

13

11050A–PMAAC–07-Apr-10

9.4

DCDC0 and DCDC1

Unless otherwise specified: External components L=2.2μH, C_OUT=22μF and C_IN=10μF. V_IN{0,1}> V_DD{0,1}+ 500mV.

T_J= [-40°C ; +125°C].

Table 9-5.

Symbol

V_IN

DCDC0 and DCDC1 Electrical Characteristics

Parameter

Comments

V_IN0, V_IN1and V_INSYS

OFF

Min

2.9

-

Typ

3.6

-

Max

5.5

1

Units

V

Operating Supply Voltage

µA

PFM operation.

40

3

80

µA

-

I_DD

Supply Current⁽¹⁾

V_DD0= 1.85V, V_DD1= 1.2V

PWM operation.

6.5

mA

V_DD0= 1.85V, V_DD1= 1.2V

PFM operation.

PWM operation.

V_DD0

-

50

600

2.2

-

mA

MHz

V

I_O

Output Current

f_SW

Switching Frequency

Default Output Voltage⁽²⁾

1.8

-

2

V_DD0

V_DD1

1.85

1.2

V_DD1

-

V

Programmable Output Voltage

Range

V_{DD_RANGE}

V_{DD_STEP}

N_STEP

T_STEP

PFM or PWM operation.

0.8

3.6

V

Output Voltage Steps

Number of Output Steps

Step time

50

mV

In case of direct output voltage

programming. Automatic ramping

not active.

step /

100µs

4

With automatic ramping.

260

-1.5

-2

280

300

2.5

3

µs

%

PFM; T_J= 25°C ; I_O= 0 mA

PFM; T_J= [-40;125°C] ; I_O= 0 mA

PWM; T_J= 25°C ; I_O= 0 mA

PWM; T_J= [-40;125°C] ; I_O= 0 mA

PWM operation.

V_{DD_ACC}

DC Output Voltage Accuracy

-1.5

-2

1.5

2

V_{DD_RIPPLE}

Ripple Voltage

2

mV

PWM operation. I_Oranging from 0

to I_OMAX

Static Load Regulation

5

Δ_{VDD_IL}

PWM. I_O: 0 to I_OMAX; 1μs rise time

PWM. I_O: I_OMAXto 0 ; 1μs fall time

-40

40

Dynamic Load Regulation

Static Line Regulation

mV

V_IN0and V_INSYSfrom 2.9 to 5.5V

Δ_{VDD_VIN}

mV

%

V_DD0= 1.85V, V_DD1= 1.2V

PWM. I_OMAXload. V_DD0= 1.85V.

Relative to V_IN0input supply.

85

78

Eff

Efficiency

PWM. I_OMAXload. V_DD1= 1.2V.

Relative to V_IN1input supply.

%

Current from V_IN(0,1)and V_INSYS

from 0 to 100% V_DD{0,1}

I_INRUSH

Inrush Current⁽¹⁾

30

200

mA

V_DD0= 1.85V, V_DD1= 1.2V

14

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Table 9-5.

Symbol

OCP

DCDC0 and DCDC1 Electrical Characteristics

Parameter

Comments

Min

Typ

Max

Units

Over-Current Protection

Output current.

1

1.4

1.8

A

From OFF to PWM operation.

V_DD(0,1)rising to 95% of final value.

T_START

T_PWM

Start-up Time

5

ms

µs

PFM to PWM Settling Time

No output load.

10

-

Power Fail Detector Threshold

Accuracy

Overload of the programmed

PWRF_DET

-1

8

+1

36

%.V_DD

µF

threshold by 10mV / 5us min⁽³⁾

.

C_OUT

Total Capacitive Load

At V_FB{0,1}pins.

Notes: 1. Current consumption without load. One DCDC converter ON, the other one OFF.

2. Default output voltage are set during manufacturing. Please contact Atmel for other default settings.

3. Threshold levels are programmed in register PMU_RST_LVL (0x04)

15

11050A–PMAAC–07-Apr-10

9.5

LDO2

Unless otherwise specified: External components C_OUT=10µF, C_IN=10μF, T_J= [-40°C ; +125°C].

Table 9-6.

Symbol

V_IN

LDO2 Electrical Characteristics

Parameter

Comments

Min

Typ

Max

3.6

1

Units

V

Operating Supply Voltage

V_IN2

1.65

1.8

OFF

-

µA

mA

V

I_DD

Supply Current⁽¹⁾

ON

250

300

-

I_O

Output Current

V_IN2> V_DD2+ 500mV.

-

V_DD2

Default Output Voltage⁽²⁾

1

Programmable Output Voltage

Range

V_{DD_RANGE}

0.8

1.35

V

V_{DD_STEP}

T_STEP

Output Voltage Steps

Step time

50

mV

µs

With automatic ramping.

570

-1

600

630

1

V_IN2> V_DD2+ 500mV

T_J= 25°C ; I_O= 0 mA

V_{DD_ACC}

DC Output Voltage Accuracy

Static Load Regulation

%

%.V_DD2

mV

V_IN2> V_DD2+ 500mV

-1.5

1.5

1

T_J= [-40°C ; 125°C] ; I_O= 0 mA

V_IN2> V_DD2+ 500mV

0.05

-50

50

I_Oranging from 0 to I_OMAX

V_IN2> V_DD2+ 500mV

Δ_{VDD_IL}

I_O:0 to I_OMAX; 1μs rise time

Dynamic Load Regulation

V_IN2> V_DD2+ 500mV

I_O:I_OMAXto 0 ; 1μs fall time

I_O= 0 mA

Δ_{VDD_VIN}

Static Line Regulation

Drop Out Voltage⁽⁴⁾

5

mV

V_IN2from 1.65 to 3.6V

I_O= 200mA

I_O= 300mA

300

450

mV

V_DROPOUT

Current from V_IN2from 0 to 95% of

final value.

I_INRUSH

Inrush Current

Start-up Time

200

500

1

mA

ms

V_DD2OFF and rising to 95% of

T_START

final value. I_O= 0 mA

Power Fail Detector Threshold

Accuracy

Overload of the programmed

threshold by 10mV / 5us min⁽³⁾

PWRF_DET

-1

-

+1

%.V_DD2

.

Notes: 1. Current consumption in V_IN2without load.

2. Default output voltage are set during manufacturing. Please contact Atmel for other default settings.

3. Threshold level is programmed in register PMU_RST_LVL (0x04)

4. V_DROPOUT= V_IN2- V_DD2when V_DD2= 98% of V_DD2obtained with V_IN2> V_DD2+ 500mV

16

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

9.6

LDO3

Unless otherwise specified: External components C_OUT=10µF, C_IN=10μF, T_J= [-40°C ; +125°C].

Table 9-7.

Symbol

V_IN

LDO3 Electrical Characteristics

Parameter

Comments

Min

Typ

3.6

-

Max

5.5

1

Units

V

Operating Supply Voltage

V_IN3

2.9

OFF

-

µA

mA

V

I_DD

Supply Current⁽¹⁾

ON

-

350

200

-

I_O

Output Current

V_IN3> V_DD3+ 300mV.

-

V_DD3

Default Output Voltage⁽²⁾

3.3

Programmable Output Voltage

Range

V_{DD_RANGE}

2.7

3.6

V

V_{DD_STEP}

T_STEP

Output Voltage Steps

Step time

50

mV

µs

With automatic ramping.

570

-1

600

630

1

V_IN3> V_DD3+ 300mV

T_J= 25°C ; I_O= 0 mA

V_{DD_ACC}

DC Output Voltage Accuracy

Static Load Regulation

%

%.V_DD3

mV

V_IN3> V_DD3+ 300mV

-1.5

1.5

0.5

T_J= [-40°C ; 125°C] ; I_O= 0 mA

V_IN3> V_DD3+ 300mV

0.05

-40

40

I_Oranging from 0 to I_OMAX

V_IN3> V_DD3+ 300mV

Δ_{VDD_IL}

I_O:0 to I_OMAX; 1μs rise time

Dynamic Load Regulation

V_IN3> V_DD3+ 300mV

I_O:I_OMAXto 0 ; 1μs fall time

V

_IN3> V_DD3+ 300mV. I_O= 0 mA

Δ_{VDD_VIN}

Static Line Regulation

Drop Out Voltage⁽⁴⁾

5

mV

V_IN3from 2.9 to 5.5V

I_O= 10mA

50

mV

V_DROPOUT

I_O= 200mA

250

V

_IN3> V_DD3+ 300mV

60

50

I_O= 1mA. DC to 3kHz.

PSRR

Power Supply Rejection Ratio

dB

V_IN3> V_DD3+ 300mV

I_O= 10mA. DC to 3kHz.

Current from V_IN3from 0 to 95%

of final value.

I_INRUSH

Inrush Current

Start-up Time

200

500

1

mA

ms

V_DD3OFF and rising to 95% of

T_START

final value. I_O= 0 mA

Power Fail Detector Threshold

Accuracy

Overload of the programmed

threshold by 10mV / 5us min⁽³⁾

PWRF_DET

-1

-

+1

%.V_DD3

.

Notes: 1. Current consumption in V_IN3without load.

2. Default output voltage are set during manufacturing. Please contact Atmel for other default settings.

3. Threshold level is programmed in register PMU_RST_LVL (0x04)

4. V_DROPOUT= V_IN3- V_DD3when V_DD3= 98% of V_DD3obtained with V_IN3> V_DD3+ 300mV

17

11050A–PMAAC–07-Apr-10

9.7

LDO4

Unless otherwise specified: External components C_OUT=10µF, C_IN=10μF, T_J= [-40°C ; +125°C].

Table 9-8.

Symbol

V_IN

LDO4 Electrical Characteristics

Parameter

Comments

Min

Typ

3.6

-

Max

5.5

1

Units

V

Operating Supply Voltage

V_IN4

2.9

OFF

-

µA

mA

V

I_DD

Supply Current⁽¹⁾

ON

-

350

200

-

I_O

Output Current

V_IN4> V_DD4+ 300mV.

-

V_DD4

Default Output Voltage⁽²⁾

3.3

Programmable Output Voltage

Range

V_{DD_RANGE}

2.7

3.6

V

V_{DD_STEP}

T_STEP

Output Voltage Steps

Step time

50

mV

µs

With automatic ramping.

570

-1

600

630

1

V_IN4> V_DD4+ 300mV

T_J= 25°C ; I_O= 0 mA

V_{DD_ACC}

DC Output Voltage Accuracy

Static Load Regulation

%

%.V_DD4

mV

V_IN4> V_DD4+ 300mV

-1.5

1.5

0.5

T_J= [-40°C ; 125°C] ; I_O= 0 mA

V_IN4> V_DD4+ 300mV

0.05

-40

40

I_Oranging from 0 to I_OMAX

V_IN4> V_DD4+ 300mV

Δ_{VDD_IL}

I_O:0 to I_OMAX; 1μs rise time

Dynamic Load Regulation

V_IN4> V_DD4+ 300mV

I_O:I_OMAXto 0 ; 1μs fall time

V

_IN4> V_DD4+ 300mV. I_O= 0 mA

Δ_{VDD_VIN}

Static Line Regulation

Drop Out Voltage⁽³⁾

5

mV

V_IN4from 2.9 to 5.5V

I_O= 10mA

50

mV

V_DROPOUT

I_O= 200mA

250

V

_IN4> V_DD4+ 300mV

60

50

I_O= 1mA. DC to 3kHz.

PSRR

Power Supply Rejection Ratio

dB

V_IN4> V_DD4+ 300mV

I_O= 10mA. DC to 3kHz.

Current from V_IN4from 0 to 95%

of final value.

I_INRUSH

T_START

Inrush Current

Start-up Time

200

500

1

mA

ms

V_DD4OFF and rising to 95% of

final value. I_O= 0 mA

Notes: 1. Current consumption in V_IN4without load.

2. Default output voltage are set during manufacturing. Please contact Atmel for other default settings.

3. V_DROPOUT= V_IN4- V_DD4when V_DD4= 98% of V_DD4obtained with V_IN4> V_DD4+ 300mV

18

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

9.8

LDO5

Unless otherwise specified: External components C_OUT=2.2µF, C_IN=10μF, T_J= [-40°C ; +125°C].

Table 9-9.

Symbol

V_IN

LDO5 Electrical Characteristics

Parameter

Comments

V_INSYS

OFF

Min

Typ

3.6

-

Max

5.5

1

Units

V

Operating Supply Voltage

2.7

-

µA

mA

V

I_DD

Supply Current⁽¹⁾

ON

-

7

I_O

Output Current

-

10

2.58

10

15

V_BACKUP

Δ_{VDD_VIN}

Output Voltage Accuracy

Static Line Regulation

2.42

2.5

3

V_INSYSfrom 2.7 to 5.5V

mV

V_INSYS=3.6V, I_Ofrom 0 to I_OMAX

10

Current from V_INSYSfrom 0 to

T_START(MAX). V_BACKUP= 2.5V

I_INRUSH

T_START

Note:

Inrush Current

Start-up Time

180

350

1

mA

ms

V_BACKUPOFF and rising to 95% of

final value.

1. Current consumption in V_INSYSwithout plugged backup battery

19

11050A–PMAAC–07-Apr-10

9.9

Measurement Bridge and 10-bit ADC

Table 9-10. Measurement Bridge and 10-bit ADC Electrical Characteristics

Symbol

Parameter

Comments

V_INSYS

OFF

Min

Typ

Max

5.5

1

Units

V

V_IN

Operating Supply Voltage⁽¹⁾

2.9

3.6

-

µA

I_DD

Supply Current

ON

2

mA

Internally connected to

VDDC pin.

V_REF

Reference Voltage

1.75

1.8

1.85

V

INL

Integral Non Linearity

Differential Non Linearity

Offset Error

End Point Method

-2

-1

-2

-

+2

+1

+2

LSB

kS/s

ns

DNL

Offset

GAIN

F_S

Gain Error

Sampling Rate

300

T_ACQ

Track and Hold Acquisition Time

500

0.4

External inputs ANA{0,1,2,3}

V_{DD{0,1,2,3,4}}inputs

V_INSYS

4

V

V_MEAS

Measured Input Voltage Range

0.4

V

V_INSYSinput

0.4

5.5

V

External inputs ANA{0,1,2,3}

-1%

96

0.25

0.4

+1%

144

V/V

kΩ

ATT_MEAS

Measured Input Scaling Factor

ANA{0,1,2,3} Input resistance

V

_{DD{0,1,2,3,4,5}}inputs

_INSYSinput

V

0.25

120

R_{IN_NOM}

T_j= 25C

T_J[-40 ; +25]. Relative to

R_{IN_NOM}

+ 20

R_{IN_TEMP}

R_INdeviation with temperature

%

T_J[25 ; 125]. Relative to

R_{IN_NOM}

-16

C_IN

ANA{0,1,2,3} Input capacitance

15

pF

Notes: 1. The 10-bit ADC is supplied from the regulated V_DDCvoltage (1.8V) which is generated from V_INSYS

.

2. Please refer to Atmel Data Converter Terminology literature

20

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

9.10 RTC Crystal Oscillator

Table 9-11. RTC Crystal Oscillator Electrical Characteristics

Symbol

V_IN

Parameter

Comments

V_BACKUP

Min

Typ

2.5

32.768

50

Max

Units

V

Operating Supply Voltage

Frequency

1.75

2.65

-

Freq

with crystal

-

40

-

kHz

%

Duty

Duty Cycle

60

OFF

-

5

nA

I_DD

Supply Current⁽¹⁾

ON

-

1.5

1500

300

µA

T_ON

Startup Time

C_L= 12pF

-

1000

250

300

10

ms

V_XIN

V_XOUT

R_F

Level Sinus Wave on XIN

Vpp On XOUT

mVpp

MΩ

mn/month

kΩ

Internal Resistor

between xin and xout

@25°C, +/- 20ppm

Drift

Esr

Accuracy

1.5

100

3

Equivalent Series Resistance Rs

Motional Capacitance

Shunt Capacitance

Load Capacitance

Crystal @ 32.768kHz

50

C_M

0.6

6

fF

C_SHUNT

C_LOAD

Note:

2

pF

12.5

pF

1. Current consumption in V_BACKUPwith crystal. In case of crystal not present on-board, back-up batteries or supercapacitors,

must be avoided.

9.11 Die Temperature Sensor

Table 9-12. Die Temperature Sensor Electrical Characteristics

Symbol

Parameter

Comments

Min

135

105

Typ

145

115

Max

155

125

Units

°C

T_SHUTDOWN

T_RESTART

130°C Shutdown Threshold

110°C Restart Threshold

°C

21

11050A–PMAAC–07-Apr-10

10. Audio Codec Electrical Characteristics

Unless otherwise specified: AVDD = 3.3V, T_A= 25C, MCLK = 12.288MHz, F_S= 48kHz. Master mode and 24-bit operation

on I²S port. All gains set to 0dB, audio effects are off. Noise measurements are made in the [20Hz-20kHz] band using the

A-Weighting filter. Distortion measurements are made from the 2^ndto the 5^thharmonic products of a 997Hz input sinewave.

Input sources have an internal impedance of 50 Ohms. Audio Path without mixing capability.

Table 10-1. Audio Codec Bias

Symbol

Parameter

Comments

Min

Typ

Max

3.6

20

Units

V

AVDD

Operating Supply Voltage

2.7

3.3

OFF

µA

I_DD

Supply Current

STANDBY

1

mA

AVDD /

2

V_MID

Mid-Supply Reference Voltage

-1%

+1%

V

T_{MID_ON}

Time to charge V_MIDcapacitor

Time to discharge V_MIDcapacitor

From 0 to 95% of final value

350

700

ms/μF

T_{MID_OFF}

Microphone Bias Reference

Voltage

V_MICBIAS

R_MICBIAS

No load.

AVDD

1.9

V

Microphone Bias Reference

Voltage Internal Resistance

1.5

2.3

kΩ

Table 10-2. Line Record Path: Line or Auxiliary Input to ADC Output

Symbol

Parameter

Comments

Min

Typ

Max

Units

Corresponds to 0dBFs digital

output signal.

AVDD /

3.3

V_FS

Full Scale Input Voltage⁽¹⁾

V_RMS

AVDD = 3.3V

85

82

85

82

-

96

93

96

93

-80

90

0

-

dB

kΩ

pF

SNR

DR

Signal-to-Noise Ratio⁽²⁾

Dynamic Range⁽³⁾

AVDD = 2.7V

AVDD = 3.3V

-

AVDD = 2.7V

-

THD

Total Harmonic Distortion

Left / Right Channel separation⁽⁵⁾

Programmable Gain Range

Gain Step Size

-1dBFS digital output

-74

-

XTALK

80

-34

-

12

-

G_LINE

1

Mute Attenuation⁽⁶⁾

80

5.9

-

R_IN

C_IN

Input Resistance

7

8.1

10

Input Capacitance

-

Table 10-3. Microphone Record Path: Microphone Input to ADC Output

Symbol

Parameter

Comments

Min

Typ

Max

Units

Corresponds to 0dBFs digital

output signal.

AVDD /

3.3

V_FS

Full Scale Input Voltage⁽¹⁾

V_RMS

AVDD = 3.3V

AVDD = 2.7V

85

82

96

93

-

dB

SNR

Signal-to-Noise Ratio⁽²⁾

22

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Table 10-3. Microphone Record Path: Microphone Input to ADC Output

Symbol

Parameter

Comments

Min

85

82

-

Typ

96

93

-84

90

-

Max

Units

dB

AVDD = 3.3V

-

DR

Dynamic Range⁽³⁾

AVDD = 2.7V

dB

THD

Total Harmonic Distortion

Left / Right Channel separation⁽⁵⁾

Programmable Gain Range

Gain Step Size

-1dBFS digital output

-74

-

dB

XTALK

80

0

dB

46

-

dB

G_LINE

-

1

dB

Mute Attenuation⁽⁶⁾

80

8.4

-

dB

R_IN

C_IN

Input Resistance

0dB gain

12

-

15.6

10

kΩ

pF

Input Capacitance

Table 10-4. Playback Path: DAC Input to Headphone Output

Symbol

Parameter

Comments

Min

Typ

Max

Units

AVDD /

3.3

V_FS

Full Scale Output Voltage⁽¹⁾

0dBFs digital input signal.

V_RMS

AVDD = 3.3V

92

89

92

89

-

97

94

97

94

-88

-65

-60

30

50

90

60

-

dB

mW

dB

SNR

DR

Signal-to-Noise Ratio⁽²⁾

Dynamic Range⁽³⁾

AVDD = 2.7V

AVDD = 3.3V

-

AVDD = 2.7V

-

0dBFs input - 10kΩ load

20mW output - 32Ω load

20mW output - 16Ω load

32Ω load - THD < -40dB or 1%

16Ω load - THD < -40dB or 1%

10kΩ AC coupled load

16Ω DC coupled load

-80

-60

-55

THD

Total Harmonic Distortion

-

P_O

Output Power

XTALK

Left / Right Channel Separation⁽⁵⁾

Programmable Gain Range

Gain Step Size

-77

-

+6

-

G_HS

1

Mute Attenuation⁽⁶⁾

80

-

Table 10-5. Analog Bypass Path: Line / Auxiliary Input to Headphone Output

Symbol

Parameter

Comments

Min

Typ

Max

Units

AVDD /

3.3

V_FS

Full Scale Output Voltage⁽¹⁾

V_RMS

AVDD = 3.3V

AVDD = 2.7V

AVDD = 3.3V

AVDD = 2.7V

92

89

92

89

97

94

97

94

-

dB

SNR

DR

Signal-to-Noise Ratio⁽²⁾

Dynamic Range⁽³⁾

23

11050A–PMAAC–07-Apr-10

Table 10-5. Analog Bypass Path: Line / Auxiliary Input to Headphone Output

Symbol

Parameter

Comments

Min

Typ

-88

-65

-60

30

50

90

60

0

Max

-80

-60

-55

Units

dB

0dBFs input - 10kΩ load

20mW output - 32Ω load

20mW output - 16Ω load

32Ω load - THD < -40dB or 1%

16Ω load - THD < -40dB or 1%

10kΩ AC coupled load

16Ω DC coupled load

-

THD

Total Harmonic Distortion

dB

mW

dB

P_O

Output Power

XTALK

G_BYP

Left / Right Channel Separation⁽⁵⁾

dB

Bypass Gain

-1

+1

-

dB

Mute Attenuation⁽⁶⁾

80

-

dB

Table 10-6. Analog Sidetone Path: Microphone Input to Headphone Output

Symbol

Parameter

Comments

Min

Typ

Max

Units

AVDD /

3.3

V_FS

Full Scale Output Voltage⁽¹⁾

V_RMS

AVDD = 3.3V

92

89

92

89

-

97

94

97

94

-88

-65

-60

30

50

90

60

-

dB

mW

dB

SNR

DR

Signal-to-Noise Ratio⁽²⁾

Dynamic Range⁽³⁾

AVDD = 2.7V

AVDD = 3.3V

-

AVDD = 2.7V

-

0dBFs input - 10kΩ load

20mW output - 32Ω load

20mW output - 16Ω load

32Ω load - THD < -40dB or 1%

16Ω load - THD < -40dB or 1%

10kΩ AC coupled load

16Ω DC coupled load

-80

-60

-55

THD

Total Harmonic Distortion

-

P_O

Output Power

XTALK

Left / Right Channel Separation⁽⁵⁾

Programmable Gain Range

Gain Steps

-30

2.5

80

0

3.5

-

G_SIDETONE

3

Mute Attenuation⁽⁶⁾

-

Notes: 1. Full Scale: A linear extrapolation to 0dBFS of the measured level at -10dBFS.

2. Signal-to-Noise Ratio: The ratio of the RMS value of a 997Hz full scale sine wave to the RMS value of output noise with no

signal applied. Device is not muted.

3. Dynamic Range: According to AES17-1991 (Audio Engineering Society) and EIAJ CP-307 (Electronic Industries Associa-

tion of Japan), an extrapolation to 0dBFS input signal of the THD+N ratio measurement at -60dBFS. As an example, if

THD+N @ -60dBFS = -36dB, then DR = 96dB.

4. Total Harmonic Distortion + Noise Ratio: The ratio of the RMS sum of the noise and the distortion components to the RMS

value of the signal.

5. XTALK: Attenuation measurement from one channel to the other one. Measurement is performed by stimulated one channel

with a 997Hz / -10dBFS sinewave and leaving the other channel unstimulated.

6. Mute Attenuation: Attenuation measurement of a -10dBFS / 997Hz input signal when concerned gain is set to mute.

24

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

11. PMU Functional Description

11.1 Power Manager State Diagram

Figure 11-1. AT73C246 Power Manager Functional State Diagram

POWERDOWN

(all supplies OFF)

RSTB = 0

POWER-OFF or POWER-FAIL

EVENT

STANDBY-OUT or POWER-FAIL

EVENT

HRST_POWERDOWN

EVENT

POWER-ON EVENT &

Vin > 3.1V

STANDBY

EVENT

RUN

(all supplies ON)

RSTB = 1

STANDBY

(selected supplies ON)

RSTB = 0

WAKEUP

EVENT

HRST

EVENT

HRST

EVENT

HRST

EVENT

HRST_RUN

EVENT

HRST

(all supplies OFF)

RSTB = 0

TWI Reset

AT73C246 is placed in POWERDOWN state at VINSYS rising following the PMU startup state

diagram described in Figure 11-2 on page 26. From this POWERDOWN state, normal CPU sup-

plies startup is achieved through validation of one of the POWER-ON events. From this state,

the PMU may be placed in STANDBY state (e.g.: during CPU sleep periods) upon software

request (STANDBY event). PMU wake-up is achieved if one of the WAKEUP events is detected.

The PMU returns to the POWERDOWN state as soon as a POWER-OFF event is detected. A

special HRST (Hard-Reset) state is provided to ensure complete stop and restart of the CPU

supplies in case of a software crash. Moreover, die temperature and VDD_{0,1,2,3}supplies are

supervised and may generate a POWER-FAIL event in case of out-of-specification detection.

25

11050A–PMAAC–07-Apr-10

11.2 PMU Startup and Shutdown State Diagram

Figure 11-2. AT73C246 Start-up and Shutdown State Diagram

Vin > 2V

V_INSYS< 2.7V

or

V_DDC_KO

Start : V_INSYSMonitor &

V_DDC= 1.8V.

PMU_RSTN = 0

AUDIO_RSTN = 0

VINSYS > 2.7V &

V_DDC_OK

PMU_RSTN = 1

AUDIO_RSTN = 1

1

READ

CONFIG

V_BACKUP< 1.8V

V_BACKUP> 1.8V

RTC_RSTN = 0

OFF

LDO5

(BACKUP)

START

LDO5

(BACKUP)

1

START

LDO5

(BACKUP)

V_BACKUP> 1.8V

RTC_RSTN = 1

V_INSYS< 2.7V

POWER

DOWN

The start-up of the AT73C246 follows the flow diagram of Figure 11-2 and aims at placing the

power manager in the POWERDOWN state.

When V_INSYSrises above 2V:

• An internal V_INSYSmonitor starts and holds the internal PMU_RSTN and AUDIO_RSTN

signals to 0, thus forcing a complete reset of AT73C246. The PMU digital core supply voltage

26

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

(V_DDC= 1.8V) is started. During this PMU reset, the ‘LED’ pin is driven to VINSYS (LED is

OFF).

• When V_DDCis ready and V_INSYS> 2.7V, the internal reset signals previously mentioned are

released, thus enabling the PMU digital core functions.

• Before starting the LDO5 (RTC supply), V_BACKUPvoltage is monitored and if it is lower than

1.8V, the RTC function is resetted. In case of V_BACKUP> 1.8V, no reset is issued on the RTC

function.

• At this step, the power manager is placed in POWERDOWN state.

11.3 Power Manager Conditional Transitions

11.3.1

POWER-ON EVENTS

POWER-ON EVENTS are validated if all these listed conditions are true:

• V_INSYS> 3.1V

• AT73C246 internal junction temperature Tj < 110°C

• PWREN pin is high for more than 100ms (see Table 11-1 on page 28).

Note:

PWREN pin, with internal 100k pull-down resistor, is active high (V_BACKUPlevel). It is possible to

hard wire the PWREN pin to V_BACKUPto always activate RUN state when V_INSYS> 3.1V. Conse-

quently, using the software POWER-OFF EVENT (described in Section 11.3.2) will lead to going

back to the RUN state just after the POWERDOWN STATE.

11.3.2

POWER-OFF EVENTS

POWER-OFF EVENTS are validated if one of these listed conditions is true:

• V_INSYS< 2.9V.

• PWREN pin goes from low to high state and high state is held for more than 5s (see Table

11-1 on page 28).

• Software request: bit 0 (OFF) of register 0x00 (PMU_MODES) is written to 1.

11.3.3

POWER-FAIL EVENTS

POWER-FAIL EVENTS are validated if one of these listed conditions is true:

• AT73C246 internal junction temperature Tj > 130°C

• Any internal power fail detection signal coming from any CPU power supply (V_DD0, V_DD1

,

V

_DD2, V_DD3) goes from low to high level.

Note:

In case of PWREN pin hard wired high (V_BACKUPlevel), the POWER-FAIL EVENTS will lead to the

POWERDOWN state without possibility to go to the RUN state. The power manager will be able to

reach the RUN state only after an HRST event. This prevents the power manager from oscillating

between RUN and POWERDOWN states in case of permanent failure on CPU supplies.

11.3.4

11.3.5

STANDBY EVENT

STANDBY EVENT is validated if the following condition is true:

• Software request: bit 1 (STANDBY) of register 0x00 (PMU_MODES) is written to 1.

STANDBY-OUT EVENT

STANDBY-OUT EVENT is validated if the following condition is true:

• V_INSYS< 2.9V.

27

11050A–PMAAC–07-Apr-10

11.3.6

WAKEUP EVENTS

WAKEUP EVENTS are validated if one of the listed condition is true:

• WAKEUP0 pin goes from low to high state and WAKEUP0 bit is set to ‘1’ (see Table 11-1) in

register 0x01 (PMU_WAKEUP_EVENTS).

• WAKEUP1 pin goes from low to high state and WAKEUP1 bit is set to ‘1’ (see Table 11-1) in

register 0x01 (PMU_WAKEUP_EVENTS).

• WAKEUP2 pin goes from low to high state and WAKEUP2 bit is set to ‘1’ (see Table 11-1) in

register 0x01 (PMU_WAKEUP_EVENTS).

• WAKEUP3 pin goes from low to high state and WAKEUP3 bit is set to ‘1’ (see Table 11-1) in

register 0x01 (PMU_WAKEUP_EVENTS).

• PWREN pin goes from low to high state and high state is held for more than 10ms (see Table

11-1) and PWREN bit is set to ‘1’ in register 0x01 (PMU_WAKEUP_EVENTS).

• An RTC alarm occurs and RTC bit is set to ‘1’ in register 0x01 (PMU_WAKEUP_EVENTS).

Notes: 1. WAKEUP0 and PWREN pins must be driven with V_BACKUPlevel, WAKEUP{1,2,3} pins must be

driven with V_PADlevel.

2. If any WAKEUP EVENT is triggered while AT73C246 is going from RUN to STANDBY state,

STANDBY state is then first reached before WAKEUP EVENT is taken into account.

11.3.7

11.3.8

HRST EVENT

HRST EVENT is validated if the following condition is true:

• HRST pin goes from low to high state and high state is held for more than 1s (see Table 11-

1).

HRST RUN EVENTS

HRST RUN EVENTS are validated if all these listed conditions are true:

• HRST pin is at low level for more than 10ms (see Table 11-1).

• V_INSYS> 3.1V

• AT73C246 internal junction temperature Tj < 110°C

Note:

In case of 110°C < Tj < 130°C, HRST state is maintained. The self cooling down of the die will lead

to Tj < 110°C, thus exit of HRST state.

11.3.9

HRST POWERDOWN EVENTS

HRST POWERDOWN EVENTS are validated if all of these listed conditions are true:

• HRST pin is at low level for more than 10ms.

• V_INSYS< 3.1V or AT73C246 internal junction temperature Tj >130°C

Table 11-1. EVENTS Timing Table

Parameter

Comments

Min

95

Typ

100

5

Max

105

Units

ms

PWREN

HRST

Pin at V_BACKUPLevel. Debouncing Time.

Pin used as POWER-ON event

Pin used as POWER-OFF event

Pin used as WAKEUP event

Pin used as HRST event

4.75

9.5

5.25

10.5

1.05

sec

ms

10

1

0.95

sec

Pin used as HRST RUN event

Pin used as HRST POWERDOWN event

HRST

Pin at GND Level. Debouncing Time.

9.5

10

10.5

ms

28

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Table 11-1. EVENTS Timing Table

Pin Parameter

Comments

Min

5

Typ

Max

Units

ns

WAKEUP0 Pin pulsed to V_BACKUPLevel. Pulse Width.

WAKEUP1 Pin pulsed to V_PADLevel. Pulse Width.

WAKEUP2 Pin pulsed to V_PADLevel. Pulse Width.

WAKEUP3 Pin pulsed to V_PADLevel. Pulse Width.

Pin used as WAKEUP event

-

5

ns

5

ns

5

ns

11.4 Power Manager State Description

AT73C246 ICs are available with 2 factory programmed power sequences. The following timing

diagrams refer to “SEQUENCE A” and “SEQUENCE B” programmed ICs as defined in section

17. “Ordering Information” on page 154. See also the structure of register “VERSION (0x7F)”.

11.4.1

POWERDOWN STATE

When AT73C246 is in POWERDOWN state:

• Only V_BACKUPsupply is active. VDD_{0,1,2,3,4}power supplies are OFF.

• Audio function is OFF.

• ADC function is OFF.

• RSTB pin is held low.

• Led pin is set as input with internal 120k pull-up resistor to VINSYS.

• TWI registers are reset to default value.

When the POWERDOWN state is reached from the RUN state, the CPU power supplies are

switched off sequentially as described in Figure 11-3 on page 30.

29

11050A–PMAAC–07-Apr-10

Figure 11-3. AT73C246 - RUN to POWERDOWN state Supplies Shutdown timing diagram.

SEQUENCE A

SEQUENCE B

RUN

STATE

POWERDOWN

STATE

RUN

STATE

POWERDOWN

STATE

SUPPLIES SHUTDOWN

T_PWRDOWN

POWEROFF

EVENT

POWEROFF

EVENT

T_{OFF_AUDIO}

3.3V

T_{OFF_AUDIO}

RSTB

1V

T_{OFF_VDD3}

T_{OFF_VDD2}

V_DD3(3.3V)

V_DD1(1.2V)

V_DD2(1V)

T_{OFF_VDD1}

1.2V

V_DD1(1.2V)

1.85V

T_{OFF_VDD0}

V

_DD0(1.85V)

V_DD0(1.85V)

T_{OFF_VDD2}

T_{OFF_VDD3}

1V

3.3V

V_DD2(1V)

V_DD3(3.3V)

T_{OFF_VDD4}

V_DD4(CODEC)

Table 11-2. RUN to POWERDOWN state timing table

Symbol

Parameter

Comments

Min

Typ

Max

Units

POWERDOWN Event detection

time

T_PWRDOWN

58

62

66

µs

Audio CODEC is OFF or Power Fail

Occurs

58

62

T_{OFF_AUDIO}

Audio CODEC Shutdown Time

VDDx SHUTDOWN Time

Audio CODEC is ON

486

58

512

62

538

66

ms

µs

VDDx is OFF in RUN state⁽¹⁾

VDDx is ON in RUN state⁽¹⁾

T_{OFF_VDDx}

4.8

5.2

5.4

ms

Note:

1. VDDx activity during RUN state is set by Bit7 of register VDDx_CTRL.

30

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

When the POWERDOWN state is reached from the STANDBY state, the CPU power supplies

are switched off sequentially as described in Figure 11-4.

Figure 11-4. AT73C246 - STANDBY to POWERDOWN state Supplies Shutdown timing diagram.

SEQUENCE A

SEQUENCE B

STANDBY

STATE

STANDBY

STATE

POWERDOWN

STATE

POWERDOWN

STATE

SUPPLIES SHUTDOWN

T_{STBY_OUT}

STANDBY_OUT

EVENT

STANDBY_OUT

EVENT

RSTB

3.3V

1V

T_{OFF_VDD3}

T_{OFF_VDD2}

V_DD3(3.3V)

V_DD1(1.2V)

V_DD0(1.85V)

V_DD2(1V)

V_DD1(1.2V)

V_DD0(1.85V)

T_{OFF_VDD1}

1.2V

T_{OFF_VDD0}

1.85V

1V

3.3V

T_{OFF_VDD2}

T_{OFF_VDD3}

V_DD2(1V)

V_DD3(3.3V)

T_{OFF_VDD4}

V_DD4(CODEC)

Table 11-3. STANDBY to POWERDOWN state timing table

Symbol

Parameter

Comments

Min

Typ

Max Units

STANDBY OUT Event

detection time

T_{STBY_OUT}

95

100

105

µs

VDDx is OFF during STANDBY state⁽¹⁾

VDDx is ON during STANDBY state⁽¹⁾

VDD4 is OFF in RUN state⁽²⁾

58

4.8

58

62

5.2

62

66

5.4

66

µs

ms

µs

T_{OFF_VDDx}

VDDx SHUTDOWN Time

VDD4 SHUTDOWN Time

T_{OFF_VDD4}

VDD4 is ON in RUN state⁽²⁾

4.8

5.2

5.4

ms

Notes: 1. VDDx activity during STANDBY state is set by register PMU_STANDBY_SUPPLIES.

2. VDD4 activity during RUN state is set by Bit7 of register VDD4_CTRL.

11.4.2

RUN STATE

When AT73C246 is in RUN state:

• VDD_{0,1,2,3,5}power supplies are ON.

• RSTB pin is released.

• PMU functions are under software control (LDO4, AUDIO CODEC, ADC Controller)

• Led pin is driven according to register PMU_LED (0x0B).

31

11050A–PMAAC–07-Apr-10

When RUN state is reached from the POWERDOWN state, the power supplies are sequentially

started-up according to the Figure 11-5

Figure 11-5. AT73C246 - POWERDOWN to RUN state Supplies Start-Up timing diagram..

SEQUENCE A

SEQUENCE B

POWERDOWN

STATE

POWERDOWN

STATE

SUPPLIES START UP

RUN STATE

PWREN

EVENT

PWREN

EVENT

1V

3.3V

T^ON_SYS

VDD2 (1V)

VDD3 (3.3V)

VDD0 (1.85V)

VDD1 (1.2V)

VDD2 (1V)

1.85V

T^ON_VDD2

T^ON_VDD3

VDD0 (1.85V)

VDD1 (1.2V)

VDD3 (3.3V)

1.2V

T^ON_VDD0

3.3V

1V

TON_VDD1

VPAD LEVEL

TON_VDD3

T^ON_VDD2

RSTB

T^RESET

Table 11-4. POWERDOWN to RUN state timing table

Symbol

T_{ON_SYS}

T_{ON_VDD0}

T_{ON_VDD1}

T_{ON_VDD2}

T_{ON_VDD3}

T_RESET

Parameter

Comments

Min

1.7

5

Typ

1.8

5.3

5.5

32

Max

Units

ms

POWER-ON Event Detection Time

VDD0 Start-up Time

1.9

5.6

ms

VDD1 Start-up Time

5

5.6

ms

VDD2 Start-up Time

5.2

30.4

5.8

ms

VDD3 Start-up Time

5.8

ms

All Regulators ON To RSTB High

33.6

ms

32

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

When RUN state is reached from the STANDBY state, the power supplies are sequentially

started-up according to the Figure 11-6.

Figure 11-6. AT73C246 - STANDBY to RUN state Supplies Start-Up timing diagram.

SEQUENCE A

SEQUENCE B

STANDBY

STATE

STANDBY

STATE

SUPPLIES START UP

RUN STATE

WAKEUP

EVENT

WAKEUP

EVENT

TON_SYS

1V

3.3V

V_DD3ON

or OFF

V_DD2(1V)

V_DD3(3.3V)

TON_VDD2

1.85V

TON_VDD3

1.85V

V_DD0

PWM

V_DD0

PWM

V_DD0(1.85V)

PFM

V_DD0(1.85V)

PFM

1.2V

TON_VDD0

V_DD1(1.2V)

PFM

V_DD1(1.2V)

PFM

V_DD1

PWM

V_DD1

PWM

TPFM

TON_VDD1

3.3V

1V

V_DD3ON

or OFF

V_DD3(3.3V)

RSTB

V_DD2(1V)

RSTB

VPAD LEVEL

TON_VDD3

TON_VDD2

TRESET

Table 11-5. STANDBY to RUN state timing table

Symbol

Parameter

Comments

Min

Typ

Max

Units

Time from validated WAKEUP event (end of debounce

time when applicable) to VDD2 or VDD3 power on.

T_{ON_SYS}

Start-up Time

810

420

900

990

520

µs

Time from validated WAKEUP event (end of debounce

time when applicable) to PFM/PWM switching if

applicable.

PFM/PWM Switching

time

T_PFM

470

VDDx is OFF during STANDBY state⁽¹⁾

VDDx is ON during STANDBY state⁽¹⁾

5.2

58

5.4

62

5.7

66

ms

µs

T_{ON_VDDx}VDDx Start-up Time

All Regulators ON To

RSTB High

T_RESET

30.4

32

33.6

ms

Note:

1. VDDx activity during STANDBY state is set by register PMU_STANDBY_SUPPLIES.

11.4.3

STANDBY STATE

When AT73C246 is in STANDBY state:

• V_BACKUPis ON.

• VDD_{0,1,2,3}are ON or OFF according to the status in register 0x03

(PMU_STANDBY_SUPPLIES)

• VDD₄is ON or OFF according to the status in register 0x0A (VDD4_CTRL)

• Audio function is OFF

• ADC function is ON or OFF according to the status in register 0x30 (ADC_CTRL)

• RSTB pin is forced to ground.

• TWI pins are ignored to prevent TWI registers from corruption

• Led pin is driven according to register PMU_LED (0x0B)

To reach the STANDBY state, the appropriate power supplies are shut down as described in the

Figure 11-7 on page 34.

33

11050A–PMAAC–07-Apr-10

Figure 11-7. AT73C246 - RUN to STANDBY state Supplies Shutdown timing diagram.

SEQUENCE A

SEQUENCE B

RUN

STATE

RUN

STATE

STANDBY

STATE

STANDBY

STATE

SUPPLIES SHUTDOWN

T_STANDBY

STANDBY

EVENT

STANDBY

EVENT

T_{WAIT +}

T_{OFF_AUDIO}

3.3V

T_{WAIT +}

T_{OFF_AUDIO}

1V

RSTB

T_{OFF_VDD3}

T_{OFF_VDD2}

(V_DD3ON

^{or OFF})

(V_DD3ON

^{or OFF})

V_DD3(3.3V)

V_DD2(1V)

T_{OFF_VDD1}

1.2V

V_DD1

PFM

V_DD1

PFM

V_DD1(1.2V)

PWM

V_DD1(1.2V)

PWM

T_{OFF_VDD0}

1.85V

V_DD0(1.85V)

PWM

V_DD0

PFM

V_DD0(1.85V)

PWM

V_DD0

PFM

TPWM

T_{OFF_VDD2}

T_{OFF_VDD3}

1V

3.3V

V_DD2(1V)

V_DD3(3.3V)

Table 11-6. RUN to STANDBY state timing table

Symbol

Parameter

Comments

Min

Typ

Max

Units

STANDBY Event

Detection Time

T_STANDBY

150

460

160

500

170

540

µs

Time from validated WAKEUP event (end of debounce

time when applicable) to PFM/PWM switching if

applicable.

PFM/PWM Switching

time

T_PWM

If a WAKEUP event occurs in this window the PMU

automatically restart at the end of the STANDBY

process.

WAKEUP Event

Detection Window

T_WAIT

150

160

170

µs

Audio CODEC is ON

486

58

512

62

538

66

ms

µs

Audio CODEC

Shutdown Time

T_{OFF_AUDIO}

Audio CODEC is OFF

VDDx is OFF during both STANBY⁽¹⁾and RUN⁽²⁾states.

VDDx is OFF during STANBY state⁽¹⁾

VDDx is ON during RUN state⁽²⁾

VDDx is ON during STANBY state⁽¹⁾

VDDx is OFF during RUN state⁽²⁾

VDDx is ON during both STANBY⁽¹⁾and RUN⁽²⁾states.

58

62

66

VDDx SHUTDOWN

Time

T_{OFF_VDDx}

.

4.8

5.2

5.4

ms

.

4.8

58

5.2

62

5.4

66

ms

µs

.

T_{ON_VDDx}

VDDx STARTUP Time

Note:

1. VDDx activity during STANDBY state is set by register PMU_STANDBY_SUPPLIES.

2. VDDx activity during RUN state is set by Bit7 of register VDDx_CTRL.

11.4.4

HRST STATE

HRST state is a transition state used to restart the CPU:

• VDD_{0,1,2,3,4}are switched off according to figure Figure 11-8 on page 35 depending on the

previous state

• VDD₅is ON

• RSTB pin is forced to ground

34

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Figure 11-8. AT73C246 - HRST state Supplies Shutdown timing diagram.

SEQUENCE A

SEQUENCE B

RUN / STANDBY /

POWERDOWN

STATE

RUN / STANDBY /

POWERDOWN

STATE

HRST

STATE

HRST

STATE

SUPPLIES SHUTDOWN

T_HRST

HRST_EVENT

EVENT

HRST_EVENT

EVENT

T_{OFF_AUDIO}

RSTB

3.3V

1V

T_{OFF_VDD3}

T_{OFF_VDD2}

V_DD3(3.3V)

V_DD1(1.2V)

V_DD0(1.85V)

V_DD2(1V)

V_DD1(1.2V)

V_DD0(1.85V)

V_DD3(3.3V)

T_{OFF_VDD1}

1.2V

1.85V

T_{OFF_VDD0}

T_{OFF_VDD2}

T_{OFF_VDD3}

1V

3.3V

T_{OFF_PMU}

PMU FUNCTIONS

(LDO4, ADC, LED,...)

Table 11-7. HRST state timing table from RUN STATE

Symbol

Parameter

Comments

Min

58

Typ

62

Max

66

Units

µs

T_HRST

HRST Event Detection Time

Audio CODEC is ON

486

58

512

62

538

66

ms

µs

T_{OFF_AUDIO}

Audio CODEC Shutdown Time

Audio CODEC is OFF

VDDx is OFF in RUN state⁽¹⁾

VDDx is ON in RUN state⁽¹⁾

58

62

66

µs

T_{OFF_VDDx}

T_{OFF_PMU}

Note:

Table 11-8. HRST state timing table from STANDBY STATE

VDDx SHUTDOWN Time

4.8

1.4

5.2

1.5

5.4

1.6

ms

PMU Functions Shutdown Time

1. VDDx activity during RUN state is set by Bit7 of register VDDx_CTRL

Symbol

Parameter

Comments

Min

Typ

Max

Units

HRST Event Detection

Time

T_HRST

58

62

66

µs

Audio CODEC is ON

486

58

512

62

538

66

ms

µs

Audio CODEC Shutdown

Time

T_{OFF_AUDIO}

Audio CODEC is OFF

VDDx is OFF during STANDBY state⁽¹⁾

VDDx is ON during STANDBY state⁽¹⁾

VDD4 is OFF in RUN state⁽²⁾

VDD4 is ON in RUN state⁽²⁾

58

62

66

µs

T_{OFF_VDDx}

VDDx SHUTDOWN Time

VDD4 SHUTDOWN Time

4.8

58

5.2

62

5.4

66

ms

µs

T_{OFF_VDD4}

4.8

5.2

5.4

ms

PMU Functions Shutdown

Time

T_{OFF_PMU}

1.4

1.5

1.6

ms

Notes: 1. VDDx activity during STANDBY state is set by register PMU_STANDBY_SUPPLIES.

2. VDD4 activity during RUN state is set by Bit7 of register VDD4_CTRL.

35

11050A–PMAAC–07-Apr-10

11.5 DCDC0 and DCDC1 Functional Description

DCDC0 and DCDC1 are 2 identical high performance synchronous step-down (buck) convert-

ers. They feature:

• 2 control modes: PFM and PWM,

• A soft start circuit,

• A software programmable output voltage between 0.8 and 3.6V with automatic ramping for

DVS application,

• An Over-Current-Protection circuit,

• A 180 degree out of phase operating mode.

11.5.1

PFM and PWM Control Modes

Pulse Frequency Modulation control is an hysteretic control of the output voltage. It is specially

intended for light loads (< 50mA typ). In this mode, the DCDC converter exhibits a very low qui-

escent current (< 50µA) thus achieving very high efficiency at light loads. The frequency of

operation in this mode is not fixed but proportional to the load current.

Pulse Width Modulation control is a fixed frequency, variable duty cycle control of the DCDC

converter. It has a fast and precise feedback loop specially intended to handle hard loads and

low output ripple voltage.

At start-up, DCDC0 and DCDC1 operate in PWM mode. This way, high load at CPU boot are

properly handled. Through software control in registers VDD0_CTRL (0x06) and VDD1_CTRL

(0x07), the user may enter the low-power mode (PFM) when the application consumption is

reduced.

11.5.2

11.5.3

Soft-start Circuit

DCDC0 and DCDC1 feature a soft start circuit to prevent high input current while charging the

output capacitor from 0V to the default output voltage. Typically, the in-rush current at start-up

(with no load) is limited to 30 mA.

Output Voltage Programming

DCDC0 and DCDC1 output voltages can be managed through software control in registers

VDD0_CTRL (0x06) and VDD1_CTRL (0x07). 50mV steps are provided from 0.8V to 3.6V. It is

recommended to use the automatic ramping function in register PMU_SUPPLY_CTRL (0x04) to

achieve smooth operation. When the DVS_VDD_{0,1}bit is active (default mode), output voltages

are ramped from the current value to the final value in 50mV / 280us steps. For users who intend

to disable the DVS_VDD_{0,1}bit, a maximum of 4 steps (= 200mV) per 100us is allowed.

At power up, DCDC0 and DCDC1 default output voltages are respectively 1.85V and 1.20V. For

different default output voltages, please contact Atmel.

11.5.4

180° Out-of-phase Operation

DCDC0 and DCDC1 can be operated in-phase or at 180° out-of-phase according to the selec-

tion bit in register PMU_SUPPLY_CTRL (0x04). When operated in phase both converters will

start charging their inductor at the same time. When operated at 180° out-of-phase, the inductor

charge start time will be shifted by half a 2MHz clock delay (= 250ns) from one converter to the

other. This latter scheme tends to average the input current of both DCDC converters.

36

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

11.6 LDO2 Functional Description

LDO2 is a linear voltage regulator intended to supply CPU core voltages in the range 0.8V to

1.35V. Its maximum input voltage is 3.6V. Thus, it must not be wired to the VIN plane with VIN-

SYS, VIN0, VIN1, VIN3 and VIN4 if VIN is above 3.6V. Considering its low-output voltage and

for the sake of efficiency and power dissipation, the user may connect it at the output of DCDC0.

This LDO features:

• A soft start circuit,

• A software programmable output voltage between 0.8 and 1.35V with automatic ramping for

DVS application.

11.6.1

11.6.2

Soft-start Circuit

LDO2 features a soft start circuit to prevent high input current while charging the output capaci-

tor from 0V to the default output voltage. This soft start circuit limits the input current during 5ms

(+/-5%) at startup to 200mA in typical conditions. After this delay, LDO2 recovers full current

capability.

Output Voltage Programming

LDO2 output voltage can be managed through software control in register VDD2_CTRL (0x08).

50mV steps are provided from 0.8V to 1.35V. It is recommended to use the automatic ramping

function in register PMU_SUPPLY_CTRL (0x04) to achieve smooth operation. When the

DVS_VDD2 bit is active (default mode), output voltages are ramped from the current value to

the final value in 50mV / 600us steps.

At power up, LDO2 default output voltage is 1V. For different default output voltage, please con-

tact Atmel.

11.7 LDO3 and LDO4 Functional Description

LDO3 and LDO4 are low dropout linear voltage regulators intended to supply CPU peripherals

(I/Os, analog functions) in the range 2.7V to 3.6V. They can be operated directly from a 5.5V

maximum input voltage. They feature:

• A soft start circuit,

• A software programmable output between 2.7V and 3.6V voltage with automatic ramping for

DVS application,

11.7.1

11.7.2

Soft-start Circuit

LDO3 and LDO4 feature a soft start circuit to prevent high input current while charging the out-

put capacitor from 0V to the default output voltage. This soft start circuit limits the input current

during 5ms (+/-5%) at startup to 200mA in typical conditions. After this delay, LDO3(4) recovers

full current capability.

Output Voltage Programming

LDO3 and LDO4 output voltages can be managed through software control in registers

VDD3_CTRL (0x09) and VDD4_CTRL (0x0A). 50mV steps are provided from 2.7V to 3.6V. It is

recommended to use the automatic ramping function in register PMU_SUPPLY_CTRL (0x04) to

achieve smooth operation. When the DVS_VDD_{3,4}bit is active (default mode), output voltages

are ramped from the current value to the final value in 50mV / 600us steps.

37

11050A–PMAAC–07-Apr-10

At power up, LDO3 an LDO4 default output voltages are both 3.3V. For different default output

voltages, please contact Atmel.

11.8 Power Fail Detectors

AT73C246 features a Power Fail detector on each CPU supplies (V_DD0, V_DD1, V_DD2, V_DD3). This

function is made of a comparator that toggles each time one the listed power supplies goes

below a defined threshold. The comparator toggling is considered by the PMU digital state

machine as a POWER-FAIL event.

The threshold value of the power fail detector is proportional to the output voltage of the regula-

tor. It is not a fixed voltage, it is adapted to the programmed output voltage. The default

threshold value is set according to register PMU_RST_LVL (0x05) and can be programmed to

another value through TWI access. For other default threshold values at startup, please contact

Atmel.

11.9 Measurement Bridge and 10-bit ADC

AT73C246 features a 10-channel measurement chain including:

• A multiplexer + attenuator followed by a unity gain buffer

• A 300kS/s 10-bit SAR ADC.

ADC function is enabled through the register ADC_CTRL (0x30). ADC_MUX_1 (0x31) and

ADC_MUX_2 (0x32) allow the selection of inputs to be measured. 1 to 10 inputs can be

selected. The ADC will then perform serial conversion on these inputs and write the correspond-

ing result in registers 0x33 to 0x49.

2 sampling modes are provided to perform periodic conversions:

• Max speed

• Low speed.

To enter these modes, refer to the sampling period bits (TS) in the register ADC_CTRL (0x30).

When MAX_SPEED mode is selected, the ADC runs at 300kS/s and loop without any dead time

over the selected inputs. When a LOW_SPEED sampling period is selected, the ADC performs

a set of input conversions (1 to 10) at 300kS/s and then wait for one sampling period (defined by

TS bits) to start another set of conversions.

38

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Figure 11-9. Measurement Bridge and 10-bit ADC Block Diagram.

ADC_MUX_1 0x31

ADC_MUX_2 0x32

VINSYS

VDD0

VDD1

VDD2

VDD3

VDD4

VDDC

TWI Registers

ADC_ANA0_MSB

ADC_ANA0_LSB

VREFP

MUX

10

1

BUFFER

ADC

ADCOUT <9:0>

VREFN

ANA0

ANA1

ANA2

ANA3

ADC_ANA_LSB

GNDSYS

ADC_CTRL 0x30

39

11050A–PMAAC–07-Apr-10

11.10 Real Time Clock (RTC) User Interface

Figure 11-10. RTC Block Diagram

RTC DATA 3

RTC DATA 2

RTC DATA 1

RTC DATA 0

CONTROL REGISTER

MODE REGISTER

TIME REGISTER

RTC_SEL

CALENDAR REGISTER

TIME ALARM REGISTER

CALENDAR ALARM REGISTER

STATUS REGISTER

RTC_EN

RTC

CTRL

RTC

STATUS CLEAR COMMAND REGISTER

INTERRUPT ENABLE REGISTER

INTERRUPT DISABLE REGISTER

INTERRUPT MASK REGISTER

VALID ENTRY REGISTER

RTC_WRITE

VERSION REGISTER

RESERVED REGISTER

RTC ADDR

Table 11-9.

Offset

0x00

Register Mapping

Register

Name

RTC_CR

Access

Read-write

Read-only

Write-only

Read-only

---

Reset

Control Register

0x0

0x04

Mode Register

RTC_MR

0x0

0x08

Time Register

RTC_TIMR

RTC_CALR

RTC_TIMALR

RTC_CALALR

RTC_SR

0x0

0x0C

0x10

Calendar Register

Time Alarm Register

Calendar Alarm Register

Status Register

0x01819819

0x0

0x14

0x01010000

0x18

0x0

---

0x1C

0x20

Status Clear Command Register

Interrupt Enable Register

Interrupt Disable Register

Interrupt Mask Register

Valid Entry Register

Version Register⁽¹⁾

Reserved Register

RTC_SCCR

RTC_IER

---

0x24

RTC_IDR

RTC_IMR

RTC_VER

RTC_VERSION

---

0x28

0x0

---

0x2C

0xFC

---

Note:

1. Values in the Version Register vary with the version of the IP block implementation.

40

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

11.10.1 RTC Register Read/Write Operation

Figure 11-11. RTC Read Operation

WRITE

RTC_ADDR

WRITE 02

@RTC_CTRL

WRITE 03

@RTC_CTRL

WRITE 02

@RTC_CTRL

READ

RTC_DATA3

READ

RTC_DATA2

READ

RTC_DATA1

READ

RTC_DATA0

WRITE 00

@RTC_CTRL

TWI ACCESS

RTC_EN = 0

RTC_EN = 1

RTC_EN = 0

RTC_SEL = 1

RTC_WRITE = 0

RTC_SEL = 1

RTC_WRITE = 0

RTC_SEL = 1

RTC_WRITE = 0

RTC_SEL = 0

RTC_WRITE = 0

RTC_ADDR

RTC_DATA

RTC_EN

RTC_SEL

RTC_WRITE

Figure 11-12. RTC Write Operation

WRITE

RTC_ADDR

WRITE

RTC_DATA3

WRITE

RTC_DATA2

WRITE

RTC_DATA1

WRITE

RTC_DATA0

WRITE 06

@RTC_CTRL

WRITE 07

@RTC_CTRL

WRITE 06

@RTC_CTRL

WRITE 00

@RTC_CTRL

TWI ACCESS

RTC_EN = 0

RTC_EN = 1

RTC_EN = 0

RTC_SEL = 1

RTC_WRITE = 1

RTC_SEL = 1

RTC_WRITE = 1

RTC_SEL = 1

RTC_WRITE = 1

RTC_SEL = 0

RTC_WRITE = 0

RTC_ADDR

RTC_DATA

RTC_EN

RTC_SEL

RTC_WRITE

41

11050A–PMAAC–07-Apr-10

11.10.2 RTC Control Register

Name:

RTC_CR

Read-write

0x00

Access:

Address:

31

–

30

–

29

–

28

–

27

–

26

–

25

–

24

–

23

–

22

–

21

–

20

–

19

–

18

–

17

16

CALEVSEL

TIMEVSEL

15

–

14

–

13

–

12

–

11

–

10

–

9

8

7

6

5

4

3

2

1

0

–

UPDCAL

UPDTIM

• UPDTIM: Update Request Time Register

0 = No effect.

1 = Stops the RTC time counting.

Time counting consists of second, minute and hour counters. Time counters can be programmed once this bit is set and

acknowledged by the bit ACKUPD of the Status Register.

• UPDCAL: Update Request Calendar Register

0 = No effect.

1 = Stops the RTC calendar counting.

Calendar counting consists of day, date, month, year and century counters. Calendar counters can be programmed once

this bit is set.

• TIMEVSEL: Time Event Selection

The event that generates the flag TIMEV in RTC_SR (Status Register) depends on the value of TIMEVSEL.

0 = Minute change.

1 = Hour change.

2 = Every day at midnight.

3 = Every day at noon.

• CALEVSEL: Calendar Event Selection

The event that generates the flag CALEV in RTC_SR depends on the value of CALEVSEL.

0 = Week change (every Monday at time 00:00:00).

1 = Month change (every 01 of each month at time 00:00:00).

2, 3 = Year change (every January 1 at time 00:00:00)

42

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

11.10.3 RTC Mode Register

Name:

RTC_MR

Read-write

0x04

Access:

Address:

31

–

30

–

29

–

28

–

27

–

26

–

25

–

24

–

23

–

22

–

21

–

20

–

19

–

18

–

17

–

16

–

15

–

14

–

13

–

12

–

11

–

10

–

9

8

–

7

6

5

4

3

2

1

0

–

HRMOD

• HRMOD: 12-/24-hour Mode

0 = 24-hour mode is selected.

1 = 12-hour mode is selected.

All non-significant bits read zero.

43

11050A–PMAAC–07-Apr-10

11.10.4 RTC Time Register

Name:

RTC_TIMR

Read-write

0x08

Access:

Address:

31

–

30

–

29

–

28

–

27

–

26

–

25

–

24

–

23

–

22

21

13

5

20

12

4

19

18

10

2

17

16

AMPM

HOUR

15

–

14

6

11

9

8

MIN

7

3

1

0

–

SEC

• SEC: Current Second

The range that can be set is 0 - 59 (BCD).

The lowest four bits encode the units. The higher bits encode the tens.

• MIN: Current Minute

The range that can be set is 0 - 59 (BCD).

The lowest four bits encode the units. The higher bits encode the tens.

• HOUR: Current Hour

The range that can be set is 1 - 12 (BCD) in 12-hour mode or 0 - 23 (BCD) in 24-hour mode.

• AMPM: Ante Meridiem Post Meridiem Indicator

This bit is the AM/PM indicator in 12-hour mode.

0 = AM.

1 = PM.

All non-significant bits read zero.

44

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

11.10.5 RTC Calendar Register

Name:

RTC_CALR

Read-write

0x0C

Access:

Address:

31

–

30

–

29

21

13

5

28

20

12

4

27

19

11

26

25

17

9

24

16

8

DATE

23

22

18

DAY

MONTH

15

14

6

10

2

YEAR

7

3

1

0

–

CENT

• CENT: Current Century

The range that can be set is 19 - 20 (BCD).

The lowest four bits encode the units. The higher bits encode the tens.

• YEAR: Current Year

The range that can be set is 00 - 99 (BCD).

The lowest four bits encode the units. The higher bits encode the tens.

• MONTH: Current Month

The range that can be set is 01 - 12 (BCD).

The lowest four bits encode the units. The higher bits encode the tens.

• DAY: Current Day

The range that can be set is 1 - 7 (BCD).

The coding of the number (which number represents which day) is user-defined as it has no effect on the date counter.

• DATE: Current Date

The range that can be set is 01 - 31 (BCD).

The lowest four bits encode the units. The higher bits encode the tens.

All non-significant bits read zero.

45

11050A–PMAAC–07-Apr-10

11.10.6 RTC Time Alarm Register

Name:

RTC_TIMALR

Read-write

0x10

Access:

Address:

31

–

30

–

29

–

28

–

27

–

26

–

25

–

24

–

23

22

21

13

5

20

12

4

19

18

10

2

17

16

HOUREN

AMPM

HOUR

15

14

6

11

9

8

MINEN

MIN

7

3

1

0

SECEN

SEC

• SEC: Second Alarm

This field is the alarm field corresponding to the BCD-coded second counter.

• SECEN: Second Alarm Enable

0 = The second-matching alarm is disabled.

1 = The second-matching alarm is enabled.

• MIN: Minute Alarm

This field is the alarm field corresponding to the BCD-coded minute counter.

• MINEN: Minute Alarm Enable

0 = The minute-matching alarm is disabled.

1 = The minute-matching alarm is enabled.

• HOUR: Hour Alarm

This field is the alarm field corresponding to the BCD-coded hour counter.

• AMPM: AM/PM Indicator

This field is the alarm field corresponding to the BCD-coded hour counter.

• HOUREN: Hour Alarm Enable

0 = The hour-matching alarm is disabled.

1 = The hour-matching alarm is enabled.

46

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

11.10.7 RTC Calendar Alarm Register

Name:

RTC_CALALR

Read-write

0x14

Access:

Address:

31

30

–

29

28

20

27

19

26

25

17

24

16

DATEEN

DATE

23

22

–

21

–

18

MTHEN

MONTH

15

–

14

–

13

–

12

–

11

–

10

–

9

8

–

7

6

5

4

3

2

1

0

–

• MONTH: Month Alarm

This field is the alarm field corresponding to the BCD-coded month counter.

• MTHEN: Month Alarm Enable

0 = The month-matching alarm is disabled.

1 = The month-matching alarm is enabled.

• DATE: Date Alarm

This field is the alarm field corresponding to the BCD-coded date counter.

• DATEEN: Date Alarm Enable

0 = The date-matching alarm is disabled.

1 = The date-matching alarm is enabled.

47

11050A–PMAAC–07-Apr-10

11.10.8 RTC Status Register

Name:

RTC_SR

Read-only

0x18

Access:

Address:

31

–

30

–

29

–

28

–

27

–

26

–

25

–

24

–

23

–

22

–

21

–

20

–

19

–

18

–

17

–

16

–

15

–

14

–

13

–

12

–

11

–

10

–

9

8

–

7

6

5

4

3

2

1

0

–

CALEV

TIMEV

SEC

ALARM

ACKUPD

• ACKUPD: Acknowledge for Update

0 = Time and calendar registers cannot be updated.

1 = Time and calendar registers can be updated.

• ALARM: Alarm Flag

0 = No alarm matching condition occurred.

1 = An alarm matching condition has occurred.

• SEC: Second Event

0 = No second event has occurred since the last clear.

1 = At least one second event has occurred since the last clear.

• TIMEV: Time Event

0 = No time event has occurred since the last clear.

1 = At least one time event has occurred since the last clear.

The time event is selected in the TIMEVSEL field in RTC_CTRL (Control Register) and can be any one of the following

events: minute change, hour change, noon, midnight (day change).

• CALEV: Calendar Event

0 = No calendar event has occurred since the last clear.

1 = At least one calendar event has occurred since the last clear.

The calendar event is selected in the CALEVSEL field in RTC_CR and can be any one of the following events: week

change, month change and year change.

48

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

11.10.9 RTC Status Clear Command Register

Name:

RTC_SCCR

Write-only

0x1C

Access:

Address:

31

–

30

–

29

–

28

–

27

–

26

–

25

–

24

–

23

–

22

–

21

–

20

–

19

–

18

–

17

–

16

–

15

–

14

–

13

–

12

–

11

–

10

–

9

8

–

7

6

5

4

3

2

1

0

–

CALCLR

TIMCLR

SECCLR

ALRCLR

ACKCLR

• ACKCLR: Acknowledge Clear

0 = No effect.

1 = Clears corresponding status flag in the Status Register (RTC_SR).

• ALRCLR: Alarm Clear

0 = No effect.

1 = Clears corresponding status flag in the Status Register (RTC_SR).

• SECCLR: Second Clear

0 = No effect.

1 = Clears corresponding status flag in the Status Register (RTC_SR).

• TIMCLR: Time Clear

0 = No effect.

1 = Clears corresponding status flag in the Status Register (RTC_SR).

• CALCLR: Calendar Clear

0 = No effect.

1 = Clears corresponding status flag in the Status Register (RTC_SR).

49

11050A–PMAAC–07-Apr-10

11.10.10 RTC Interrupt Enable Register

Name:

RTC_IER

Write-only

0x20

Access:

Address:

31

–

30

–

29

–

28

–

27

–

26

–

25

–

24

–

23

–

22

–

21

–

20

–

19

–

18

–

17

–

16

–

15

–

14

–

13

–

12

–

11

–

10

–

9

8

–

7

6

5

4

3

2

1

0

–

CALEN

TIMEN

SECEN

ALREN

ACKEN

• ACKEN: Acknowledge Update Interrupt Enable

0 = No effect.

1 = The acknowledge for update interrupt is enabled.

• ALREN: Alarm Interrupt Enable

0 = No effect.

1 = The alarm interrupt is enabled.

• SECEN: Second Event Interrupt Enable

0 = No effect.

1 = The second periodic interrupt is enabled.

• TIMEN: Time Event Interrupt Enable

0 = No effect.

1 = The selected time event interrupt is enabled.

• CALEN: Calendar Event Interrupt Enable

0 = No effect.

• 1 = The selected calendar event interrupt is enabled.

50

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

11.10.11 RTC Interrupt Disable Register

Name:

RTC_IDR

Write-only

0x24

Access:

Address:

31

–

30

–

29

–

28

–

27

–

26

–

25

–

24

–

23

–

22

–

21

–

20

–

19

–

18

–

17

–

16

–

15

–

14

–

13

–

12

–

11

–

10

–

9

8

–

7

6

5

4

3

2

1

0

–

CALDIS

TIMDIS

SECDIS

ALRDIS

ACKDIS

• ACKDIS: Acknowledge Update Interrupt Disable

0 = No effect.

1 = The acknowledge for update interrupt is disabled.

• ALRDIS: Alarm Interrupt Disable

0 = No effect.

1 = The alarm interrupt is disabled.

• SECDIS: Second Event Interrupt Disable

0 = No effect.

1 = The second periodic interrupt is disabled.

• TIMDIS: Time Event Interrupt Disable

0 = No effect.

1 = The selected time event interrupt is disabled.

• CALDIS: Calendar Event Interrupt Disable

0 = No effect.

1 = The selected calendar event interrupt is disabled.

51

11050A–PMAAC–07-Apr-10

11.10.12 RTC Interrupt Mask Register

Name:

RTC_IMR

Read-only

0x28

Access:

Address:

31

–

30

–

29

–

28

–

27

–

26

–

25

–

24

–

23

–

22

–

21

–

20

–

19

–

18

–

17

–

16

–

15

–

14

–

13

–

12

–

11

–

10

–

9

8

–

7

6

5

4

3

2

1

0

–

CAL

TIM

SEC

ALR

ACK

• ACK: Acknowledge Update Interrupt Mask

0 = The acknowledge for update interrupt is disabled.

1 = The acknowledge for update interrupt is enabled.

• ALR: Alarm Interrupt Mask

0 = The alarm interrupt is disabled.

1 = The alarm interrupt is enabled.

• SEC: Second Event Interrupt Mask

0 = The second periodic interrupt is disabled.

1 = The second periodic interrupt is enabled.

• TIM: Time Event Interrupt Mask

0 = The selected time event interrupt is disabled.

1 = The selected time event interrupt is enabled.

• CAL: Calendar Event Interrupt Mask

0 = The selected calendar event interrupt is disabled.

1 = The selected calendar event interrupt is enabled.

52

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

11.10.13 RTC Valid Entry Register

Name:

RTC_VER

Read-only

0x2C

Access:

Address:

31

–

30

–

29

–

28

–

27

–

26

–

25

–

24

–

23

–

22

–

21

–

20

–

19

–

18

–

17

–

16

–

15

–

14

–

13

–

12

–

11

–

10

–

9

8

–

7

6

5

4

3

2

1

0

–

NVCALALR

NVTIMALR

NVCAL

NVTIM

• NVTIM: Non-valid Time

0 = No invalid data has been detected in RTC_TIMR (Time Register).

1 = RTC_TIMR has contained invalid data since it was last programmed.

• NVCAL: Non-valid Calendar

0 = No invalid data has been detected in RTC_CALR (Calendar Register).

1 = RTC_CALR has contained invalid data since it was last programmed.

• NVTIMALR: Non-valid Time Alarm

0 = No invalid data has been detected in RTC_TIMALR (Time Alarm Register).

1 = RTC_TIMALR has contained invalid data since it was last programmed.

• NVCALALR: Non-valid Calendar Alarm

0 = No invalid data has been detected in RTC_CALALR (Calendar Alarm Register).

1 = RTC_CALALR has contained invalid data since it was last programmed.

53

11050A–PMAAC–07-Apr-10

11.10.14 RTC Version register

Name:

RTC_VERSION

Read-only

0xFC

Access:

Address:

31

–

30

–

29

–

28

–

27

–

26

–

25

–

24

–

23

–

22

–

21

–

20

–

19

–

18

10

2

17

16

MFN

15

–

14

–

13

–

12

–

11

9

1

8

VERSION

7

6

5

4

3

0

VERSION

• VERSION

Reserved. Value subject to change. No funcionality associated. This is the Atmel internal version of the macrocell.

• MFN

Reserved. Value subject to change. No funcionality associated.

11.11 Die Temperature Sensor

The AT73C246 features a die temperature sensor for protection reasons. If the junction temper-

ature rises above the shutdown threshold for a minimum time of 1ms (+/- 5%), the power

manager event T_J> 130°C is asserted. In a similar fashion, if the temperature falls through the

restart threshold for more than 1ms, the power manager event T_J<110°C is asserted.

The two internal thresholds shutdown and restart are defined in Section 9.11 “Die Temperature

Sensor” on page 21.

54

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

12. Audio Codec Functional Description

12.1 Description

AT73C246 features a high quality, low power stereo audio codec with integrated headphone

amplifier.

The playback channel accommodates 16 to 24-bit stereo programmable format entering the dig-

ital audio interface (I²S) and delivers an internal analog audio output through a 100dB SNR

Sigma Delta Stereo DAC. An output mixer allows to mix this DAC output with a line / aux or

microphone input.

A 16-32 Ohms Stereo headphone amplifier with virtual ground output provides a 97dB SNR out-

put for line / headphone loads. The virtual ground output allows to remove 2 space demanding

coupling capacitors on board.

On the record side, a multiplexer can select between a main stereo line input and a stereo auxil-

iary input such as an FM radio. A stereo microphone input with up to 46dB gain is provided. A

stereo input mixer allows mixing between line (or aux) and microphone channels before entering

a 96dB SNR Stereo Sigma Delta ADC. The digital audio signal is then digitally filtered and trans-

ferred to the I²S audio interface.

12.2 Audio Codec Block Diagram

Figure 12-1. Audio Codec Block Diagram

BYPASS

0 -> -30dB

1dB Step

-34 -> +12dB

1dB Step

MUX

LINL

-77/+6dB

1dB Step

AUXL

ADC

DAC

HPL

0 -> +46dB

1dB Step

MICL

DSP

+

Audio

Controller

MICLN

VMID

HPVCM

0 -> +46dB

1dB Step

MICR

-77/+6dB

1dB Step

MICRN

ADC

DAC

HPR

-34 -> +12dB

1dB Step

MUX

LINR

AUXR

HPDET

0 -> -30dB

1dB Step

BYPASS

Codec Bias

200K

I²S

2K

200K

MICBIAS AVDD

VMID AGND

PAO

DAI

LRFS BCLK MCLK

55

11050A–PMAAC–07-Apr-10

12.3 Audio Codec Controls

Figure 12-2. Audio Codec Controls

RHSBOTH

LHSBOTH

ENASR

ASRTIME

STDBY

ENAC

LINBOTH

RINBOTH

PATHSEL

BCLKINV

MASTER

MCLKSEL

SSCMODE

WL

DAIMODE

SELFS

56

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

12.4 Audio Controller

The audio controller sequences the power-up and power-down of the audio codec sub-functions

(Mic.amp / ADC / DAC / …). During these transitioning phases, the controller also manages the

gain steps to fade them in and out, thus providing smooth operation.

Depending on the application, two modes are provided:

1. Automatic path control

Dedicated to the major audio path scenarios (those described in Table 13-25 on page 95), this

mode enables the whole audio path setup only via "PATHSEL" bits in register AUTOSTART

(0x10).

2. Custom path control

Dedicated to audio path scenarios not described in the previously mentioned table, this mode

brings the flexibility to start manually the audio sub-functions.

The following figure shows the global context of the audio codec control.

Figure 12-3. Audio Codec Typical Control Sequence

Apply Supply

& MCLK

1

Registers to set

AUDIO_CONTROL (0x11)

(Set DCBlock bit here)

:

Configure

Analog & Digital

Interfaces

-

Registers to set

See dedicated sections.

Automatic path

control

Custom path

control

6

2

-

MIC_CONTROL (0x12)

DAI_CONTROL (0x13)

FRAME_CONTROL (0x14)

Register to set

MUTE (0x15)

:

Register to set

:

Shutdown

Audio Codec

-

Unmute Codec

3

4

7

-

AUTOSTART (0x10)

Start Audio

Codec in

Standby

8

Register to set

:

At least 1s.

See “Power-off Time”

-

AUTOSTART (0x10)

-

Software

Wait

section.

5

Typically 350ms.

See VMID section.

Register to set

:

Unset

DCBLOCK bit

-

9

-

AUDIO_CONTROL (0x11)

See “AC/DC coupled load

Software

Wait

management” section.

Remove MCLK

& supply

10

57

11050A–PMAAC–07-Apr-10

12.4.1

Audio Codec General Recommendations

12.4.1.1

V_MID

• V_MIDis the common mode voltage of the audio codec analog core. It is recommended to

decouple this voltage with a 1uF capacitor to ensure low noise operation as well as slow

(thus silent) transients at codec power up and power down.

• The V_MIDcapacitor is charged and discharged whenever the ENAC bit is set or cleared.

Particularly, placing the audio codec in STANDBY mode does not discharge the V_MID

capacitor. The software WAIT operations in the previous diagram (step #5 and step #8 in

“Audio Codec Typical Control Sequence” on page 57) should accommodate V_MID's settling

time constant. See “Audio Codec Bias” on page 22..

12.4.1.2

AC / DC Coupled Load Management

• By default the audio codec is in DC-coupled load configuration: DCBLOCK = 0 in register

AUDIO_CONTROL(0x11). In this case, a virtual ground voltage is provided on pin HPVCM (a

buffered version of V_MID). It allows to directly connect headphones or line loads between

HPVCM and HPL(or R) without any coupling capacitors. To prevent any audio pop at start-up

or shutdown in this DC coupling mode, the audio codec fastly starts HPL, HPR and HPVCM

outputs shorted all together. No software management is required to achieve pop-less

operation.

• If output loads are AC coupled to the headphone amplifier, the audio codec DCBLOCK bit

must be set and unset as described in “Audio Codec Typical Control Sequence” on page 57.

This bit partially controls the two switches S1 and S2 described in the following figure. When

DCBLOCK = 1 and the headphone amplifier is OFF, the output coupling capacitors are

charged and discharged by the amplifier “VMID_BUFFER”. In order to achieve silent startup

and shutdown, the following rules must be respected:

– DCBLOCK = 0 at supply power-on and power-off. This ensures that the LDO4

power-on and power-off transients are not transmitted to the audio loads.

– DCBLOCK = 1 when ENAC = 1. Particularly, DCBLOCK must be set before

ENAC=1 and unset after ENAC=0. This ensures that the full VMID waveform is

properly buffered to the output loads.

– DCBLOCK = 1 after ENAC = 0 and until V_MIDcapacitor is fully discharged. At codec

shutdown (ENAC=0), VMID will discharge slowly. The VMID_BUFFER ensures slow

and silent discharge of the output coupling capacitors, and needs S1 and S2 to be

closed.

58

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Figure 12-4. AC / DC Coupled Load Management Schematic View

VIN4

AT73C246

C_L

LDO4

HPL

LEFT

VDD4

S1

R_L

10uF

ENAC

DCBLOCK.ONHP

AVDD

VMID

BUFFER

R_R

C_R

S2

200k

RIGHT

HPR

200k

1uF

AGND

Figure 12-5. Audio Codec Typical Startup and Shutdown Waveforms With AC Coupled Loads.

VDD4

VMID

HP(L/R)

DCBLOCK

ENAC

STANDBY

S1 & S2

S1 AND S2 OPENED

BY AUDIO CODEC

12.4.1.3

12.4.1.4

12.4.1.5

MUTE Register

By default, the audio codec starts muted. To enable the audio processing, the MUTE register

(0x15) must be cleared. Unmute operation can be performed before or after releasing the

STANDBY mode. During operation, this register provides a convenient way of muting the audio

signal without changing the various gain registers.

Master Clock Input (MCLK)

The Audio Controller is clocked by MCLK pin. Therefore a clock must be present at this pin

before each codec control change. Particularly, the master clock must be present at power-on,

power-off, gain change, path change. The master clock must also be available when fully analog

path are used.

Power-off Conditions

Three audio codec power-off conditions can occur:

• Sofware request (ENAC = 0 in AUTOSTART register). In this case, the codec is smoothly

powered off by the audio controller.

• PMU Power-off event or Standby event (as defined in Section 11.3 “Power Manager

Conditional Transitions” on page 27). In this case, the codec is smoothly powered off with a

59

11050A–PMAAC–07-Apr-10

500ms timeout. Contrary to the first point, which has no timeout, the audio power-off time

limit is here fixed to 500ms. Beyond this limit, the codec is hardly reseted as in the following

point.

• PMU Power-fail event. In this case, the PMU finite state machine makes an immediate hard

reset of the audio codec to ensure fast shutdown. This case may generate an audible click /

pop noise.

12.4.1.6

Power-off Time

At power-off, the audio controller needs to perform several controls on audio codec sub-func-

tions and to discharge the output coupling capacitors. Therefore, the codec’s power-off time is

divided into:

• a digital power-off time and,

• an analogue one.

During this power-off phase, the codec‘s master clock and supply must be present. See “Audio

Codec Power-off Waveforms” on page 60.

Figure 12-6. Audio Codec Power-off Waveforms

VDD4

MCLK

ENAC

VMID

analog

power-oﬀ

time

AUDIO

SIGNAL

digital

power-oﬀ

time

The digital power-off time depends on the number of controls (power-off, gain steps ramping, ...)

to perform and for this reason strongly varies according to:

• the master clock frequency,

• the current path,

• the current gains and

• the current Automatic Soft Ramping time (ASR_TIME in AUDIO_CONTROL(0x11)).

In worst case conditions (slowest clock, maximum ASR_TIME, maximum complexity audio path,

maximum gains everywhere), the power-off time reaches 3 seconds. During this period, the

60

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

master clock must be running to properly shutdown the codec. This time linearly varies with

ASR_TIME value. See Table 12-1

Table 12-1. Audio Codec Maximum Power-off Time

ASR_TIME

Power-off time (ms)

00

01

10

11

375

750

1500

3000

The analog power-off time corresponds to the VMID’s discharge time specified in “Audio Codec

Bias” on page 22: T_{MID_OFF}

.

Finally, the wait step #8 in “Audio Codec Typical Control Sequence” on page 57 needs to acco-

modate the digital power-off time + the analog power-off time.

12.4.2

Automatic Path Configuration

In this automatic path mode, the audio path control is fully managed by the AUTOSTART(0x10)

register and more precisely by the following bits:

• ENAC (Enable Audio codec),

• STANDBY⁽¹⁾(Audio standby) and

• PATHSEL (Audio path selection).

When the audio controller detects a change in these bits, it generates sequential controls to the

audio codec sub-functions (power-up, gain ramping, unmute,…) with the right timing and order.

Notes: 1. Audio STANDBY does not refer to the PMU STANDBY state as defined in “AT73C246 Power

Manager Functional State Diagram” on page 25. The audio STANDBY mode activated by reg-

ister AUTOSTART (0x10) only refers to the audio codec controller.

12.4.2.1

STANDBY Release

Once the CODEC is started and in standby mode (ENAC=1 and STANDBY=1, step #5 in “Audio

Codec Typical Control Sequence” on page 57), the audio path is simply selected by PATHSEL

bits.

At STANDBY release (STANDBY=0), the audio controller will:

• Power-up the requested audio sub-functions. To do so, the audio controller makes WRITE

accesses to the registers

– INPUT_CONTROL (0x1E),

– OUTPUT_CONTROL (0x1F) and

– INPUT_MIXER (0x20).

• Ramp-up the concerned path gains from mute to their current register value.

Notes: 1. Changing PATHSEL value with STANDBY=1 does not changes the codec state. It remains in

STANDBY mode.

2. The audio controller always ensures minimum power consumption by powering only needed

sub-functions.

3. Audio parameters (volume, mute, effects…) can be modified before or after releasing the

standby mode.

61

11050A–PMAAC–07-Apr-10

12.4.2.2

Pause Management With STANDBY Bit

To pause the audio codec activity and reduce power consumption to few hundreds of micro-

amps, the STANDBY bit can be activated in register AUTOSTART (0x10). The Audio codec will

then:

• Softly ramp down all the path concerned gains down-to mute and

• Power off all the audio sub-functions. The registers INPUT_CONTROL (0x1E),

OUTPUT_CONTROL (0x1F), and INPUT_MIXER (0x20) are modified by the audio

controller.

Notes: 1. Placing the codec in standby mode maintains the common mode voltage at VMID pin and thus

allows to re-start fastly,

2. Standby release is simply achieved by clearing the STANDBY bit (STANDBY = 0). The proce-

dure described in “STANDBY Release” on page 61 applies.

12.4.2.3

On-the-fly Path Change

The audio controller is able to softly switch from one audio path configuration to another without

shutting down the codec nor entering the STANDBY mode. As soon as it detects a change in the

PATHSEL value, the following mechanism occurs:

• Power up and/or power down of the audio sub-functions according to the final state to reach.

This operation generates automatic changes in the registers INPUT_CONTROL (0x1E),

OUTPUT_CONTROL (0x1F), and INPUT_MIXER (0x20).

• Ramp up and/or ramp down of the concerned path gain.

Notes: 1. A channel may be temporarily and smoothly switched off and on to reach the new path.

2. Any software write operation in the registers INPUT_CONTROL (0x1E), OUTPUT_CONTROL

(0x1F), and INPUT_MIXER (0x20) will generate a series of control on the audio codec sub-

functions. In automatic path control, the order of the write operations in those registers is of

prime importance. Please note that changing those registers updates the used audio path

without updating the PATHSEL value. Therefore, these write operations are not recommended

and must be limited to simple ones (for example changing LINESEL bit in register

INPUT_CONTROL (0x1E) ).

12.4.2.4

Audio Codec Shutdown

The Audio controller will start to shutdown the codec if ENAC = 0. The shutdown sequence is

made of the following steps:

• Softly ramp down all the path concerned gains down-to mute,

• Power off all the audio sub-functions and,

• Power off the common voltage VMID.

Notes: 1. In this mode, the power consumption is reduced to few hundreds of nA.

2. The common mode voltage power-off follows VMID time constant and thus may take a few

hundreds of milliseconds depending on VMID capacitor. See “Audio Codec Bias” on page

22.

A software example of audio codec control using automatic path control is provided in the sec-

tion “Basic Audio Codec Setting Using Automatic Path Control” on page 134.

12.4.3

Custom Path Configuration

In this custom path mode, the audio path control is managed by the following registers:

• AUTOSTART (0x10) (ENAC and STANDBY bits only)

• AUDIO_CONTROL (0x11) (ENCONF and CUSTCONF bits only)

62

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

• INPUT_CONTROL (0x1E)

• OUTPUT_CONTROL (0x1F)

• INPUT_MIXER (0x20)

Like in the automatic path configuration, the audio controller will sequence audio codec sub-

functions ON/OFF as well as gain stepping. However, the audio path is no more selected via the

"PATHSEL" value in register AUTOSTART.

To specify a custom audio path:

• The bit CUSTCONF in register AUDIO_CONTROL (0x11) must be set to '1' to specify the

'custom' path configuration mode.

• The registers INPUT_CONTROL (0x1E), OUTPUT_CONTROL (0x1F), and INPUT_MIXER

(0x20) are set to define the audio path,

• The bit ENCONF in register AUDIO_CONTROL (0x11) is pulsed to '1' to enable the audio

controller sequencing.

Notes: 1. “Pulsed to ‘1’ ”means written to ‘1’ and then written to ’0’.

2. In this mode, the STANDBY bit behaves like in the automatic mode. It is possible to place the

CODEC in standby mode to reduce power consumption during audio pause by simply setting

the STANDBY bit to 1. STANDBY release is achieved by clearing this bit.

3. On-the-fly path change is achieved by modifying the registers INPUT_CONTROL (0x1E),

OUTPUT_CONTROL (0x1F) , and INPUT_MIXER (0x20) to define the new audio path config-

uration and then pulsing to '1' the ENCONF bit. In this case, a channel may be temporarily

(and smoothly) switched off and on to reach the new configuration.

4. Changing the three registers INPUT_CONTROL (0x1E), OUTPUT_CONTROL (0x1F) , and

INPUT_MIXER (0x20) with the ENCONF bit set to ‘1’ makes the changes to take effect imme-

diately. Therefore, the order of write operations is of prime importance. It is then recommended

to write these registers with ENCONF set to 0 and then pulse ENCONF to ‘1’ once the new

audio path is fully specified. Knowing the final state to reach, the audio controller is able to

sequence the controls with the right order and timings to ensure noise-free operation.

5. In this custom mode, the Audio Controller may forbid any configuration that does not make

sense. For example, it will prevent the headphone amplifier from being switched on if it has no

input source (DAC, Microphone, or Line).

6. It is possible and sometimes convenient to switch from an automatically set path to a custom

one. In this case, the audio controller softly performs the required path change. However, acti-

vating an automatic path configuration from a current custom path configuration is not allowed.

The audio codec must be switched off first (ENAC=0).

A software example of audio codec control using custom path control is provided in the section

“Basic Audio Codec Setting Using Custom Path Control” on page 135.

12.5 Audio Codec Power Consumption Versus Programmed Audio Path

Unless otherwise specified:

• A_VDD= 3.3V

• MCLK = 12.288MHz , FS = 48KHz

• All Gains set to 0dB

• No audio signal

• T_A= 25°C.

• Headphone amplifier set in AC coupling mode.

63

11050A–PMAAC–07-Apr-10

• Current consumptions don’t account for load consumption and are measured in A_VDDpin and

_INSYSpin.

V

Table 12-2. Audio PATH Power Consumption

Consumption

PATH_SEL

AUDIO PATH

Description

Units

V_INSYS

A_VDD

0.61

5.2

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

No Path

0.10

1.80

0.10

2.00

1.80

mA

DAC Playback

Mic Sidetone

Digital IN - Headphone OUT

Microphone IN - Headphone OUT

Aux IN - Headphone OUT

2.65

3.40

5.05

3.70

5.60

Aux Bypass

Line Bypass

Line IN - Headphone OUT

Mic IN - Digital OUT

Mic Record

Aux Record

Aux IN - Digital OUT

Line Record

Line IN - DIGITAL OUT

Mic Sidetone + Record

Aux Bypass + Record

Line Bypass + Record

Mic + Aux Record

Mic + Line Record

Mic IN - Headphone and Digital OUT

Aux IN - Headphone and Digital OUT

Line IN - Headphone and Digital OUT

Mic + Aux IN - Digital OUT

Mic + Line IN - Digital OUT

DAC Playback + Mic Sidetone Digital + Mic IN - Headphone OUT

DAC Playback + Aux Bypass

DAC Playback + Line Bypass

Digital + Aux IN - Headphone OUT

Digital + Line IN - Headphone OUT

DAC Playback + Mic Sidetone

+ Aux Bypass

10000

10001

10010

10011

10100

10101

10110

Digital + Mic + Aux IN - Headphone OUT

Digital + Mic + Line IN - Headphone OUT

1.80

3.80

5.85

8.00

mA

DAC Playback + Mic Sidetone

+ Line Bypass

DAC Playback and

MIC Record

Digital IN - Headphone OUT

Mic IN - Digital OUT

DAC Playback and

Aux Record

Digital IN - Headphone OUT

Aux IN - Digital OUT

DAC Playback and

Line Record

Digital IN - Headphone OUT

Line IN - Digital OUT

DAC Playback + Mic Sidetone Digital + Mic IN - Headphone OUT

and Mic Record

Mic IN - Digital OUT

DAC Playback + Aux Bypass

and Aux Record

Digital + Aux IN - Headphone OUT

Aux IN - Digital OUT

64

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Table 12-2. Audio PATH Power Consumption

Consumption

PATH_SEL

AUDIO PATH

Description

Units

V_INSYS

A_VDD

DAC Playback + Line Bypass

and Line Record

Digital + Line IN - Headphone OUT

Line IN - Digital OUT

10111

3.80

8.00

mA

DAC Playback + Mic Sidetone

+ Aux Bypass and

Mic + Aux Record

Digital + Mic + Aux IN - Headphone OUT

Mic + Aux IN - Digital OUT

11000

11001

3.80

8.25

mA

DAC Playback + Mic Sidetone

+ Line Bypass and

Mic + Line Record

Digital + Mic + Line IN - Headphone OUT

Mic + Line IN - Digital OUT

65

11050A–PMAAC–07-Apr-10

12.6 Digital Audio Interface

12.6.1

General Description

AT73C246 features a 16 to 24-bit multi-mode master / slave I²S port. The following modes are

provided:

• I2S,

• Left Justified,

• Right Justified, and

• SSC

The I²S port is configured through register I2S_CONTROL (0x13) and FRAME_CONTROL

(0x14). For each of the listed modes, the data transfer is described in the following sections.

The following table provides authorized MCLK / FS ratios and associated filter types:

Table 12-3. Authorized MCLK / FS Ratios & Filter Types

12 MHz⁽¹⁾

12.288 MHz

18.432 MHz

11.2896 MHz

16.9344 MHz

8 KHz

0

3

4

1

3

2

NA

1

NA

1

16 KHz

32 KHz

48 KHz

96 KHz

22.05 KHz

44.1 KHz

88.2 KHz

2

1

3

NA

1

3

Note:

1. 12.0000 MHz case is not provided if DAI is configured in Right-Justified and Master mode in

DAI_CONTROL (0x13) and FRAME_CONTROL registers (0x14).

12.6.2

Data Transfer: I²S MODE

Figure 12-7. N-bit I²S Mode (FS = 44.1KHz - MCLK = 256 x FS)

MCLK

LRFS

BCLK

SDOUT

SDIN

L_n

L_n-1

L₀

R_n

R_n-1

R₃

R₂

R₁

R₀

n bits Left Channel

n bits Right Channel

66

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

12.6.3

Data Transfer: Left Justified Mode

Figure 12-8. N-bit Left Justified Mode (FS = 44.1KHz - MCLK = 256 x FS)

MCLK

LRFS

BCLK

SDOUT

SDIN

L_n

L_n-1

L_n-2

L₀

R_n

R_n-1

R_n-2

R₃

R₂

R₁

R₀

n bits Left Channel

n bits Right Channel

12.6.4

Data Transfer: Right Justified Mode

Figure 12-9. N-bit Right Justified Mode (FS = 44.1KHz - MCLK = 256 x FS)

MCLK

LRFS

BCLK

SDOUT

SDIN

L_n

L_n-1

L_n-2

L₀

R_n

R_n-1

R_n-2

R₃

R₂

R₁

R₀

n bits Right Channel

n bits Left Channel

67

11050A–PMAAC–07-Apr-10

12.6.5

Timing Specifications

Figure 12-10. Timing Diagram of data interface (I²S Mode)

T

LRCLK

TLRCLK

V

IH

LRFS

BCLK

V

IL

T

BCLK

VIH

V

IL

T

HSDX

T

LSDX

V

XH

DAI

MSB

LSB

MSB

LSB

DAO

V

XL

Word N

Left Channel

Word N-1

Right Channel

Word N

Right Channel

Table 12-4. Digital Audio InterfaceTiming Specifications

Parameter

Symbols

T_LRCLK

Min

Typ

1 / (2 x F_S)

Max

Unit

Left/Right Word Cycle Time

Bit Clock Period

s

T_BCLK

T_MCLK/ 2

5

BCLK Posedge to {DAI, DAO and LRFS} Change

Hold Time

T_HSDX

T_LSDX

ns

{DAI, DAO and LRFS} Change to BCLK

Posedge Setup Time

5

12.7 Digital Filters Transfer Function

12.7.1

DAC Frequency Response

The following diagrams are referred to FS = 1 (Sampling Frequency).

Figure 12-11. DAC Type 0 Frequency Response

Overall

Ripple

68

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Figure 12-12. DAC Type 1 Frequency Response

Overall

Ripple

Figure 12-13. DAC Type 2 Frequency Response

Overall

Figure 12-14. DAC Type 3 Frequency Response

Overall

69

11050A–PMAAC–07-Apr-10

Figure 12-15. DAC Type 4 Frequency Response

Overall

Ripple

12.7.2

ADC Frequency Response

The following diagrams are referred to FS = 1 (Sampling Frequency).

Figure 12-16. ADC Type 0 Frequency Response

Overall

Ripple

Figure 12-17. ADC Type 1 Frequency Response

Overall

Ripple

70

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Figure 12-18. ADC Type 2 Frequency Response

Overall

Ripple

Figure 12-19. ADC Type 3 Frequency Response

Overall

Ripple

Figure 12-20. ADC Type 4 Frequency Response

Overall

Ripple

71

11050A–PMAAC–07-Apr-10

12.7.3

De-Emphasis Filter Frequency Response

12.7.3.1

De-Emphasis Filter: Frequency Response & Error (FS = 32kHz)

Figure 12-21. De-Emphasis Filter: Frequency Response & Error (FS = 32kHz)

Response

Error

Fequency (Hz)

12.7.3.2

De-Emphasis Filter: Frequency Response & Error (FS = 44.1kHz)

Figure 12-22. De-Emphasis Filter: Frequency Response & Error (FS = 44.1kHz)

Response

Error

Fequency (Hz)

12.7.3.3

De-Emphasis Filter: Frequency Response & Error (FS = 48kHz)

Figure 12-23. De-Emphasis Filter: Frequency Response & Error (FS = 48kHz)

Response

Error

Fequency (Hz)

72

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

12.7.4

Equalizer Frequency Response

The following figures show the frequency response of the equalizer function implemented in the

D/A channels.

Figure 12-24. Bass Filters Response

dB

Fs

Figure 12-25. Medium Filters Response

dB

Fs

73

11050A–PMAAC–07-Apr-10

Figure 12-26. Treble Filters Response

dB

Fs

12.8 Analog Audio Interfaces

12.8.1

Microphone Inputs

The following figures show recommended application circuits for microphone inputs

configurations:

• Mono - single-ended and differential microphone

• Stereo - single ended and differential microphone

• Long-wires microphone

Recommended resistor / capacitor / inductor value may be tuned to the final application,

depending on:

• the microphone specified load resistance,

• the high pass filter desired corner frequency,

• the level and frequency of unwanted signals to be rejected.

Depending also on desired high frequency filtering: common-mode or differential, the differential

suggested application diagrams may be modified.

74

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Figure 12-27. Mono - Single Ended and Differential Microphone Applications

VIN4

LDO4

VDD4

AVDD

VDD4

AVDD

10uF

2k

MICBIAS

2k

1k

AT73C246

10uF

1uF

MICL

MICLN

MICR

MICL

MICLN

MICR

2.2nF

M

NC

M

2.2nF

NC

MICRN

NC

Figure 12-28. Stereo - Single Ended and Differential Microphone Applications

VIN4

LDO4

VDD4

AVDD

VDD4

AVDD

470

10uF

2k

10uF

NC

MICBIAS

2k

1k

AT73C246

1uF

MICL

2.2nF

M

1uF

MICLN

NC

MICLN

1k

2k

1uF

MICR

2.2nF

M

1k

MICRN

NC

MICRN

Figure 12-29. Long Wires Microphone Applications

VIN4

LDO4

VDD4

VIN4

LDO4

VDD4

AVDD

10uF

470

AVDD

2k

10uF

1k

10uF

NC

MICBIAS

2k

AT73C246

10uF

10uH

1uF

MICL

10uH

2.2nF

1nF

M

long wires

1uF

MICLN

NC

MICLN

10uH

M

2.2nF

1nF

1k

long wires

1k

10uH

1uF

MICR

NC

MICR

1nF

10uH

M

2.2nF

long wires

MICRN

1k

75

11050A–PMAAC–07-Apr-10

12.8.2

Aux / Line Inputs

Figure 12-30. Aux and Line Input Application Circuits

3.3uF

100

AUXL

10nF

ON-BOARD

AUDIO IC

SOURCE

(FM receiver, ...)

AUXR

100

3.3uF

AT73C246

100

LINL

LINR

10nF

jack

100

3.3uF

12.8.3

Line / Headphone Outputs

Figure 12-31. AC Coupled Output Application Circuits

3.3uF

330uF

100

HPR

HPVCM

HPL

jack

HPVCM

NC

AT73C246

line-output

headphone

output

16 / 32 Ohms

3.3uF

330uF

100

HPL

Figure 12-32. DC Coupled (CAPLESS) Application Circuits

HPR

DIFF. IN /

DIFF. OUT

POWER AMP.

jack

HPVCM

AT73C246

headphone

output

16 / 32 Ohms

DIFF. IN /

DIFF. OUT

POWER AMP.

HPL

76

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

13. Two Wire Interface and Control Registers

13.1 Two-wire Interface (TWI) Protocol

The two-wire interface interconnects components on a unique two-wire bus, made up of one

clock line and one data line with speeds up to 400 Kbits per second, based one a byte oriented

transfer format. The TWI is slave only and single byte access.

The interface adds flexibility to the power supply solution, enabling LDO regulators to be con-

trolled depending on the instantaneous application requirements.

The AT73C246 has the following 7-bit address:1001001.

Attempting to read data from register addresses not listed in this section results in 0xFF being

read out.

• TWCK is an input pin for the clock

• TWD is an open-drain pin that drives or receives the serial data

The data put on the TWD line must be 8 bits long. Data is transferred MSB first. Each byte must

be followed by an acknowledgement.

Each transfer begins with a START condition and terminates with a STOP condition.

• A high-to-low transition on TWD while TWCK is high defines a START condition.

• A low-to-high transition on TWD while TWCK is high defines a STOP condition.

Figure 13-1. TWI Start/Stop Cycle

TWD

TWCK

Start

Stop

Figure 13-2. TWI Data Cycle

TWD

TWCK

Start

Address

R/W

Ack

Data

Ack

Data

Ack

Stop

After the host initiates a Start condition, it sends the 7-bit slave address defined above to notify

the slave device. A Read/Write bit follows (Read = 1, Write = 0).

The device acknowledges each received byte.

The first byte sent after device address and R/W bit is the address of the device register the host

wants to read or write.

For a write operation the data follows the internal address

77

11050A–PMAAC–07-Apr-10

For a read operation a repeated Start condition needs to be generated followed by a read on the

device.

Figure 13-3. TWD Write Operation

S

ADDR

W

DATA

A

IADDR

A

P

TWD

Figure 13-4. TWD Read Operation

TWD

S

ADDR

W

A

IADDR

A

S

ADDR

R

A

DATA

N

P

• S = Start

• P = Stop

• W = Write

• R = Read

• A = Acknowledge

• N = Not Acknowledge

• ADDR = Device address

• IADDR = Internal address

78

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

13.2 PMU Register Tables

13.2.1

Register Mapping

Table 13-1. Register Mapping

Addr

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x30

0x31

0x32

0x33

Name

7

-

6

-

5

-

4

3

2

1

0

PMU_MODES

PMU_WAKEUP_EVENTS

PMU_WAKEUP_TRIG

PMU_STANDBY_SUPPLIES

PMU_SUPPLY_CTRL

PMU_RST_LEVEL

VDD0_CTRL

-

STANDBY

WAKEUP2

VDD2

PWRDOWN

WAKEUP1

VDD1

RUN

-

RTC

PWREN

LP_VDD0

DVS_VDD4

WAKEUP3

VDD3

WAKEUP0

VDD0

-

RTCR

LP_VDD1

IN_PHASE

-

DVS_VDD3

DVS_VDD2

DVS_VDD1

DVS_VDD0

RST_VDD3

RST_VDD2

RST_VDD1

RST_VDD0

ON_VDD0

ON_VDD1

ON_VDD2

ON_VDD3

ON_VDD4

LPMODE

VDD0_SEL

VDD1_SEL

VDD1_CTRL

LPMODE

VDD2_CTRL

-

VDD2_SEL

VDD3_CTRL

-

VDD3_SEL

VDD4_SEL

VDD4_CTRL

-

PMU_LED

TON_LED

PERIOD_LED

BLINK

ON_LED

RTC_IT

PMU_MASK

-

RTC_ALARM

VDD2_WUP

PMU_IT

-

RTC_IT

PMU_WAKEUP_SUPPLIES

AUTOSTART

-

VDD0_WUP

VDD1_WUP

PATH_SEL

ENASR

VDD3_WUP

-

ENAC

STANDBY

DCBLOCK

MICLDIFF

AUDIO_CONTROL

MIC_CONTROL

DAI_CONTROL

FRAME_CONTROL

MUTE

-

BCLKINV

ENCONF

CUSTCONF

ASR_TIME

-

MICRDIFF

MICDET

ONMICBIAS

MCLKSEL

SELFS

MICDET_ST

MUTEHPR

-

MASTER

SSCMODE

MUTEDACL

-

WL

DAIMODE

MUTEDACR

MUTEINL

MUTEINR

MUTEMICL

MUTEMICR

MUTEHPL

MICLVOL

-

MICLVOL

MICRVOL

INLVOL

INRVOL

HPLVOL

HPRVOL

MICRVOL

-

INLVOL

INLBOTH

INRBOTH

INRVOL

HPLVOL

HPRVOL

HP_CONTROL

AUDIO_EFFECTS

INPUT_CONTROL

OUTPUT_CONTROL

INPUT_MIXER

SIDETONE_VOL

EQUALIZER

HPDET_ST

LHPBOTH

RHPBOTH

ONDEEMP

ONLINR

3DFX_DEPTH

ON3DFX

SWAP_DAC

SWAP_ADC

ONADCL

ONHPL

MONO_DAC MONO_ADC

-

LINESEL

ONMICL

ONMICR

ONBYPASS

MIXMICR

ONADCR

ONHPR

ONLINL

ONDACL

ONMIXL

ONSIDETONE

ONPLAYBACK

-

ONDACR

ONMIXR

-

MIXMICL

MIXLINEL

MIXLINER

-

SIDETONE_VOL

-

ON_BUF

VIN

-

EQ_SEL

ADC_CTRL

ON_ADC

TS

ADC_MUX_1

-

VDD4

-

VDD3

ANA3

VDD2

ANA2

VDD1

ANA1

VDD0

ANA0

ADC_MUX_2

-

ADC_ANA0_MSB

ADC<9:2>

79

11050A–PMAAC–07-Apr-10

Table 13-1. Register Mapping

Addr

0x34

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

0x40

0x41

0x42

0x43

0x44

0x47

0x48

0x49

0x50

0X51

0x52

0x53

0x54

0x55

0x56

0x7F

Name

7

6

5

4

3

2

1

0

ADC_ANA0_LSB

ADC_ANA1_MSB

ADC_ANA1_LSB

ADC_ANA2_MSB

ADC_ANA2_LSB

ADC_ANA3_MSB

ADC_ANA3_LSB

ADC_VDD0_MSB

ADC_VDD0_LSB

ADC_VDD1_MSB

ADC_VDD1_LSB

ADC_VDD2_MSB

ADC_VDD2_LSB

ADC_VDD3_MSB

ADC_VDD3_LSB

ADC_VDD4_MSB

ADC_VDD4_LSB

ADC_VIN_MSB

ADC_VIN_LSB

ADC_ANA_LSB

RTC_CTRL

-

ADC<1:0>

ADC<9:2>

-

ADC_ANA3<1:0>

- -

ADC_ANA2<1:0>

- -

ADC_ANA1<1:0>

RTC_WRITE

ADC_ANA0<1:0>

-

RTC_SEL

RTC_EN

RTC_ADDR

RTC_DATA0

RTC_DATA1

RTC_DATA2

RTC_DATA3

RTC_DATA0

RTC_DATA1

RTC_DATA2

RTC_DATA3

BACKUP_CTRL

VERSION

-

OSC_UPDT

OSC_EN

OSC_STAT

RST_BKUP

SOFTWARE_TAG

VERSION

80

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

13.2.2

PMU Control

Name:

PMU_MODES

Read / Write

0x00

Access:

Address:

7

-

6

-

5

-

4

-

3

-

2

1

0

STANDBY

PWRDOWN

RUN

Table 13-2. PMU_MODES (0x00) Structure

Bit

Name

Description

Reset value

7:3

-

unused

00000

STANDBY request

0: Default value.

1: STANDBY request. Reset to 0 at STANDBY

exit.

2

STANDBY

0

POWERDOWN request

0: Default value.

1: POWERDOWN request. Reset to 0 when

POWERDOWN state reached.

1

0

PWRDOWN

RUN

0

RUN mode

Notes: 1. Please refer to Section 11. “PMU Functional Description” on page 25

2. ‘RUN’ bit is read-only. Only ‘STANDBY’ and ‘PWRDOWN’ bits can be written

81

11050A–PMAAC–07-Apr-10

Name:

PMU_WAKEUP_EVENTS

Read / Write

Access:

Address:

0x01

7

-

6

-

5

4

3

2

1

0

RTC

PWREN

WAKEUP3

WAKEUP2

WAKEUP1

WAKEUP0

Table 13-3. PMU_WAKEUP_EVENTS (0x01) Structure

Bit

Name

Description

Reset value

7:6

-

unused

00

Wake up by RTC alarm input

0: disabled

1: enabled

5

4

3

2

1

RTC

0

1

Wake up by PWREN input

0: disabled

1: enabled

PWREN

Wake up by WAKEUP3 input

0: disabled

1: enabled

WAKEUP3

WAKEUP2

WAKEUP1

WAKEUP0

Wake up by WAKEUP2 input

0: disabled

1: enabled

Wake up by WAKEUP1 input

0: disabled

1: enabled

Wake up by WAKEUP0 input

0: disabled

0

1: enabled

Note:

Please refer to Section 11. “PMU Functional Description” on page 25

82

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Name:

PMU_WAKEUP_TRIG

Read Only

Access:

Address:

0x02

7

-

6

-

5

4

3

2

1

0

RTCR

PWREN

WAKEUP3

WAKEUP2

WAKEUP1

WAKEUP0

Table 13-4. PMU_WAKEUP_TRIG (0x02) Structure

Bit

7:6

5

Name

Description

Reset value

-

unused

00

0

RTCR

WAKEUP_EVENT trigged on RTC alarm

WAKEUP_EVENT trigged on PWREN

WAKEUP_EVENT trigged on WAKEUP3

WAKEUP_EVENT trigged on WAKEUP2

WAKEUP_EVENT trigged on WAKEUP1

WAKEUP_EVENT trigged on WAKEUP0

4

PWREN

WAKEUP3

WAKEUP2

WAKEUP1

WAKEUP0

0

3

0

2

0

1

0

Note:

Please refer to Section 11. “PMU Functional Description” on page 25

83

11050A–PMAAC–07-Apr-10

Name:

PMU_STANDBY_SUPPLIES

Access:

Address:

Read / Write

0x03

7

-

6

-

5

4

3

2

1

0

LP_VDD1

LP_VDD0

VDD3

VDD2

VDD1

VDD0

Table 13-5. PMU_STANDBY_SUPPLIES (0x03) Structure

Bit

Name

Description

Reset value

7:6

-

unused

00

VDD1 Low power mode in STANDBY

0: Full power (PWM)

1: Low power (PFM)

5

4

3

2

1

0

LP_VDD1

LP_VDD0

VDD3

1

0

1

VDD0 Low power mode in STANDBY

0: Full power (PWM)

1: Low power (PFM)

VDD3 in STANDY state

0: OFF

1: ON

VDD2 in STANDY state

0: OFF

1: ON

VDD2

VDD1 in STANDY state

0: OFF

1: ON

VDD1

VDD0 in STANDY state

0: OFF

1: ON

VDD0

84

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Name:

PMU_SUPPLY_CTRL

Read / Write

0x04

Access:

Address:

7

-

6

-

5

4

3

2

1

0

IN_PHASE

DVS_VDD4 DVS_VDD3 DVS_VDD2 DVS_VDD1 DVS_VDD0

Table 13-6. PMU_SUPPLY_CTRL (0x04) Structure

Bit

Name

Description

Reset value

7:6

-

unused

00

DCDC0 and DCDC1 phase operation

0: out-of phase

1: in-phase

5

4

3

2

1

0

IN_PHASE

DVS_VDD4

DVS_VDD3

DVS_VDD2

DVS_VDD1

DVS_VDD0

0

1

DVS function on VDD4

0: OFF

1: ON

DVS function on VDD3

0: OFF

1: ON

DVS function on VDD2

0: OFF

1: ON

DVS function on VDD1

0: OFF

1: ON

DVS function on VDD0

0: OFF

1: ON

85

11050A–PMAAC–07-Apr-10

Name:

PMU_RST_LVL

Read / Write

0x05

Access:

Address:

7

6

5

4

3

2

1

0

RST_VDD3

RST_VDD2

RST_VDD1

RST_VDD0

Table 13-7. PMU_RST_LVL (0x05) Structure

Bit

7:6

5:4

3:2

1:0

Name

Description

Reset value

RST_VDD3

RST_VDD2

RST_VDD1

RST_VDD0

RST level on VDD3

RST level on VDD2

RST level on VDD1

RST level on VDD0

01

10

11

Table 13-8. VDDx Reset Level Selection Table

RST_VDDx

RST LEVEL

0.85 x VDDx

0.90 x VDDx

0.92 x VDDx

0.95 x VDDx

00

01

10

11

86

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Name:

VDD0_CTRL

Read / Write

0x06

Access:

Address:

7

6

5

4

3

2

1

0

ON_VDD0

LPMODE

VDD0_SEL

Table 13-9. VDD0_CTRL (0x06) Structure

Bit

Name

Description

Reset value

VDD0 ON/OFF

0: OFF

7

ON_VDD0

0

1: ON

VDD0 Low power mode

0: Full power (PWM)

1: Low power (PFM)

6

LPMODE

0

5:0

VDD0_SEL

VDD0 voltage selection

010101

Table 13-10. VDD0 Voltage Selection Table

VDD0_SEL

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

010001

010010

VDD0 (V)

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

VDD0_SEL

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

VDD0 (V)

VDD0_SEL

100110

100111

101000

101001

101010

101011

101100

101101

101110

101111

110000

110001

110010

110011

110100

110101

110110

110111

111000

VDD0 (V)

2.70

2.75

2.80

2.85

2.90

2.95

3.00

3.05

3.10

3.15

3.20

3.25

3.30

3.35

3.40

3.45

3.50

3.55

3.60

1.75

1.80

1.85

1.90

1.95

2.00

2.05

2.10

2.15

2.20

2.25

2.30

2.35

2.40

2.45

2.50

2.55

2.60

2.65

100000

100001

100010

100011

100100

100101

87

11050A–PMAAC–07-Apr-10

Name:

VDD1_CTRL

Read / Write

0x07

Access:

Address:

7

6

5

4

3

2

1

0

ON_VDD1

LPMODE

VDD1_SEL

Table 13-11. VDD1_CTRL (0x07) Structure

Bit

Name

Description

Reset value

VDD1 ON / OFF

0: OFF

7

ON_VDD1

0

1: ON

VDD1 Low power mode

0: Full power (PWM)

1: Low power (PFM)

6

LPMODE

0

5:0

VDD1_SEL

VDD1 voltage selection

001000

Table 13-12. VDD1 Voltage Selection Table

VDD1_SEL

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

010001

010010

VDD1 (V)

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

VDD1_SEL

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

VDD1 (V)

VDD1_SEL

100110

100111

101000

101001

101010

101011

101100

101101

101110

101111

110000

110001

110010

110011

110100

110101

110110

110111

111000

VDD1 (V)

2.70

2.75

2.80

2.85

2.90

2.95

3.00

3.05

3.10

3.15

3.20

3.25

3.30

3.35

3.40

3.45

3.50

3.55

3.60

1.75

1.80

1.85

1.90

1.95

2.00

2.05

2.10

2.15

2.20

2.25

2.30

2.35

2.40

2.45

2.50

2.55

2.60

2.65

100000

100001

100010

100011

100100

100101

88

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Name:

VDD2_CTRL

Read / Write

0x08

Access:

Address:

7

6

-

5

-

4

3

2

1

0

ON_VDD2

VDD2_SEL

Table 13-13. VDD2_CTRL (0x08) Structure

Bit

Name

Description

Reset value

VDD2 ON / OFF

0: OFF

7

ON_VDD2

0

1: ON

6:5

4:0

-

unused

00

VDD2_SEL

VDD2 voltage selection

00100

Table 13-14. VDD2 Voltage Selection Table

VDD2_SEL

00000

00001

00010

00011

00100

00101

00110

00111

VDD2 (V)

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

01000

01001

01010

01011

89

11050A–PMAAC–07-Apr-10

Name:

VDD3_CTRL

Read / Write

0x09

Access:

Address:

7

6

-

5

-

4

3

2

1

0

ON_VDD3

VDD3_SEL

Table 13-15. VDD3_CTRL (0x09) Structure

Bit

Name

Description

Reset value

VDD3 ON / OFF

0: OFF

7

ON_VDD3

0

1: ON

6:5

4:0

-

unused

00

VDD3_SEL

VDD3 voltage selection

01100

Table 13-16. VDD3 Voltage Selection Table

VDD3_SEL

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

VDD3 (V)

2.70

2.75

2.80

2.85

2.90

2.95

3.00

3.05

3.10

3.15

3.20

3.25

3.30

3.35

3.40

3.45

3.50

3.55

3.60

10000

10001

10010

90

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Name:

VDD4_CTRL

Read / Write

0x0A

Access:

Address:

7

6

-

5

-

4

3

2

1

0

ON_VDD4

VDD4_SEL

Table 13-17. VDD4_CTRL (0x0A) Structure

Bit

Name

Description

Reset value

VDD4 ON / OFF

0: OFF

7

ON_VDD4

0

1: ON

6:5

4:0

-

unused

00

VDD4_SEL

VDD4 voltage selection

01100

Table 13-18. VDD4 Voltage Selection Table

VDD4_SEL

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

VDD4 (V)

2.70

2.75

2.80

2.85

2.90

2.95

3.00

3.05

3.10

3.15

3.20

3.25

3.30

3.35

3.40

3.45

3.50

3.55

3.60

10000

10001

10010

91

11050A–PMAAC–07-Apr-10

Name:

PMU_LED

Read / Write

0x0B

Access:

Address:

7

6

5

4

3

2

1

0

TON_LED

PERIOD_LED

BLINK

ON_LED

Table 13-19. PMU_LED (0x0B) Structure

Bit

7:5

4:2

Name

Description

Reset value

000

TON_LED

PERIOD_LED

LED ‘ON’ time

LED blinking period

010

Blinking function ON / OFF

1

0

BLINK

0: OFF

1: ON

0

Led ON / OFF

0: OFF

ON_LED

1: ON

Table 13-20. LED Blinking Function Parameters Selection Table

TON_LED

000

LED ‘ON’ Time (ms)

PERIOD_LED

BLINKING PERIOD (s)

25

000

001

010

011

100

101

110

111

0.5

1

001

50

010

75

2

011

100

125

150

175

200

3

100

4

101

5

110

6

111

8

Note:

In case of TON_LED = 175ms, PERIOD_LED=5s and BLINK=1 selection, the LED pin is driven

according to the following diagram. During 9 clock periods (internal RC 32kHz oscillator) the pin is

driven to 0, and during 1 clock period the pin is configured as ‘input’ with an internal pull up resis-

tor to VINSYS.

Figure 13-5. LED Pin Timing Diagram for TON_LED = 175ms and PERIOD_LED=5s

Internal

RC 32kHz

Pin forced to ‘0’

LED Pin

9 x 32kHz clock periods

92

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Name:

PMU_MASK

Read / Write

0x0C

Access:

Address:

7

-

6

-

5

-

4

-

3

-

2

-

1

0

RTC_ALA

RM

RTC_IT

Table 13-21. PMU_MASK (0x0C) Structure

Bit

Name

Description

Reset value

7:2

-

unused

111111

Mask RTC alarm

0: not masked

1: masked

1

0

RTC_ALARM

RTC_IT

1

Mask RTC interrupt

0: not masked

1: masked

Name:

PMU_IT

Access:

Address:

Read Only

0x0D

7

-

6

-

5

-

4

-

3

-

2

-

1

0

RTC_ALA

RM

RTC_IT

Table 13-22. PMU_IT (0x0D) Structure

Bit

Name

Description

Reset value

7:2

-

unused

000000

RTC alarm interrupt

0: default value

1: RTC alarm has occurred. Reset to 0 at read.

1

0

RTC_ALARM

RTC_IT

0

RTC interrupt

0: default value

1: RTC interrupt has occurred. Reset to 0 at read.

93

11050A–PMAAC–07-Apr-10

Name:

PMU_WAKEUP_SUPPLIES

Read / Write

Access:

Address:

0x0E

7

-

6

-

5

-

4

-

3

2

1

0

VDD0_WUP VDD1_WUP VDD2_WUP VDD3_WUP

Table 13-23. PMU_WAKEUP_SUPPLIES (0x0E) Structure

Bit

Name

Description

Reset value

7:4

-

unused

0000

VDD0 Value at WAKEUP

0: Programmed value

1: Default value

3

2

1

0

VDD0_WUP

VDD1_WUP

VDD2_WUP

VDD3_WUP

1

VDD1Value at WAKEUP

0: Programmed value

1: Default value

VDD2 Value at WAKEUP

0: Programmed value

1: Default value

VDD3 Value at WAKEUP

0: Programmed value

1: Default value

94

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Name:

AUTOSTART

Read / Write

0x10

Access:

Address:

7

-

6

5

4

3

2

1

0

ENAC

STANDBY

PATH_SEL

Table 13-24. AUTOSTART (0x10) Structure

Bit

Name

Description

Reset value

7

-

unused

0

Audio Codec ON / OFF

6

ENAC

0: OFF

1: ON

0

Audio STANDBY mode ON / OFF

0: Audio codec active

1: Audio codec in standby

5

STANDBY

PATH_SEL

1

4:0

Audio PATH selection

00000

Table 13-25. Audio Path Selection Table

PATH_SEL

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

AUDIO PATH

No Path

DAC Playback

Mic Sidetone

Digital IN - Headphone OUT

Microphone IN - Headphone OUT

Aux IN - Headphone OUT

Line IN - Headphone OUT

Mic IN - Digital OUT

Aux Bypass

Line Bypass

Mic Record

Aux Record

Aux IN - Digital OUT

Line Record

Line IN - DIGITAL OUT

Mic Sidetone + Record

Aux Bypass + Record

Line Bypass + Record

Mic + Aux Record

Mic + Line Record

Mic IN - Headphone and Digital OUT

Aux IN - Headphone and Digital OUT

Line IN - Headphone and Digital OUT

Mic + Aux IN - Digital OUT

Mic + Line IN - Digital OUT

DAC Playback + Mic Sidetone Digital + Mic IN - Headphone OUT

DAC Playback + Aux Bypass

DAC Playback + Line Bypass

Digital + Aux IN - Headphone OUT

Digital + Line IN - Headphone OUT

DAC Playback + Mic Sidetone

+ Aux Bypass

10000

10001

10010

Digital + Mic + Aux IN - Headphone OUT

Digital + Mic + Line IN - Headphone OUT

DAC Playback + Mic Sidetone

+ Line Bypass

DAC Playback and

MIC Record

Digital IN - Headphone OUT

Mic IN - Digital OUT

95

11050A–PMAAC–07-Apr-10

Table 13-25. Audio Path Selection Table

PATH_SEL

AUDIO PATH

DAC Playback and

Aux Record

Digital IN - Headphone OUT

Aux IN - Digital OUT

10011

DAC Playback and

Line Record

Digital IN - Headphone OUT

Line IN - Digital OUT

10100

10101

10110

10111

DAC Playback + Mic Sidetone Digital + Mic IN - Headphone OUT

and Mic Record

Mic IN - Digital OUT

DAC Playback + Aux Bypass

and Aux Record

Digital + Aux IN - Headphone OUT

Aux IN - Digital OUT

DAC Playback + Line Bypass

and Line Record

Digital + Line IN - Headphone OUT

Line IN - Digital OUT

DAC Playback + Mic Sidetone

+ Aux Bypass and

Mic + Aux Record

Digital + Mic + Aux IN - Headphone OUT

Mic + Aux IN - Digital OUT

11000

11001

DAC Playback + Mic Sidetone

+ Line Bypass and

Mic + Line Record

Digital + Mic + Line IN - Headphone OUT

Mic + Line IN - Digital OUT

96

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Name:

AUDIO_CONTROL

Read / Write

0x11

Access:

Address:

7

-

6

5

4

3

2

1

0

CUST_CO

NF

BCLKINV

DCBLOCK

ENCONF

ENASR

ASR_TIME

Table 13-26. AUDIO_CONTROL (0x11) Structure

Bit

Name

Description

Reset value

7

-

0

Bit clock inversion on I²S port

0: not inverted

6

5

BLCKINV

0

1: inverted

Headphone output coupling configuration

0: DC coupled (capless operation)

1: AC coupled

DCBLOCK

Custom configuration enable

0: Default value.

1: custom configuration is send to audio

controller.

4

3

ENCONF

0

Custom audio configuration

0: Audio path are set with PATH_SEL

1: Custom audio path set by software

CUST_CONF

Gain soft ramping ON / OFF

2

ENASR

0: OFF

1: ON

1

1:0

ASR_TIME

Gain soft ramping timing selection

11

Table 13-27. Gain Soft Ramping Timing Selection Table

ASR_TIME

Timing

00

01

10

11

MCLK / (32 x 512)

MCLK / (64 x 512)

MCLK / (128 x 512)

MCLK / (256 x 512)

97

11050A–PMAAC–07-Apr-10

Name:

MIC_CONTROL

Read / Write

0x12

Access:

Address:

7

-

6

-

5

4

3

2

1

0

MICLDIFF

MICRDIFF

MICDET

ONMICBIAS MICDET_ST

Table 13-28. MIC_CONTROL (0x12) Structure

Bit

Name

Description

Reset value

7:6

-

unused

00

Left microphone differential configuration

0: Single-ended

5

MICLDIFF

0

1: Differential

Right microphone differential configuration

0: Single-ended

1: Differential

4

MICRDIFF

MICDET

0

3:2

1

Microphone detector threshold

00

0

Microphone bias generator ON / OFF

0: OFF

1: ON

ONMICBIAS

MICBIAS pin microphone detector status bit

0: No microphone detected

0

MICDET_ST

0

1: Microphone detected

Table 13-29. Microphone Detector Threshold Selection Table

MICDET

MICBIAS PIN LEVEL (V)

AVDD - 0.1

00

01

10

11

AVDD - 0.2

AVDD - 0.3

AVDD - 0.4

98

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Name:

DAI_CONTROL

Read / Write

0x13

Access:

Address:

7

-

6

-

5

-

4

-

3

2

1

0

MASTER

MCLKSEL

Table 13-30. DAI_CONTROL (0x13) Structure

Bit

Name

Description

Reset value

7:4

-

unused

0000

MASTER / SLAVE operation on DAI port

0: Slave

1: Master

3

MASTER⁽¹⁾

MCLKSEL

0

2:0

Audio Master clock frequency selection

001

Note:

1. The MASTER mode is not provided for 12.0000 MHz clock case and Right-Justified mode on

DAI.

Table 13-31. Audio Master Clock Selection Table

MCLKSEL

000

MCLK (MHz) MCLKSEL

MCLK (MHz)

12.000

12.288

11.2896

18.432

100

101

110

111

16.9344

001

-

010

011

99

11050A–PMAAC–07-Apr-10

Name:

FRAME_CONTROL

Read / Write

0x14

Access:

Address:

7

6

5

4

3

2

1

0

SSCMODE

WL

DAI_MODE

SELFS

Table 13-32. FRAME_CONTROL (0x14) Structure

Bit

Name

Description

Reset value

SSC mode for DAI

7

SSCMODE

0: DAI according to DAI_MODE bits

1: SSC mode

0

6:5

4:3

2:0

WL

Word length selection

11

DAI_MODE

SELFS

Digital Audio Interface mode control

Audio Frame frequency selection

00

011

Table 13-33. Digital Audio Interface Word Length Selection Table

WL

00

01

10

11

MODE

16

18

20

24

Table 13-34. Digital Audio Interface Mode Selection Table

DAIMODE

MODE

00

01

10

11

I2S

Left-Justified

Right-Justified⁽¹⁾

N/A

Note:

1. The Right-Justified mode is not provided for 12.0000 MHz clock case and MASTER mode on

DAI.

Table 13-35. Audio Sampling Frequency Selection Table

SELFS

000

FS (kHz)

SELFS

100

FS (kHz)

96

8

001

16

32

48

101

22.050

44.100

88.200

010

110

011

111

100

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Name:

MUTE

Access:

Address:

Read / Write

0x15

7

6

5

4

3

2

1

0

MUTEDAC

MUTEDACL

MUTEINL

MUTEINR

MUTEMICL MUTEMICR

MUTEHPL

MUTEHPR

R

Table 13-36. MUTE (0x15) Structure

Bit

Name

Description

Reset value

DAC Left mute

0: active

7

MUTEDACL

1

1: muted

DACR Right mute

0: active

1: muted

6

5

4

3

2

1

0

MUTEDACR

MUTEINL

1

AUX / LINE Left mute

0: active

1: muted

AUX / LINE Right mute

0: active

1: muted

MUTEINR

MUTEMICL

MUTEMICR

MUTEHPL

MUTEHPR

MIC Left mute

0: active

1: muted

MIC Right mute

0: active

1: muted

Headphone Left mute

0: active

1: muted

Headphone Right mute

0: active

1: muted

101

11050A–PMAAC–07-Apr-10

Name:

MICLVOL

Read / Write

0x16

Access:

Address:

7

-

6

-

5

4

3

2

1

0

MICLVOL

Table 13-37. MICLVOL (0x16) Structure

Bit

7:6

5:0

Name

Description

Reset value

00

-

unused

MICLVOL

Microphone Left volume selection

000000

Table 13-38. Microphone Left Volume Selection Table

MICLVOL

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

GAIN(dB)

MICLVOL

010000

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

GAIN(dB)

16

MICLVOL

100000

100001

100010

100011

100100

100101

100110

100111

101000

101001

101010

101011

101100

101101

101110

GAIN(dB)

32

0

1

17

33

2

18

34

3

19

35

4

20

36

5

21

37

6

22

38

7

23

39

8

24

40

9

25

41

10

11

12

13

14

15

26

42

27

43

28

44

29

45

30

46

31

Other values

46

102

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Name:

MICRVOL

Read / Write

0x17

Access:

Address:

7

-

6

-

5

4

3

2

1

0

MICRVOL

Table 13-39. MICRVOL (0x17) Structure

Bit

7:6

5:0

Name

Description

Reset value

0

-

unused

MICRVOL

Microphone Right volume selection

000000

Table 13-40. Microphone Right Volume Selection Table

MICRVOL

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

GAIN(dB)

MICRVOL

010000

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

GAIN(dB)

16

MICRVOL

100000

100001

100010

100011

100100

100101

100110

100111

GAIN(dB)

32

0

1

17

33

2

18

34

3

19

35

4

20

36

5

21

37

6

22

38

7

23

39

8

24

101000

101001

101010

101011

101100

101101

101110

40

9

25

41

10

11

12

13

14

15

26

42

27

43

28

44

29

45

30

46

31

Other values

46

103

11050A–PMAAC–07-Apr-10

Name:

INLVOL

Read / Write

0x18

Access:

Address:

7

6

5

4

3

2

1

0

INLBOTH

INLVOL

Table 13-41. INLVOL (0x18) Structure

Bit

Name

Description

Reset value

1

AUX / LINE Left volume controls Right channel

0: inactive

1: active. Prioritary bit over INRBOTH.

7

INLBOTH

INLVOL

6:0

AUX / LINE input Left volume selection

0000000

Table 13-42. AUX / LINE Left Volume Selection Table

INLVOL

≤1011100

1011101

1011110

1011111

1100000

1100001

1100010

1100011

1100100

1100101

1100110

1100111

1101000

1101001

1101010

1101011

1101100

GAIN(dB)

MUTE

-35

INLVOL

1101101

1101110

1101111

1110000

1110001

1110010

1110011

1110100

1110101

1110110

1110111

1111000

1111001

1111010

1111011

1111100

1111101

GAIN(dB)

-19

-18

-17

-16

-15

-14

-13

-12

-11

-10

-9

INLVOL

1111110

GAIN(dB)

-2

-1

0

1111111

-34

0000000

0000001

0000010

0000011

0000100

0000101

0000110

0000111

0001000

0001001

0001010

0001011

>=0101111

-33

1

-32

2

-31

3

-30

4

-29

5

-28

6

-27

7

-26

8

-25

-8

9

-24

-7

10

11

12

-23

-6

-22

-5

-21

-4

-20

-3

104

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Name:

INRVOL

Read / Write

0x19

Access:

Address:

7

6

5

4

3

2

1

0

INRBOTH

INRVOL

Table 13-43. INRVOL (0x19) Structure

Bit

Name

Description

Reset value

0

AUX / LINE Right volume controls left channel

0: inactive

1: active.

7

INRBOTH

INRVOL

6:0

AUX / LINE input Right volume selection

0000000

Table 13-44. AUX / LINE Right Volume Selection Table

INLVOL

≤1011100

1011101

1011110

1011111

1100000

1100001

1100010

1100011

1100100

1100101

1100110

1100111

1101000

1101001

1101010

1101011

1101100

GAIN(dB)

MUTE

-35

INLVOL

1101101

1101110

1101111

1110000

1110001

1110010

1110011

1110100

1110101

1110110

1110111

1111000

1111001

1111010

1111011

1111100

1111101

GAIN(dB)

-19

-18

-17

-16

-15

-14

-13

-12

-11

-10

-9

INLVOL

1111110

GAIN(dB)

-2

-1

0

1111111

-34

0000000

0000001

0000010

0000011

0000100

0000101

0000110

0000111

0001000

0001001

0001010

0001011

>=0101111

-33

1

-32

2

-31

3

-30

4

-29

5

-28

6

-27

7

-26

8

-25

-8

9

-24

-7

10

11

12

-23

-6

-22

-5

-21

-4

-20

-3

105

11050A–PMAAC–07-Apr-10

Name:

HPLVOL

Read / Write

0x1A

Access:

Address:

7

6

5

4

3

2

1

0

HPLVOL

Table 13-45. HPLVOL (0x1A) Structure

Bit

Name

Description

Headphone Left volume selection

Reset value

7:0

HPLVOL

00000000

Table 13-46. Headphone Left Volume Selection Table

GAIN

(dB)

GAIN

(dB)

GAIN

(dB)

GAIN

(dB)

HPLVOL

MUT

E

≤10110010

11001000

-56

11011110

-34

11110100

-12

10110011

10110100

10110101

10110110

10110111

10111000

10111001

10111010

10111011

10111100

10111101

10111110

10111111

11000000

11000001

11000010

11000011

11000100

11000101

11000110

11000111

-77

-76

-75

-74

-73

-72

-71

-70

-69

-68

-67

-66

-65

-64

-63

-62

-61

-60

-59

-58

-57

11001001

11001010

11001011

11001100

11001101

11001110

11001111

11010000

11010001

11010010

11010011

11010100

11010101

11010110

11010111

11011000

11011001

11011010

11011011

11011100

11011101

-55

-54

-53

-52

-51

-50

-49

-48

-47

-46

-45

-44

-43

-42

-41

-40

-39

-38

-37

-36

-35

11011111

11100000

11100001

11100010

11100011

11100100

11100101

11100110

11100111

11101000

11101001

11101010

11101011

11101100

11101101

11101110

11101111

11110000

11110001

11110010

11110011

-33

-32

-31

-30

-29

-28

-27

-26

-25

-24

-23

-22

-21

-20

-19

-18

-17

-16

-15

-14

-13

11110101

11110110

11110111

11111000

11111001

11111010

11111011

11111100

11111101

11111110

11111111

-11

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0

00000000

00000001

00000010

00000011

00000100

00000101

>=00000110

1

2

3

4

5

6

106

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Name:

HPRVOL

Read / Write

0x1B

Access:

Address:

7

6

5

4

3

2

1

0

HPRVOL

Table 13-47. HPRVOL (0x1B) Structure

Bit

Name

Description

HEADSET Right volume selection

Reset value

7:0

HPRVOL

00000000

Table 13-48. Headphone Right Volume Selection Table

GAIN

(dB)

GAIN

(dB)

GAIN

(dB)

GAIN

(dB)

HPRVOL

MUTE

-77

-76

-75

-74

-73

-72

-71

-70

-69

-68

-67

-66

-65

-64

-63

-62

-61

-60

-59

-58

-57

≤10110010

10110011

10110100

10110101

10110110

10110111

10111000

10111001

10111010

10111011

10111100

10111101

10111110

10111111

11000000

11000001

11000010

11000011

11000100

11000101

11000110

11000111

11001000

11001001

11001010

11001011

11001100

11001101

11001110

11001111

11010000

11010001

11010010

11010011

11010100

11010101

11010110

11010111

11011000

11011001

11011010

11011011

11011100

11011101

-56

-55

-54

-53

-52

-51

-50

-49

-48

-47

-46

-45

-44

-43

-42

-41

-40

-39

-38

-37

-36

-35

11011110

11011111

11100000

11100001

11100010

11100011

11100100

11100101

11100110

11100111

11101000

11101001

11101010

11101011

11101100

11101101

11101110

11101111

11110000

11110001

11110010

11110011

-34

-33

-32

-31

-30

-29

-28

-27

-26

-25

-24

-23

-22

-21

-20

-19

-18

-17

-16

-15

-14

-13

11110100

11110101

11110110

11110111

11111000

11111001

11111010

11111011

11111100

11111101

11111110

11111111

-12

-11

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0

00000000

00000001

00000010

00000011

00000100

00000101

>=00000110

1

2

3

4

5

6

107

11050A–PMAAC–07-Apr-10

Name:

HP_CONTROL

Read / Write

0x1C

Access:

Address:

7

-

6

-

5

4

-

3

-

2

1

0

-

HPDET_ST

LHPBOTH

RHPBOTH

Table 13-49. HP_CONTROL (0x1C) Structure

Bit

Name

Description

Reset value

7:3

-

unused

00000

Headphone plug in-out detector

2

1

0

HPDET_ST

LHPBOTH

RHPBOTH

0: OFF

1: ON

0

1

0

Right Headphone volume follows left

0: inactive

1: active. Prioritary bit over RHPBOTH.

Left Headphone volume follows right

0: inactive

1: active

108

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Name:

AUDIO_EFFECTS

Read / Write

0x1D

Access:

Address:

7

6

5

4

3

2

1

0

3DFX_DEPTH

ON3DFX

SWAP_DAC SWAP_ADC MONO_DAC MONO_ADC ONDEEMP

Table 13-50. AUDIO_EFFECTS (0x1D) Structure

Bit

Name

Description

Reset value

7:6

3DFX_DEPTH 3D effect depth control

00

3D effect

5

4

3

2

1

0

ON3DFX

0: OFF

1: ON

0

DAC Left / Right channel swap

0: Left / Right inputs on Left / Right outputs

1: Left / Right inputs on Right / Left outputs

SWAP_DAC

SWAP_ADC

MONO_DAC

MONO_ADC

ONDEEMP

ADC Left / Right channel swap

0: Left / Right inputs on Left / Right outputs

1: Left / Right inputs on Right / Left outputs

(Left + Right) / 2 on Left and Right channels

0: inactive

1: active

Left ADC output on both Left and Right channels

0: inactive

1: active

De-emphasis filter

0: OFF

1: ON

Table 13-51. 3-D Effect Depth Control Table

3DFX_DEPTH

Attenuation

0dB

00

01

10

11

-6dB

-12dB

-18dB

109

11050A–PMAAC–07-Apr-10

Name:

INPUT_CONTROL

Access:

Read / Write.

This register is modified by Audio Controller at audio path change.

0x1E

Address:

7

-

6

5

4

3

2

1

0

LINESEL

ONMICL

ONMICR

ONADCL

ONADCR

ONLINL

ONLINR

Table 13-52. INPUT_CONTROL (0x1E) Structure

Bit

Name

Description

Reset value

7

unused

0

LINE / AUX input selection

0: Aux input selected

1: Line input selected

LINESEL

ONMICL

ONMICR

ONADCL

ONADCR

ONLINL

6

5

4

3

2

1

0

1

0

Left microphone amplifier

0: OFF

1: ON

Right microphone amplifier

0: OFF

1: ON

Left ADC

0: OFF

1: ON

Right ADC

0: OFF

1: ON

Left line input amplifier

0: OFF

1: ON

Right line input amplifier

0: OFF

1: ON

ONLINR

110

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Name:

OUTPUT_CONTROL

Read / Write

Access:

This register is modified by Audio Controller at audio path change.

0x1F

Address:

7

-

6

5

4

3

2

1

0

ONSIDETONE

ONPLAYBACK

ONBYPASS

ONHPL

ONHPR

ONDACL

ONDACR

Table 13-53. OUTPUT_CONTROL (0x1F) Structure

Bit

Name

Description

Reset value

7

unused

0

Sidetone switch

0: muted

1: enabled

ONSIDETONE

ONPLAYBACK

ONBYPASS

ONHPL

6

5

4

3

2

1

0

Playback switch

0: muted

1: enabled

Bypass switch

0: muted

1: enabled

Left headphone amplifier

0: OFF

1: ON

Right headphone amplifier

0: OFF

1: ON

ONHPR

Left DAC

0: OFF

1: ON

ONDACL

Right DAC

0: OFF

ONDACR

1: ON

111

11050A–PMAAC–07-Apr-10

Name:

INPUT_MIXER

Access:

Read / Write

This register is modified by Audio Controller at audio path change.

0x20

Address:

7

-

6

-

5

4

3

2

1

0

MIXMICL

MIXMICR

MIXLINEL

MIXLINER

ONMIXL

ONMIXR

Table 13-54. INPUT_MIXER (0x20) Structure

Bit

Name

Description

Reset value

7:6

-

unused

00

Left microphone input mixer switch

5

4

3

2

1

0

MIXMICL

MIXMICR

MIXLINEL

MIXLINER

ONMIXL

0: muted

1: enabled

0

Right microphone input mixer switch

0: muted

1: enabled

Left line / aux input mixer switch

0: muted

1: enabled

Right line / aux input mixer switch

0: muted

1: enabled

Left input mixer ON / OFF

0: muted

1: enabled

Right input mixer ON / OFF

0: muted

ONMIXR

1: enabled

112

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Name:

SIDETONE_VOL

Read / Write

0x21

Access:

Address:

7

-

6

-

5

-

4

3

2

1

0

SIDETONE_VOL

Table 13-55. SIDETONE_VOL (0x21) Structure

Bit

7:5

4:0

Name

Description

Reset value

000

unused

SIDETONE_VOL

Left / Right sidetone path attenuation

01011

Table 13-56. Left / Right Sidetone Path Attenuation Selection Table

SIDETONE_VOL

00000

ATT(dB)

SIDETONE_VOL

00100

ATT(dB)

SIDETONE_VOL

01000

ATT(dB)

0

3

6

9

12

15

18

21

24

27

30

00001

00101

01001

00010

00110

01010

00011

00111

>=01011

113

11050A–PMAAC–07-Apr-10

Name:

EQUALIZER

Read / Write

0x22

Access:

Address:

7

-

6

-

5

-

4

-

3

2

1

0

EQ_SEL

Table 13-57. EQUALIZER (0x22) Structure

Bit

7:4

3:0

Name

Description

Reset value

0

EQ_SEL

Equalizer selection

0000

Table 13-58. Equalizer Selection Table(0x22) Structure

EQ_SEL

0000

Description

Flat Response

0001

Bass boost +12dB

Bass boost +6dB

Bass cut -12dB

Bass cut -6dB

0010

0011

0100

0101

Medium boost +3dB

Medium boost +8dB

Medium cut -3dB

Medium cut -8dB

Treble boost +12dB

Treble boost +6dB

Treble cut -12dB

Treble cut -6dB

Flat response.

0110

0111

1000

1001

1010

1011

1100

Other value

114

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Name:

ADC_CTRL

Read / Write

0x30

Access:

Address:

7

6

5

-

4

-

3

-

2

1

0

ON_ADC

ON_BUF

TS

Table 13-59. ADC_CTRL (0x30) Structure

Bit

Name

Description

Reset value

ADC function

0: OFF

7

ON_ADC

0

1: ON

Analog buffer

0: OFF

6

ON_BUF

0

1: ON

5:3

2:0

unused

TS

-

000

Sampling period

Table 13-60. ADC Sampling Period Selection Table

SAMPLING

PERIOD (s)

TS

000

001

010

011

100

101

110

111

0.01

0.02

0.1

1

2

3

4

Max speed

115

11050A–PMAAC–07-Apr-10

Name:

ADC_MUX_1

Read / Write

0x31

Access:

Address:

7

-

6

5

-

4

3

2

1

0

VIN

VDD4

VDD3

VDD2

VDD1

VDD0

Table 13-61. ADC_MUX1 (0x31) Structure

Bit

Name

Description

Reset value

7

unused

-

0

VIN channel selection

0: Not selected

1: Selected

6

5

4

VIN

1

unused

VDD4

-

VDD4 channel selection

0: Not selected

1: Selected

VDD3 channel selection

0: Not selected

1: Selected

3

2

1

0

VDD3

VDD2

VDD1

VDD0

1

VDD2 channel selection

0: Not selected

1: Selected

VDD1 channel selection

0: Not selected

1: Selected

VDD0 channel selection

0: Not selected

1: Selected

116

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Name:

ADC_MUX_2

Read / Write

0x32

Access:

Address:

7

-

6

-

5

-

4

-

3

2

1

0

ANA3

ANA2

ANA1

ANA0

Table 13-62. ADC_MUX2 (0x32) Structure

Bit

Name

Description

Reset value

7:4

unused

-

0000

ANA3 channel selection

0: Not selected

1: Selected

3

2

1

0

ANA3

ANA2

ANA1

ANA0

1

ANA2 channel selection

0: Not selected

1: Selected

ANA1 channel selection

0: Not selected

1: Selected

ANA0 channel selection

0: Not selected

1: Selected

117

11050A–PMAAC–07-Apr-10

Name:

ADC_ANA0_MSB

Read Only

0x33

Access:

Address:

7

6

5

4

3

2

1

0

ADC<9:2>

Table 13-63. ADC_ANA0_MSB (0x33) Structure

Bit

Name

Description

ADC_OUT<9:2> for ANA0 Channel

Reset value

7:0

ADC<9:2>

00000000

Name:

ADC_ANA0_LSB

Read Only

0x34

Access:

Address:

7

6

5

4

3

2

1

0

ADC<1:0>

Table 13-64. ADC_ANA0_LSB (0x34) Structure

Bit

7:2

1:0

Name

Description

Reset value

-

unused

ADC<1:0>

ADC_OUT<1:0> for ANA0 Channel

00

118

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Name:

ADC_ANA1_MSB

Read Only

0x35

Access:

Address:

7

6

5

4

3

2

1

0

ADC<9:2>

Table 13-65. ADC_ANA1_MSB (0x35) Structure

Bit

Name

Description

ADC_OUT<9:2> for ANA1 Channel

Reset value

7:0

ADC<9:2>

00000000

Name:

ADC_ANA1_LSB

Read Only

0x36

Access:

Address:

7

6

5

4

3

2

1

0

ADC<1:0>

Table 13-66. ADC_ANA1_LSB (0x36) Structure

Bit

7:2

1:0

Name

Description

Reset value

-

unused

ADC<1:0>

ADC_OUT<1:0> for ANA1 Channel

00

119

11050A–PMAAC–07-Apr-10

Name:

ADC_ANA2_MSB

Read Only

0x37

Access:

Address:

7

6

5

4

3

2

1

0

ADC<9:2>

Table 13-67. ADC_ANA2_MSB (0x37) Structure

Bit

Name

Description

ADC_OUT<9:2> for ANA2 Channel

Reset value

7:0

ADC<9:2>

00000000

Name:

ADC_ANA2_LSB

Read Only

0x38

Access:

Address:

7

6

5

4

3

2

1

0

ADC<1:0>

Table 13-68. ADC_ANA2_LSB (0x38) Structure

Bit

7:2

1:0

Name

Description

Reset value

-

unused

ADC<1:0>

ADC_OUT<1:0> for ANA2 Channel

00

120

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Name:

ADC_ANA3_MSB

Read Only

0x39

Access:

Address:

7

6

5

4

3

2

1

0

ADC<9:2>

Table 13-69. ADC_ANA3_MSB (0x39) Structure

Bit

Name

Description

ADC_OUT<9:2> for ANA3 Channel

Reset value

7:0

ADC<9:2>

00000000

Name:

ADC_ANA3_LSB

Read Only

0x3A

Access:

Address:

7

6

5

4

3

2

1

0

ADC<1:0>

Table 13-70. ADC_ANA3_LSB (0x3A) Structure

Bit

7:2

1:0

Name

Description

Reset value

-

unused

ADC<1:0>

ADC_OUT<1:0> for ANA3 Channel

00

121

11050A–PMAAC–07-Apr-10

Name:

ADC_VDD0_MSB

Read Only

0x3B

Access:

Address:

7

6

5

4

3

2

1

0

ADC<9:2>

Table 13-71. ADC_VDD0_MSB (0x3B) Structure

Bit

Name

Description

ADC_OUT<9:2> for VDD0 Channel

Reset value

7:0

ADC<9:2>

00000000

Name:

ADC_VDD0_LSB

Read Only

0x3C

Access:

Address:

7

6

5

4

3

2

1

0

ADC<1:0>

Table 13-72. ADC_VDD0_LSB (0x3C) Structure

Bit

7:2

1:0

Name

Description

Reset value

-

unused

ADC<1:0>

ADC_OUT<1:0> for VDD0 Channel

00

122

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Name:

ADC_VDD1_MSB

Read Only

0x3D

Access:

Address:

7

6

5

4

3

2

1

0

ADC<9:2>

Table 13-73. ADC_VDD1_MSB (0x3D) Structure

Bit

Name

Description

ADC_OUT<9:2> for VDD1 Channel

Reset value

7:0

ADC<9:2>

00000000

Name:

ADC_VDD1_LSB

Read Only

0x3E

Access:

Address:

7

6

5

4

3

2

1

0

ADC<1:0>

Table 13-74. ADC_VDD1_LSB (0x3E) Structure

Bit

Name

Description

Reset value

7:2

1:0

-

unused

ADC<1:0>

ADC_OUT<1:0> for VDD1 Channel

00

123

11050A–PMAAC–07-Apr-10

Name:

ADC_VDD2_MSB

Read Only

0x3F

Access:

Address:

7

6

5

4

3

2

1

0

ADC<9:2>

Table 13-75. ADC_VDD2_MSB (0x3F) Structure

Bit

Name

Description

ADC_OUT<9:2> for VDD2 Channel

Reset value

7:0

ADC<9:2>

00000000

Name:

ADC_VDD2_LSB

Read Only

0x40

Access:

Address:

7

6

5

4

3

2

1

0

ADC<1:0>

Table 13-76. ADC_VDD2_LSB (0x40) Structure

Bit

7:2

1:0

Name

Description

Reset value

-

unused

ADC<1:0>

ADC_OUT<1:0> for VDD2 Channel

00

124

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Name:

ADC_VDD3_MSB

Read Only

0x41

Access:

Address:

7

6

5

4

3

2

1

0

ADC<9:2>

Table 13-77. ADC_VDD3_MSB (0x41) Structure

Bit

Name

Description

ADC_OUT<9:2> for VDD3 Channel

Reset value

7:2

ADC<9:2>

00000000

Name:

ADC_VDD3_LSB

Read Only

0x42

Access:

Address:

7

6

5

4

3

2

1

0

ADC<1:0>

Table 13-78. ADC_VDD3_LSB (0x42) Structure

Bit

7:2

1:0

Name

Description

Reset value

-

unused

ADC<1:0>

ADC_OUT<1:0> for VDD3 Channel

00

125

11050A–PMAAC–07-Apr-10

Name:

ADC_VDD4_MSB

Read Only

0x43

Access:

Address:

7

6

5

4

3

2

1

0

ADC<9:2>

Table 13-79. ADC_VDD4_MSB (0x43) Structure

Bit

Name

Description

ADC_OUT<9:2> for VDD4 Channel

Reset value

7:0

ADC<9:2>

00000000

Name:

ADC_VDD4_LSB

Read Only

0x44

Access:

Address:

7

6

5

4

3

2

1

0

ADC<1:0>

Table 13-80. ADC_VDD4_LSB (0x44) Structure

Bit

7:2

1:0

Name

Description

Reset value

-

unused

ADC<1:0>

ADC_OUT<1:0> for VDD4 Channel

00

126

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Name:

ADC_VIN_MSB

Read Only

0x47

Access:

Address:

7

6

5

4

3

2

1

0

ADC<9:2>

Table 13-81. ADC_VIN_MSB (0x47) Structure

Bit

Name

Description

ADC_OUT<9:2> for VIN Channel

Reset value

7:0

ADC<9:2>

00000000

Name:

ADC_VIN_LSB

Read Only

0x48

Access:

Address:

7

6

5

4

3

2

1

0

ADC<1:0>

Table 13-82. ADC_VIN_LSB (0x48) Structure

Bit

7:2

1:0

Name

Description

Reset value

-

unused

ADC<1:0>

ADC_OUT<1:0> for VIN Channel

00

127

11050A–PMAAC–07-Apr-10

Name:

ADC_ANA_LSB

Read Only

0x49

Access:

Address:

7

6

5

4

3

2

1

0

ADC_ANA3<1:0>

ADC_ANA2<1:0>

ADC_ANA1<1:0>

ADC_ANA0<1:0>

Table 13-83. ADC_ANA_LSB (0x49) Structure

Bit

7:6

5:4

3:2

1:0

Name

Description

Reset value

ADC_ANA3<1:0>

ADC_ANA2<1:0>

ADC_ANA1<1:0>

ADC_ANA0<1:0>

ADC_OUT<1:0:> for ANA3 Channel

ADC_OUT<1:0:> for ANA2 Channel

ADC_OUT<1:0:> for ANA1 Channel

ADC_OUT<1:0:> for ANA0 Channel

00

Name:

RTC_CTRL

Access:

Address:

Read / Write

0x50

7

-

6

-

5

4

3

2

1

0

RTC_WRITE RTC_SEL

RTC_EN

Table 13-84. RTC_CTRL (0x50) Structure

Bit

Name

Description

unused

Reset value

7:3

-

RTC read/write:

2

1

0

RTC_WRITE

RTC_SEL

RTC_EN

RTC_WRITE = 0: Read mode

RTC_WRITE = 1: Write mode

0

RTC block select:

RTC_SEL = 0: Not Selected

RTC_SEL = 1: Selected

RTC block enable:

RTC_EN = 0: Disabled

RTC_EN = 1: Enabled

128

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Name:

RTC_ADDR

Read / Write

0x51

Access:

Address:

7

6

5

4

3

2

1

0

RTC_ADDR

Table 13-85. RTC_ADDR (0x51) Structure

Bit

Name

Description

Reset value

7:0

RTC_ADDR

RTC address

0000

Name:

RTC_DATA0

Read / Write

0x52

Access:

Address:

7

6

5

4

3

2

1

0

RTC_DATA0

Table 13-86. RTC_DATA0 (0x52) Structure

Bit

Name

Description

Reset value

7:0

RTC_DATA0

RTC DATA 0

0000000

129

11050A–PMAAC–07-Apr-10

Name:

RTC_DATA1

Read / Write

0x53

Access:

Address:

7

6

5

4

3

2

1

0

RTC_DATA1

Table 13-87. RTC_DATA1 (0x53) Structure

Bit

Name

Description

Reset value

7:0

RTC_DATA1

RTC DATA 1

0000000

Name:

RTC_DATA2

Read / Write

0x54

Access:

Address:

7

6

5

4

0

RTC_DATA2

Table 13-88. RTC_DATA2 (0x54) Structure

Bit

Name

Description

Reset value

7:0

RTC_DATA2

RTC DATA 2

0000000

Name:

RTC_DATA3

Read / Write

0x55

Access:

Address:

7

6

5

4

0

RTC_DATA3

Table 13-89. RTC_DATA3 (0x55) Structure

Bit

Name

Description

Reset value

7:0

RTC_DATA3

RTC DATA 3

0000000

130

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Name:

BACKUP_CTRL

Read / Write

0x56

Access:

Address:

7

-

6

-

5

-

4

-

3

2

1

0

OSC_UPDT

OSC_EN

OSC_STAT RST_BKUP

Table 13-90. BACKUP_CTRL (0x56) Structure

Bit

Name

Description

Reset value

7:4

-

unused

0000

RTC Oscillator update

0: No action.

1: Update RTC oscillator with OSC_EN

3

2

1

0

OSC_UPDT

OSC_EN

0

RTC Oscillator enable request

0: Oscillator off.

1: Oscillator on.

RTC Oscillator status (read only)

0: Oscillator off.

1: Oscillator on.

OSC_STAT

RST_BKUP

Reset of the Backup Area

0: Backup area active

1: Backup area in reset state

Name:

VERSION

Access:

Address:

Read

0x7F

7

6

5

4

3

2

1

0

SOFTWARE_TAG

VERSION

Table 13-91. VERSION (0x7F) Structure

Bit

Name

Description

Reset value

Software Tag to identify product specificities as

described in Section 17. “Ordering Information”

on page 154.

SOFTWARE_TAG

7:4

XXXX

‘0001’: Rev. C samples

‘0010’: Rev. D samples

3:0

VERSION

XXXX

131

11050A–PMAAC–07-Apr-10

14. PMU and Audio Soft Control: Quick Start

14.1 RTC Examples

14.1.1

14.1.2

14.1.3

14.1.4

RTC Oscillator POWER-ON

// Set OSC_EN = 1 and OSC_UPDT = 1

TWI_WRITE 0x0C @BACKUP_CTRL

// Wait > 200us.

WAIT 200us

// Set OSC_UPDT = 0

TWI_WRITE 0x04 @BACKUP_CTRL

// Read BACKUP_CTRL to verify OSC_STAT bit. Result = 0x06.

TWI_READ @BACKUP_CTRL

RTC Oscillator POWER-OFF

// Set OSC_EN = 0 and OSC_UPDT = 1

TWI_WRITE 0x08 @BACKUP_CTRL

// Wait 200us

WAIT 200us

// Set OSC_UPDT = 0

TWI_WRITE 0x00 @BACKUP_CTRL

// Read BACKUP_CTRL to verify OSC_STAT bit. Result = 0x00.

TWI_READ @BACKUP_CTRL

RTC Domain RESET

// Set RST_BKUP = 1

TWI_WRITE 0x01 @BACKUP_CTRL

// Wait 200s

WAIT 200us

// Set RST_BKUP = 0

TWI_WRITE 0x00 @BACKUP_CTRL

Note:

RTC Write Operation

Reset of the RTC domain powers off the RTC oscillator.

The following example makes a generic 32-bit write operation into the RTC macro. The 32-bit

data is split into 4 bytes, that are successively sent over the TWI.

unsigned int RTC_DATA;

char DATA0 = (char) (RTC_DATA); // LSBs

char DATA1 = (char) (RTC_DATA >> 8);

char DATA2 = (char) (RTC_DATA >> 16);

char DATA3 = (char) (RTC_DATA >> 24); // MSBs

// Select RTC_ADDR = ADDR. ADDR is the RTC macro register to write,

TWI_WRITE ADDR @RTC_ADDR

// Set RTC_DATA0 to RTC_DATA4 registers.

TWI_WRITE DATA0 @RTC_DATA0

TWI_WRITE DATA1 @RTC_DATA1

132

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

TWI_WRITE DATA2 @RTC_DATA2

TWI_WRITE DATA3 @RTC_DATA3

// Set RTC_WRITE = 1 (write) and RTC_SEL = 1

TWI_WRITE 0x06 @ RTC_CTRL

// Pulse RTC_EN

TWI_WRITE 0x07 @ RTC_CTRL

TWI_WRITE 0x06 @ RTC_CTRL

// Disable RTC access

TWI_WRITE 0x00 @ RTC_CTRL

14.1.5

RTC Read Operation

The following example makes a generic 32-bit read operation into the RTC macro. The 32-bit

RTC data is split into 4 bytes, that are successively read over the TWI.

// Select RTC_ADDR = ADDR. ADDR is the RTC macro register to read,

TWI_WRITE ADDR @RTC_ADDR

// Set RTC_WRITE = 0 (read) and RTC_SEL = 1

TWI_WRITE 0x02 @ RTC_CTRL

// Pulse RTC_EN

TWI_WRITE 0x03 @ RTC_CTRL

TWI_WRITE 0x02 @ RTC_CTRL

// Read RTC_DATA0 to RTC_DATA4 registers.

TWI_READ @RTC_DATA0 // LSBs

TWI_READ @RTC_DATA1

TWI_READ @RTC_DATA2

TWI_READ @RTC_DATA3 // MSBs

// Disable RTC access

TWI_WRITE 0x00 @ RTC_CTRL

14.1.6

RTC Date and Time Update

In the following example, the RTC date and time is set to “12 October 2004, 08h 49min 59s”.

The WRITE_RTC and READ_RTC functions operate as described in the previous sections.

// Disable RTC interrupt MASK

TWI_WRITE 0xFE @PMU_MASK

// Enable RTC ACKUPD IT @RTC_IER (RTC_ADDR 0x20).

WRITE_RTC 0x00000001 @RTC_IER

// Set UPDTIME and UPDCAL @RTC_CR (RTC_ADDR 0x00).

WRITE_RTC 0x00000003 @RTC_CR

// Wait ITB low. This ensures that the RTC is ready to be updated.

// Reset IT by read operation, result is 0x01.

TWI_READ @PMU_IT

// Read in RTC_SR that ACKUPD = 1 (RTC_ADDR = 0x18)

READ_RTC @RTC_SR

// Disable ACKUPD IT @RTC_IDR (RTC_ADDR = 0x24)

WRITE_RTC 0x00000001 @RTC_IDR

// Write Date @RTC_CALR (RTC_ADDR = 0x0C) (12 October 2004)

WRITE_RTC 0x12300420 @RTC_CALR

133

11050A–PMAAC–07-Apr-10

// Write Time @RTC_TIMR (RTC_ADDR = 0x08) (08h 49min 59s)

WRITE_RTC 0x00084959 @RTC_TIMR

// Start RTC @RTC_CR (RTC_ADDR = 0x00)

WRITE_RTC 0x00000000 @RTC_CR

14.2 Audio Examples

14.2.1

Basic Audio Codec Setting Using Automatic Path Control

The following example demonstrates an automatic audio path setting. Assuming that the audio

codec is supplied by the LDO4, the sequence is the following:

• Make the codec interface configuration,

• Set the Digital-IN to Headphone-OUT path,

• Put the audio codec in standby mode,

• Release the standby mode to re-activate the selected path,

• Change the path on-the-fly,

• Shutdown the codec.

// Start LDO4 @3.3V

TWI_WRITE 0x8C @ VDD4_CTRL

// Digital Audio Interface configuration

// Master clock = 12.288MHz, Master / Slave = slave.

// DAI mode = I2S mode, Word length = 24 bits, FS = 48kHz

TWI_WRITE 0x01 @ DAI_CONTROL

TWI_WRITE 0x63 @ FRAME_CONTROL

// Analog interface configuration

// Mic. config: L & R single ended, Micbias = OFF, Mic. detection = OFF.

// Headphone config: AC coupled,

// Automatic Soft Ramping = ON, ASR timing = 11 (~10ms / step)

TWI_WRITE 0x00 @ MIC_CONTROL

TWI_WRITE 0x27 @ AUDIO_CONTROL

// Analog gain

// Headphone (L & R) gain: -20dB. (LHPBOTH set by default in HP_CONTROL)

// Mic L & R gain: +26 dB.

// Unmute all gains. No power-up is performed.

TWI_WRITE 0xEC @ HPLVOL

TWI_WRITE 0x1A @ MICLVOL

TWI_WRITE 0x1A @ MICRVOL

TWI_WRITE 0x00 @ MUTE

// Audio Start

// ENAC = 1, STANDBY = 1. PATH = 1 (DAC playback)

// At the first start, VMID capacitor is charged.

134

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

// Wait (3.tau) = 300ms with 1uF before standby release. (VMID will be

// discharged only when ENAC = 0.)

// From this point Audio Data can be sent over the Digital audio interface.

TWI_WRITE 0x61 @ AUTOSTART.

WAIT 300ms

// Release standby. The audio codec starts silently, the gains are slowly

// ramped up from mute to the register gains. The codec is active.

TWI_WRITE 0x41 @ AUTOSTART

// Codec Pause by Standby

// All gains are softly ramped down to mute. The codec functions are

// shut down. Current consumption is reduced to a few hundreds of micro-

// amps. VMID remains charged

TWI_WRITE 0x61 @ AUTOSTART

// Pause out: Standby release. The codec softly re-starts.

TWI_WRITE 0x41 @ AUTOSTART

// On-the-fly path change

// PATH = 19: Digital IN to Headphone OUT + Mic IN to Digital OUT.

// The codec controller powers up automatically the new path. The DAC

// playback is not affected by starting the Mic. recording.

TWI_WRITE 0x52 @ AUTOSTART

// Codec Shutdown. ENAC = 0, STANDBY = 1. The codec turns off smoothly.

// In case of AC Coupling output configuration, HPR & HPL will slowly

// discharge following VMID time constant.

TWI_WRITE 0x20 @ AUTOSTART

WAIT 600ms

// Disable DCBLOCK bit.

TWI_WRITE 0x07 @ AUDIO_CONTROL

// LDO4 shutdown.

TWI_WRITE 0x0C @ VDD4_CONTROL

14.2.2

Basic Audio Codec Setting Using Custom Path Control

The following example demonstrates a custom audio path setting. Assuming that the audio

codec is supplied by the LDO4, the sequence is the following:

• Make the codec analog and digital interfaces configuration,

• Enter the custom path mode and configure a path with DAC input and Headphone Amplifier

output,

• Put the audio codec in standby mode,

• Release the standby mode to re-activate the selected path,

• Change the path on-the-fly to add the microphone inputs to the DAC signal,

• Shutdown the codec.

135

11050A–PMAAC–07-Apr-10

// Start LDO4 @3.3V

TWI_WRITE 0x8C @ VDD4_CTRL

// Digital Audio Interface configuration

// Master clock = 12.288MHz, Master / Slave = slave.

// DAI mode = I2S mode, Word length = 24 bits, FS = 48kHz

TWI_WRITE 0x01 @ DAI_CONTROL

TWI_WRITE 0x63 @ FRAME_CONTROL

// Analog interface configuration

// Mic. config: L & R single ended, Micbias = OFF, Mic. detection = OFF.

// Headphone config: AC coupled,

// Automatic Soft Ramping = ON, ASR timing = 11 (~10ms / step)

TWI_WRITE 0x00 @ MIC_CONTROL

TWI_WRITE 0x27 @ AUDIO_CONTROL

// Analog gain

// Headphone (L & R) gain: -20dB. (LHPBOTH set by default in HP_CONTROL)

// Mic L & R gain: +26 dB.

// Unmute all gains. No power-up is performed.

TWI_WRITE 0xEC @ HPLVOL

TWI_WRITE 0x1A @ MICLVOL

TWI_WRITE 0x1A @ MICRVOL

TWI_WRITE 0x00 @ MUTE

// Enter the custom path configuration mode

TWI_WRITE 0x2F @ AUDIO_CONTROL

// Audio Start

// ENAC = 1, STANDBY = 1. PATH = 0 (Not read by the audio controller)

// At the first start, VMID capacitor is charged.

// Wait (3.tau) = 300ms with 1uF before standby release. (VMID will be

// discharged only when ENAC = 0.)

// From this point Audio Data can be sent over the Digital audio interface.

TWI_WRITE 0x60 @ AUTOSTART.

WAIT 300ms

// Audio path definition: DAC input to Headphone output. The software sets

// the bits: ONDACL, ONDACR, ONHPL, ONHPR and PLAYBACK by writing

// the registers INPUT_CONTROL, OUTPUT_CONTROL, and INPUT_MIXER.

// The changes are not taken immediately into account (ENCONF = 0).

TWI_WRITE 0x40 @ INPUT_CTRL

TWI_WRITE 0x2F @ OUTPUT_CTRL

TWI_WRITE 0x00 @ INPUT_MIXER

// ENCONF pulse: the audio controller takes the requested changes into

136

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

// account.

TWI_WRITE 0x3F @ AUDIO_CONTROL

TWI_WRITE 0x2F @ AUDIO_CONTROL

// STANDBY release. The codec softly starts.

TWI_WRITE 0x40 @ AUTOSTART.

// Codec Pause by Standby

// All gains are softly ramped down to mute. The codec functions are

// shut down. Current consumption is reduced to a few hundreds of micro-

// amps. VMID remains charged

TWI_WRITE 0x60 @ AUTOSTART

// Pause out: Standby release. The codec softly re-starts.

TWI_WRITE 0x40 @ AUTOSTART

// On-the-fly path change: the stereo microphone inputs are added to the

// DAC playback. The software sets: ONMICL, ONMICR, and ONSIDETONE.

TWI_WRITE 0x70 @ INPUT_CTRL

TWI_WRITE 0x6F @ OUTPUT_CTRL

TWI_WRITE 0x00 @ INPUT_MIXER

// Sidetone gain

TWI_WRITE 0x00 @ SIDETONE_VOL

// ENCONF pulse: the audio controller takes the requested changes into

// account. The path modification is here immediate because STANDBY=0.

TWI_WRITE 0x3F @ AUDIO_CONTROL

TWI_WRITE 0x2F @ AUDIO_CONTROL

// Codec Shutdown. ENAC = 0, STANDBY = 1. The codec turns off smoothly.

// In case of AC Coupling output configuration, HPR & HPL will slowly

// discharge following VMID time constant.

TWI_WRITE 0x20 @ AUTOSTART

WAIT 600ms

// Disable DCBLOCK bit.

TWI_WRITE 0x07 @ AUDIO_CONTROL

// LDO4 shutdown.

TWI_WRITE 0x0C @ VDD4_CONTROL

137

11050A–PMAAC–07-Apr-10

138

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

15. Typical Performance Characteristics

15.1 PMU: Power Supply Sequences

Figure 15-1. Powerdown State to Run State Supplies Start-Up

Powerdown to Run State

SEQUENCE A

Powerdown to Run State

SEQUENCE B

Figure 15-2. Run Sate to Powerdown State Supplies Shut-Down

Run to Powerdown State

SEQUENCE A

Run to Powerdown State

SEQUENCE B

139

11050A–PMAAC–07-Apr-10

Figure 15-3. Detailed Supplies Start-Up

Detailed Supplies Start-Up

SEQUENCE A

Detailed Supplies Start-Up

SEQUENCE B

Figure 15-4. Detailed Supplies Shutdown

Detailed Supplies Shutdown

SEQUENCE A

Detailed Supplies shutdown

SEQUENCE B

140

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Figure 15-5. Run State to Standby State

Run To Standby State (default setting)

SEQUENCE A

Run To Standby State (default setting)

SEQUENCE B

Figure 15-6. Standby To Run State

Standby To Run State (default setting)

SEQUENCE A

Standby To Run State (default setting)

SEQUENCE B

141

11050A–PMAAC–07-Apr-10

15.2 DCDC0 and DCDC1

Unless otherwise noted, the reported measurement were performed at room temperature. External components are those

described in Section 5. “Application Block Diagram” on page 8.

Figure 15-7. DCDC0 Transient Load Regulation Performance

DCDC0 - VIN = 3.3V - VOUT = 1.85V

Load Step 0 To 600mA / 1us

DCDC0 - VIN = 3.3V - VOUT = 1.85V

Load Step 600 To 0mA / 1us

DCDC0 - VIN = 5.5V - VOUT = 1.85V

Load Step 0 To 600mA / 1us

DCDC0 - VIN = 5.5V - VOUT = 1.85V

Load Step 600 To 0mA / 1us

142

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Figure 15-8. DCDC0 Ripple and Efficency Performance

DCDC0 - VOUT = 1.8V

Efficiency in PFM and PWM modes

DCDC0 - VIN = 5.5V - VOUT = 1.8V

Output Voltage Ripple

143

11050A–PMAAC–07-Apr-10

Figure 15-9. DCDC1Transient Load Regulation Performance

DCDC0 - VIN = 3.3V - VOUT = 1.2V

Load Step 0 To 600mA / 1us

DCDC0 - VIN = 3.3V - VOUT = 1.2V

Load Step 600 To 0mA / 1us

DCDC0 - VIN = 5.5V - VOUT = 1.2V

Load Step 0 To 600mA / 1us

Load Step 600 To 0mA / 1us

144

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Figure 15-10. DCDC0 Ripple and Efficiency Performance

DCDC1 - VOUT = 1.2V

Efficiency in PFM and PWM modes

DCDC1 - VIN = 5.5V - VOUT = 1.2V

Output Voltage Ripple

145

11050A–PMAAC–07-Apr-10

15.3 LDO2

Unless otherwise noted, the reported measurement were performed at room temperature. External components are those

described in Section 5. “Application Block Diagram” on page 8.

Figure 15-11. LDO2 Tansient and Static Load Regulation Performance

LDO2- VIN = 1.8V - VOUT = 1V

Load Step 0 To 300mA / 1us

LDO2 - VIN = 1.8V - VOUT = 1V

Load Step 300 To 0mA / 1us

LDO2 - VIN = 1.8V - VOUT = 1V

LDO2 - VIN = 1.7V - VOUT = 1.2V

Static Load Regulation - 0 To 300mA

146

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

15.4 LDO3

Unless otherwise noted, the reported measurement were performed at room temperature. External components are those

described in Section 5. “Application Block Diagram” on page 8.

Figure 15-12. LDO3 Transient and Static Load Regulation Performance

LDO3- VIN = 5.5V - VDD3 = 3.3V

Load Step 0 To 200mA / 1us

LDO3 - VIN = 5.5V - VDD3 = 3.3V

Load Step 200 To 0mA / 1us

LDO3 - VIN = 3.6V - VDD3 = 3.3V

Static Load Regulation - 0 To 200mA

LDO3 - VDD3 = 3.3V - 200mA output load

Drop Out Characteristic.

(VDD3_REG= VDD3 with VIN3 > VDD3 + 300mV)

147

11050A–PMAAC–07-Apr-10

15.5 AUDIO

Unless otherwise noted, the reported measurement were performed at room temperature with AVDD = 3.3V supplied from

LDO4. Typical components as described in Section 5. “Application Block Diagram” on page 8 are used.

Figure 15-13. Microphone Recording Waveforms

Diﬀerential Microphone Recording ( Path 5)

-1dBV / 1kHz Input - Fs = 48kHz - 16kpts FFT

Diﬀerential Microphone Recording ( Path 5)

-60dBV / 1kHz Input - Fs = 48kHz - 16kpts FFT

Diﬀerential Microphone Recording ( Path 5)

THD+N Ratio Versus Input Level

148

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Figure 15-14. DAC Playback Waveforms

DAC playback ( Path 1) - Load 10k

0 dBFs / 1kHz Input - Fs = 48kHz - 32kpts FFT

DAC playback ( Path 1) - Load 10k

-60 dBFs / 1kHz Input - Fs = 48kHz - 32kpts FFT

DAC playback ( Path 1) - Load 10k

THD+N Ratio Versus Input Level

DAC playback ( Path 1) - Load 32 Ohms AC coupled

20mW Ouput Power - Fs = 48kHz - 32kpts FFT

149

11050A–PMAAC–07-Apr-10

Figure 15-15. Line Record Waveforms

Line Record (path 7)

-1 dBV / 1kHz Input - Fs = 48kHz - 32kpts FFT

Line Record (path 7)

-60 dBV / 1kHz Input - Fs = 48kHz - 32kpts FFT

Line Record (path 7)

THD+N Ratio Versus Input Level

150

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

Figure 15-16. Line Bypass Waveforms

Line Bypass (path 5)

0 dBV / 1kHz Input - 10k load - 16kpts FFT

Line Bypass (path 5)

-60 dBV / 1kHz Input - 10k load - 16kpts FFT

Line Record (path 5) - 10k load

THD+N Ratio Versus Input Level

151

11050A–PMAAC–07-Apr-10

152

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

16. Package Information

Figure 16-1. Mechanical Package Drawing for 64-lead Quad Flat No Lead Package

153

11050A–PMAAC–07-Apr-10

17. Ordering Information

Table 17-1. Ordering Information

Temperature

Ordering Code

Package

Power Sequence

Type⁽²⁾

Software

Tag⁽¹⁾

Supplies Default Values

and Marking

Operating Range

VDD0 = 1.85V

VDD1 = 1.20V

VDD2 = 1.00V

VDD3 = 3.30V

VDD4 = 3.30V

QFN64 7.5 x7.5mm

AT73C246

Green

-40°C to +85°C

A

B

0000

0001

0010

VDD0 = 1.80V

VDD1 = 1.20V

VDD2 = 1.20V

VDD3 = 3.30V

VDD4 = 3.30V

QFN64 7.5 x7.5mm

AT73C246-A

Green

VDD0 = 1.80V

VDD1 = 1.00V

VDD2 = 1.00V

VDD3 = 3.30V

VDD4 = 3.30V

QFN64 7.5 x7.5mm

AT73C246-B

Green

Notes: 1. See “VERSION” (0x7F) register definition.

2. See “Power Manager State Description” on page 29 and “Typical Performance Characteristics” on page 139.

154

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

18. Revision History

Table 18-1. Revision History

Change

Request

Ref.

Doc. Rev

Date

Comments

11050A

07-Apr-10

First issue

155

11050A–PMAAC–07-Apr-10

156

AT73C246

11050A–PMAAC–07-Apr-10

AT73C246

1

2

3

4

5

6

7

8

9

Description ............................................................................................... 2

Block Diagram .......................................................................................... 3

Package and Pinout ................................................................................. 4

Pin Description ......................................................................................... 5

Application Block Diagram ..................................................................... 8

Absolute Maximum Ratings .................................................................. 11

Recommended Operating Conditions .................................................. 11

Power Dissipation Ratings .................................................................... 11

PMU Electrical Characteristics ............................................................. 12

9.1Current Consumption Versus Modes ......................................................................12

9.2Supply Monitor Thresholds ......................................................................................12

9.3Digital I/Os DC Characteristics ................................................................................13

9.4DCDC0 and DCDC1 ................................................................................................14

9.5LDO2 .......................................................................................................................16

9.6LDO3 .......................................................................................................................17

9.7LDO4 .......................................................................................................................18

9.8LDO5 .......................................................................................................................19

9.9Measurement Bridge and 10-bit ADC .....................................................................20

9.10RTC Crystal Oscillator ...........................................................................................21

9.11Die Temperature Sensor .......................................................................................21

10 Audio Codec Electrical Characteristics ............................................... 22

11 PMU Functional Description ................................................................. 25

11.1Power Manager State Diagram .............................................................................25

11.2PMU Startup and Shutdown State Diagram ..........................................................26

11.3Power Manager Conditional Transitions ................................................................27

11.4Power Manager State Description .........................................................................29

11.5DCDC0 and DCDC1 Functional Description .........................................................36

11.6LDO2 Functional Description .................................................................................37

11.7LDO3 and LDO4 Functional Description ...............................................................37

11.8Power Fail Detectors .............................................................................................38

11.9Measurement Bridge and 10-bit ADC ....................................................................38

11.10Real Time Clock (RTC) User Interface ................................................................40

11.11Die Temperature Sensor .....................................................................................54

i

11050A–PMAAC–07-Apr-10

12 Audio Codec Functional Description ................................................... 55

12.1Description .............................................................................................................55

12.2Audio Codec Block Diagram ..................................................................................55

12.3Audio Codec Controls ............................................................................................56

12.4Audio Controller .....................................................................................................57

12.5Audio Codec Power Consumption Versus Programmed Audio Path ....................63

12.6Digital Audio Interface ...........................................................................................66

12.7Digital Filters Transfer Function .............................................................................68

12.8Analog Audio Interfaces ........................................................................................74

13 Two Wire Interface and Control Registers ........................................... 77

13.1Two-wire Interface (TWI) Protocol .........................................................................77

13.2PMU Register Tables ............................................................................................79

14 PMU and Audio Soft Control: Quick Start ......................................... 132

14.1RTC Examples ....................................................................................................132

14.2Audio Examples ...................................................................................................134

15 Typical Performance Characteristics ................................................. 139

15.1PMU: Power Supply Sequences .........................................................................139

15.2DCDC0 and DCDC1 ............................................................................................142

15.3LDO2 ...................................................................................................................146

15.4LDO3 ...................................................................................................................147

15.5AUDIO .................................................................................................................148

16 Package Information ............................................................................ 153

17 Ordering Information ........................................................................... 154

18 Revision History ................................................................................... 155

ii

AT73C246

11050A–PMAAC–07-Apr-10

Headquarters

International

Atmel Corporation

2325 Orchard Parkway

San Jose, CA 95131

USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Atmel Asia

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimshatsui

East Kowloon

Hong Kong

Tel: (852) 2721-9778

Fax: (852) 2722-1369

Atmel Europe

Le Krebs

Atmel Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

8, Rue Jean-Pierre Timbaud

BP 309

78054 Saint-Quentin-en-

Yvelines Cedex

France

Tel: (33) 1-30-60-70-00

Fax: (33) 1-30-60-71-11

Product Contact

Web Site

www.atmel.com

www.atmel.com/PowerManage

Technical Support

pmaac@atmel.com

Atmel Techincal Support

Sales Contacts

www.atmel.com/contacts/

Literature Requests

www.atmel.com/literature

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any

intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-

TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY

WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR

PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-

TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT

OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no

representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifica-

tions and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically pro-

vided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted

for use as components in applications intended to support or sustain life.

Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

11050A–PMAAC–07-Apr-10


型号：	AT73C246-B
厂家：	MICROCHIP
描述：	Power Supply Support Circuit, Fixed, 6 Channel, 7.50 X 7.50 MM, 0.90 MM HEIGHT, GREEN, MO-220, QFN-64
文件：	总159页 (文件大小：11597K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT73C246-B [MICROCHIP]

相关型号：

AT73C260

AT73C500

AT73C500-JC

AT73C501

AT73C501-JC

AT73C502

AT73C502-QC

AT74011-H2B1-4F

AT74011-H2B1-4N

AT74013-H2B-4N

AT74013-H2B1-4F

AT74013-H2B1-4N