AT17LV002-10TQI [ATMEL]
FPGA Configuration EEPROM Memory; FPGA配置EEPROM存储器
| 型号： | AT17LV002-10TQI |
| 厂家： | 
ATMEL |
| 描述： | FPGA Configuration EEPROM Memory |
| 文件： | 总19页 (文件大小：245K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• EE Reprogrammable 2,097,152 x 1-bit Serial Memories Designed to Store
Configuration Programs for Field Programmable Gate Arrays (FPGAs)
• In-System Programmable via 2-wire Bus
• Simple Interface to SRAM FPGAs
• Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera FLEX®, APEX™
Devices, Lucent ORCA® FPGAs, Xilinx XC3000™, XC4000™, XC5200™, Spartan®,
Virtex™ FPGAs
• Cascadable Read Back to Support Additional Configurators or Higher-density Arrays
• Low-power CMOS EEPROM Process
• Programmable Reset Polarity
FPGA
• Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC
Packages), 20-lead PLCC, 44-lead PLCC and 44-lead TQFP Packages (Pin-compatible
Across Product Family)
Configuration
EEPROM
Memory
2-megabit
• Emulation of Atmel’s AT24CXXX Serial EEPROMs
• Available in 3.3V 10% LV and 5V 5% C Versions
• System-friendly READY Pin
• Low-power Standby Mode
• Replacement for AT17C/LV020
Description
The AT17C002 and AT17LV002 (high-density AT17 Series) FPGA Configuration
EEPROMs (Configurators) provide an easy-to-use, cost-effective configuration mem-
ory for programming Field Programmable Gate Arrays. The AT17 Series is packaged
in the popular 8-lead LAP, 20-lead PLCC, 44-lead PLCC and the 44-lead TQFP. The
AT17 Series family uses a simple serial-access procedure to configure one or more
FPGA devices. The user can select the polarity of the reset function by programming
four EEPROM bytes. These devices support a write protection mode and a system-
friendly READY pin, which signifies a “good” power level to the FPGA and can be used
to ensure reliable system power-up.
AT17C002
AT17LV002
The AT17 Series Configurators can be programmed with industry-standard program-
mers, Atmel’s ATDH2200E Programming System and Atmel’s ATDH2225 ISP Cable.
Rev. 2281D–12/01
Pin Configuration
8-lead LAP
20-lead PLCC
DATA 1
CLK 2
8 VCC
7 SER_EN
6 CEO (A2)
5 GND
RESET/OE 3
CE 4
CLK
WP1
4
5
6
7
8
18 NC
17 SER_EN
16 NC
RESET/OE
NC
15 READY
14 CEO(A2)
CE
44-lead TQFP
44-lead PLCC
NC
WP1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
7
8
9
39
38
37
36
35
34
33
32
31
30
29
33
32
31
30
29
28
27
26
25
24
23
NC
NC
1
2
3
4
5
6
7
8
9
NC
NC
NC
NC
NC
NC
NC
NC
NC
10
11
12
13
14
15
16
17
NC
NC
NC
NC
NC
NC
NC
WP1
NC
NC
NC
NC
NC
NC
NC
NC
NC 10
NC 11
READY
NC
READY
2
AT17C/LV002
2281D–12/01
AT17C/LV002
Block Diagram
SER_EN
WP1
PROGRAMMING
DATA SHIFT
REGISTER
PROGRAMMING
MODE LOGIC
OSC
CONTROL
ROW
ADDRESS
COUNTER
EEPROM
CELL
MATRIX
ROW
DECODER
OSC
BIT
COUNTER
COLUMN
DECODER
POWER ON
RESET
TC
CLK READY
RESET/OE
CE
CEO(A2)
DATA
Device Description
The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) inter-
face directly with the FPGA device control signals. All FPGA devices can control the
entire configuration process and retrieve data from the configuration EEPROM without
requiring an external intelligent controller.
The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the
DATA output pin and enable the address counter. When RESET/OE is driven High, the
configuration EEPROM resets its address counter and tri-states its DATA pin. The CE
pin also controls the output of the AT17 Series Configurator. If CE is held High after the
RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated.
When OE is subsequently driven Low, the counter and the DATA output pin are
enabled. When RESET/OE is driven High again, the address counter is reset and the
DATA output pin is tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven Low, the device
tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the
address counter is automatically reset.
This is the default setting for the device. Since almost all FPGAs use RESET Low and
OE High, this document will describe RESET/OE.
3
2281D–12/01
Pin Configurations
8
LAP
Pin
20
PLCC
Pin
44
TQFP
Pin
44
PLCC
Pin
Name
I/O Description
1
2
–
2
4
5
40
43
7
2
5
7
DATA
I/O Three-state DATA output for configuration. Open-collector bi-directional
pin for programming.
CLK
I
Clock input. Used to increment the internal address and bit counter for
reading and programming.
WP1(1)
I
WRITE PROTECT (1). Used to protect portions of memory during
programming. Disabled by default due to internal pull-down resistor.
This input pin is not used during FPGA loading operations.
3
4
5
6
13
15
18
19
21
24
RESET/OE
I
I
Output Enable (active High) and RESET (active Low) when SER_EN is
High. A Low level on RESET/OE resets both the address and bit
counters. A High level (with CE Low) enables the data output driver. The
logic polarity of this input is programmable as either RESET/OE or
RESET/OE. For most applications, RESET should be programmed
active Low. This document describes the pin as RESET/OE.
8
CE
Chip Enable input (active Low). A Low level (with OE High) allows DCLK
to increment the address counter and enables the data output driver. A
High level on CE disables both the address and bit counters and forces
the device into a low-power standby mode. Note that this pin will not
enable/disable the device in the 2-wire Serial Programming mode
(SER_EN Low).
10
GND
CEO
Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is
recommended.
O
Chip Enable Output (active Low). This output goes Low when the
address counter has reached its maximum value. In a daisy chain of
AT17 Series devices, the CEO pin of one device must be connected to
the CE input of the next device in the chain. It will stay Low as long as
CE is low and OE is High. It will then follow CE until OE goes Low;
thereafter, CEO will stay High until the entire EEPROM is read again.
6
14
21
27
A2
I
O
I
Device selection input, A2. This is used to enable (or select) the device
during programming (i.e., when SER_EN is Low). A2 has an internal
pulldown resistor.
–
7
8
15
17
20
23
35
38
29
41
44
READY(1)
SER_EN
VCC
Open collector reset state indicator. Driven Low during power-up reset,
released when power-up is complete. (Recommend a 4.7 kΩ pull-up on
this pin if used).
Serial enable must be held High during FPGA loading operations.
Bringing SER_EN Low enables the 2-wire Serial Programming Mode.
For non-ISP applications, SER_EN should be tied to VCC
.
+3.3V/+5V power supply pin.
Note:
1. This pin is not available on the 8-lead packages.
4
AT17C/LV002
2281D–12/01
AT17C/LV002
FPGA Master Serial
Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configura-
tion program. The program is loaded either automatically upon power-up, or on
command, depending on the state of the FPGA mode pins. In Master Mode, the FPGA
automatically loads the configuration program from an external memory. The AT17
Serial Configuration EEPROM has been designed for compatibility with the Master
Serial Mode.
This document discusses the AT40K, AT40KAL and AT94KAL applications, as well as
Xilinx applications.
Control of
Configuration
Most connections between the FPGA device and the AT17 Serial EEPROM are simple
and self-explanatory:
•
•
The DATA output of the AT17 Series Configurator drives DIN of the FPGA devices.
The master FPGA CCLK output drives the CLK input of the AT17 Series
Configurator.
•
The CEO output of any AT17 Series Configurator drives the CE input of the next
Configurator in a cascade chain of EEPROMs.
•
•
SER_EN must be connected to VCC (except during ISP).
The READY pin is available as an open-collector indicator of the device’s reset
status; it is driven Low while the device is in its power-on reset cycle and released
(tri-stated) when the cycle is complete.
Cascading Serial
Configuration
EEPROMs
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configu-
ration memories, cascaded Configurators provide additional memory.
As the last bit from the first Configurator is read, the clock signal to the Configurator
asserts its CEO output Low and disables its DATA line driver. The second Configurator
recognizes the Low level on its CE input and enables its DATA output.
After configuration is complete, the address counters of all cascaded Configurators are
reset if the RESET/OE on each Configurator is driven to its active (Low) level.
If the address counters are not to be reset upon completion, then the RESET/OE input
can be tied to its inactive (High) level.
AT17 Series Reset
Polarity
The AT17 Series Configurator allows the user to program the reset polarity as either
RESET/OE or RESET/OE. This feature is supported by industry-standard programmer
algorithms.
Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can
be programmed by the 2-wire serial bus. The programming is done at VCC supply only.
Programming super voltages are generated inside the chip. The AT17C parts are
read/write at 5V nominal. The AT17LV parts are read/write at 3.3V nominal.
Standby Mode
The AT17C/LV002 Series Configurator enters a low-power standby mode whenever CE
is asserted High. In this mode, the Configurator consumes less than 0.5 mA of current at
5V. The output remains in a high-impedance state regardless of the state of the OE
input.
5
2281D–12/01
Example Circuits
Figure 1. AT17 Series Device for Programming PSLI Devices
AT40K/AT40KAL/AT94K
VCC
AT17 Series Device
DATA
SER_EN
RESET
DATA0
CCLK
CON
RESET
CLK
CE
RESET/OE(1) READY(2)
M2
M1
M0
INIT
GND
Notes: 1. Reset polarity must be set to active Low.
2. Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices.
The FPGA CON/DONE output drives the CE input of the AT17 Series Configurator, while the RESET/OE input is driven by
the FPGA INIT pin. This connection works under all normal circumstances, even when the user aborts the configuration
before CON/DONE has gone High. A Low level on the RESET/OE input, during FPGA reset, clears the configurator’s inter-
nal address pointer so that the reconfiguration starts at the beginning.
Figure 2. Drop-In Replacement of XC17/ATT17 PROMs for Xilinx/Lucent FPGA Applications
V
CC
4.7 k
V
CC
XILINX FPGA
AT17 Series Device
DATA
SER_EN
PROGRAM
DIN
PROGRAM
CLK
CE
CCLK
DONE(3)
INIT
RESET/OE(1) READY(2)
M2
M1
M0
GND
Notes: 1. Reset polarity must be set to active Low.
2. Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices.
3. An internal pull-up resistor is enabled here for DONE.
6
AT17C/LV002
2281D–12/01
AT17C/LV002
For details of ISP, please refer to the “Programming Specification for Atmel's AT17 and AT17A Series FPGA Configuration
EEPROMs”, available on the Atmel web site, at http://www.atmel.com/atmel/acrobat/doc0437.pdf.
Figure 3. In-System Programming of AT17 Series for PSLI Applications
V
V
CC CC
4.7 k
4.7 k
2
DATA 1
V
CC
4
SCLK 3
6
5
7
9
8
10
GND
AT17 Series Device
AT40K/AT40KAL/AT94K
SER_EN
DATA0
CCLK
CON
DATA
CLK
CE
SER_EN
RESET
RESET
M2
M1
M0
RESET/OE(1) READY(2)
INIT
GND
Notes: 1. Reset polarity must be set to active Low.
2. Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices.
Figure 4. In-System Programming of AT17 Series for Xilinx/Lucent FPGA Application
s
VCC VCC
4.7 k
4.7 k
2
DATA
1
3
5
7
9
VCC
4
SCLK
6
VCC
VCC
8
10
4.7 k
4.7 k
XILINX FPGA
AT17 Series Device
GND
SER_EN
DATA
CLK
CE
SER_EN
PROGRAM
DIN
PROGRAM
CCLK
DONE(3)
INIT
RESET/OE(1) READY(2)
M2
M1
M0
GND
Notes: 1. Reset polarity must be set to active Low.
2. Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices.
3. An internal pull-up resistor is enabled here for DONE.
7
2281D–12/01
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those listed under oper-
ating conditions is not implied. Exposure to Abso-
lute Maximum Rating conditions for extended
periods of time may affect device reliability.
Operating Temperature.................................. -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground..............................-0.1V to VCC +0.5V
Supply Voltage (VCC) .........................................-0.5V to +7.0V
Maximum Soldering Temp. (10 sec. @ 1/16 in.).............260°C
ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V
Operating Conditions
AT17C002
AT17LV002
Symbol
Description
Min
Max
Min
Max
Units
Commercial
Supply voltage relative to GND,
4.75
5.25
3.0
3.6
V
-0°C to +70°C
Industrial
Military
Supply voltage relative to GND,
-40°C to +85°C
4.5
4.5
5.5
3.0
3.0
3.6
3.6
V
V
VCC
Supply voltage relative to GND,
-55°C to +125°C
5.5
8
AT17C/LV002
2281D–12/01
AT17C/LV002
DC Characteristics
VCC = 5V 5% Commercial, 5V 10% Industrial/Military
Symbol
VIH
Description
Min
2.0
Max
VCC
0.8
Units
V
High-Level Input Voltage
VIL
Low-level input voltage
0.0
V
VOH
VOL
VOH
VOL
VOH
VOL
ICCA
IL
High-level Output Voltage (IOH = -4 mA)
Low-level Output Voltage (IOL = +4 mA)
High-level Output Voltage (IOH = -4 mA)
Low-level Output Voltage (IOL = +4 mA)
High-level Output Voltage (IOH = -4 mA)
Low-level Output Voltage (IOL = +4 mA)
Supply Current, Active Mode
3.86
V
Commercial
Industrial
Military
0.32
0.37
V
3.76
3.7
V
V
V
0.4
10
V
mA
µA
mA
mA
mA
Input or Output Leakage Current (VIN = VCC or GND)
-10
10
Commercial
0.5
0.75
1
ICCS1
ICCS2
Supply Current, Standby Mode, CMOS
Supply Current, Standby Mode, TTL
Industrial/Military
Commercial/Industrial
DC Characteristics
VCC = 3.3V 10%
Symbol
VIH
Description
Min
2.0
0.0
2.4
Max
VCC
0.8
Units
V
High-level input voltage
VIL
Low-level input voltage
V
VOH
VOL
VOH
VOL
VOH
VOL
ICCA
IL
High-level Output Voltage (IOH = -2.5 mA)
Low-level Output Voltage (IOL = +3 mA)
High-level Output Voltage (IOH = -2 mA)
Low-level Output Voltage (IOL = +3 mA)
High-level Output Voltage (IOH = -2 mA)
Low-level Output Voltage (IOL = +2.5 mA)
Supply Current, Active Mode
V
Commercial
Industrial
Military
0.4
0.4
V
2.4
2.4
V
V
V
0.4
5
V
mA
µA
µA
µA
Input or Output Leakage Current (VIN = VCC or GND)
-10
10
Commercial
200
200
ICCS
Supply Current, Standby Mode
Industrial/Military
9
2281D–12/01
AC Characteristics
CE
TSCE
THCE
TSCE
RESET/OE
CLK
THOE
TLC
THC
TOH
TOE
TCAC
TDF
TCE
DATA
TOH
AC Characteristics when Cascading
RESET/OE
CE
CLK
T
CDF
FIRST BIT
LAST BIT
DATA
CEO
T
OCK
T
OCE
T
OOE
T
OCE
10
AT17C/LV002
2281D–12/01
AT17C/LV002
.
AC Characteristics for AT17C002
VCC = 5V 5% Commercial, VCC = 5V 10% Industrial/Military
Commercial
Industrial/Military(1)
Symbol
Description
Min
Max
Min
Max
35
Units
ns
(2)
TOE
OE to Data Delay
30
45
50
(2)
TCE
CE to Data Delay
45
ns
(2)
TCAC
CLK to Data Delay
50
ns
TOH
Data Hold From CE, OE or CLK
CE or OE to Data Float Delay
CLK Low Time
0
0
ns
(3)
TDF
50
50
ns
TLC
20
20
20
0
20
20
25
0
ns
THC
CLK High Time
ns
TSCE
THCE
THOE
FMAX
CE Setup Time to CLK (to guarantee proper counting)
CE Hold Time from CLK (to guarantee proper counting)
OE High Time (guarantees counter is reset)
Maximum Input Clock Frequency
ns
ns
20
15
20
15
ns
MHz
Notes: 1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady state active levels.
AC Characteristics for AT17C002 when Cascading
VCC = 5V 5% Commercial/VCC = 5V 10% Industrial/Military
Commercial
Industrial/Military(1)
Symbol
Description
Min
Max
Min
Max
50
Units
ns
(3)
TCDF
CLK to Data Float Delay
CLK to CEO Delay
50
35
35
30
(2)
TOCK
40
ns
(2)
TOCE
CE to CEO Delay
35
ns
(2)
TOOE
RESET/OE to CEO Delay
Maximum Input Clock Frequency
30
ns
FMAX
12.5
12.5
MHz
Notes: 1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady state active levels.
11
2281D–12/01
AC Characteristics for AT17LV002
VCC = 3.3V 10%
Commercial
Industrial/Military(1)
Symbol
Description
Min
Max
Min
Max
55
Units
ns
(2)
TOE
OE to Data Delay
50
55
55
(2)
TCE
CE to Data Delay
60
ns
(2)
TCAC
CLK to Data Delay
60
ns
TOH
Data Hold From CE, OE or CLK
CE or OE to Data Float Delay
CLK Low Time
0
0
ns
(3)
TDF
50
50
ns
TLC
25
25
30
0
25
25
35
0
ns
THC
CLK High Time
ns
TSCE
THCE
THOE
FMAX
CE Setup Time to CLK (to guarantee proper counting)
CE Hold Time from CLK (to guarantee proper counting)
OE High Time (guarantees counter is reset)
Maximum Input Clock Frequency
ns
ns
25
15
25
10
ns
MHz
Notes: 1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady state active levels.
AC Characteristics for AT17LV002 when Cascading
VCC = 3.3V 10%
Commercial
Industrial/Military(1)
Symbol
Description
Min
Max
Min
Max
50
Units
ns
(3)
TCDF
CLK to Data Float Delay
CLK to CEO Delay
50
50
35
35
(2)
TOCK
55
ns
(2)
TOCE
CE to CEO Delay
40
ns
(2)
TOOE
RESET/OE to CEO Delay
Maximum Input Clock Frequency
35
ns
FMAX
12.5
10
MHz
Notes: 1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady state active levels.
12
AT17C/LV002
2281D–12/01
AT17C/LV002
Thermal Resistance Coefficients(1)
θJA [°C/W]
Package Type
θJC [°C/W]
Airflow = 0 ft/min
Leadless Array Package
(LAP)
8CN4
20J
45
159.60
Plastic Leaded Chip Carrier
(PLCC)
35
17
15
90
62
50
Thin Plastic Quad Flat
Package (TQFP)
44A
44J
Plastic Leaded Chip Carrier
(PLCC)
Note:
1. For more information refer to the “Thermal Characteristics of Atmel’s Packages”, available on the Atmel web site, at
http://www.atmel.com/atmel/acrobat/doc0636.pdf.
13
2281D–12/01
Ordering Information – 5V Devices
Memory Size
Ordering Code
Package
Operation Range
2-Mbit
AT17C002-10CC
AT17C002-10JC
AT17C002-10TQC
AT17C002-10BJC
8CN4
20J
44A
44J
Commercial
(0°C to 70°C)
AT17C002-10CI
AT17C002-10JI
AT17C002-10TQI
AT17C002-10BJI
8CN4
20J
44A
44J
Industrial
(-40°C to 85°C)
Ordering Information – 3.3V Devices
Memory Size
Ordering Code
Package
Operation Range
2-Mbit
AT17LV002-10CC
AT17LV002-10JC
AT17LV002-10TQC
AT17LV002-10BJC
8CN4
20J
44A
44J
Commercial
(0°C to 70°C)
AT17LV002-10CI
AT17LV002-10JI
AT17LV002-10TQI
AT17LV002-10BJI
8CN4
20J
44A
44J
Industrial
(-40°C to 85°C)
Package Type
8CN4
20J
8-lead, 6 mm x 6 mm x 1 mm, Leadless Array Package (LAP) – Pin-compatible with 8-lead SOIC/VOIC Packages
20-lead, Plastic J-leaded Chip Carrier (PLCC)
44A
44J
44-lead, Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP)
44-lead, Plastic J-leaded Chip Carrier (PLCC)
14
AT17C/LV002
2281D–12/01
AT17C/LV002
Packaging Information
8CN4 – LAP
Marked Pin1 Indentifier
E
A
D
A1
Top View
Side View
Pin1 Corner
L1
0.10 mm
TYP
8
7
1
e
COMMON DIMENSIONS
(Unit of Measure = mm)
2
3
MIN
0.94
0.30
0.45
5.89
4.89
MAX
1.14
0.38
0.55
6.09
6.09
NOM
1.04
NOTE
SYMBOL
A
6
5
A1
b
0.34
b
0.50
1
4
D
5.99
E
5.99
e1
L
e
1.27 BSC
1.10 REF
1.00
e1
L
Bottom View
0.95
1.25
1.05
1.35
1
1
L1
1.30
Note: 1. Metal Pad Dimensions.
11/14/01
DRAWING NO. REV.
TITLE
1150 E.Cheyenne Mtn Blvd.
Colorado Springs, CO 80906
8CN4, 8-lead (6 x 6 x 1.04 mm Body), Lead Pitch 1.27 mm,
Leadless Array Package (LAP)
A
8CN4
R
15
2281D–12/01
20J – PLCC
PIN NO. 1
1.14(0.045) X 45˚
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
e
E1
E
D2/E2
B1
B
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
4.191
2.286
0.508
9.779
8.890
9.779
8.890
7.366
0.660
0.330
MAX
4.572
3.048
–
NOM
NOTE
SYMBOL
A
–
A1
A2
D
–
–
–
10.033
D1
E
–
9.042 Note 2
10.033
–
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AA.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
E1
D2/E2
B
–
9.042 Note 2
8.382
–
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
0.533
e
1.270 TYP
10/04/01
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC)
20J
B
R
16
AT17C/LV002
2281D–12/01
AT17C/LV002
44A – TQFP
PIN 1
B
PIN 1 IDENTIFIER
E1
E
e
D1
D
C
0˚~7˚
A2
A
A1
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
NOM
NOTE
SYMBOL
A
–
–
A1
A2
D
0.05
0.95
11.75
9.90
11.75
9.90
0.30
0.09
0.45
0.15
1.00
12.00
10.00
12.00
10.00
–
1.05
12.25
D1
E
10.10 Note 2
12.25
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
E1
B
10.10 Note 2
0.45
C
–
0.20
3. Lead coplanarity is 0.10 mm maximum.
L
–
0.75
e
0.80 TYP
10/5/2001
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
44A
B
R
17
2281D–12/01
44J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
D2/E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
COMMON DIMENSIONS
(Unit of Measure = mm)
45˚ MAX (3X)
MIN
4.191
MAX
4.572
3.048
–
NOM
NOTE
SYMBOL
A
–
A1
A2
D
2.286
–
0.508
–
17.399
16.510
17.399
16.510
–
17.653
D1
E
–
16.662 Note 2
17.653
–
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
E1
–
16.662 Note 2
16.002
D2/E2 14.986
–
B
0.660
0.330
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
44J
B
R
18
AT17C/LV002
2281D–12/01
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Available on web site
© Atmel Corporation 2001.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
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2281D–12/01/xM
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