AT17LV002A-10JJ [ATMEL]
Configuration Memory, 2MX1, Serial, CMOS, PQCC20, PLASTIC, MS-018AA, LCC-20;
| 型号： | AT17LV002A-10JJ |
| 厂家： | 
ATMEL |
| 描述： | Configuration Memory, 2MX1, Serial, CMOS, PQCC20, PLASTIC, MS-018AA, LCC-20 |
| 文件： | 总18页 (文件大小：318K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• EE Programmable 65,536 x 1-, 131,072 x 1-, 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1- and
2,097,152 x 1-bit Serial Memories Designed to Store Configuration Programs for
Altera® FLEX® and APEX™ FPGAs (Device Selection Guide Included)
• Available as a 3.3V ( 10%) and 5.0V ( 5% Commercial, 10% Industrial) Version
• In-System Programmable (ISP) via 2-wire Bus
• Simple Interface to SRAM FPGAs
• Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera FLEX, APEX
Devices, ORCA® FPGAs, Xilinx® XC3000, XC4000, XC5200, Spartan®, Virtex™ FPGAs,
Motorola MPA1000 FPGAs
• Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
• Very Low-power CMOS EEPROM Process
• Programmable Reset Polarity
• Available 8-lead PDIP, 20-lead PLCC and 32-lead TQFP Packages (Pin Compatible
Across Product Family)
FPGA
Configuration
EEPROM
Memory
• Emulation of Atmel’s AT24CXXX Serial EEPROMs
• Low-power Standby Mode
• High-reliability
AT17LV65A
AT17LV128A
AT17LV256A
AT17LV512A
AT17LV010A
AT17LV002A
– Endurance: 100,000 Write Cycles
– Data Retention: 90 Years for Industrial Parts (at 85°C) and 190 Years for
Commercial Parts (at 70°C)
• Green (Pb/Halide-free/RoHS Compliant) Package Options Available
1. Description
The AT17A series FPGA configuration EEPROMs (Configurators) provide an easy-to-
use, cost-effective configuration memory for Field Programmable Gate Arrays. The
AT17A series device is packaged in the 8-lead PDIP(1), 20-lead PLCC and 32-lead
TQFP, see Table 1-1. The AT17A series configurator uses a simple serial-access pro-
cedure to configure one or more FPGA devices. The user can select the polarity of the
reset function by programming four EEPROM bytes.These devices also support a
write-protection mechanism within its programming mode.
3.3V and 5V
System Support
Note:
1. The 8-lead LAP, PDIP and SOIC packages for the AT17LV65A/128A/256A do not
have an A label. However, the 8-lead packages are pin compatible with the 8-lead
package of Altera’s EEPROMs, refer to the AT17LV65/128/256/512/010/002/040
datasheet available on the Atmel web site for more information.
The AT17A series configurators can be programmed with industry-standard program-
mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.
Table 1-1.
AT17A Series Packages
AT17LV65A/
AT17LV128A/
Package
AT17LV256A
AT17LV512A
AT17LV010A
AT17LV002A
8-lead
PDIP
Yes
Yes
Yes
–
Yes
–
20-lead
PLCC
Yes
–
Yes
Yes
Yes
Yes
32-lead
TQFP
2322G–CNFG–03/06
2. Pin Configuration
Figure 2-1. 8-lead PDIP
DATA
1
2
3
4
8
7
6
5
VCC
DCLK
SER_EN
(A2) nCASC(4)
GND
(WP(1)) RESET/OE
nCS
Figure 2-2. 20-lead PLCC
DCLK
WP1(2)
NC
4
5
6
7
8
18 SER_EN
17 NC
16 NC
NC
15 NC (READY(2))
14 NC
(WP(1)) RESET/OE
Figure 2-3. 32-lead TQFP
24 NC
NC
1
2
3
4
5
6
7
8
23 SER_EN
DCLK
NC
(WP1(3)) NC
NC
22 NC
21 NC
20 READY
19 NC
18 NC
17 NC
NC
RESET/OE
NC
Notes: 1. This pin is only available on AT17LV65A/128A/256A devices.
2. This pin is only available on AT17LV512A/010A/002A devices.
3. This pin is only available on AT17LV010A/002A devices.
4. The nCASC feature is not available on the AT17LV65A device.
2
AT17LV65A/128A/256A/512A/002A
2322G–CNFG–03/06
AT17LV65A/128A/256A/512A/002A
Figure 2-4. Block Diagram
SER_EN
WP1(2)
OSCILLATOR
CONTROLL
OSCILLATOR(3)
POWER ON
RESET
READY(2)
nCS
nCASC
DCLK
RESET/OE
(WP(1))
Notes: 1. This pin is only available on AT17LV65A/128A/256A devices.
2. This pin is only available on AT17LV512A/010A/002A devices.
3. The nCASC feature is not available on the AT17LV65A device.
3
2322G–CNFG–03/06
3. Device Description
The control signals for the configuration EEPROM (nCS, RESET/OE and DCLK) interface
directly with the FPGA device control signals. All FPGA devices can control the entire configura-
tion process and retrieve data from the configuration EEPROM without requiring an external
controller.
The configuration EEPROM’s RESET/OE and nCS pins control the tri-state buffer on the DATA
output pin and enable the address counter and the oscillator. When RESET/OE is driven Low,
the configuration EEPROM resets its address counter and tri-states its DATA pin. The nCS pin
also controls the output of the AT17A series configurator. If nCS is held High after the
RESET/OE pulse, the counter is disabled and the DATA output pin is tri-stated. When nCS is
driven subsequently Low, the counter and the DATA output pin are enabled. When RESET/OE
is driven Low again, the address counter is reset and the DATA output pin is tri-stated, regard-
less of the state of the nCS.
When the configurator has driven out all of its data and nCASC is driven Low, the device tri-
states the DATA pin to avoid contention with other configurators. Upon power-up, the address
counter is automatically reset.
This is the default setting for the device. Since almost all FPGAs use RESET Low and OE High,
this document will describe RESET/OE.
4. Pin Description
AT17LV65A/
AT17LV128A/
AT17LV256A
AT17LV512A/
AT17LV010A
AT17LV002A
20
8
20
32
20
32
Name
DATA
I/O
PLCC
PDIP
PLCC
TQFP
PLCC
TQFP
I/O
2
4
1
2
–
3
4
5
2
4
31
2
2
4
31
2
DCLK
WP1
I
I
I
I
–
5
4
5
4
RESET/OE
nCS
8
8
7
8
7
9
9
10
12
9
10
12
GND
10
10
10
nCASC
A2
O
I
12
6
12
15
12
15
READY
SER_EN
VCC
O
I
–
–
7
8
15
18
20
20
23
27
15
18
20
20
23
27
18
20
Note:
1. The nCASC feature is not available on the AT17LV65A device.
4
AT17LV65A/128A/256A/512A/002A
2322G–CNFG–03/06
AT17LV65A/128A/256A/512A/002A
4.1
4.2
DATA
DCLK
Three-state DATA output for configuration. Open-collector bi-directional pin for programming.
Clock output or clock input. Rising edges on DCLK increment the internal address counter and
present the next bit of data to the DATA pin. The counter is incremented only if the RESET/OE
input is held High, the nCS input is held Low, and all configuration data has not been transferred
to the target device (otherwise, as the master device, the DCLK pin drives Low).
4.3
4.4
WP1
WRITE PROTECT (1). This pin is used to protect portions of memory during programming, and
it is disabled by default due to internal pull-down resistor. This input pin is not used during FPGA
loading operations. This pin is only available on AT17LV512A/010A/002A devices.
RESET/OE
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low logic level
resets the address counter. A High logic level (with nCS Low) enables DATA and permits the
address counter to count. In the mode, if this pin is Low (reset), the internal oscillator becomes
inactive and DCLK drives Low. The logic polarity of this input is programmable and must be pro-
grammed active High (RESET active Low) by the user during programming for Altera
applications.
4.5
4.6
WP
Write protect (WP) input (when nCS is Low) during programming only (SER_EN Low). When
WP is Low, the entire memory can be written. When WP is enabled (High), the lowest block of
the memory cannot be written. This pin is only available on AT17LV65A/128A/256A devices.
nCS
Chip Select input (active Low). A Low input (with OE High) allows DCLK to increment the
address counter and enables DATA to drive out. If the AT17A series is reset with nCS Low, the
device initializes as the first (and master) device in a daisy-chain. If the AT17A series is reset
with nCS High, the device initializes as a subsequent AT17A series device in the chain.
4.7
4.8
GND
Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is recommended.
nCASC
Cascade Select Output (active Low). This output goes Low when the address counter has
reached its maximum value. In a daisy-chain of AT17A series devices, the nCASC pin of one
device is usually connected to the nCS input pin of the next device in the chain, which permits
DCLK from the master configurator to clock data from a subsequent AT17A series device in the
chain. This feature is not available on the AT17LV65A device.
4.9
A2
Device selection input, A2. This is used to enable (or select) the device during programming
(i.e., when SER_EN is Low). A2 has an internal pull-down resistor.
5
2322G–CNFG–03/06
4.10 READY
4.11 SER_EN
Open collector reset state indicator. Driven Low during power-on reset cycle, released when
power-up is complete. (recommended 4.7 kΩ pull-up on this pin if used).
Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low
enables the 2-wire Serial Programming Mode. For non-ISP applications, SER_EN should be tied
to VCC
.
4.12 VCC
3.3V ( 10%) and 5.0V ( 5% Commercial, 10% Industrial) power supply pin.
5. FPGA Master Serial Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration pro-
gram. The program is loaded either automatically upon power-up, or on command, depending
on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the config-
uration program from an external memory. The AT17A Serial Configuration EEPROM has been
designed for compatibility with the Master Serial mode.
This document discusses the Altera FLEX FPGA device interfaces
6. Control of Configuration
Most connections between the FPGA device and the AT17A Serial EEPROM are simple and
self-explanatory.
• The DATA output of the AT17A series configurator drives DIN of the FPGA devices.
• The master FPGA DCLK output or external clock source drives the DCLK input of the AT17A
series configurator.
• The nCASC output of any AT17A series configurator drives the nCS input of the next
configurator in a cascaded chain of EEPROMs.
• SER_EN must be connected to VCC (except during ISP).
7. Cascading Serial Configuration EEPROMs
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration
memories, cascaded configurators provide additional memory.
After the last bit from the first configurator is read, the next clock signal to the configurator
asserts its nCASC output low and disables its DATA line driver. The second configurator recog-
nizes the low level on its nCS input and enables its DATA output.
After configuration is complete, the address counters of all cascaded configurators are reset if
the RESET/OE on each configurator is driven to a Low level.
If the address counters are not to be reset upon completion, then the RESET/OE input can be
tied to a High level.
The AT17LV65A devices do not have the nCASC feature to perform cascaded configurations.
6
AT17LV65A/128A/256A/512A/002A
2322G–CNFG–03/06
AT17LV65A/128A/256A/512A/002A
8. AT17A Series Reset Polarity
The AT17A series configurator allows the user to program the polarity of the RESET/OE pin as
either RESET/OE or RESET/OE. This feature is supported by industry-standard programmer
algorithms.
9. Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can be pro-
grammed by the 2-wire serial bus. The programming is done at VCC supply only. Programming
super voltages are generated inside the chip.
10. Standby Mode
The AT17LV65A/128A/256A enters a low-power standby mode whenever nCS is asserted High.
In this mode, the configurator consumes less than 50 µA of current at 3.3V (100 µA for the
AT17LV512A/010A/002A). The output remains in a high-impedance state regardless of the state
of the RESET/OE input.
11. Absolute Maximum Ratings*
Operating Temperature.................................... -40°C to +85°C
*NOTICE:
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those listed under oper-
ating conditions is not implied. Exposure to Abso-
lute Maximum Rating conditions for extended
periods of time may affect device reliability.
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground..............................-0.1V to VCC +0.5V
Supply Voltage (VCC) .........................................-0.5V to +7.0V
Maximum Soldering Temp. (10 sec. @ 1/16 in.).............260°C
ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V
12. Operating Conditions
3.3V
5V
Symbol
Description
Min
Max
Min
Max
Units
Supply voltage relative to GND
-0°C to +70°C
Commercial
3.0
3.6
4.75
5.25
V
VCC
Supply voltage relative to GND
-40°C to +85°C
Industrial
3.0
3.6
4.5
5.5
V
7
2322G–CNFG–03/06
13. DC Characteristics
VCC = 3.3V 10%
AT17LV65A/
AT17LV128A/
AT17LV256A
AT17LV512A/
AT17LV010A
AT17LV002A
Symbol
VIH
Description
Min
2.0
0
Max
VCC
0.8
Min
2.0
0
Max
VCC
0.8
Min
2.0
0
Max
VCC
0.8
Units
V
High-level Input Voltage
VIL
Low-level Input Voltage
V
VOH
VOL
VOH
VOL
ICCA
IL
High-level Output Voltage (IOH = -2.5 mA)
Low-level Output Voltage (IOL = +3 mA)
High-level Output Voltage (IOH = -2 mA)
Low-level Output Voltage (IOL = +3 mA)
Supply Current, Active Mode
2.4
2.4
2.4
V
Commercial
Industrial
0.4
0.4
0.4
V
2.4
-10
2.4
-10
2.4
-10
V
0.4
5
0.4
5
0.4
5
V
mA
µA
µA
µA
Input or Output Leakage Current (VIN = VCC or GND)
Commercial
Industrial
10
50
100
10
10
100
100
150
150
ICCS
Supply Current, Standby Mode
14. DC Characteristics
VCC = 5V 5% Commercial; VCC = 5V 10% Industrial
AT17LV65A/
AT17LV128A/
AT17LV256A
AT17LV512A/
AT17LV010A
AT17LV002A
Symbol
VIH
Description
Min
2.0
0
Max
VCC
0.8
Min
2.0
0
Max
VCC
0.8
Min
2.0
0
Max
VCC
0.8
Units
V
High-level Input Voltage
VIL
Low-level Input Voltage
V
VOH
VOL
VOH
VOL
ICCA
IL
High-level Output Voltage (IOH = -2.5 mA)
Low-level Output Voltage (IOL = +3 mA)
High-level Output Voltage (IOH = -2 mA)
Low-level Output Voltage (IOL = +3 mA)
Supply Current, Active Mode
3.7
3.86
3.86
V
Commercial
Industrial
0.32
0.32
0.32
V
3.6
-10
3.76
-10
3.76
-10
V
0.37
10
0.37
10
0.37
10
V
mA
µA
µA
µA
Input or Output Leakage Current (VIN = VCC or GND)
Commercial
Industrial
10
10
10
75
200
200
350
350
ICCS1
Supply Current, Standby Mode
150
8
AT17LV65A/128A/256A/512A/002A
2322G–CNFG–03/06
AT17LV65A/128A/256A/512A/002A
15. AC Waveforms
nCS
TSCE
THCE
TSCE
RESET/OE
DCLK
THOE
TLC
THC
TOE
TCAC
TOH
TDF
TCE
DATA
TOH
16. AC Waveforms when Cascading
RESET/OE
nCS
DCLK
T
CDF
LAST BIT
FIRST BIT
DATA
T
T
T
OOE
OCK
OCE
nCASL
T
OCE
9
2322G–CNFG–03/06
17. AC Characteristics
VCC = 3.3V 10%
AT17LV65A/128A/256A
Commercial Industrial
AT17LV512A/010A/002A
Commercial Industrial
Symbol
Description
Min
Max
50
Min
Max
Min
Max
50
Min
Max
Units
ns
(1)
TOE
OE to Data Delay
55
60
80
55
60
60
(1)
TCE
CE to Data Delay
60
55
ns
(1)
TCAC
CLK to Data Delay
Data Hold from CE, OE, or CLK
CE or OE to Data Float Delay
CLK Low Time
75
55
ns
TOH
0
0
0
0
ns
(2)
TDF
55
55
50
50
ns
TLC
THC
25
25
25
25
25
25
25
25
ns
CLK High Time
ns
CE Setup Time to CLK
(to guarantee proper counting)
TSCE
35
0
60
0
30
0
35
0
ns
ns
CE Hold Time from CLK
(to guarantee proper counting)
THCE
THOE
FMAX
OE High Time (guarantees counter is reset)
Maximum Input Clock Frequency
25
10
25
10
25
15
25
10
ns
MHz
Notes: 1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels.
18. AC Characteristics when Cascading
VCC = 3.3V 10%
AT17LV65A/128A/256A
Commercial Industrial
AT17LV512A/010A/002A
Commercial Industrial
Symbol
Description
Min
Max
60
Min
Max
Min
Max
50
Min
Max
Units
ns
(2)
TCDF
CLK to Data Float Delay
CLK to CEO Delay
60
60
60
45
50
55
40
35
(1)
TOCK
55
50
ns
(1)
TOCE
CE to CEO Delay
55
35
ns
(1)
TOOE
RESET/OE to CEO Delay
Maximum Input Clock Frequency
40
35
ns
FMAX
8
8
12.5
10
MHz
Notes: 1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels.
10
AT17LV65A/128A/256A/512A/002A
2322G–CNFG–03/06
AT17LV65A/128A/256A/512A/002A
19. AC Characteristics
VCC = 5V 5% Commercial; VCC = 5V 10% Industrial
AT17LV65A/128A/256A
Commercial Industrial
AT17LV512A/010A/002A
Commercial Industrial
Symbol
Description
Min
Max
30
Min
Max
Min
Max
30
Min
Max
Units
ns
(1)
TOE
OE to Data Delay
35
45
55
35
45
50
(1)
TCE
CE to Data Delay
45
45
ns
(1)
TCAC
CLK to Data Delay
Data Hold from CE, OE, or CLK
CE or OE to Data Float Delay
CLK Low Time
50
50
ns
TOH
0
0
0
0
ns
(2)
TDF
50
50
50
50
ns
TLC
THC
20
20
20
20
20
20
20
20
ns
CLK High Time
ns
CE Setup Time to CLK (to guarantee proper
counting)
TSCE
35
0
40
0
20
0
25
0
ns
ns
CE Hold Time from CLK (to guarantee proper
counting)
THCE
THOE
FMAX
OE High Time (guarantees counter is reset)
Maximum Input Clock Frequency
20
20
20
15
20
15
ns
12.5
12.5
MHz
Notes: 1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels.
20. AC Characteristics when Cascading
VCC = 5V 5% Commercial; VCC = 5V 10% Industrial
AT17LV65A/128A/256A
Commercial Industrial
AT17LV512A/010A/002A
Commercial Industrial
Symbol
Description
Min
Max
50
Min
Max
Min
Max
50
Min
Max
Units
ns
(2)
TCDF
CLK to Data Float Delay
CLK to CEO Delay
50
40
35
35
50
40
35
30
(1)
TOCK
35
35
ns
(1)
TOCE
CE to CEO Delay
35
35
ns
(1)
TOOE
RESET/OE to CEO Delay
Maximum Input Clock Frequency
30
30
ns
FMAX
10
10
12.5
12.5
MHz
Notes: 1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels.
11
2322G–CNFG–03/06
21. Thermal Resistance Coefficients(1)
AT17LV65A/
AT17LV128A/
AT17LV256A
AT17LV512A/
AT17LV010A
Package Type
AT17LV002A
θ
θ
θ
θ
θ
θ
θ
θ
JC [°C/W]
JA [°C/W](2)
37
107
35
8P3
20J
32A
44J
Plastic Dual Inline Package (PDIP)
Plastic Leaded Chip Carrier (PLCC)
JC [°C/W]
35
90
35
90
JA [°C/W](2)
JC [°C/W]
JA [°C/W](2)
90
Thin Plastic Quad Flat Package
(TQFP)
JC [°C/W]
JA [°C/W](2)
–
–
–
–
15
50
Plastic Leaded Chip Carrier (PLCC)
Notes: 1. For more information refer to the “Thermal Characteristics of Atmel’s Packages”, available on the Atmel web site.
2. Airflow = 0 ft/min.
12
AT17LV65A/128A/256A/512A/002A
2322G–CNFG–03/06
AT17LV65A/128A/256A/512A/002A
22. Ordering Information
Figure 22-1. Ordering Code(1)
AT17LV65A-10PC
Vo l t ag e
Size (Bits)
Special Pinouts
= Altera
Package
Te mperature
C = Commercial
I = Industrial
3.3V Nominal to
5V Nominal
P
J
65
= 65K
= 128K
= 256K
= 512K
= 1M
A
= 8P3
= 20J
= 32A
128
256
512
010
002
Blank = Xilinx/Atmel/
Other
Q
U = Fully Green
= 2M
Note:
1. The 8-lead LAP and SOIC packages for the AT17LV65A/128A/256A do not have an A label. However, the 8-lead packages
are pin compatible with the 8-lead package of Altera’s EEPROMs, refer to the AT17LV65/128/256/512/010/002/040
datasheet available on the Atmel web site for more information.
Package Type
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
20-lead, Plastic J-leaded Chip Carrier (PLCC)
8P3
20J
32A
32-lead, Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP)
13
2322G–CNFG–03/06
22.1 Standard Package Options(1)
Memory Size
Ordering Code
Package
Operation Range
Commercial
AT17LV65A-10JC
AT17LV65A-10JI
AT17LV128A-10JC
AT17LV128A-10JI
AT17LV256A-10JC
AT17LV256A-10JI
20J
(0°C to 70°C)
64-Kbit(2)(7)
Industrial
20J
20J
20J
20J
20J
(-40°C to 85°C)
Commercial
(0°C to 70°C)
128-Kbit(7)
256-Kbit(3)(7)
512-Kbit(4)(7)
Industrial
(-40°C to 85°C)
Commercial
(0°C to 70°C)
Industrial
(-40°C to 85°C)
Commercial
AT17LV512A-10PC
AT17LV512A-10JC
8P3
20J
(0°C to 70°C)
Industrial
AT17LV512A-10PI
AT17LV512A-10JI
8P3
20J
(-40°C to 85°C)
AT17LV010A-10PC
AT17LV010A-10JC
AT17LV010A-10QC
8P3
20J
32A
Commercial
(0°C to 70°C)
1-Mbit(5)(7)
AT17LV010A-10PI
AT17LV010A-10JI
AT17LV010A-10QI
8P3
20J
32A
Industrial
(-40°C to 85°C)
Commercial
AT17LV002A-10JC
AT17LV002A-10QC
20J
32A
(0°C to 70°C)
2-Mbit(6)(7)
Industrial
AT17LV002A-10JI
AT17LV002A-10QI
20J
32A
(-40°C to 85°C)
22.2 Green Package Options (Pb/Halide-free/RoHS Compliant)(1)
Memory Size
Ordering Code
Package
Operation Range
Industrial
512-Kbit(4)(7)
AT17LV512A-10JU
20J
(-40°C to 85°C)
AT17LV010A-10JU
AT17LV010A-10PU
20J
Industrial
1-Mbit(5)(7)
2-Mbit(4)(7)
8P3
(-40°C to 85°C)
Industrial
AT17LV002A-10JU
20J
(-40°C to 85°C)
Notes: 1. Currently, there are two types of low-density configurators. The new version will be identified by a “B” after the datacode. The
“B” version is fully backward-compatible with the original devices so existing customers will not be affected. The new parts
no longer require a MUX for ISP. See programming specification for more details.
2. Use 64-Kbit density parts to replace Altera EPC1064.
3. Use 256-Kbit density parts to replace Altera EPC1213.
4. Use 512-Kbit density parts to replace Altera EPC1441.
5. Use 1-Mbit density parts to replace Altera EPC1
6. Use 2-Mbit density parts to replace Altera EPC2. Atmel AT17LV002A devices do not support JTAG programming; Atmel
AT17LV002A devices use a 2-wire serial interface for in-system programming.
7. For operating voltage of 5V 10%, please refer to the 5V 10% AC and DC Characteristics.
14
AT17LV65A/128A/256A/512A/002A
2322G–CNFG–03/06
AT17LV65A/128A/256A/512A/002A
23. Packaging Information
23.1 8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
MAX
NOM
NOTE
SYMBOL
D1
A2 A
A
0.210
0.195
0.022
0.070
0.045
0.014
0.400
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.325
0.280
b
E1
e
0.100 BSC
0.300 BSC
0.130
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
15
2322G–CNFG–03/06
23.2 20J – PLCC
PIN NO. 1
1.14(0.045) X 45˚
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
e
E1
E
D2/E2
B1
B
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
4.191
2.286
0.508
9.779
8.890
9.779
8.890
7.366
0.660
0.330
MAX
4.572
3.048
–
NOM
NOTE
SYMBOL
A
A1
A2
D
–
–
–
–
10.033
D1
E
–
9.042 Note 2
10.033
–
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AA.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
E1
D2/E2
B
–
9.042 Note 2
8.382
–
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC)
20J
B
R
16
AT17LV65A/128A/256A/512A/002A
2322G–CNFG–03/06
AT17LV65A/128A/256A/512A/002A
23.3 32A – TQFP
PIN 1
B
PIN 1 IDENTIFIER
E1
E
e
D1
D
C
0˚~7˚
A2
A
A1
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
0.15
1.05
9.25
7.10
9.25
7.10
0.45
0.20
0.75
NOM
NOTE
SYMBOL
A
–
–
A1
A2
D
0.05
0.95
8.75
6.90
8.75
6.90
0.30
0.09
0.45
1.00
9.00
7.00
9.00
7.00
–
D1
E
Note 2
Note 2
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ABA.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
E1
B
C
–
3. Lead coplanarity is 0.10 mm maximum.
L
–
e
0.80 TYP
10/5/2001
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
32A
B
R
17
2322G–CNFG–03/06
Atmel Corporation
Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Regional Headquarters
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
Fax: (41) 26-426-5500
Fax: 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel: (33) 2-40-18-18-18
Fax: (33) 2-40-18-19-60
BP 123
38521 Saint-Egreve Cedex, France
Tel: (33) 4-76-58-30-00
Fax: (33) 4-76-58-34-80
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle
13106 Rousset Cedex, France
Tel: (33) 4-42-53-60-00
Fax: (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
Atmel Programmable SLI Hotline
Literature Requests
www.atmel.com/literature
(408) 436-4119
Atmel Programmable SLI e-mail
configurator@atmel.com
FAQ
Available on web site
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-
TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY
WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-
TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT
OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no
representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications
and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided
otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use
as components in applications intended to support or sustain life.
© Atmel Corporation 2006. All rights reserved. Atmel®, logo and combinations thereof, Everywhere You Are®
and others, are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and
product names may be trademarks of others.
Printed on recycled paper.
2322G–CNFG–03/06
相关型号：
©2020 ICPDF网 联系我们和版权申明