AT17LV002-10TQU [MICROCHIP]
IC FPGA EEPROM 2M 10MHZ 44TQFP;
| 型号： | AT17LV002-10TQU |
| 厂家： | 
MICROCHIP |
| 描述： | IC FPGA EEPROM 2M 10MHZ 44TQFP 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 ATM 异步传输模式 内存集成电路 |
| 文件： | 总23页 (文件大小：670K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AT17LV65(1), AT17LV128(1), AT17LV256,
AT17LV512, AT17LV010, AT17LV002, AT17LV040
FPGA Configuration EEPROM Memory
3.3V and 5.0V System Support
Note 1.
AT17LV65 and AT17LV128
are Not Recommended for
New Designs (NRND) and
are Replaced by AT17LV256.
DATASHEET
Features
EE Programmable Serial Memories Designed to Store Configuration Programs
for Field Programmable Gate Arrays (FPGAs)
̶
̶
̶
65,536 x 1-bit(1)
131,072 x 1-bit(1)
262,144 x 1-bit
̶
̶
524,288 x 1-bit
̶
̶
2,097,152 x 1-bit
4,194,304 x 1-bit
1,048,576 x 1-bit
Supports both 3.3V and 5.0V Operating Voltage Applications
In-System Programmable (ISP) via 2-wire Bus
Simple Interface to SRAM FPGAs
Compatible with the Atmel® AT6000, AT40K and AT94K Devices, Altera®
FLEX®, APEX™ Devices, ORCA®, Xilinx® XC3000, XC4000, XC5200,
Spartan®, Virtex® FPGAs
Cascadable Read-back to Support Additional Configurations or Higher-density
Arrays
Very Low-power CMOS EEPROM Process
Programmable Reset Polarity
Available in 6mm x 6mm x 1mm 8-lead LAP (Pin-compatible with 8-lead SOIC
Package), 8-lead PDIP, 8-lead SOIC, 20-lead PLCC, 20-lead SOIC and
44-lead TQFP Packages
Emulation of the Atmel AT24CXXX Serial EEPROMs
Low-power Standby Mode
High-reliability
̶
̶
Endurance: 100,000 Write Cycles
Data Retention: 90 Years for Industrial Parts (at 85C)
Green (Pb/Halide-free/RoHS Compliant) Package Options Available
Description
The AT17LV FPGA Configuration EEPROMs (Configurators) provide an easy-to-
use, cost-effective configuration memory solution for Field Programmable Gate
Arrays. The AT17LV devices are packaged in the 8-lead LAP, 8-lead PDIP, 8-lead
SOIC, 20-lead PLCC, 20-lead SOIC and 44-lead TQFP options(Table 1). The
AT17LV Configurators use a simple serial-access procedure to configure one or
more FPGA devices. The user can select the polarity of the reset function during
programming. These devices also support a write protection mechanism within its
programming mode.
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
The AT17LV configurators can be programmed with industry-standard programmers, the Atmel ATDH2200E
Programming Kit, or the Atmel ATDH2225 ISP Cable.
Table 1.
AT17LV Packages
AT17LV65/128/256(4)
Package
AT17LV512/010
AT17LV002
AT17LV040
(3)
8-lead LAP
Yes
Yes
Yes
Yes
Yes(2)
—
Yes
Yes
8-lead PDIP
8-lead SOIC
20-lead PLCC
20-lead SOIC
44-lead TQFP
Yes
–
Use 8-lead LAP(1)
Yes
—
(3)
Use 8-lead LAP(1)
Yes
—
—
—
Yes(2)
—
Yes
Yes
Notes: 1. The 8-lead LAP package has the same footprint as the 8-lead SOIC. Since an 8-lead SOIC package is not
available for the AT17LV512/010/002 devices, it is possible to use an 8-lead LAP package instead.
2. The pinout for the AT17LV65 (NRND), AT17LV128 (NRND), and AT17LV256 is not pin-for-pin compatible with
the AT17LV512/010/002 devices.
3. Refer to the AT17F datasheet which is available on the Atmel website.
4. The AT17LV65 and AT17LV128 are not recommended for new designs (NRND).
2
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
1.
Pin Configuration and Descriptions
Table 1-1.
Pin
Pin Descriptions
Description
Three-state Data Output for Configuration. Open-collector bi-directional pin for
programming.
DATA
CLK
Clock Input. Used to increment the internal address and bit counter for reading and
programming.
Write Protect (1). Used to protect portions of memory during programming. Disabled
by default due to internal pull-down resistor. This input pin is not used during FPGA loading
operations. This pin is only available on AT17LV512/010/002 devices.
WP1
RESET (Active Low) / Output Enable (Active High) when SER_EN is High. A Low level on
RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the
data output driver. The logic polarity of this input is programmable as either RESET/OE or
RESET/OE. For most applications, RESET should be programmed active Low. This document
describes the pin as RESET/OE.
RESET/OE
Write Protect Input (when CE is Low) during programming only (SER_EN Low). When WP is
Low, the entire memory can be written. When WP is enabled (High), the lowest block of the
memory cannot be written. This pin is only available on the AT17LV65 (NRND),
AT17LV128 (NRND), and the AT17LV256.
WP
Write Protect (2). Used to protect portions of memory during programming. Disabled
by default due to internal pull-down resistor. This input pin is not used during FPGA loading
operations. This pin is only available on the AT17LV512/010.
WP2
Chip Enable Input (Active Low). A Low level (with OE High) allows CLK to increment the
address counter and enables the data output driver. A High level on CE disables both the
address and bit counters and forces the device into a low-power standby mode. Note that this
pin will not enable/disable the device in the Two-Wire Serial Programming mode (SER_EN
Low).
CE
GND
Ground. A 0.2μF decoupling capacitor between VCC and GND is recommended.
Chip Enable Output (Active Low). This output goes Low when the address counter has
reached its maximum value. In a daisy chain of AT17LV devices, the CEO pin of one device
must be connected to the CE input of the next device in the chain. It will stay Low as long as
CE is Low and OE is High. It will then follow CE until OE goes Low; thereafter, CEO will stay
High until the entire EEPROM is read again. This CEO feature is not available on the
AT17LV65 (NRND).
CEO
Device Selection Input, A2. This is used to enable (or select) the device during programming
(i.e., when SER_EN is Low). A2 has an internal pull-down resistor.
A2
Open Collector Reset State Indicator. Driven Low during power-up reset, released when
power-up is complete. It is recommended to use a 4.7k pull-up resistor when this pin is used.
READY
Serial Enable must be held High during FPGA loading operations. Bringing SER_EN Low
SER_EN
VCC
enables the 2-wire Serial Programming Mode. For non-ISP applications, SER_EN should be
tied to VCC
.
Power Supply. 3.3V (±10%) and 5.0V (±10%) power supply pin.
AT17LV65/128/256/512/010/002/040 [DATASHEET]
3
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
Table 1-2.
Pin Configurations
AT17LV65/128/256(2)
AT17LV512/010
8-lead
AT17LV002
AT17LV040
8-lead
DIP/LAP/ 20-lead 20-lead
DIP/
LAP
20-lead
PLCC
8-lead
LAP
20-lead 20-lead 44-lead
44-lead
TQFP
Name
I/O
SOIC
PLCC
SOIC
PLCC
SOIC
TQFP
DATA
I/O
1
2
2
1
2
–
3
–
4
5
2
4
1
2
–
3
–
4
5
2
1
40
40
43
–
CLK
I
I
I
I
I
2
–
3
–
4
5
4
–
4
–
4
5
3
–
43
7
WP1
5
RESET/OE
WP2
6
6
6
6
8
13
–
13
–
–
–
7
7
–
CE
8
8
8
8
10
11
13
–
15
18
15
18
GND
10
10
10
10
CEO(1)
A2
O
I
6
14
14
6
14
6
14
21
21
READY
SER_EN
VCC
O
I
–
7
8
–
–
–
7
8
15
17
20
–
7
8
15
17
20
–
23
35
38
23
35
38
17
20
17
20
18
20
Notes: 1. The CEO feature is not available on the AT17LV65 (NRND).
2. The AT17LV65 and AT17LV128 are not recommended for new designs.
4
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
Figure 1-1.
Pinouts(1)
8-lead LAP
(Top View)
8-lead JEDEC SOIC
(Top View)
8-lead PDIP
(Top View)
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
DATA
VCC
DATA
VCC
1
2
3
4
8
7
6
5
DATA
VCC
CLK
(WP(2)) RESET/OE
CE
SER_EN
CEO (A2)
GND
CLK
(WP(2)) RESET/OE
CE
SER_EN
CEO (A2)
GND
CLK
(WP(2)) RESET/OE
CE
SER_EN
CEO (A2)
GND
20-lead PLCC
(Top View)
44-lead TQFP
(Top View)
AT17LV002 Only
4
5
6
7
8
18
17
16
15
14
CLK
NC
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
(WP1(3)) NC
(WP1(2)) RESET/OE
(WP2(3)) NC
SER_EN
NC
NC (READY(3)
CEO(4) (A2)
)
CE
(WP1(1)) NC
NC
NC
NC
NC
9
10
11
READY
20-lead SOIC
(Top View)
20-lead SOIC
(Top View)
AT17LV002 Only
AT17LV65/128/256 Only(5)
NC
1
20
19
18
17
16
15
14
13
12
11
VCC
NC
NC
DATA
1
20
19
18
17
16
15
14
13
12
11
VCC
NC
DATA
NC
2
NC
CLK
2
3
3
SER_EN
NC
CLK
4
SER_EN
NC
NC
4
NC
5
NC
5
NC
RESET/OE
NC
6
NC
NC
6
NC
7
CEO (A2)
NC
NC
7
NC
CEO(4)
CE
8
RESET/OE
NC
8
NC
9
NC
9
NC
GND
10
NC
CE
10
GND
Notes: 1. Drawings are not to scale.
2. This pin is only available on the AT17LV65 (NRND), AT17LV128 (NRND), and AT17LV256.
3. This pin is only available on the AT17LV512/010/002.
4. This pin is not available on the AT17LV65 (NRND).
5. The AT17LV65 and AT17LV128 are not recommended for new designs.
AT17LV65/128/256/512/010/002/040 [DATASHEET]
5
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
2.
Block Diagram
Figure 2-1.
Block Diagram
SER_EN
WP1(2)
WP2(2)
Programming
Data Shift
Register
Programming
Mode Logic
Power On
Reset
Row Decoder
EEPROM
Cell Matrix
Column Decoder
TC
CLK READY(2) REST/OE (WP(1)
)
CE
CEO(3) (A2)
DATA
Notes: 1. This pin is only available on the AT17LV65 (NRND), AT17LV128 (NRND), and AT17LV256.
2. This pin is only available on AT17LV512, AT17LV010, and AT17LV002.
3. The CEO feature is not available on the AT17LV65 (NRND).
6
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
3.
Device Description
The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) interface directly with the FPGA
device control signals. All FPGA devices can control the entire configuration process and retrieve data from the
configuration EEPROM without requiring an external intelligent controller.
The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the DATA output pin and
enable the address counter. When RESET/OE is driven High, the configuration EEPROM resets its address
counter and tri-states its DATA pin. The CE pin also controls the output of the AT17LV configurator. If CE is held
High after the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is
subsequently driven Low, the counter and the DATA output pin are enabled. When RESET/OE is driven High
again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven Low, the device tri-states the DATA pin to
avoid contention with other configurators. Upon power-up, the address counter is automatically reset.
This is the default setting for the device. Since almost all FPGAs use RESET Low and OE High, this document
will describe RESET/OE.
4.
5.
FPGA Master Serial Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The
program is loaded either automatically upon power-up, or on command, depending on the state of the FPGA
mode pins. In Master mode, the FPGA automatically loads the configuration program from an external memory.
The AT17LV Serial Configuration EEPROM has been designed for compatibility with the Master Serial mode.
This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as Xilinx applications.
Control of Configuration
Most connections between the FPGA device and the AT17LV Serial EEPROM are simple and self-explanatory.
The DATA output of the AT17LV configurator drives DIN of the FPGA devices.
The master FPGA CCLK output drives the CLK input of the AT17LV configurator.
The CEO output of any AT17LV configurator drives the CE input of the next configurator in a cascaded
chain of EEPROMs.
SER_EN must be connected to VCC (except during ISP).
The READY(1) pin is available as an open-collector indicator of the device’s reset status; it is driven Low
while the device is in its power-on reset cycle and released (tri-stated) when the cycle is complete.
Note: 1. This pin is not available for the AT17LV65 (NRND), AT17LV128 (NRND), and AT17LV256.
AT17LV65/128/256/512/010/002/040 [DATASHEET]
7
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
6.
Cascading Serial Configuration EEPROMs
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration memories,
cascaded configurators provide additional memory.
After the last bit from the first configurator is read, the clock signal to the configurator asserts its CEO output
Low and disables its DATA line driver. The second configurator recognizes the Low level on its CE input and
enables its DATA output.
After configuration is complete, the address counters of all cascaded configurators are reset if the RESET/OE
on each configurator is driven to its active (Low) level.
If the address counters are not to be reset upon completion, then the RESET/OE input can be tied to its inactive
(High) level.
The AT17LV65 (NRND) devices do not have the CEO feature to perform cascaded configurations.
7.
8.
AT17LV Reset Polarity
The AT17LV configurator allows the user to program the reset polarity as either RESET/OE or RESET/OE. This
feature is supported by industry-standard programmer algorithms.
Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can be programmed by the
2-wire serial bus. The programming is done at VCC supply only. Programming super voltages are generated
inside the chip.
9.
Standby Mode
The AT17LV configurators enter a low-power standby mode whenever CE is asserted High. In this mode, the
AT17LV65 (NRND), AT17LV128 (NRND), or the AT17LV256 configurator consumes less than 50μA of current
at 3.3V (100μA for the AT17LV512/010 and 200μA for the AT17LV002/040). The output remains in a high-
impedance state regardless of the state of the OE input.
8
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
10. Electrical Specifications
10.1 Absolute Maximum Ratings*
*Notice: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent
damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions beyond those
listed under operating conditions is not
implied. Exposure to Absolute Maximum
Rating conditions for extended periods of
time may affect device reliability.
Operating Temperature . . . . . . . . . . . . . . . . .-40C to +85C
Storage Temperature . . . . . . . . . . . . . . . . . .-65C to +150C
Voltage on Any Pin
with Respect to Ground . . . . . . . . . . . . . .-0.1V to VCC +0.5V
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Maximum Soldering Temp. (10s @ 1/16 in.) . . . . . . . .260C
ESD (RZAP = 1.5K, CZAP = 100pF) . . . . . . . . . . . . . . . .2000V
10.2 Operating Conditions
Table 10-1.
Operating Conditions
3.3V
5.0V
Symbol Description
Industrial
Min
Max
Min
Max
Units
Supply voltage relative to GND
-40C to +85C
3.0
3.6
4.5
5.5
V
VCC
10.3 DC Characteristics
Table 10-2.
DC Characteristics for VCC = 3.3V ± 10%
AT17LV65/128/256(1)
AT17LV512/010
AT17LV002/40
Symbol
Description
Min
Max
Min
Max
Min
Max
Units
VIH
High-level Input Voltage
2.0
VCC
2.0
VCC
2.0
VCC
V
VIL
Low-level Input Voltage
0
0.8
0
0.8
0
0.8
V
V
High-level Output Voltage
(IOH = -2mA)
VOH
2.4
2.4
2.4
Low-level Output Voltage
(IOL = +3mA)
VOL
ICCA
IL
0.4
5
0.4
5
0.4
5
V
Supply Current, Active Mode
mA
μA
μA
Input or Output Leakage Current
(VIN = VCC or GND)
-10
10
100
-10
10
100
-10
10
150
ICCS
Supply Current, Standby Mode
Note:
1. The AT17LV65 and AT17LV128 are not recommended for new designs.
AT17LV65/128/256/512/010/002/040 [DATASHEET]
9
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
Table 10-3.
DC Characteristics for VCC = 5.0V ± 10%
AT17LV65/128/256(1)
AT17LV512/010 AT17LV002/040
Symbol
VIH
Description
Min
2.0
0
Max
VCC
0.8
Min
2.0
0
Max
VCC
0.8
Min
2.0
0
Max
VCC
0.8
Units
High-level Input Voltage
Low-level Input Voltage
V
V
VIL
High-level Output Voltage
(IOH = -2mA)
VOH
3.60
3.76
3.76
V
Low-level Output Voltage
(IOL = +3mA)
VOL
ICCA
IL
0.37
10
0.37
10
0.37
10
V
Supply Current, Active Mode
mA
μA
μA
Input or Output Leakage Current
(VIN = VCC or GND)
-10
10
-10
10
-10
10
ICCS
Supply Current, Standby Mode
150
200
350
Note:
1. The AT17LV65 and AT17LV128 are not recommended for new designs.
10.4 AC Characteristics
Table 10-4.
AC Characteristics for VCC = 3.3V ± 10%
AT17LV65/128/256(3)
AT17LV512/010/002/040
Symbol
Description
Min
Max
55
Min
Max
55
Units
ns
(1)
TOE
OE to Data Delay
(1)
TCE
CE to Data Delay
60
60
ns
(1)
TCAC
CLK to Data Delay
Data Hold from CE, OE, or CLK
CE or OE to Data Float Delay
CLK Low Time
80
60
ns
TOH
0
0
ns
(2)
TDF
55
50
ns
TLC
THC
25
25
25
25
ns
CLK High Time
ns
CE Setup Time to CLK
(to guarantee proper counting)
TSCE
60
0
35
0
ns
ns
CE Hold Time from CLK
(to guarantee proper counting)
THCE
OE High Time
(guarantees counter is reset)
THOE
FMAX
25
25
ns
Maximum Clock Frequency
10
10
MHz
Notes: 1. AC test lead = 50pF.
2. Float delays are measured with 5pF AC loads. Transition is measured ± 200mV from steady-state active levels.
3. The AT17LV65 and AT17LV128 are not recommended for new designs.
10
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
Table 10-5.
Symbol
AC Characteristics when Cascading for VCC = 3.3V ± 10%
AT17LV65/128/256(3)
AT17LV512/010/002/040
Description
Min
Max
60
60
60
45
8
Min
Max
50
Units
ns
(2)
TCDF
CLK to Data Float Delay
CLK to CEO Delay
(1)
TOCK
55
ns
(1)
TOCE
CE to CEO Delay
40
ns
(1)
TOOE
RESET/OE to CEO Delay
Maximum Clock Frequency
35
ns
FMAX
10
MHz
Notes: 1. AC test lead = 50pF.
2. Float delays are measured with 5pF AC loads. Transition is measured ± 200mV from steady-state active levels.
3. The AT17LV65 and AT17LV128 are not recommended for new designs.
Table 10-6.
AC Characteristics for VCC = 5V ± 10%
AT17LV65/128/256(3)
AT17LV512/010/002/040
Symbol
Description
Min
Max
35
Min
Max
35
Units
ns
(1)
TOE
OE to Data Delay
(1)
TCE
CE to Data Delay
45
45
ns
(1)
TCAC
CLK to Data Delay
Data Hold from CE, OE, or CLK
CE or OE to Data Float Delay
CLK Low Time
55
50
ns
TOH
0
0
ns
(2)
TDF
50
50
ns
TLC
THC
20
20
20
20
ns
CLK High Time
ns
CE Setup Time to CLK
(To Guarantee Proper Counting)
TSCE
40
0
25
0
ns
ns
CE Hold Time from CLK
(To Guarantee Proper Counting)
THCE
OE High Time
(Guarantees Counter is Reset)
THOE
FMAX
20
20
ns
Maximum Clock Frequency
12.5
15
MHz
Notes: 1. AC test lead = 50pF.
2. Float delays are measured with 5pF AC loads. Transition is measured ± 200mV from steady-state active levels.
3. The AT17LV65 and AT17LV128 are not recommended for new designs.
AT17LV65/128/256/512/010/002/040 [DATASHEET]
11
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
Table 10-7.
Symbol
AC Characteristics When Cascading for VCC = 5V ± 10%
AT17LV65/128/256(3)
AT17LV512/010/002/040
Description
Min
Max
50
Min
Max
50
Units
ns
(2)
TCDF
CLK to Data Float Delay
CLK to CEO Delay
(1)
TOCK
40
40
ns
(1)
TOCE
CE to CEO Delay
35
35
ns
(1)
TOOE
RESET/OE to CEO Delay
Maximum Clock Frequency
35
30
ns
FMAX
10
12.5
MHz
Notes: 1. AC test lead = 50pF.
2. Float delays are measured with 5pF AC loads. Transition is measured ± 200mV from steady-state active levels.
3. The AT17LV65 and AT17LV128 are not recommended for new designs.
Figure 10-1. AC Waveforms
CE
RESET/OE
CLK
TSCE
THCE
TSCE
THOE
TLC
THC
TOH
TOE
TCAC
TDF
TCE
DATA
TOH
Figure 10-2. AC Waveforms when Cascading
RESET/OE
CE
CLK
TCDF
FIRST BIT
LAST BIT
DATA
TOCK
TOCE
TOOE
CEO
TOCE
12
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
10.5 Thermal Resistance Coefficients
Table 10-8.
Thermal Resistance Coefficients
Package Type
AT17LV65/128/256(2) AT17LV512/010 AT17LV002 AT17LV040
JC [C/W]
JA [C/W](1)
JC [C/W]
JA [C/W](1)
JC [C/W]
JA [C/W](1)
JC [C/W]
JA [C/W](1)
JC [C/W]
JA [C/W](1)
JC [C/W]
JA [C/W](1)
45
115.71
37
45
135.71
37
45
159.60
—
—
—
—
—
—
—
—
—
—
—
17
62
Leadless Array
Package (LAP)
8CN4
8P3
Plastic Dual Inline
Package (PDIP)
107
45
107
—
—
—
Plastic Gull Wing
Small Outline (SOIC)
8S1
150
35
—
—
35
35
Plastic Leaded Chip
Carrier (PLCC)
20J
90
90
90
Plastic Gull Wing
Small Outline (SOIC)
20S2
44A
—
—
—
—
17
62
Thin Plastic Quad
Flat Package (TQFP)
Notes: 1. Airflow = 0ft/min.
2. The AT17LV65 and AT17LV128 are not recommended for new designs.
AT17LV65/128/256/512/010/002/040 [DATASHEET]
13
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
11. Ordering Information
11.1 Ordering Code Detail
A T 1 7 L V 2 5 6 A - 1 0 P U
Package Device Grade
Atmel Designator
U
= Green, Industrial
Temperature Range
(-40°C to +85°C)
Product Family
17LV = FPGA EEPROM
Configuration Memory
Package Option
Device Density
C
P
N
J
= 8CN4, 8-lead LAP
= 8P3, 8-lead PDIP
65 = 64 kilobit
128 = 128 kilobit
256 = 256 kilobit
512 = 512 kilobit
010 = 1 Mbit
= 8S1, 8-lead JEDEC SOIC
= 20J, 20-lead PLCC
S
= 20S2, 20-lead JEDEC SOIC
TQ = 44A, 44-lead TQFP
002 = 2 Mbit
040 = 4 Mbit
Special Pinouts
Product Variation
10 = Default Value
A = Altera
Blank = Xilinx/Atmel/Other
14
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
11.2 Ordering Information
Memory Size
Atmel Ordering Code
Lead Finish
Package
Voltage
Operation Range
CuNiAu
(Lead-free/Halogen-free)
AT17LV256-10CU
8CN4
AT17LV256-10JU
AT17LV256-10NU
AT17LV256-10PU
AT17LV256-10SU
20J
8S1
Industrial
(-40C to 85C)
256-Kbit
3.0V to 5.5V
Sn
(Lead-free/Halogen-free)
8P3
20S2
CuNiAu
(Lead-free/Halogen-free)
AT17LV512-10CU
AT17LV512-10JU
8CN4
20J
Industrial
(-40C to 85C)
512-Kbit
1-Mbit
3.0V to 5.5V
3.0V to 5.5V
Sn
(Lead-free/Halogen-free)
CuNiAu
(Lead-free/Halogen-free)
AT17LV010-10CU
8CN4
Industrial
(-40C to 85C)
AT17LV010-10JU
AT17LV010-10PU
20J
Sn
(Lead-free/Halogen-free)
8P3
CuNiAu
(Lead-free/Halogen-free)
AT17LV002-10CU
8CN4
Industrial
(-40C to 85C)
AT17LV002-10JU
AT17LV002-10SU
AT17LV002-10TQU
20J
20S2
44A
2-Mbit
4-Mbit
3.0V to 5.5V
3.0V to 5.5V
Sn
(Lead-free/Halogen-free)
Sn
Industrial
(-40C to 85C)
AT17LV040-10TQU
44A
(Lead-free/Halogen-free)
Package Type
8CN4
8P3
8-lead, 6mm x 6mm x 1mm, Leadless Array Package (LAP) (Pin-compatible with 8-lead SOIC Packages)
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
20-lead, Plastic J-leaded Chip Carrier (PLCC)
20J
20S2
44A
20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
44-lead, Thin (1.0mm) Plastic Quad Flat Package Carrier (TQFP)
AT17LV65/128/256/512/010/002/040 [DATASHEET]
15
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
12. Packaging Information
12.1 8CN4 – LAP
Marked Pin1 Indentifier
E
A
A1
D
Side View
Top View
Pin1 Corner
L1
0.10 mm
TYP
8
7
1
COMMON DIMENSIONS
(Unit of Measure = mm)
e
2
3
MIN
0.94
0.30
0.45
5.89
5.89
MAX
1.14
0.38
0.55
6.09
6.09
NOM
1.04
NOTE
1
SYMBOL
A
A1
b
0.34
6
5
0.50
b
D
5.99
4
E
5.99
e
1.27 BSC
1.10 REF
1.00
e1
L
e1
L
0.95
1.25
1.05
1.35
1
1
Bottom View
L1
1.30
Note: 1. Metal Pad Dimensions.
2. All exposed metal area shall have the following finished platings.
Ni: 0.0005 to 0.015 mm
Au: 0.0005 to 0.001 mm
2/15/08
GPC
DMH
DRAWING NO.
TITLE
REV.
8CN4, 8-lead (6 x 6 x 1.04 mm Body),
Package Drawing Contact:
packagedrawings@atmel.com
8CN4
D
Lead Pitch 1.27mm,
Leadless Array Package (LAP)
16
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
12.2 8P3 – PDIP
E
1
E1
.381
Gage Plane
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
D
e
MIN
MAX
5.334
-
NOM
-
NOTE
SYMBOL
D1
A2 A
A
-
2
A1
A2
b
0.381
2.921
0.356
1.143
0.762
0.203
9.017
0.127
7.620
6.096
-
3.302
0.457
1.524
0.991
0.254
9.271
0.000
7.874
6.350
2.540 BSC
7.620 BSC
3.302
4.953
0.559
1.778
1.143
0.356
10.160
0.000
8.255
7.112
5
6
6
b2
b3
c
A1
b2
D
3
3
4
3
L
b3
D1
E
m
b
4 PLCS
0.254
C
v
E1
e
Side View
eA
L
4
2
2.921
3.810
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
07/31/14
REV.
TITLE
GPC
PTC
DRAWING NO.
8P3
8P3, 8-lead, 0.300” Wide Body, Plastic Dual
In-line Package (PDIP)
E
Package Drawing Contact:
packagedrawings@atmel.com
AT17LV65/128/256/512/010/002/040 [DATASHEET]
17
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
12.3 8S1 – SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.35
0.10
MAX
1.75
0.25
NOM
–
–
NOTE
SYMBOL
A1
A
A1
b
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.05
3.99
6.20
C
D
E1
E
e
–
–
D
–
–
SIDE VIEW
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
1.27 BSC
L
0.40
0°
–
–
1.27
8°
Ø
6/22/11
DRAWING NO. REV.
8S1
TITLE
GPC
8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
SWB
G
Package Drawing Contact:
packagedrawings@atmel.com
18
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
12.4 20J – PLCC
PIN NO. 1
1.14(0.045) X 45°
1.14(0.045) X 45°
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
e
E1
E
D2/E2
B1
B
A2
A1
D1
D
A
0.51(0.020)MAX
45° MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
4.191
2.286
0.508
9.779
8.890
9.779
8.890
7.366
0.660
0.330
MAX
4.572
3.048
–
NOM
NOTE
SYMBOL
A
A1
A2
D
–
–
–
–
10.033
D1
E
–
9.042 Note 2
10.033
–
Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
E1
D2/E2
B
–
9.042 Note 2
8.382
–
–
–
0.813
3. Lead coplanarity is 0.004" (0.102mm) maximum
B1
e
0.533
1.270 TYP
10/04/01
DRAWING NO. REV.
20J
TITLE
Package Drawing Contact:
packagedrawings@atmel.com
20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC)
B
AT17LV65/128/256/512/010/002/040 [DATASHEET]
19
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
12.5 20S2 – SOIC
C
1
10
E
E1
E1
11
20
TOP VIEW
L
A2
e
b
END VIEW
A1
A
D
SIDE VIEW
Notes:
1. This drawing is for general information only. Refer to JEDEC Drawing
MS-013, Variation AC, for proper dimensions, tolerances, datums, etc.
2. Dimension D does not include mold flash, protrusions or gate burrs. Mold
flash, protrustions or gate burrs shall not exceed 0.15 mm per end.
Diminsion E1 does not include interlead flash or protursion. Interlead flash
or protrusion shall not exceed 0.25 mm per side.
3. The package top may be smaller than the package bottom. Dimensions D
and E1 are determinded at the outermost extremes of the plastic body
exclusive of mold flash, the bar burrs, gate burrs and interlead flash, but
including any mismatch between the top and bottom of the plastic body.
4. The dimensions apply to the flat section of the lead between 0.10 to
0.25 mm from the lead tip.
5. Dimension ‘b’ does not include the dambar protrusion. Allowable dambar
protrusion shall be 0.10 mm total in excess of the ‘b’ dimension at maximum
material condition. The dambar may not be located on the lower radius of
the foot.
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D
E1
E
12.80 BSC
2,3
2,3
7.50 BSC
10.30 BSC
A
-
-
2.65
0.30
-
A1
A2
e
0.10
2.05
-
6
-
1.27 BSC
b
0.31
0.40
0.20
-
-
-
0.51
1.27
0.33
4,5
4
L
6. ‘A1’ is defined as the vertical distance from the seating plane to the lowest
point on the package body excluding the lid or thermal enhancement on the
cavity down package configuration.
C
7/1/14
TITLE
DRAWING NO.
REV.
GPC
20S2, 20-lead, 0.300” Wide Body, Plastic
Gull Wing Small Outline Package (SOIC)
SRJ
20S2
E
Package Drawing Contact:
packagedrawings@atmel.com
20
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
12.6 44A – TQFP
D1
D
e
E
E1
b
BOTTOM VIEW
TOP VIEW
SIDE VIEW
C
0°~7°
A2
A1
A
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
NOM
NOTE
SYMBOL
A
–
–
A1
A2
D
0.05
0.95
11.75
9.90
11.75
9.90
0.30
0.09
0.45
0.15
1.00
12.00
10.00
12.00
10.00
–
1.05
12.25
D1
E
10.10 Note 2
12.25
E1
B
10.10 Note 2
0.45
Notes:
1. This package conforms to JEDEC reference MS-026,
Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion.
C
–
0.20
Allowable protrusion is 0.25 mm per side. Dimensions D1
and E1 are maximum plastic body size dimensions including
mold mismatch.
L
–
0.75
e
0.80 TYP
3. Lead coplanarity is 0.10 mm maximum.
1/10/13
TITLE
DRAWING NO.
REV.
GPC
AIX
44A, 44-lead 10.0 x 10.0x1.0 mm Body, 0.80 mm
Lead Pitch, Thin Profile Plastic Quad Flat
Package (TQFP)
44A
D
Package Drawing Contact:
packagedrawings@atmel.com
AT17LV65/128/256/512/010/002/040 [DATASHEET]
21
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
13. Revision History
Rev. No.
Date
History
The AT17LV65 and AT17LV128 are not recommended for new designs.
Removed the commercial options.
2321J
10/2014
Updated the 8P3, 8S1, 20S2, and 44A package outline drawings, ordering code details,
ordering code table, document’s template, Atmel logos, disclaimer page.
2321I
02/2008
03/2006
Removed -10SC, 10SI, -10TQC, -10TQI, -10BJC and -10BJI devices from ordering information.
Added last-time buy for AT17LVXXX-10CC and AT17LVXXX-10CI.
2321H
22
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
X X
X X X X
Atmel Corporation
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© 2014 Atmel Corporation. / Rev.: Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014.
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