AT17LV002A [ATMEL]
FPGA Configuration EEPROM Memory; FPGA配置EEPROM存储器
| 型号： | AT17LV002A |
| 厂家： | 
ATMEL |
| 描述： | FPGA Configuration EEPROM Memory |
| 文件： | 总14页 (文件大小：233K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Serial EEPROM Family for Configuring FLEX® Devices
• Simple Interface to SRAM FPGAs
• EE Programmable 2-Mbit Serial Memories Designed to Store Configuration Programs
for Field Programmable Gate Arrays (FPGAs)
• Cascadable Read Back to Support Additional Configurations or Future Higher-density
Arrays
• Low-power CMOS EEPROM Process
• Programmable Reset Polarity
• Available in the Space-efficient Surface-mount PLCC Package
• In-System Programmable via 2-wire Bus
FPGA
• Emulation of Atmel’s AT24CXXX Serial EEPROMs
• Available in 3.3V 5% LV and 5V 5% C Versions
• System-friendly READY Pin
Configuration
EEPROM
Memory
2-megabit
• Replacement for AT17C/LV002A
Description
The AT17C002A and AT17LV002A (high-density AT17A Series) FPGA Configuration
EEPROMs (configurators) provide an easy-to-use, cost-effective configuration mem-
ory for programming Altera FLEX devices. The AT17A Series is packaged in the
popular 20-lead PLCC and the 32-lead TQFP. The AT17A Series family uses a simple
serial-access procedure to configure one or more FPGA devices. The AT17A Series
organization supplies enough memory to configure one or multiple smaller FPGAs.
Using a feature of the AT17A Series, the user can select the polarity of the reset func-
tion by programming internal EEPROM bytes. The AT17A parts generate their own
internal clock and can be used as a system “master” for loading the FPGA devices.
Altera Pinout
AT17C002A
AT17LV002A
The Atmel devices also support a system-friendly READY pin. The READY pin is used
to simplify system power-up considerations.
The AT17A Series Configurators can be programmed with industry-standard program-
mers or Atmel’s ATDH2200E Programming Kit.
Rev. 2280B–08/01
Pin Configuration
32-lead TQFP
20-lead PLCC
24 NC
NC
DCLK
NC
1
2
3
4
5
6
7
8
DCLK
WP1
NC
4
5
6
7
8
18 SER_EN
23 SER_EN
22 NC
17 NC
21 NC
WP1
NC
16 NC
20 READY
19 NC
NC
15 READY
14 NC
NC
OE
18 NC
OE
17 NC
NC
Block Diagram
SER_EN
WP1
PROGRAMMING
DATA SHIFT
REGISTER
PROGRAMMING
MODE LOGIC
OSC
CONTROL
ROW
ADDRESS
COUNTER
EEPROM
CELL
MATRIX
ROW
DECODER
OSC
BIT
COUNTER
COLUMN
DECODER
POWER-ON
RESET
TC
DCLK READY
OE
nCS
nCASC (A2)
DATA
2
AT17C/LV002A
2280B–08/01
AT17C/LV002A
Device
Configuration
The control signals for the configuration EEPROM (nCS, OE and DCLK) interface directly with
the FPGA device control signals. All FPGA devices can control the entire configuration pro-
cess and retrieve data from the configuration EEPROM without requiring an external intelligent
controller.
The configuration EEPROM’s OE and nCS pins control the tri-state buffer on the DATA output
pin and enable the address counter and the oscillator. When OE is driven Low, the configura-
tion EEPROM resets its address counter and tri-states its DATA pin. The nCS pin also
controls the output of the AT17A Series Configurator. If nCS is held High after the OE reset
pulse, the counter is disabled and the DATA output pin is tri-stated. When nCS is driven Low,
the counter and the DATA output pin are enabled. When OE is driven Low again, the address
counter is reset and the DATA output pin is tri-stated, regardless of the state of the nCS.
When the Configurator has driven out all of its data and nCASC is driven Low, the device tri-
states the DATA pin to avoid contention with other Configurators. Upon power-up, the address
counter is automatically reset.
The READY pin is available as an open-collector indicator of the device’s reset status; it is
driven Low while the device is in its power-on reset cycle and released (tri-stated) when the
cycle is complete.
This document discusses the EPF10K device interface. For more details or information on
other Altera applications, please reference the “AT17A Series Conversions from Altera FPGA
Serial Configuration Memories” application note.
FPGA Device
Configuration
FPGA devices can be configured with an AT17A Series EEPROM (see Figure 1). The AT17A
Series device stores configuration data in its EEPROM array and clocks the data out serially
with its internal oscillator. The OE, nCS and DCLK pins supply the control signals for the
address counter and the output tri-state buffer. The AT17A Series device sends a serial bit-
stream of configuration data to its DATA pin, which is connected to the DATA0 input pin on the
FPGA device.
When the configuration data for an FPGA device exceeds the capacity of a single AT17A
Series device, multiple AT17A Series devices can be serially linked together (see Figure 2).
When multiple AT17A Series devices are required, the nCASC and nCS pins provide hand-
shaking between the cascaded EEPROMs.
The position of an AT17A Series device in a chain determines its operation. The first AT17A
Series device in a configurator chain is powered up or reset with nCS Low and is configured
for the FPGA device’s protocol. This AT17A Series device supplies all clock pulses to one or
more FPGA devices and to any downstream AT17A Series Configurator during configuration.
The first AT17A Series Configurator also provides the first stream of data to the FPGA devices
during multi-device configuration. Once the first AT17A Series device finishes sending config-
uration data, it drives its nCASC pin Low, which drives the nCS pin of the second AT17A
Series device Low. This activates the second AT17A Series device to send configuration data
to the FPGA device.
3
2280B–08/01
Figure 1. Configuration with a Single AT17A Series Configurator(1)(2)(3)
V
V
CC
CC
V
CC
1 k
1 k
V
CC
1 k
AT17C512A/010A/020A/002A
AT17LV512A/010A/020A/002A
EPF6K/EPF10K
DCLK
DCLK
nCONFIG
SER_EN
0.1
F
DATA
nCS
DATA0
CONF_DONE
nSTATUS
nCE
OE
MSEL0
MSEL1
READY
GND
Notes: 1. Use of the READY pin is optional.
2. Introducing an RC delay to the input of nCONFIG is recommended to ensure that VCC (5V/3.3V) is reached before
configuration begins. (nCONFIG can instead be connected to an active Low system reset signal.)
3. Reset polarity of EEPROM must be set active Low (OE active High).
Figure 2. Configuration with Multiple AT17A Series Configurators(1)(2)(3)
V
V
CC
CC
1 k
1 k
AT17C512A/010A/020A/002A AT17C512A/010A/020A/002A
AT17LV512A/010A/020A/002A AT17LV512A/010A/020A/002A
V
1 k
CC
DEVICE 1
DEVICE 2
EPF10K
DCLK
DCLK
DCLK
nCONFIG
SER_EN
0.1
F
DATA
DATA
nCS
OE
DATA0
nCE CONF_DONE
nCS nCASC
OE
MSEL0
MSEL1
nSTATUS
READY
GND
Notes: 1. Use of the READY pin is optional.
2. Introducing an RC delay to the input of nCONFIG is recommended to ensure that VCC (5V/3.3V) is reached before
configuration begins. (nCONFIG can instead be connected to an active Low system reset signal.)
3. Reset polarity of EEPROM must be set active Low (OE active High).
4
AT17C/LV002A
2280B–08/01
AT17C/LV002A
The READY pin is available as an open-collector indicator of the device’s reset status; it is
driven Low while the device is in its power-on reset cycle and released (tri-stated) when the
cycle is complete. It can be used to hold the FPGA device in reset while it is completing its
power-on reset but it cannot be used to effectively delay configuration (i.e., the output is
released well before the system VCC has stabilized).
The first AT17A Series device clocks all subsequent AT17A Series devices until configuration
is complete. Once all configuration data is transferred and nCS on the first AT17A Series
device is driven High by CONF_DONE on the FPGA devices, the first AT17A Series device
clocks 16 additional cycles to initialize the FPGA device before going into zero-power (idle)
state. If nCS on the first AT17A Series device is driven High before all configuration data is
transferred – or if the nCS is not driven High after all configuration data is transferred – nSTA-
TUS is driven Low, indicating a configuration error.
AT17A Series
Reset Polarity
The AT17A Series Configurator allows the user to program the polarity of the OE pin as either
RESET/OE or RESET/OE. For more details, please reference the “Programming Specification
for Atmel’s FPGA Configuration EEPROMs” application note.
Programming
Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can be
programmed by the 2-wire serial interface. The programming is done at VCC supply only. Pro-
gramming supervoltages are generated inside the chip. See the “Programming Specification
for Atmel’s Configuration EEPROMs” application note for further information. The AT17 A-
series parts are read/write at 5V nominal. The AT17LV A-series parts are read/write at 3.3V
nominal.
Standby Mode
The AT17A Series Configurator enters a low-power standby mode whenever nCS is asserted
High. In this mode, the configuration consumes less than 0.5 mA of current at 5V. The output
remains in a high-impedance state regardless of the state of the OE input.
5
2280B–08/01
Pin Configurations
20
PLCC
Pin
32
TQFP
Pin
Name
DATA
DCLK
I/O Description
2
4
31
2
I/O Three-state data output for configuration. Open-collector bi-directional pin for programming.
I/O Clock output or clock input. Rising edges on DCLK increment the internal address counter
and present the next bit of data to the DATA pin. The counter is incremented only if the OE
input is held High, the nCS input is held Low, and all configuration data has not been
transferred to the target device (otherwise, as the master device, the DCLK pin drives Low).
5
8
4
7
WP1
OE
I
WRITE PROTECT (1). Used to protect portions of memory during programming. Disabled by
default due to internal pull-down resistor. This input pin is not used during FPGA loading
operations. See the “Programming Specification for Atmel’s Configuration EEPROMs”
application note for more details.
I
Output enable (active High) and reset (active Low) when SER_EN is High. A Low logic level
resets the address counter. A High logic level (with nCS Low) enables DATA and permits the
address counter to count. In the mode, if this pin is Low (reset), the internal oscillator
becomes inactive and DCLK drives Low. The logic polarity of this input is programmable and
must be programmed active High (RESET active Low) by the user during programming for
Altera applications.
9
10
nCS
I
Chip select input (active Low). A Low input (with OE High) allows DCLK to increment the
address counter and enables DATA to drive out. If the AT17A Series is reset with nCS Low,
the device initializes as the first (and master) device in a daisy chain. If the AT17A Series is
reset with nCS High, the device initializes as a subsequent AT17A Series device in the chain.
10
12
12
15
GND
Ground pin. A 0.2 µF decoupling capacitor should be placed between the VCC and GND
pins.
nCASC
O
Cascade select output (active Low). This output goes Low when the address counter has
reached its maximum value. In a daisy chain of AT17A Series devices, the nCASC pin of one
device is usually connected to the nCS input pin of the next device in the chain, which
permits DCLK from the master configurator to clock data from a subsequent AT17A Series
device in the chain.
A2
I
Device selection input, A2. This is used to enable (or select) the device during programming,
(i.e., when SER_EN is Low; please refer to the “Programming Specification for Atmel’s
Configuration EEPROMs” application note for more details.)
15
18
20
20
23
27
READY
SER_EN
VCC
O
I
Open collector reset state indicator. Driven Low during power-up reset, released (tri-stated)
when power-up is complete. (Recommend a 4.7 kΩ pull-up on this pin if used.)
Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low
enables the 2-wire serial programming mode.
+3.3V/+5V power supply pin
6
AT17C/LV002A
2280B–08/01
AT17C/LV002A
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent dam-
age to the device. These are stress ratings only,
and functional operation of the device at these or
any other conditions beyond those listed under
Operating Conditions is not implied. Exposure to
Absolute Maximum Ratings conditions for
extended periods of time may affect device
reliability.
Operating Temperature.................................. -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground..............................-0.1V to VCC +0.5V
Supply Voltage (VCC) .........................................-0.5V to +7.0V
Maximum Soldering Temp. (10 sec @ 1/16 in.)..............260°C
Operating Conditions
AT17C002A
AT17LV002A
Symbol Description
Min
Max
Min
Max
Units
Commercial
Industrial
Military
Supply voltage relative to GND
-0°C to +70°C
4.75
5.25
3.15
3.45
V
Supply voltage relative to GND
-40°C to +85°C
4.5
5.5
5.5
3.15
3.15
3.45
3.45
VCC
V
V
Supply voltage relative to GND
-55°C to +125°C
4.5
7
2280B–08/01
DC Characteristics
VCC = 5V 5% Commercial/5V 10% Industry/Military
Symbol
VIH
Description
Min
2.0
Max
VCC
0.8
Units
V
High-level Input Voltage
VIL
Low-level Input Voltage
0.0
V
VOH
VOL
VOH
VOL
VOH
VOL
ICCA
IL
High-level Output Voltage (IOH = -4 mA)
Low-level Output Voltage (IOL = +4 mA)
High-level Output Voltage (IOH = -4 mA)
Low-level Output Voltage (IOL = +4 mA)
High-level Output Voltage (IOH = -4 mA)
Low-level Output Voltage (IOL = +4 mA)
Supply Current, Active Mode (at FMAX)
Input or Output Leakage Current (VIN = VCC or GND)
3.86
V
Commercial
Industrial
Military
0.32
0.37
V
3.76
3.7
V
V
V
0.4
10
V
mA
µA
µA
µA
-10
10
Commercial
500
500
ICCS
Supply Current, Standby Mode AT17C512A/010A
Industrial/Military
DC Characteristics
VCC = 3.3V 5%
Symbol
VIH
Description
Min
2.0
0.0
2.4
Max
VCC
0.8
Units
V
High-level Input Voltage
VIL
Low-level Input Voltage
V
VOH
VOL
VOH
VOL
VOH
VOL
ICCA
IL
High-level Output Voltage (IOH = -2.5 mA)
Low-level Output Voltage (IOL = +3 mA)
High-level Output Voltage (IOH = -2 mA)
Low-level Output Voltage (IOL = +3 mA)
High-level Output Voltage (IOH = -2 mA)
Low-level Output Voltage (IOL = +2.5 mA)
Supply Current, Active Mode (at FMAX)
Input or Output Leakage Current (VIN = VCC or GND)
V
Commercial
Industrial
Military
0.4
0.4
V
2.4
2.4
V
V
V
0.4
5
V
mA
µA
µA
µA
-10
10
Commercial
100
100
ICCS
Supply Current, Standby Mode
Industrial/Military
8
AT17C/LV002A
2280B–08/01
AT17C/LV002A
AC Characteristics
nCS
TSCE
THCE
TSCE
OE
THOE
TLC
THC
DCLK
TOE
TCAC
TOH
TDF
TCE
DATA
TOH
AC Characteristics When Cascading
OE
nCS
DCLK
T
CDF
LAST BIT
FIRST BIT
DATA
T
T
T
OOE
OCK
OCE
nCASL
T
OCE
9
2280B–08/01
.
AC Characteristics for AT17C002A
VCC = 5V 5% Commercial/VCC = 5V 10% Industry/Military
Commercial
Industrial/Military(1)
Symbol
Description
Min
Max
Min
Max
35
Units
ns
(2)
TOE
OE to Data Delay
30
45
50
(2)
TCE
nCS to Data Delay
45
ns
(2)
TCAC
DCLK to Data Delay
55
ns
TOH
Data Hold From nCS, OE or DCLK
nCS or OE to Data Float Delay
DCLK Low Time Slave Mode
DCLK High Time Slave Mode
nCS Setup Time to DCLK (to guarantee proper counting)
0
0
ns
(3)
TDF
50
50
ns
TLC
20
20
20
0
20
20
25
0
ns
THC
ns
TSCE
THCE
ns
nCS Hold Time from DCLK (to guarantee proper
counting)
ns
TLOE
FMAX
TLC
OE Low Time (guarantees counter is reset)
Maximum Input Clock Frequency Slave Mode
DCLK Low Time Master Mode
20
12
30
30
20
12.5
30
ns
MHz
ns
250
250
250
250
THC
DCLK High Time Master Mode
30
ns
Notes: 1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady state active levels.
AC Characteristics for AT17C002A When Cascading
VCC = 5V 5% Commercial/VCC = 5V 10% Industry/Military
Commercial
Industrial/Military(1)
Symbol
Description
Min
Max
Min
Max
50
Units
ns
(3)
TCDF
DCLK to Data Float Delay
DCLK to nCASC Delay
nCS to nCASC Delay
OE to nCASC Delay
50
35
35
30
(2)
TOCK
40
ns
(2)
TOCE
35
ns
(2)
TOOE
30
ns
FMAX
Maximum Input Clock Frequency
12.5
12.5
MHz
Notes: 1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady state active levels.
10
AT17C/LV002A
2280B–08/01
AT17C/LV002A
.
AC Characteristics for AT17LV002A
VCC = 3.3V 5% Commercial/VCC = 3.3V 5% Industry/Military
Commercial
Industrial/Military(1)
Symbol
Description
Min
Max
Min
Max
55
Units
ns
(2)
TOE
OE to Data Delay
50
55
60
(2)
TCE
nCS to Data Delay
60
ns
(2)
TCAC
DCLK to Data Delay
65
ns
TOH
Data Hold From nCS, OE or DCLK
nCS or OE to Data Float Delay
DCLK Low Time Slave Mode
DCLK High Time Slave Mode
nCS Setup Time to DCLK (to guarantee proper counting)
0.0
0
ns
(3)
TDF
50
50
ns
TLC
25
25
35
0
25
25
40
0
ns
THC
ns
TSCE
THCE
ns
nCS Hold Time from DCLK (to guarantee proper
counting)
ns
TLOE
FMAX
TLC
OE Low Time (guarantees counter is reset)
Maximum Input Clock Frequency Slave Mode
DCLK Low Time Master Mode
20
15
30
30
20
10
30
30
ns
MHz
ns
300
300
300
300
THC
DCLK High Time Master Mode
ns
Notes: 1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady state active levels.
AC Characteristics for AT17LV002A When Cascading
VCC = 3.3V 5% Commercial/VCC = 3.3V 5% Industry/Military
Commercial
Industrial/Military(1)
Symbol
Description
Min
Max
Min
Max
50
Units
ns
(3)
TCDF
DCLK to Data Float Delay
DCLK to nCASC Delay
nCS to nCASC Delay
50
50
35
35
(2)
TOCK
55
ns
(2)
TOCE
40
ns
(2)
TOOE
OE to nCASC Delay
35
ns
FMAX
Maximum Input Clock Frequency Slave Mode
12.0
10
MHz
Notes: 1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady state active levels.
11
2280B–08/01
Ordering Information – 5V Devices
Memory
Size
Ordering Code
Package
Operation Range
2-Mbit(1)
AT17C002A-10JC
20J
Commercial
(0°C to 70°C)
AT17C002A-10JI
AT17C002A-10QC
AT17C002A-10QI
20J
32A
32A
Industrial
(-40°C to 85°C)
2-Mbit(1)
Commercial
(0°C to 70°C)
Industrial
(-40°C to 85°C
Note:
1. Use 2-Mbit density parts to replace Altera EPC2.
Ordering Information – 3.3V Devices
Memory
Size
Ordering Code
Package
Operation Range
2-Mbit(1)
AT17LV002A-10JC
20J
Commercial
(0°C to 70°C)
AT17LV002A-10JI
AT17LV002A-10QC
AT17LV002A-10Q1
20J
32A
32A
Industrial
(-40°C to 85°C)
2-Mbit(1)
Commercial
(0°C to 70°C)
Industrial
(-40°C to 85°C
Note:
1. Use 2-Mbit density parts to replace Altera EPC2. Atmel AT127C/LV002A devices do not support JTAG programming; Atmel
AT17X002A devices use a 2-wire serial interface for in-system programming.
Package Type
20-lead, Plastic J-leaded Chip Carrier (PLCC)
20J
32A
32-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
12
AT17C/LV002A
2280B–08/01
Packaging Information
20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AA
32A, 32-lead, Thin (1.0 mm) Plastic Gull Wing Quad
Flat Package (TQFP)
Dimensions in Millimeters and (Inches)
PIN 1 ID
9.00 (0.354) BSC
0.45 (0.018)
0.30 (0.012)
0.80 (0.031) BSC
9.00 (0.354) BSC
7.00 (0.276) BSC
1.20 (0.047) MAX
0˚
7˚
0.20 (0.008)
0.10 (0.004)
0.15 (0.006)
0.05 (0.002)
0.75 (0.030)
0.45 (0.018)
13
AT17C/LV002A
2280B–08/01
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© Atmel Corporation 2001.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
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Atmel® is the registered trademark of Atmel.
FLEX® is the registered trademark of Altera Corporation.
Other terms and product names may be trademarks of others.
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2280B–08/01/xM
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